---------- Begin Simulation Statistics ----------
sim_seconds                                 47.216814                       # Number of seconds simulated
sim_ticks                                47216814145000                       # Number of ticks simulated
final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1152960                       # Simulator instruction rate (inst/s)
host_op_rate                                  1356355                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            55808802200                       # Simulator tick rate (ticks/s)
host_mem_usage                                 723640                       # Number of bytes of host memory used
host_seconds                                   846.05                       # Real time elapsed on the host
sim_insts                                   975457230                       # Number of instructions simulated
sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       152320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       128704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3903156                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         35201416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       222016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       221568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2639368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         38466864                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        412736                       # Number of bytes read from this memory
system.physmem.bytes_read::total             81348148                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3903156                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2639368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6542524                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    100538752                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total         100559336                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2380                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2011                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            101394                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            550035                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3469                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3462                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             41347                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            601061                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6449                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1311608                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1570918                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1573492                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3226                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2726                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               82665                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              745527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4702                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               55899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              814686                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8741                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1722864                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          82665                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          55899                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             138563                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2129300                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                436                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2129736                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2129300                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2726                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              82665                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             745963                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4702                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              55899                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             814686                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8741                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3852600                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   125229                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               125229                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       125229                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         125229    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       125229                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96746     89.71%     89.71% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11103     10.29%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       107849                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       125229                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       125229                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107849                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107849                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       233078                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    92662773                       # DTB read hits
system.cpu0.dtb.read_misses                     88786                       # DTB read misses
system.cpu0.dtb.write_hits                   85694958                       # DTB write hits
system.cpu0.dtb.write_misses                    36443                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36354                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  5600                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10503                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                92751559                       # DTB read accesses
system.cpu0.dtb.write_accesses               85731401                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        178357731                       # DTB hits
system.cpu0.dtb.misses                         125229                       # DTB misses
system.cpu0.dtb.accesses                    178482960                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    61377                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                61377                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        61377                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          61377    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        61377                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        55424     98.80%     98.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          672      1.20%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        56096                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61377                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61377                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56096                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56096                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       117473                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   497696393                       # ITB inst hits
system.cpu0.itb.inst_misses                     61377                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25032                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               497757770                       # ITB inst accesses
system.cpu0.itb.hits                        497696393                       # DTB hits
system.cpu0.itb.misses                          61377                       # DTB misses
system.cpu0.itb.accesses                    497757770                       # DTB accesses
system.cpu0.numCycles                     94433641544                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  497466384                       # Number of instructions committed
system.cpu0.committedOps                    584970773                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            536103359                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                526132                       # Number of float alu accesses
system.cpu0.num_func_calls                   28869117                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     76496594                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   536103359                       # number of integer instructions
system.cpu0.num_fp_insts                       526132                       # number of float instructions
system.cpu0.num_int_register_reads          784958858                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         425337843                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              849923                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             443780                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           133878831                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          133531045                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    178459396                       # number of memory refs
system.cpu0.num_load_insts                   92737001                       # Number of load instructions
system.cpu0.num_store_insts                  85722395                       # Number of store instructions
system.cpu0.num_idle_cycles              93848337191.325058                       # Number of idle cycles
system.cpu0.num_busy_cycles              585304352.674931                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.006198                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.993802                       # Percentage of idle cycles
system.cpu0.Branches                        111287587                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                405476023     69.28%     69.28% # Class of executed instruction
system.cpu0.op_class::IntMult                 1232194      0.21%     69.49% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59840      0.01%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             72507      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::MemRead                92737001     15.84%     85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite               85722395     14.65%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 585300003                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13253                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          6272773                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.885315                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          172015769                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6273285                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.420366                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.885315                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978292                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.978292                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        363162250                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       363162250                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     86214909                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86214909                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     80919814                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      80919814                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       215654                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       215654                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       262024                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       262024                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2076465                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2076465                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036713                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2036713                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    167134723                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       167134723                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    167350377                       # number of overall hits
system.cpu0.dcache.overall_hits::total      167350377                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3309384                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3309384                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1475628                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1475628                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       772139                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       772139                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       831696                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       831696                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119817                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       119817                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158430                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       158430                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4785012                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4785012                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5557151                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5557151                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     89524293                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     89524293                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     82395442                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     82395442                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       987793                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       987793                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1093720                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1093720                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2196282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2196282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2195143                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2195143                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    171919735                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    171919735                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    172907528                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    172907528                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036966                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036966                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781681                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781681                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.760429                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.760429                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054554                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054554                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072173                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072173                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027833                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027833                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032139                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032139                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4471084                       # number of writebacks
system.cpu0.dcache.writebacks::total          4471084                       # number of writebacks
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5539078                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.989005                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          492212894                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5539590                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.853669                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       5759896500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989005                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses       1001044573                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses      1001044573                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    492212894                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      492212894                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    492212894                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       492212894                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    492212894                       # number of overall hits
system.cpu0.icache.overall_hits::total      492212894                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5539595                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5539595                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5539595                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5539595                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5539595                       # number of overall misses
system.cpu0.icache.overall_misses::total      5539595                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    497752489                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    497752489                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    497752489                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    497752489                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    497752489                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    497752489                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011129                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011129                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011129                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011129                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011129                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011129                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2709460                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16213.748169                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          11555205                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2725459                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            4.239728                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  5709.903296                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    52.786445                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    57.022731                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4531.359232                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  5862.676466                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.348505                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003222                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003480                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.276572                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.357829                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989609                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           48                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15951                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           33                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          234                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1167                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4590                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5333                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4627                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002930                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.973572                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       278732920                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      278732920                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       271204                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       143552                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4971662                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2944246                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       8330664                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4471084                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4471084                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       223142                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       223142                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         3523                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         3523                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       635192                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       635192                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       271204                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       143552                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4971662                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3579438                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8965856                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       271204                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       143552                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4971662                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3579438                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8965856                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11221                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8442                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       567933                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data      1257094                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1844690                       # number of ReadReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       608192                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       608192                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       128237                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       128237                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158430                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       158430                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       709038                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       709038                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11221                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8442                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       567933                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1966132                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2553728                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11221                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8442                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       567933                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1966132                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2553728                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       282425                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       151994                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5539595                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      4201340                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total     10175354                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4471084                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4471084                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       831334                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       831334                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       131760                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       131760                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       158430                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       158430                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1344230                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1344230                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       282425                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       151994                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5539595                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5545570                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11519584                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       282425                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       151994                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5539595                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5545570                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11519584                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039731                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.055542                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.102522                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.299213                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.181290                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.731586                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.731586                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.973262                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.973262                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.527468                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.527468                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039731                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.055542                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102522                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.354541                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.221686                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039731                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.055542                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102522                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.354541                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.221686                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1573136                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1573136                       # number of writebacks
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      10363944                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10363944                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        32419                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        32419                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      4471084                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       831334                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       831334                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       131760                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158430                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       290190                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1344230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1344230                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     11165440                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17935148                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       366654                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       728076                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         30195318                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    354706580                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    694464585                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1466616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2912304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1053550085                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    3357578                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     20506010                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.181419                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.385365                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          16785836     81.86%     81.86% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           3720174     18.14%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      20506010                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   144041                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               144041                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       144041                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         144041    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       144041                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -274403872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       111414     88.97%     88.97% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        13807     11.03%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       125221                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       144041                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       144041                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       125221                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       125221                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       269262                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    90153061                       # DTB read hits
system.cpu1.dtb.read_misses                    111753                       # DTB read misses
system.cpu1.dtb.write_hits                   81132787                       # DTB write hits
system.cpu1.dtb.write_misses                    32288                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   44587                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4554                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11374                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                90264814                       # DTB read accesses
system.cpu1.dtb.write_accesses               81165075                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        171285848                       # DTB hits
system.cpu1.dtb.misses                         144041                       # DTB misses
system.cpu1.dtb.accesses                    171429889                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    60885                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60885                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        60885                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60885    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60885                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -274404872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        53790     99.07%     99.07% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          505      0.93%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        54295                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60885                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60885                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       115180                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   478248118                       # ITB inst hits
system.cpu1.itb.inst_misses                     60885                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31530                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               478309003                       # ITB inst accesses
system.cpu1.itb.hits                        478248118                       # DTB hits
system.cpu1.itb.misses                          60885                       # DTB misses
system.cpu1.itb.accesses                    478309003                       # DTB accesses
system.cpu1.numCycles                     94433634550                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  477990846                       # Number of instructions committed
system.cpu1.committedOps                    562567642                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            516282159                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                374678                       # Number of float alu accesses
system.cpu1.num_func_calls                   28237407                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     73185792                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   516282159                       # number of integer instructions
system.cpu1.num_fp_insts                       374678                       # number of float instructions
system.cpu1.num_int_register_reads          763231058                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         411079626                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              608455                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             306456                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           126379788                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          126112608                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    171406825                       # number of memory refs
system.cpu1.num_load_insts                   90251973                       # Number of load instructions
system.cpu1.num_store_insts                  81154852                       # Number of store instructions
system.cpu1.num_idle_cycles              93870750285.000458                       # Number of idle cycles
system.cpu1.num_busy_cycles              562884264.999552                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.005961                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.994039                       # Percentage of idle cycles
system.cpu1.Branches                        106497601                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                390236864     69.33%     69.33% # Class of executed instruction
system.cpu1.op_class::IntMult                 1137629      0.20%     69.53% # Class of executed instruction
system.cpu1.op_class::IntDiv                    60962      0.01%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             37059      0.01%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::MemRead                90251973     16.03%     85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite               81154852     14.42%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 562879339                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    6259                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5945049                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          438.290639                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          165346662                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5945561                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.810103                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8470277778500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   438.290639                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.856036                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.856036                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        348813711                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       348813711                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     83697564                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       83697564                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     76990302                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      76990302                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187854                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       187854                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        63438                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total        63438                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062256                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      2062256                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048921                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      2048921                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    160687866                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       160687866                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    160875720                       # number of overall hits
system.cpu1.dcache.overall_hits::total      160875720                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3358222                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3358222                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1453174                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1453174                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       792351                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       792351                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       427061                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       427061                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       146820                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       146820                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158828                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       158828                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4811396                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4811396                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5603747                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5603747                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     87055786                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     87055786                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     78443476                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     78443476                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       980205                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       980205                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       490499                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       490499                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2209076                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2209076                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2207749                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2207749                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    165499262                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    165499262                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    166479467                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    166479467                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038576                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.038576                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018525                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018525                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808352                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808352                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.870666                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.870666                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071941                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071941                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029072                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029072                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033660                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.033660                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      4032690                       # number of writebacks
system.cpu1.dcache.writebacks::total          4032690                       # number of writebacks
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4741297                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.426080                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          473560604                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4741809                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            99.869186                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8470205816000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.426080                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969582                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969582                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        961346635                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       961346635                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    473560604                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      473560604                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    473560604                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       473560604                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    473560604                       # number of overall hits
system.cpu1.icache.overall_hits::total      473560604                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4741809                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4741809                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4741809                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4741809                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4741809                       # number of overall misses
system.cpu1.icache.overall_misses::total      4741809                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst    478302413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    478302413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    478302413                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    478302413                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    478302413                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    478302413                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009914                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009914                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009914                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009914                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009914                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009914                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2276750                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13455.535871                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10863007                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2292767                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.737946                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9713557209000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5167.508425                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.262953                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    86.675159                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2849.798557                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5285.290777                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.315400                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004044                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005290                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.173938                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.322589                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.821261                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           96                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15921                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           49                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1571                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5986                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4452                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3831                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.971741                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       254014080                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      254014080                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       324472                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       140015                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4218186                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      3058286                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       7740959                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      4032690                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      4032690                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       161150                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       161150                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3831                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         3831                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614491                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       614491                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       324472                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       140015                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4218186                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3672777                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8355450                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       324472                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       140015                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4218186                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3672777                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8355450                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12267                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9705                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       523623                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data      1239107                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1784702                       # number of ReadReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       265696                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       265696                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133668                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       133668                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158828                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       158828                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       701399                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       701399                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12267                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9705                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       523623                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1940506                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2486101                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12267                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9705                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       523623                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1940506                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2486101                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       336739                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149720                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4741809                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      4297393                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      9525661                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      4032690                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      4032690                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       426846                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       426846                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137499                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       137499                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       158828                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       158828                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1315890                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1315890                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       336739                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149720                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4741809                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5613283                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10841551                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       336739                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149720                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4741809                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5613283                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10841551                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.110427                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.288339                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.187357                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.622463                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.622463                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.972138                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.972138                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.533023                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.533023                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110427                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345699                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.229312                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036429                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.064821                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110427                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345699                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.229312                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1183004                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1183004                       # number of writebacks
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       9645413                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9645413                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         6383                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         6383                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4032690                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       426846                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       426846                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       137499                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       158828                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       296327                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1315890                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1315890                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9483878                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16731086                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       364008                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       835436                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         27414408                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    303476296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    644698812                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1456032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3341744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         952972884                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    3837128                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     19395843                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.220254                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.414418                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          15123827     77.97%     77.97% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           4272016     22.03%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      19395843                       # Request fanout histogram
system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136634                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29906                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47636                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122570                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353858                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47656                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155677                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496611                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements               115585                       # number of replacements
system.iocache.tags.tagsinuse               11.290896                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115601                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9107775783009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.851982                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.438915                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240749                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.464932                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705681                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040793                       # Number of tag accesses
system.iocache.tags.data_accesses             1040793                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8876                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8913                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8876                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8916                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8876                       # number of overall misses
system.iocache.overall_misses::total             8916                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8876                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8913                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8876                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8916                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8876                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8916                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1759191                       # number of replacements
system.l2c.tags.tagsinuse                62867.167491                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3704436                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1817948                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.037702                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                483416500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35264.935108                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.422401                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    57.110376                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3318.609191                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6952.273283                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   314.594733                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   425.085194                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2976.403767                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    13512.733438                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.538100                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000693                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000871                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.050638                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.106083                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004800                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.045416                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.206188                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.959277                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          227                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        58530                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          225                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3441                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5617                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        48852                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003464                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.893097                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 66366738                       # Number of tag accesses
system.l2c.tags.data_accesses                66366738                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6239                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4535                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             509640                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             744526                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5366                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3579                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             482377                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             691195                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2447457                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2756140                       # number of Writeback hits
system.l2c.Writeback_hits::total              2756140                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       121071                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data        98425                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       219496                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           13420                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           10778                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               24198                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          1497                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1278                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              2775                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           202220                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           170877                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               373097                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6239                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4535                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              509640                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              946746                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5366                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3579                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              482377                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              862072                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2820554                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6239                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4535                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             509640                       # number of overall hits
system.l2c.overall_hits::cpu0.data             946746                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5366                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3579                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             482377                       # number of overall hits
system.l2c.overall_hits::cpu1.data             862072                       # number of overall hits
system.l2c.overall_hits::total                2820554                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2380                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2011                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            58293                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           183599                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         3469                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         3462                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            41246                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           189649                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               484109                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       479323                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       160634                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       639957                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         58449                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         54093                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            112542                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         7788                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         7462                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           15250                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         377640                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         418302                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             795942                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2380                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2011                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             58293                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            561239                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3469                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3462                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             41246                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            607951                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1280051                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2380                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2011                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            58293                       # number of overall misses
system.l2c.overall_misses::cpu0.data           561239                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3469                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3462                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            41246                       # number of overall misses
system.l2c.overall_misses::cpu1.data           607951                       # number of overall misses
system.l2c.overall_misses::total              1280051                       # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8619                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6546                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         567933                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         928125                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         8835                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7041                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         523623                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         880844                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2931566                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2756140                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2756140                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       600394                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       259059                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       859453                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        71869                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        64871                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          136740                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         9285                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         8740                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         18025                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       579860                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       589179                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1169039                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8619                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          567933                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1507985                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8835                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7041                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          523623                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1470023                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4100605                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8619                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         567933                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1507985                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8835                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7041                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         523623                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1470023                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4100605                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.102641                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.197817                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.078770                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.215304                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.165137                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.798347                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.620067                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.744610                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.813271                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.833855                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.823036                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.838772                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.853776                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.846047                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.651261                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.709974                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.680852                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.102641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.372178                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.078770                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.413566                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.312161                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.276134                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.307211                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.102641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.372178                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.392643                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.491692                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.078770                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.413566                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.312161                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1464224                       # number of writebacks
system.l2c.writebacks::total                  1464224                       # number of writebacks
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              575153                       # Transaction distribution
system.membus.trans_dist::ReadResp             575153                       # Transaction distribution
system.membus.trans_dist::WriteReq              38802                       # Transaction distribution
system.membus.trans_dist::WriteResp             38802                       # Transaction distribution
system.membus.trans_dist::Writeback           1570918                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       742110                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       742110                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           328170                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         314483                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          149857                       # Transaction distribution
system.membus.trans_dist::ReadExReq            965890                       # Transaction distribution
system.membus.trans_dist::ReadExResp           778455                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122570                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27558                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6331701                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6481921                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337982                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       337982                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6819903                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55116                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    215372636                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    215583633                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14229440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14229440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               229813073                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           4535526                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4535526    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4535526                       # Request fanout histogram
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            3711525                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3711525                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38802                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38802                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2756140                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       859453                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       859453                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          330303                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        317258                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         647561                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1356474                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1356474                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8686436                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7297334                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15983770                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    301115229                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    249782916                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              550898145                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          117325                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9485599                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.012192                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.109740                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                9369955     98.78%     98.78% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115644      1.22%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9485599                       # Request fanout histogram

---------- End Simulation Statistics   ----------