stats.txt revision 11353:31c5786945b4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660643 # Number of seconds simulated 4sim_ticks 51660642512000 # Number of ticks simulated 5final_tick 51660642512000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 304990 # Simulator instruction rate (inst/s) 8host_op_rate 358371 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16937149026 # Simulator tick rate (ticks/s) 10host_mem_usage 683404 # Number of bytes of host memory used 11host_seconds 3050.14 # Real time elapsed on the host 12sim_insts 930261902 # Number of instructions simulated 13sim_ops 1093080704 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 377280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10274880 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61682056 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 384384 # Number of bytes read from this memory 21system.physmem.bytes_read::total 73038600 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10274880 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10274880 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 89590976 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 89611556 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5895 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5000 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 160545 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 963795 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6006 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1141241 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1399859 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1402432 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 7303 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6194 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 198892 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1193985 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7441 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1413815 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 198892 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 198892 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1734221 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1734619 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1734221 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 7303 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6194 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 198892 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1194384 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7441 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3148435 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1141241 # Number of read requests accepted 55system.physmem.writeReqs 1402432 # Number of write requests accepted 56system.physmem.readBursts 1141241 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1402432 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 72981760 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 57664 # Total number of bytes read from write queue 60system.physmem.bytesWritten 89610624 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 73038600 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 89611556 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 901 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 67748 # Per bank write bursts 67system.physmem.perBankRdBursts::1 75024 # Per bank write bursts 68system.physmem.perBankRdBursts::2 69908 # Per bank write bursts 69system.physmem.perBankRdBursts::3 64252 # Per bank write bursts 70system.physmem.perBankRdBursts::4 67104 # Per bank write bursts 71system.physmem.perBankRdBursts::5 72834 # Per bank write bursts 72system.physmem.perBankRdBursts::6 66007 # Per bank write bursts 73system.physmem.perBankRdBursts::7 65201 # Per bank write bursts 74system.physmem.perBankRdBursts::8 62658 # Per bank write bursts 75system.physmem.perBankRdBursts::9 122060 # Per bank write bursts 76system.physmem.perBankRdBursts::10 69885 # Per bank write bursts 77system.physmem.perBankRdBursts::11 74467 # Per bank write bursts 78system.physmem.perBankRdBursts::12 66975 # Per bank write bursts 79system.physmem.perBankRdBursts::13 66087 # Per bank write bursts 80system.physmem.perBankRdBursts::14 62026 # Per bank write bursts 81system.physmem.perBankRdBursts::15 68104 # Per bank write bursts 82system.physmem.perBankWrBursts::0 85430 # Per bank write bursts 83system.physmem.perBankWrBursts::1 89554 # Per bank write bursts 84system.physmem.perBankWrBursts::2 89147 # Per bank write bursts 85system.physmem.perBankWrBursts::3 85797 # Per bank write bursts 86system.physmem.perBankWrBursts::4 87375 # Per bank write bursts 87system.physmem.perBankWrBursts::5 90488 # Per bank write bursts 88system.physmem.perBankWrBursts::6 83025 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85134 # Per bank write bursts 90system.physmem.perBankWrBursts::8 84926 # Per bank write bursts 91system.physmem.perBankWrBursts::9 90963 # Per bank write bursts 92system.physmem.perBankWrBursts::10 87836 # Per bank write bursts 93system.physmem.perBankWrBursts::11 92829 # Per bank write bursts 94system.physmem.perBankWrBursts::12 87557 # Per bank write bursts 95system.physmem.perBankWrBursts::13 87424 # Per bank write bursts 96system.physmem.perBankWrBursts::14 84847 # Per bank write bursts 97system.physmem.perBankWrBursts::15 87834 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 50 # Number of times write queue was full causing retry 100system.physmem.totGap 51660640624000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1141226 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1399859 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1072907 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 61649 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 723 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 449 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1108 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 583 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 155 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 34167 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 39504 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 78543 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80306 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82649 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 80800 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 81768 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 85658 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85076 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 81194 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 82459 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 85799 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 82823 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 82988 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 84778 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 80804 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 79640 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 79007 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2607 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1103 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 824 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 673 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 570 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 578 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 411 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 395 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 375 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 313 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 273 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 229 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 195 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 165 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 144 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 169 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 180 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 132 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 648089 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 250.879123 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 152.008733 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 285.888919 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 280289 43.25% 43.25% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 166837 25.74% 68.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 60882 9.39% 78.39% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 33521 5.17% 83.56% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 23050 3.56% 87.11% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 16307 2.52% 89.63% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 11522 1.78% 91.41% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 9570 1.48% 92.89% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 46111 7.11% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 648089 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 76765 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 14.854530 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 142.199486 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 76763 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 76765 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 76765 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 18.239640 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 17.683114 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 7.179019 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 64873 84.51% 84.51% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 9480 12.35% 96.86% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 455 0.59% 97.45% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 326 0.42% 97.88% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 60 0.08% 97.95% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 114 0.15% 98.10% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 230 0.30% 98.40% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 35 0.05% 98.45% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 294 0.38% 98.83% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 75 0.10% 98.93% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 27 0.04% 98.96% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 50 0.07% 99.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 318 0.41% 99.44% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 35 0.05% 99.49% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 31 0.04% 99.53% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 111 0.14% 99.67% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 179 0.23% 99.91% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 6 0.01% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::176-179 7 0.01% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 76765 # Writes before turning the bus around for reads 271system.physmem.totQLat 16541565713 # Total ticks spent queuing 272system.physmem.totMemAccLat 37922940713 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 5701700000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 14505.82 # Average queueing delay per DRAM burst 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 276system.physmem.avgMemAccLat 33255.82 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.02 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing 287system.physmem.readRowHits 872320 # Number of row buffer hits during reads 288system.physmem.writeRowHits 1020096 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 72.85 # Row buffer hit rate for writes 291system.physmem.avgGap 20309466.12 # Average gap between requests 292system.physmem.pageHitRate 74.49 # Row buffer hit rate, read and write combined 293system.physmem_0.actEnergy 2456674920 # Energy for activate commands per rank (pJ) 294system.physmem_0.preEnergy 1340447625 # Energy for precharge commands per rank (pJ) 295system.physmem_0.readEnergy 4274961600 # Energy for read commands per rank (pJ) 296system.physmem_0.writeEnergy 4509756000 # Energy for write commands per rank (pJ) 297system.physmem_0.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) 298system.physmem_0.actBackEnergy 1317434781870 # Energy for active background per rank (pJ) 299system.physmem_0.preBackEnergy 29840739448500 # Energy for precharge background per rank (pJ) 300system.physmem_0.totalEnergy 34544977929315 # Total energy per rank (pJ) 301system.physmem_0.averagePower 668.690476 # Core power per rank (mW) 302system.physmem_0.memoryStateTime::IDLE 49641970693393 # Time in different power states 303system.physmem_0.memoryStateTime::REF 1725062300000 # Time in different power states 304system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem_0.memoryStateTime::ACT 293608746107 # Time in different power states 306system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.physmem_1.actEnergy 2442877920 # Energy for activate commands per rank (pJ) 308system.physmem_1.preEnergy 1332919500 # Energy for precharge commands per rank (pJ) 309system.physmem_1.readEnergy 4619643600 # Energy for read commands per rank (pJ) 310system.physmem_1.writeEnergy 4563319680 # Energy for write commands per rank (pJ) 311system.physmem_1.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) 312system.physmem_1.actBackEnergy 1319027164650 # Energy for active background per rank (pJ) 313system.physmem_1.preBackEnergy 29839342629750 # Energy for precharge background per rank (pJ) 314system.physmem_1.totalEnergy 34545550413900 # Total energy per rank (pJ) 315system.physmem_1.averagePower 668.701557 # Core power per rank (mW) 316system.physmem_1.memoryStateTime::IDLE 49639611346782 # Time in different power states 317system.physmem_1.memoryStateTime::REF 1725062300000 # Time in different power states 318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 319system.physmem_1.memoryStateTime::ACT 295966370718 # Time in different power states 320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 321system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 324system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 325system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 326system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 327system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 328system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 329system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 335system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 336system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 337system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 338system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 339system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 340system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 341system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 342system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 343system.cpu.branchPred.lookups 254908438 # Number of BP lookups 344system.cpu.branchPred.condPredicted 178242351 # Number of conditional branches predicted 345system.cpu.branchPred.condIncorrect 12005241 # Number of conditional branches incorrect 346system.cpu.branchPred.BTBLookups 187385958 # Number of BTB lookups 347system.cpu.branchPred.BTBHits 132827814 # Number of BTB hits 348system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 349system.cpu.branchPred.BTBHitPct 70.884615 # BTB Hit Percentage 350system.cpu.branchPred.usedRAS 31213174 # Number of times the RAS was used to get a target. 351system.cpu.branchPred.RASInCorrect 2144347 # Number of incorrect RAS predictions. 352system.cpu_clk_domain.clock 500 # Clock period in ticks 353system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 362system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 363system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 364system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 365system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 366system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 382system.cpu.dtb.walker.walks 567320 # Table walker walks requested 383system.cpu.dtb.walker.walksLong 567320 # Table walker walks initiated with long descriptors 384system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20723 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walksLongTerminationLevel::Level3 182198 # Level at which table walker walks with long descriptors terminate 386system.cpu.dtb.walker.walkWaitTime::samples 567320 # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::0 567320 100.00% 100.00% # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::total 567320 # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkCompletionTime::samples 202921 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::0-65535 200464 98.79% 98.79% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::65536-131071 14 0.01% 98.80% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::131072-196607 2073 1.02% 99.82% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::196608-262143 61 0.03% 99.85% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::262144-327679 133 0.07% 99.91% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.94% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.98% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::458752-524287 15 0.01% 99.99% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::total 202921 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 408system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 409system.cpu.dtb.walker.walkPageSizes::4K 182199 89.79% 89.79% # Table walker page sizes translated 410system.cpu.dtb.walker.walkPageSizes::2M 20723 10.21% 100.00% # Table walker page sizes translated 411system.cpu.dtb.walker.walkPageSizes::total 202922 # Table walker page sizes translated 412system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 567320 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::total 567320 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202922 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202922 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin::total 770242 # Table walker requests started/completed, data/inst 419system.cpu.dtb.inst_hits 0 # ITB inst hits 420system.cpu.dtb.inst_misses 0 # ITB inst misses 421system.cpu.dtb.read_hits 179769202 # DTB read hits 422system.cpu.dtb.read_misses 468572 # DTB read misses 423system.cpu.dtb.write_hits 159383411 # DTB write hits 424system.cpu.dtb.write_misses 98748 # DTB write misses 425system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 426system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 427system.cpu.dtb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID 428system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 429system.cpu.dtb.flush_entries 78846 # Number of entries that have been flushed from TLB 430system.cpu.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 431system.cpu.dtb.prefetch_faults 15815 # Number of TLB faults due to prefetch 432system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 433system.cpu.dtb.perms_faults 23199 # Number of TLB faults due to permissions restrictions 434system.cpu.dtb.read_accesses 180237774 # DTB read accesses 435system.cpu.dtb.write_accesses 159482159 # DTB write accesses 436system.cpu.dtb.inst_accesses 0 # ITB inst accesses 437system.cpu.dtb.hits 339152613 # DTB hits 438system.cpu.dtb.misses 567320 # DTB misses 439system.cpu.dtb.accesses 339719933 # DTB accesses 440system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 449system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 450system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 451system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 452system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 453system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 454system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 458system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 459system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 460system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 461system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 462system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 463system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 464system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 465system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 466system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 467system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 468system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 469system.cpu.itb.walker.walks 135719 # Table walker walks requested 470system.cpu.itb.walker.walksLong 135719 # Table walker walks initiated with long descriptors 471system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate 472system.cpu.itb.walker.walksLongTerminationLevel::Level3 118398 # Level at which table walker walks with long descriptors terminate 473system.cpu.itb.walker.walkWaitTime::samples 135719 # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkWaitTime::0 135719 100.00% 100.00% # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkWaitTime::total 135719 # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkCompletionTime::samples 119465 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::mean 30823.412715 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::0-65535 116639 97.63% 97.63% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.64% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::131072-196607 2565 2.15% 99.79% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::196608-262143 80 0.07% 99.85% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::262144-327679 132 0.11% 99.96% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.99% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::total 119465 # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 491system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 492system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 493system.cpu.itb.walker.walkPageSizes::4K 118398 99.11% 99.11% # Table walker page sizes translated 494system.cpu.itb.walker.walkPageSizes::2M 1067 0.89% 100.00% # Table walker page sizes translated 495system.cpu.itb.walker.walkPageSizes::total 119465 # Table walker page sizes translated 496system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135719 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Requested::total 135719 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119465 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::total 119465 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin::total 255184 # Table walker requests started/completed, data/inst 503system.cpu.itb.inst_hits 443155891 # ITB inst hits 504system.cpu.itb.inst_misses 135719 # ITB inst misses 505system.cpu.itb.read_hits 0 # DTB read hits 506system.cpu.itb.read_misses 0 # DTB read misses 507system.cpu.itb.write_hits 0 # DTB write hits 508system.cpu.itb.write_misses 0 # DTB write misses 509system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 510system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 511system.cpu.itb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID 512system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 513system.cpu.itb.flush_entries 56716 # Number of entries that have been flushed from TLB 514system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 515system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 516system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 517system.cpu.itb.perms_faults 363456 # Number of TLB faults due to permissions restrictions 518system.cpu.itb.read_accesses 0 # DTB read accesses 519system.cpu.itb.write_accesses 0 # DTB write accesses 520system.cpu.itb.inst_accesses 443291610 # ITB inst accesses 521system.cpu.itb.hits 443155891 # DTB hits 522system.cpu.itb.misses 135719 # DTB misses 523system.cpu.itb.accesses 443291610 # DTB accesses 524system.cpu.numCycles 2560430377 # number of cpu cycles simulated 525system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 526system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 527system.cpu.committedInsts 930261902 # Number of instructions committed 528system.cpu.committedOps 1093080704 # Number of ops (including micro ops) committed 529system.cpu.discardedOps 94082781 # Number of ops (including micro ops) which were discarded before commit 530system.cpu.numFetchSuspends 7654 # Number of times Execute suspended instruction fetching 531system.cpu.quiesceCycles 100762000477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 532system.cpu.cpi 2.752376 # CPI: cycles per instruction 533system.cpu.ipc 0.363322 # IPC: instructions per cycle 534system.cpu.kern.inst.arm 0 # number of arm instructions executed 535system.cpu.kern.inst.quiesce 16514 # number of quiesce instructions executed 536system.cpu.tickCycles 1756892100 # Number of cycles that the object actually ticked 537system.cpu.idleCycles 803538277 # Total number of cycles that the object has spent stopped 538system.cpu.dcache.tags.replacements 10835760 # number of replacements 539system.cpu.dcache.tags.tagsinuse 511.930073 # Cycle average of tags in use 540system.cpu.dcache.tags.total_refs 323161698 # Total number of references to valid blocks. 541system.cpu.dcache.tags.sampled_refs 10836272 # Sample count of references to valid blocks. 542system.cpu.dcache.tags.avg_refs 29.822221 # Average number of references to valid blocks. 543system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 544system.cpu.dcache.tags.occ_blocks::cpu.data 511.930073 # Average occupied blocks per requestor 545system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 546system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 547system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 548system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 549system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id 550system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 551system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 552system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 553system.cpu.dcache.tags.tag_accesses 1357625936 # Number of tag accesses 554system.cpu.dcache.tags.data_accesses 1357625936 # Number of data accesses 555system.cpu.dcache.ReadReq_hits::cpu.data 165326360 # number of ReadReq hits 556system.cpu.dcache.ReadReq_hits::total 165326360 # number of ReadReq hits 557system.cpu.dcache.WriteReq_hits::cpu.data 148822242 # number of WriteReq hits 558system.cpu.dcache.WriteReq_hits::total 148822242 # number of WriteReq hits 559system.cpu.dcache.SoftPFReq_hits::cpu.data 515783 # number of SoftPFReq hits 560system.cpu.dcache.SoftPFReq_hits::total 515783 # number of SoftPFReq hits 561system.cpu.dcache.WriteLineReq_hits::cpu.data 336254 # number of WriteLineReq hits 562system.cpu.dcache.WriteLineReq_hits::total 336254 # number of WriteLineReq hits 563system.cpu.dcache.LoadLockedReq_hits::cpu.data 3901835 # number of LoadLockedReq hits 564system.cpu.dcache.LoadLockedReq_hits::total 3901835 # number of LoadLockedReq hits 565system.cpu.dcache.StoreCondReq_hits::cpu.data 4210707 # number of StoreCondReq hits 566system.cpu.dcache.StoreCondReq_hits::total 4210707 # number of StoreCondReq hits 567system.cpu.dcache.demand_hits::cpu.data 314148602 # number of demand (read+write) hits 568system.cpu.dcache.demand_hits::total 314148602 # number of demand (read+write) hits 569system.cpu.dcache.overall_hits::cpu.data 314664385 # number of overall hits 570system.cpu.dcache.overall_hits::total 314664385 # number of overall hits 571system.cpu.dcache.ReadReq_misses::cpu.data 6435963 # number of ReadReq misses 572system.cpu.dcache.ReadReq_misses::total 6435963 # number of ReadReq misses 573system.cpu.dcache.WriteReq_misses::cpu.data 4178110 # number of WriteReq misses 574system.cpu.dcache.WriteReq_misses::total 4178110 # number of WriteReq misses 575system.cpu.dcache.SoftPFReq_misses::cpu.data 1419320 # number of SoftPFReq misses 576system.cpu.dcache.SoftPFReq_misses::total 1419320 # number of SoftPFReq misses 577system.cpu.dcache.WriteLineReq_misses::cpu.data 1240241 # number of WriteLineReq misses 578system.cpu.dcache.WriteLineReq_misses::total 1240241 # number of WriteLineReq misses 579system.cpu.dcache.LoadLockedReq_misses::cpu.data 310588 # number of LoadLockedReq misses 580system.cpu.dcache.LoadLockedReq_misses::total 310588 # number of LoadLockedReq misses 581system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses 582system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses 583system.cpu.dcache.demand_misses::cpu.data 10614073 # number of demand (read+write) misses 584system.cpu.dcache.demand_misses::total 10614073 # number of demand (read+write) misses 585system.cpu.dcache.overall_misses::cpu.data 12033393 # number of overall misses 586system.cpu.dcache.overall_misses::total 12033393 # number of overall misses 587system.cpu.dcache.ReadReq_miss_latency::cpu.data 119289543000 # number of ReadReq miss cycles 588system.cpu.dcache.ReadReq_miss_latency::total 119289543000 # number of ReadReq miss cycles 589system.cpu.dcache.WriteReq_miss_latency::cpu.data 206542043000 # number of WriteReq miss cycles 590system.cpu.dcache.WriteReq_miss_latency::total 206542043000 # number of WriteReq miss cycles 591system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53400604000 # number of WriteLineReq miss cycles 592system.cpu.dcache.WriteLineReq_miss_latency::total 53400604000 # number of WriteLineReq miss cycles 593system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5170357500 # number of LoadLockedReq miss cycles 594system.cpu.dcache.LoadLockedReq_miss_latency::total 5170357500 # number of LoadLockedReq miss cycles 595system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245500 # number of StoreCondReq miss cycles 596system.cpu.dcache.StoreCondReq_miss_latency::total 245500 # number of StoreCondReq miss cycles 597system.cpu.dcache.demand_miss_latency::cpu.data 325831586000 # number of demand (read+write) miss cycles 598system.cpu.dcache.demand_miss_latency::total 325831586000 # number of demand (read+write) miss cycles 599system.cpu.dcache.overall_miss_latency::cpu.data 325831586000 # number of overall miss cycles 600system.cpu.dcache.overall_miss_latency::total 325831586000 # number of overall miss cycles 601system.cpu.dcache.ReadReq_accesses::cpu.data 171762323 # number of ReadReq accesses(hits+misses) 602system.cpu.dcache.ReadReq_accesses::total 171762323 # number of ReadReq accesses(hits+misses) 603system.cpu.dcache.WriteReq_accesses::cpu.data 153000352 # number of WriteReq accesses(hits+misses) 604system.cpu.dcache.WriteReq_accesses::total 153000352 # number of WriteReq accesses(hits+misses) 605system.cpu.dcache.SoftPFReq_accesses::cpu.data 1935103 # number of SoftPFReq accesses(hits+misses) 606system.cpu.dcache.SoftPFReq_accesses::total 1935103 # number of SoftPFReq accesses(hits+misses) 607system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576495 # number of WriteLineReq accesses(hits+misses) 608system.cpu.dcache.WriteLineReq_accesses::total 1576495 # number of WriteLineReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4212423 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.LoadLockedReq_accesses::total 4212423 # number of LoadLockedReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::cpu.data 4210710 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.StoreCondReq_accesses::total 4210710 # number of StoreCondReq accesses(hits+misses) 613system.cpu.dcache.demand_accesses::cpu.data 324762675 # number of demand (read+write) accesses 614system.cpu.dcache.demand_accesses::total 324762675 # number of demand (read+write) accesses 615system.cpu.dcache.overall_accesses::cpu.data 326697778 # number of overall (read+write) accesses 616system.cpu.dcache.overall_accesses::total 326697778 # number of overall (read+write) accesses 617system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037470 # miss rate for ReadReq accesses 618system.cpu.dcache.ReadReq_miss_rate::total 0.037470 # miss rate for ReadReq accesses 619system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027308 # miss rate for WriteReq accesses 620system.cpu.dcache.WriteReq_miss_rate::total 0.027308 # miss rate for WriteReq accesses 621system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733460 # miss rate for SoftPFReq accesses 622system.cpu.dcache.SoftPFReq_miss_rate::total 0.733460 # miss rate for SoftPFReq accesses 623system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786708 # miss rate for WriteLineReq accesses 624system.cpu.dcache.WriteLineReq_miss_rate::total 0.786708 # miss rate for WriteLineReq accesses 625system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073731 # miss rate for LoadLockedReq accesses 626system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073731 # miss rate for LoadLockedReq accesses 627system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 628system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 629system.cpu.dcache.demand_miss_rate::cpu.data 0.032683 # miss rate for demand accesses 630system.cpu.dcache.demand_miss_rate::total 0.032683 # miss rate for demand accesses 631system.cpu.dcache.overall_miss_rate::cpu.data 0.036833 # miss rate for overall accesses 632system.cpu.dcache.overall_miss_rate::total 0.036833 # miss rate for overall accesses 633system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18534.839775 # average ReadReq miss latency 634system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775 # average ReadReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49434.323893 # average WriteReq miss latency 636system.cpu.dcache.WriteReq_avg_miss_latency::total 49434.323893 # average WriteReq miss latency 637system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960 # average WriteLineReq miss latency 638system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960 # average WriteLineReq miss latency 639system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16646.996986 # average LoadLockedReq miss latency 640system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16646.996986 # average LoadLockedReq miss latency 641system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81833.333333 # average StoreCondReq miss latency 642system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333 # average StoreCondReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.data 30698.072832 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 30698.072832 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.282858 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 27077.282858 # average overall miss latency 647system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.dcache.fast_writes 0 # number of fast writes performed 654system.cpu.dcache.cache_copies 0 # number of cache copies performed 655system.cpu.dcache.writebacks::writebacks 8326510 # number of writebacks 656system.cpu.dcache.writebacks::total 8326510 # number of writebacks 657system.cpu.dcache.ReadReq_mshr_hits::cpu.data 781266 # number of ReadReq MSHR hits 658system.cpu.dcache.ReadReq_mshr_hits::total 781266 # number of ReadReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841490 # number of WriteReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::total 1841490 # number of WriteReq MSHR hits 661system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 148 # number of WriteLineReq MSHR hits 662system.cpu.dcache.WriteLineReq_mshr_hits::total 148 # number of WriteLineReq MSHR hits 663system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69021 # number of LoadLockedReq MSHR hits 664system.cpu.dcache.LoadLockedReq_mshr_hits::total 69021 # number of LoadLockedReq MSHR hits 665system.cpu.dcache.demand_mshr_hits::cpu.data 2622756 # number of demand (read+write) MSHR hits 666system.cpu.dcache.demand_mshr_hits::total 2622756 # number of demand (read+write) MSHR hits 667system.cpu.dcache.overall_mshr_hits::cpu.data 2622756 # number of overall MSHR hits 668system.cpu.dcache.overall_mshr_hits::total 2622756 # number of overall MSHR hits 669system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5654697 # number of ReadReq MSHR misses 670system.cpu.dcache.ReadReq_mshr_misses::total 5654697 # number of ReadReq MSHR misses 671system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2336620 # number of WriteReq MSHR misses 672system.cpu.dcache.WriteReq_mshr_misses::total 2336620 # number of WriteReq MSHR misses 673system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1411789 # number of SoftPFReq MSHR misses 674system.cpu.dcache.SoftPFReq_mshr_misses::total 1411789 # number of SoftPFReq MSHR misses 675system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1240093 # number of WriteLineReq MSHR misses 676system.cpu.dcache.WriteLineReq_mshr_misses::total 1240093 # number of WriteLineReq MSHR misses 677system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241567 # number of LoadLockedReq MSHR misses 678system.cpu.dcache.LoadLockedReq_mshr_misses::total 241567 # number of LoadLockedReq MSHR misses 679system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses 680system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses 681system.cpu.dcache.demand_mshr_misses::cpu.data 7991317 # number of demand (read+write) MSHR misses 682system.cpu.dcache.demand_mshr_misses::total 7991317 # number of demand (read+write) MSHR misses 683system.cpu.dcache.overall_mshr_misses::cpu.data 9403106 # number of overall MSHR misses 684system.cpu.dcache.overall_mshr_misses::total 9403106 # number of overall MSHR misses 685system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 686system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 687system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 688system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 689system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 690system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97635804500 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_latency::total 97635804500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109449194500 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::total 109449194500 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26743318000 # number of SoftPFReq MSHR miss cycles 696system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26743318000 # number of SoftPFReq MSHR miss cycles 697system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52153246000 # number of WriteLineReq MSHR miss cycles 698system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52153246000 # number of WriteLineReq MSHR miss cycles 699system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3514198000 # number of LoadLockedReq MSHR miss cycles 700system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3514198000 # number of LoadLockedReq MSHR miss cycles 701system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 242500 # number of StoreCondReq MSHR miss cycles 702system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 242500 # number of StoreCondReq MSHR miss cycles 703system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207084999000 # number of demand (read+write) MSHR miss cycles 704system.cpu.dcache.demand_mshr_miss_latency::total 207084999000 # number of demand (read+write) MSHR miss cycles 705system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233828317000 # number of overall MSHR miss cycles 706system.cpu.dcache.overall_mshr_miss_latency::total 233828317000 # number of overall MSHR miss cycles 707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197367000 # number of ReadReq MSHR uncacheable cycles 708system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197367000 # number of ReadReq MSHR uncacheable cycles 709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207571500 # number of WriteReq MSHR uncacheable cycles 710system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207571500 # number of WriteReq MSHR uncacheable cycles 711system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404938500 # number of overall MSHR uncacheable cycles 712system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404938500 # number of overall MSHR uncacheable cycles 713system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032922 # mshr miss rate for ReadReq accesses 714system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032922 # mshr miss rate for ReadReq accesses 715system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015272 # mshr miss rate for WriteReq accesses 716system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015272 # mshr miss rate for WriteReq accesses 717system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729568 # mshr miss rate for SoftPFReq accesses 718system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729568 # mshr miss rate for SoftPFReq accesses 719system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786614 # mshr miss rate for WriteLineReq accesses 720system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786614 # mshr miss rate for WriteLineReq accesses 721system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057346 # mshr miss rate for LoadLockedReq accesses 722system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057346 # mshr miss rate for LoadLockedReq accesses 723system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 724system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 725system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024607 # mshr miss rate for demand accesses 726system.cpu.dcache.demand_mshr_miss_rate::total 0.024607 # mshr miss rate for demand accesses 727system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028782 # mshr miss rate for overall accesses 728system.cpu.dcache.overall_mshr_miss_rate::total 0.028782 # mshr miss rate for overall accesses 729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17266.319398 # average ReadReq mshr miss latency 730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17266.319398 # average ReadReq mshr miss latency 731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46840.819004 # average WriteReq mshr miss latency 732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46840.819004 # average WriteReq mshr miss latency 733system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18942.857608 # average SoftPFReq mshr miss latency 734system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18942.857608 # average SoftPFReq mshr miss latency 735system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42055.915161 # average WriteLineReq mshr miss latency 736system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42055.915161 # average WriteLineReq mshr miss latency 737system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14547.508559 # average LoadLockedReq mshr miss latency 738system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14547.508559 # average LoadLockedReq mshr miss latency 739system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80833.333333 # average StoreCondReq mshr miss latency 740system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80833.333333 # average StoreCondReq mshr miss latency 741system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25913.751013 # average overall mshr miss latency 742system.cpu.dcache.demand_avg_mshr_miss_latency::total 25913.751013 # average overall mshr miss latency 743system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24867.136136 # average overall mshr miss latency 744system.cpu.dcache.overall_avg_mshr_miss_latency::total 24867.136136 # average overall mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183914.502775 # average ReadReq mshr uncacheable latency 746system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183914.502775 # average ReadReq mshr uncacheable latency 747system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.145137 # average WriteReq mshr uncacheable latency 748system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.145137 # average WriteReq mshr uncacheable latency 749system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.340890 # average overall mshr uncacheable latency 750system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.340890 # average overall mshr uncacheable latency 751system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 752system.cpu.icache.tags.replacements 24282731 # number of replacements 753system.cpu.icache.tags.tagsinuse 511.885324 # Cycle average of tags in use 754system.cpu.icache.tags.total_refs 418496927 # Total number of references to valid blocks. 755system.cpu.icache.tags.sampled_refs 24283243 # Sample count of references to valid blocks. 756system.cpu.icache.tags.avg_refs 17.233980 # Average number of references to valid blocks. 757system.cpu.icache.tags.warmup_cycle 32778398500 # Cycle when the warmup percentage was hit. 758system.cpu.icache.tags.occ_blocks::cpu.inst 511.885324 # Average occupied blocks per requestor 759system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 760system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 761system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 762system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 763system.cpu.icache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 764system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 765system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 766system.cpu.icache.tags.tag_accesses 467063432 # Number of tag accesses 767system.cpu.icache.tags.data_accesses 467063432 # Number of data accesses 768system.cpu.icache.ReadReq_hits::cpu.inst 418496927 # number of ReadReq hits 769system.cpu.icache.ReadReq_hits::total 418496927 # number of ReadReq hits 770system.cpu.icache.demand_hits::cpu.inst 418496927 # number of demand (read+write) hits 771system.cpu.icache.demand_hits::total 418496927 # number of demand (read+write) hits 772system.cpu.icache.overall_hits::cpu.inst 418496927 # number of overall hits 773system.cpu.icache.overall_hits::total 418496927 # number of overall hits 774system.cpu.icache.ReadReq_misses::cpu.inst 24283253 # number of ReadReq misses 775system.cpu.icache.ReadReq_misses::total 24283253 # number of ReadReq misses 776system.cpu.icache.demand_misses::cpu.inst 24283253 # number of demand (read+write) misses 777system.cpu.icache.demand_misses::total 24283253 # number of demand (read+write) misses 778system.cpu.icache.overall_misses::cpu.inst 24283253 # number of overall misses 779system.cpu.icache.overall_misses::total 24283253 # number of overall misses 780system.cpu.icache.ReadReq_miss_latency::cpu.inst 329126236000 # number of ReadReq miss cycles 781system.cpu.icache.ReadReq_miss_latency::total 329126236000 # number of ReadReq miss cycles 782system.cpu.icache.demand_miss_latency::cpu.inst 329126236000 # number of demand (read+write) miss cycles 783system.cpu.icache.demand_miss_latency::total 329126236000 # number of demand (read+write) miss cycles 784system.cpu.icache.overall_miss_latency::cpu.inst 329126236000 # number of overall miss cycles 785system.cpu.icache.overall_miss_latency::total 329126236000 # number of overall miss cycles 786system.cpu.icache.ReadReq_accesses::cpu.inst 442780180 # number of ReadReq accesses(hits+misses) 787system.cpu.icache.ReadReq_accesses::total 442780180 # number of ReadReq accesses(hits+misses) 788system.cpu.icache.demand_accesses::cpu.inst 442780180 # number of demand (read+write) accesses 789system.cpu.icache.demand_accesses::total 442780180 # number of demand (read+write) accesses 790system.cpu.icache.overall_accesses::cpu.inst 442780180 # number of overall (read+write) accesses 791system.cpu.icache.overall_accesses::total 442780180 # number of overall (read+write) accesses 792system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054843 # miss rate for ReadReq accesses 793system.cpu.icache.ReadReq_miss_rate::total 0.054843 # miss rate for ReadReq accesses 794system.cpu.icache.demand_miss_rate::cpu.inst 0.054843 # miss rate for demand accesses 795system.cpu.icache.demand_miss_rate::total 0.054843 # miss rate for demand accesses 796system.cpu.icache.overall_miss_rate::cpu.inst 0.054843 # miss rate for overall accesses 797system.cpu.icache.overall_miss_rate::total 0.054843 # miss rate for overall accesses 798system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.630397 # average ReadReq miss latency 799system.cpu.icache.ReadReq_avg_miss_latency::total 13553.630397 # average ReadReq miss latency 800system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.630397 # average overall miss latency 801system.cpu.icache.demand_avg_miss_latency::total 13553.630397 # average overall miss latency 802system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.630397 # average overall miss latency 803system.cpu.icache.overall_avg_miss_latency::total 13553.630397 # average overall miss latency 804system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 805system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 807system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 809system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu.icache.fast_writes 0 # number of fast writes performed 811system.cpu.icache.cache_copies 0 # number of cache copies performed 812system.cpu.icache.writebacks::writebacks 24282731 # number of writebacks 813system.cpu.icache.writebacks::total 24282731 # number of writebacks 814system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24283253 # number of ReadReq MSHR misses 815system.cpu.icache.ReadReq_mshr_misses::total 24283253 # number of ReadReq MSHR misses 816system.cpu.icache.demand_mshr_misses::cpu.inst 24283253 # number of demand (read+write) MSHR misses 817system.cpu.icache.demand_mshr_misses::total 24283253 # number of demand (read+write) MSHR misses 818system.cpu.icache.overall_mshr_misses::cpu.inst 24283253 # number of overall MSHR misses 819system.cpu.icache.overall_mshr_misses::total 24283253 # number of overall MSHR misses 820system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 821system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 822system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 823system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 824system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304842984000 # number of ReadReq MSHR miss cycles 825system.cpu.icache.ReadReq_mshr_miss_latency::total 304842984000 # number of ReadReq MSHR miss cycles 826system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304842984000 # number of demand (read+write) MSHR miss cycles 827system.cpu.icache.demand_mshr_miss_latency::total 304842984000 # number of demand (read+write) MSHR miss cycles 828system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304842984000 # number of overall MSHR miss cycles 829system.cpu.icache.overall_mshr_miss_latency::total 304842984000 # number of overall MSHR miss cycles 830system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 831system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 832system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 833system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 834system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for ReadReq accesses 835system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054843 # mshr miss rate for ReadReq accesses 836system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for demand accesses 837system.cpu.icache.demand_mshr_miss_rate::total 0.054843 # mshr miss rate for demand accesses 838system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for overall accesses 839system.cpu.icache.overall_mshr_miss_rate::total 0.054843 # mshr miss rate for overall accesses 840system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.630438 # average ReadReq mshr miss latency 841system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.630438 # average ReadReq mshr miss latency 842system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.630438 # average overall mshr miss latency 843system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.630438 # average overall mshr miss latency 844system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.630438 # average overall mshr miss latency 845system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.630438 # average overall mshr miss latency 846system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 847system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 848system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 849system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 850system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 851system.cpu.l2cache.tags.replacements 1528241 # number of replacements 852system.cpu.l2cache.tags.tagsinuse 65327.330583 # Cycle average of tags in use 853system.cpu.l2cache.tags.total_refs 66279197 # Total number of references to valid blocks. 854system.cpu.l2cache.tags.sampled_refs 1591645 # Sample count of references to valid blocks. 855system.cpu.l2cache.tags.avg_refs 41.641947 # Average number of references to valid blocks. 856system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 857system.cpu.l2cache.tags.occ_blocks::writebacks 36821.900434 # Average occupied blocks per requestor 858system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 322.022869 # Average occupied blocks per requestor 859system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 395.139834 # Average occupied blocks per requestor 860system.cpu.l2cache.tags.occ_blocks::cpu.inst 8029.956207 # Average occupied blocks per requestor 861system.cpu.l2cache.tags.occ_blocks::cpu.data 19758.311238 # Average occupied blocks per requestor 862system.cpu.l2cache.tags.occ_percent::writebacks 0.561858 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004914 # Average percentage of cache occupancy 864system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006029 # Average percentage of cache occupancy 865system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122527 # Average percentage of cache occupancy 866system.cpu.l2cache.tags.occ_percent::cpu.data 0.301488 # Average percentage of cache occupancy 867system.cpu.l2cache.tags.occ_percent::total 0.996816 # Average percentage of cache occupancy 868system.cpu.l2cache.tags.occ_task_id_blocks::1023 229 # Occupied blocks per task id 869system.cpu.l2cache.tags.occ_task_id_blocks::1024 63175 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 872system.cpu.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id 873system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2412 # Occupied blocks per task id 874system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id 875system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54751 # Occupied blocks per task id 876system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003494 # Percentage of cache occupancy per task id 877system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963974 # Percentage of cache occupancy per task id 878system.cpu.l2cache.tags.tag_accesses 576746891 # Number of tag accesses 879system.cpu.l2cache.tags.data_accesses 576746891 # Number of data accesses 880system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 934890 # number of ReadReq hits 881system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 285217 # number of ReadReq hits 882system.cpu.l2cache.ReadReq_hits::total 1220107 # number of ReadReq hits 883system.cpu.l2cache.WritebackDirty_hits::writebacks 8326510 # number of WritebackDirty hits 884system.cpu.l2cache.WritebackDirty_hits::total 8326510 # number of WritebackDirty hits 885system.cpu.l2cache.WritebackClean_hits::writebacks 24279004 # number of WritebackClean hits 886system.cpu.l2cache.WritebackClean_hits::total 24279004 # number of WritebackClean hits 887system.cpu.l2cache.UpgradeReq_hits::cpu.data 10570 # number of UpgradeReq hits 888system.cpu.l2cache.UpgradeReq_hits::total 10570 # number of UpgradeReq hits 889system.cpu.l2cache.ReadExReq_hits::cpu.data 1643650 # number of ReadExReq hits 890system.cpu.l2cache.ReadExReq_hits::total 1643650 # number of ReadExReq hits 891system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24174985 # number of ReadCleanReq hits 892system.cpu.l2cache.ReadCleanReq_hits::total 24174985 # number of ReadCleanReq hits 893system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6987496 # number of ReadSharedReq hits 894system.cpu.l2cache.ReadSharedReq_hits::total 6987496 # number of ReadSharedReq hits 895system.cpu.l2cache.InvalidateReq_hits::cpu.data 703999 # number of InvalidateReq hits 896system.cpu.l2cache.InvalidateReq_hits::total 703999 # number of InvalidateReq hits 897system.cpu.l2cache.demand_hits::cpu.dtb.walker 934890 # number of demand (read+write) hits 898system.cpu.l2cache.demand_hits::cpu.itb.walker 285217 # number of demand (read+write) hits 899system.cpu.l2cache.demand_hits::cpu.inst 24174985 # number of demand (read+write) hits 900system.cpu.l2cache.demand_hits::cpu.data 8631146 # number of demand (read+write) hits 901system.cpu.l2cache.demand_hits::total 34026238 # number of demand (read+write) hits 902system.cpu.l2cache.overall_hits::cpu.dtb.walker 934890 # number of overall hits 903system.cpu.l2cache.overall_hits::cpu.itb.walker 285217 # number of overall hits 904system.cpu.l2cache.overall_hits::cpu.inst 24174985 # number of overall hits 905system.cpu.l2cache.overall_hits::cpu.data 8631146 # number of overall hits 906system.cpu.l2cache.overall_hits::total 34026238 # number of overall hits 907system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5895 # number of ReadReq misses 908system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5000 # number of ReadReq misses 909system.cpu.l2cache.ReadReq_misses::total 10895 # number of ReadReq misses 910system.cpu.l2cache.UpgradeReq_misses::cpu.data 37884 # number of UpgradeReq misses 911system.cpu.l2cache.UpgradeReq_misses::total 37884 # number of UpgradeReq misses 912system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 913system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 914system.cpu.l2cache.ReadExReq_misses::cpu.data 644745 # number of ReadExReq misses 915system.cpu.l2cache.ReadExReq_misses::total 644745 # number of ReadExReq misses 916system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 108265 # number of ReadCleanReq misses 917system.cpu.l2cache.ReadCleanReq_misses::total 108265 # number of ReadCleanReq misses 918system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320328 # number of ReadSharedReq misses 919system.cpu.l2cache.ReadSharedReq_misses::total 320328 # number of ReadSharedReq misses 920system.cpu.l2cache.InvalidateReq_misses::cpu.data 536094 # number of InvalidateReq misses 921system.cpu.l2cache.InvalidateReq_misses::total 536094 # number of InvalidateReq misses 922system.cpu.l2cache.demand_misses::cpu.dtb.walker 5895 # number of demand (read+write) misses 923system.cpu.l2cache.demand_misses::cpu.itb.walker 5000 # number of demand (read+write) misses 924system.cpu.l2cache.demand_misses::cpu.inst 108265 # number of demand (read+write) misses 925system.cpu.l2cache.demand_misses::cpu.data 965073 # number of demand (read+write) misses 926system.cpu.l2cache.demand_misses::total 1084233 # number of demand (read+write) misses 927system.cpu.l2cache.overall_misses::cpu.dtb.walker 5895 # number of overall misses 928system.cpu.l2cache.overall_misses::cpu.itb.walker 5000 # number of overall misses 929system.cpu.l2cache.overall_misses::cpu.inst 108265 # number of overall misses 930system.cpu.l2cache.overall_misses::cpu.data 965073 # number of overall misses 931system.cpu.l2cache.overall_misses::total 1084233 # number of overall misses 932system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 809439000 # number of ReadReq miss cycles 933system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 684634500 # number of ReadReq miss cycles 934system.cpu.l2cache.ReadReq_miss_latency::total 1494073500 # number of ReadReq miss cycles 935system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1447800500 # number of UpgradeReq miss cycles 936system.cpu.l2cache.UpgradeReq_miss_latency::total 1447800500 # number of UpgradeReq miss cycles 937system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 238000 # number of SCUpgradeReq miss cycles 938system.cpu.l2cache.SCUpgradeReq_miss_latency::total 238000 # number of SCUpgradeReq miss cycles 939system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85591105500 # number of ReadExReq miss cycles 940system.cpu.l2cache.ReadExReq_miss_latency::total 85591105500 # number of ReadExReq miss cycles 941system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14347099000 # number of ReadCleanReq miss cycles 942system.cpu.l2cache.ReadCleanReq_miss_latency::total 14347099000 # number of ReadCleanReq miss cycles 943system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43249450500 # number of ReadSharedReq miss cycles 944system.cpu.l2cache.ReadSharedReq_miss_latency::total 43249450500 # number of ReadSharedReq miss cycles 945system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 14977000 # number of InvalidateReq miss cycles 946system.cpu.l2cache.InvalidateReq_miss_latency::total 14977000 # number of InvalidateReq miss cycles 947system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 809439000 # number of demand (read+write) miss cycles 948system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 684634500 # number of demand (read+write) miss cycles 949system.cpu.l2cache.demand_miss_latency::cpu.inst 14347099000 # number of demand (read+write) miss cycles 950system.cpu.l2cache.demand_miss_latency::cpu.data 128840556000 # number of demand (read+write) miss cycles 951system.cpu.l2cache.demand_miss_latency::total 144681728500 # number of demand (read+write) miss cycles 952system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 809439000 # number of overall miss cycles 953system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 684634500 # number of overall miss cycles 954system.cpu.l2cache.overall_miss_latency::cpu.inst 14347099000 # number of overall miss cycles 955system.cpu.l2cache.overall_miss_latency::cpu.data 128840556000 # number of overall miss cycles 956system.cpu.l2cache.overall_miss_latency::total 144681728500 # number of overall miss cycles 957system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 940785 # number of ReadReq accesses(hits+misses) 958system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 290217 # number of ReadReq accesses(hits+misses) 959system.cpu.l2cache.ReadReq_accesses::total 1231002 # number of ReadReq accesses(hits+misses) 960system.cpu.l2cache.WritebackDirty_accesses::writebacks 8326510 # number of WritebackDirty accesses(hits+misses) 961system.cpu.l2cache.WritebackDirty_accesses::total 8326510 # number of WritebackDirty accesses(hits+misses) 962system.cpu.l2cache.WritebackClean_accesses::writebacks 24279004 # number of WritebackClean accesses(hits+misses) 963system.cpu.l2cache.WritebackClean_accesses::total 24279004 # number of WritebackClean accesses(hits+misses) 964system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48454 # number of UpgradeReq accesses(hits+misses) 965system.cpu.l2cache.UpgradeReq_accesses::total 48454 # number of UpgradeReq accesses(hits+misses) 966system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) 967system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) 968system.cpu.l2cache.ReadExReq_accesses::cpu.data 2288395 # number of ReadExReq accesses(hits+misses) 969system.cpu.l2cache.ReadExReq_accesses::total 2288395 # number of ReadExReq accesses(hits+misses) 970system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24283250 # number of ReadCleanReq accesses(hits+misses) 971system.cpu.l2cache.ReadCleanReq_accesses::total 24283250 # number of ReadCleanReq accesses(hits+misses) 972system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7307824 # number of ReadSharedReq accesses(hits+misses) 973system.cpu.l2cache.ReadSharedReq_accesses::total 7307824 # number of ReadSharedReq accesses(hits+misses) 974system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1240093 # number of InvalidateReq accesses(hits+misses) 975system.cpu.l2cache.InvalidateReq_accesses::total 1240093 # number of InvalidateReq accesses(hits+misses) 976system.cpu.l2cache.demand_accesses::cpu.dtb.walker 940785 # number of demand (read+write) accesses 977system.cpu.l2cache.demand_accesses::cpu.itb.walker 290217 # number of demand (read+write) accesses 978system.cpu.l2cache.demand_accesses::cpu.inst 24283250 # number of demand (read+write) accesses 979system.cpu.l2cache.demand_accesses::cpu.data 9596219 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::total 35110471 # number of demand (read+write) accesses 981system.cpu.l2cache.overall_accesses::cpu.dtb.walker 940785 # number of overall (read+write) accesses 982system.cpu.l2cache.overall_accesses::cpu.itb.walker 290217 # number of overall (read+write) accesses 983system.cpu.l2cache.overall_accesses::cpu.inst 24283250 # number of overall (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.data 9596219 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::total 35110471 # number of overall (read+write) accesses 986system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006266 # miss rate for ReadReq accesses 987system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017228 # miss rate for ReadReq accesses 988system.cpu.l2cache.ReadReq_miss_rate::total 0.008851 # miss rate for ReadReq accesses 989system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781855 # miss rate for UpgradeReq accesses 990system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781855 # miss rate for UpgradeReq accesses 991system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 992system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 993system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.281746 # miss rate for ReadExReq accesses 994system.cpu.l2cache.ReadExReq_miss_rate::total 0.281746 # miss rate for ReadExReq accesses 995system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004458 # miss rate for ReadCleanReq accesses 996system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004458 # miss rate for ReadCleanReq accesses 997system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043834 # miss rate for ReadSharedReq accesses 998system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043834 # miss rate for ReadSharedReq accesses 999system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.432301 # miss rate for InvalidateReq accesses 1000system.cpu.l2cache.InvalidateReq_miss_rate::total 0.432301 # miss rate for InvalidateReq accesses 1001system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006266 # miss rate for demand accesses 1002system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017228 # miss rate for demand accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004458 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.data 0.100568 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::total 0.030881 # miss rate for demand accesses 1006system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006266 # miss rate for overall accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017228 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004458 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.data 0.100568 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::total 0.030881 # miss rate for overall accesses 1011system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137309.414758 # average ReadReq miss latency 1012system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136926.900000 # average ReadReq miss latency 1013system.cpu.l2cache.ReadReq_avg_miss_latency::total 137133.868747 # average ReadReq miss latency 1014system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38216.674586 # average UpgradeReq miss latency 1015system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38216.674586 # average UpgradeReq miss latency 1016system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79333.333333 # average SCUpgradeReq miss latency 1017system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79333.333333 # average SCUpgradeReq miss latency 1018system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132751.871670 # average ReadExReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132751.871670 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132518.348497 # average ReadCleanReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132518.348497 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135016.141268 # average ReadSharedReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135016.141268 # average ReadSharedReq miss latency 1024system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 27.937265 # average InvalidateReq miss latency 1025system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 27.937265 # average InvalidateReq miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137309.414758 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136926.900000 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132518.348497 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133503.430310 # average overall miss latency 1030system.cpu.l2cache.demand_avg_miss_latency::total 133441.546697 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137309.414758 # average overall miss latency 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136926.900000 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132518.348497 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133503.430310 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::total 133441.546697 # average overall miss latency 1036system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1040system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1041system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1042system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1043system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1044system.cpu.l2cache.writebacks::writebacks 1293229 # number of writebacks 1045system.cpu.l2cache.writebacks::total 1293229 # number of writebacks 1046system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1047system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1048system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1049system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1050system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1051system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1054system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1056system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5895 # number of ReadReq MSHR misses 1057system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5000 # number of ReadReq MSHR misses 1058system.cpu.l2cache.ReadReq_mshr_misses::total 10895 # number of ReadReq MSHR misses 1059system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1060system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1061system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37884 # number of UpgradeReq MSHR misses 1062system.cpu.l2cache.UpgradeReq_mshr_misses::total 37884 # number of UpgradeReq MSHR misses 1063system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1064system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1065system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 644745 # number of ReadExReq MSHR misses 1066system.cpu.l2cache.ReadExReq_mshr_misses::total 644745 # number of ReadExReq MSHR misses 1067system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 108262 # number of ReadCleanReq MSHR misses 1068system.cpu.l2cache.ReadCleanReq_mshr_misses::total 108262 # number of ReadCleanReq MSHR misses 1069system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320307 # number of ReadSharedReq MSHR misses 1070system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320307 # number of ReadSharedReq MSHR misses 1071system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 536094 # number of InvalidateReq MSHR misses 1072system.cpu.l2cache.InvalidateReq_mshr_misses::total 536094 # number of InvalidateReq MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5895 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5000 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::cpu.inst 108262 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.demand_mshr_misses::cpu.data 965052 # number of demand (read+write) MSHR misses 1077system.cpu.l2cache.demand_mshr_misses::total 1084209 # number of demand (read+write) MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5895 # number of overall MSHR misses 1079system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5000 # number of overall MSHR misses 1080system.cpu.l2cache.overall_mshr_misses::cpu.inst 108262 # number of overall MSHR misses 1081system.cpu.l2cache.overall_mshr_misses::cpu.data 965052 # number of overall MSHR misses 1082system.cpu.l2cache.overall_mshr_misses::total 1084209 # number of overall MSHR misses 1083system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1084system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1085system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1086system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1087system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1088system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1089system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1090system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses 1091system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 750489000 # number of ReadReq MSHR miss cycles 1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 634634500 # number of ReadReq MSHR miss cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1385123500 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2576694000 # number of UpgradeReq MSHR miss cycles 1095system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2576694000 # number of UpgradeReq MSHR miss cycles 1096system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 208000 # number of SCUpgradeReq MSHR miss cycles 1097system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 208000 # number of SCUpgradeReq MSHR miss cycles 1098system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79143640031 # number of ReadExReq MSHR miss cycles 1099system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79143640031 # number of ReadExReq MSHR miss cycles 1100system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13264181071 # number of ReadCleanReq MSHR miss cycles 1101system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13264181071 # number of ReadCleanReq MSHR miss cycles 1102system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40044031927 # number of ReadSharedReq MSHR miss cycles 1103system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40044031927 # number of ReadSharedReq MSHR miss cycles 1104system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 37345893500 # number of InvalidateReq MSHR miss cycles 1105system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37345893500 # number of InvalidateReq MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 750489000 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 634634500 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13264181071 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119187671958 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::total 133836976529 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 750489000 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 634634500 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13264181071 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119187671958 # number of overall MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::total 133836976529 # number of overall MSHR miss cycles 1116system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1117system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776092000 # number of ReadReq MSHR uncacheable cycles 1118system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712166000 # number of ReadReq MSHR uncacheable cycles 1119system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819357000 # number of WriteReq MSHR uncacheable cycles 1120system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819357000 # number of WriteReq MSHR uncacheable cycles 1121system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles 1122system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595449000 # number of overall MSHR uncacheable cycles 1123system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531523000 # number of overall MSHR uncacheable cycles 1124system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for ReadReq accesses 1125system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for ReadReq accesses 1126system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008851 # mshr miss rate for ReadReq accesses 1127system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1128system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1129system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781855 # mshr miss rate for UpgradeReq accesses 1130system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781855 # mshr miss rate for UpgradeReq accesses 1131system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1132system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1133system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281746 # mshr miss rate for ReadExReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281746 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for ReadCleanReq accesses 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004458 # mshr miss rate for ReadCleanReq accesses 1137system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043831 # mshr miss rate for ReadSharedReq accesses 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043831 # mshr miss rate for ReadSharedReq accesses 1139system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.432301 # mshr miss rate for InvalidateReq accesses 1140system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.432301 # mshr miss rate for InvalidateReq accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::total 0.030880 # mshr miss rate for demand accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::total 0.030880 # mshr miss rate for overall accesses 1151system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average ReadReq mshr miss latency 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average ReadReq mshr miss latency 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127133.868747 # average ReadReq mshr miss latency 1154system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68015.362686 # average UpgradeReq mshr miss latency 1155system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68015.362686 # average UpgradeReq mshr miss latency 1156system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69333.333333 # average SCUpgradeReq mshr miss latency 1157system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69333.333333 # average SCUpgradeReq mshr miss latency 1158system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122751.847678 # average ReadExReq mshr miss latency 1159system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122751.847678 # average ReadExReq mshr miss latency 1160system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122519.268728 # average ReadCleanReq mshr miss latency 1161system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122519.268728 # average ReadCleanReq mshr miss latency 1162system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125017.660953 # average ReadSharedReq mshr miss latency 1163system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125017.660953 # average ReadSharedReq mshr miss latency 1164system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429 # average InvalidateReq mshr miss latency 1165system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429 # average InvalidateReq mshr miss latency 1166system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency 1167system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency 1168system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency 1169system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency 1170system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency 1171system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency 1172system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency 1173system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency 1174system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency 1176system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1177system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010 # average ReadReq mshr uncacheable latency 1178system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920 # average ReadReq mshr uncacheable latency 1179system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660 # average WriteReq mshr uncacheable latency 1180system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660 # average WriteReq mshr uncacheable latency 1181system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency 1182system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476 # average overall mshr uncacheable latency 1183system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998 # average overall mshr uncacheable latency 1184system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1185system.cpu.toL2Bus.snoop_filter.tot_requests 70987580 # Total number of requests made to the snoop filter. 1186system.cpu.toL2Bus.snoop_filter.hit_single_requests 35868028 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1187system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4400 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1188system.cpu.toL2Bus.snoop_filter.tot_snoops 2259 # Total number of snoops made to the snoop filter. 1189system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1190system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1191system.cpu.toL2Bus.trans_dist::ReadReq 1747427 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadResp 33339280 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::WritebackDirty 9726418 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::WritebackClean 24282731 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::CleanEvict 2753122 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::UpgradeReq 48457 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::UpgradeResp 48460 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::ReadExReq 2288395 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::ReadExResp 2288395 # Transaction distribution 1203system.cpu.toL2Bus.trans_dist::ReadCleanReq 24283253 # Transaction distribution 1204system.cpu.toL2Bus.trans_dist::ReadSharedReq 7316706 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::InvalidateReq 1346757 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::InvalidateResp 1240093 # Transaction distribution 1207system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953851 # Packet count per connected master and slave (bytes) 1208system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32740884 # Packet count per connected master and slave (bytes) 1209system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695726 # Packet count per connected master and slave (bytes) 1210system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2196697 # Packet count per connected master and slave (bytes) 1211system.cpu.toL2Bus.pkt_count::total 108587158 # Packet count per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3111570496 # Cumulative packet size per connected master and slave (bytes) 1213system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1147294802 # Cumulative packet size per connected master and slave (bytes) 1214system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2321736 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7526280 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_size::total 4268713314 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu.toL2Bus.snoops 2190531 # Total snoops (count) 1218system.cpu.toL2Bus.snoop_fanout::samples 38708484 # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::mean 0.018284 # Request fanout histogram 1220system.cpu.toL2Bus.snoop_fanout::stdev 0.133976 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::0 38000745 98.17% 98.17% # Request fanout histogram 1223system.cpu.toL2Bus.snoop_fanout::1 707739 1.83% 100.00% # Request fanout histogram 1224system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1226system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1227system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::total 38708484 # Request fanout histogram 1229system.cpu.toL2Bus.reqLayer0.occupancy 68659919994 # Layer occupancy (ticks) 1230system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1231system.cpu.toL2Bus.snoopLayer0.occupancy 1469394 # Layer occupancy (ticks) 1232system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1233system.cpu.toL2Bus.respLayer0.occupancy 36510728693 # Layer occupancy (ticks) 1234system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1235system.cpu.toL2Bus.respLayer1.occupancy 15090009225 # Layer occupancy (ticks) 1236system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1237system.cpu.toL2Bus.respLayer2.occupancy 405546924 # Layer occupancy (ticks) 1238system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1239system.cpu.toL2Bus.respLayer3.occupancy 1255965393 # Layer occupancy (ticks) 1240system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1241system.iobus.trans_dist::ReadReq 40330 # Transaction distribution 1242system.iobus.trans_dist::ReadResp 40330 # Transaction distribution 1243system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1244system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1245system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1255system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1257system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1258system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1259system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231018 # Packet count per connected master and slave (bytes) 1260system.iobus.pkt_count_system.realview.ide.dma::total 231018 # Packet count per connected master and slave (bytes) 1261system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1262system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1263system.iobus.pkt_count::total 353802 # Packet count per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1278system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334504 # Cumulative packet size per connected master and slave (bytes) 1279system.iobus.pkt_size_system.realview.ide.dma::total 7334504 # Cumulative packet size per connected master and slave (bytes) 1280system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1281system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1282system.iobus.pkt_size::total 7492424 # Cumulative packet size per connected master and slave (bytes) 1283system.iobus.reqLayer0.occupancy 42214500 # Layer occupancy (ticks) 1284system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1285system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1286system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks) 1288system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1289system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1290system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1291system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1292system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 1294system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 1296system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1298system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1300system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1301system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) 1302system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1303system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1304system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1305system.iobus.reqLayer23.occupancy 25698500 # Layer occupancy (ticks) 1306system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1307system.iobus.reqLayer24.occupancy 34147500 # Layer occupancy (ticks) 1308system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1309system.iobus.reqLayer25.occupancy 566993946 # Layer occupancy (ticks) 1310system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1311system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1312system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1313system.iobus.respLayer3.occupancy 147778000 # Layer occupancy (ticks) 1314system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1315system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1316system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1317system.iocache.tags.replacements 115490 # number of replacements 1318system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use 1319system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1320system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. 1321system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1322system.iocache.tags.warmup_cycle 13153331095000 # Cycle when the warmup percentage was hit. 1323system.iocache.tags.occ_blocks::realview.ethernet 3.521304 # Average occupied blocks per requestor 1324system.iocache.tags.occ_blocks::realview.ide 6.919950 # Average occupied blocks per requestor 1325system.iocache.tags.occ_percent::realview.ethernet 0.220081 # Average percentage of cache occupancy 1326system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy 1327system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy 1328system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1329system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1330system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1331system.iocache.tags.tag_accesses 1039938 # Number of tag accesses 1332system.iocache.tags.data_accesses 1039938 # Number of data accesses 1333system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1334system.iocache.ReadReq_misses::realview.ide 8845 # number of ReadReq misses 1335system.iocache.ReadReq_misses::total 8882 # number of ReadReq misses 1336system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1337system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1338system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1339system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1340system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1341system.iocache.demand_misses::realview.ide 8845 # number of demand (read+write) misses 1342system.iocache.demand_misses::total 8885 # number of demand (read+write) misses 1343system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1344system.iocache.overall_misses::realview.ide 8845 # number of overall misses 1345system.iocache.overall_misses::total 8885 # number of overall misses 1346system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 1347system.iocache.ReadReq_miss_latency::realview.ide 1624796190 # number of ReadReq miss cycles 1348system.iocache.ReadReq_miss_latency::total 1629882190 # number of ReadReq miss cycles 1349system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1350system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1351system.iocache.WriteLineReq_miss_latency::realview.ide 13412464756 # number of WriteLineReq miss cycles 1352system.iocache.WriteLineReq_miss_latency::total 13412464756 # number of WriteLineReq miss cycles 1353system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 1354system.iocache.demand_miss_latency::realview.ide 1624796190 # number of demand (read+write) miss cycles 1355system.iocache.demand_miss_latency::total 1630233190 # number of demand (read+write) miss cycles 1356system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 1357system.iocache.overall_miss_latency::realview.ide 1624796190 # number of overall miss cycles 1358system.iocache.overall_miss_latency::total 1630233190 # number of overall miss cycles 1359system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1360system.iocache.ReadReq_accesses::realview.ide 8845 # number of ReadReq accesses(hits+misses) 1361system.iocache.ReadReq_accesses::total 8882 # number of ReadReq accesses(hits+misses) 1362system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1363system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1364system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1365system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1366system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1367system.iocache.demand_accesses::realview.ide 8845 # number of demand (read+write) accesses 1368system.iocache.demand_accesses::total 8885 # number of demand (read+write) accesses 1369system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1370system.iocache.overall_accesses::realview.ide 8845 # number of overall (read+write) accesses 1371system.iocache.overall_accesses::total 8885 # number of overall (read+write) accesses 1372system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1373system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1374system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1375system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1376system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1377system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1378system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1379system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1380system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1381system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1382system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1383system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1384system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1385system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 1386system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205 # average ReadReq miss latency 1387system.iocache.ReadReq_avg_miss_latency::total 183503.961946 # average ReadReq miss latency 1388system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1389system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1390system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713 # average WriteLineReq miss latency 1391system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713 # average WriteLineReq miss latency 1392system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1393system.iocache.demand_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency 1394system.iocache.demand_avg_miss_latency::total 183481.507034 # average overall miss latency 1395system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1396system.iocache.overall_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency 1397system.iocache.overall_avg_miss_latency::total 183481.507034 # average overall miss latency 1398system.iocache.blocked_cycles::no_mshrs 31904 # number of cycles access was blocked 1399system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1400system.iocache.blocked::no_mshrs 3290 # number of cycles access was blocked 1401system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1402system.iocache.avg_blocked_cycles::no_mshrs 9.697264 # average number of cycles each access was blocked 1403system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1404system.iocache.fast_writes 0 # number of fast writes performed 1405system.iocache.cache_copies 0 # number of cache copies performed 1406system.iocache.writebacks::writebacks 106630 # number of writebacks 1407system.iocache.writebacks::total 106630 # number of writebacks 1408system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1409system.iocache.ReadReq_mshr_misses::realview.ide 8845 # number of ReadReq MSHR misses 1410system.iocache.ReadReq_mshr_misses::total 8882 # number of ReadReq MSHR misses 1411system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1412system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1413system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1414system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1415system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1416system.iocache.demand_mshr_misses::realview.ide 8845 # number of demand (read+write) MSHR misses 1417system.iocache.demand_mshr_misses::total 8885 # number of demand (read+write) MSHR misses 1418system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1419system.iocache.overall_mshr_misses::realview.ide 8845 # number of overall MSHR misses 1420system.iocache.overall_mshr_misses::total 8885 # number of overall MSHR misses 1421system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 1422system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182546190 # number of ReadReq MSHR miss cycles 1423system.iocache.ReadReq_mshr_miss_latency::total 1185782190 # number of ReadReq MSHR miss cycles 1424system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1425system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1426system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8074127324 # number of WriteLineReq MSHR miss cycles 1427system.iocache.WriteLineReq_mshr_miss_latency::total 8074127324 # number of WriteLineReq MSHR miss cycles 1428system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 1429system.iocache.demand_mshr_miss_latency::realview.ide 1182546190 # number of demand (read+write) MSHR miss cycles 1430system.iocache.demand_mshr_miss_latency::total 1185983190 # number of demand (read+write) MSHR miss cycles 1431system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 1432system.iocache.overall_mshr_miss_latency::realview.ide 1182546190 # number of overall MSHR miss cycles 1433system.iocache.overall_mshr_miss_latency::total 1185983190 # number of overall MSHR miss cycles 1434system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1435system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1436system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1437system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1438system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1439system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1440system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1441system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1442system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1443system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1444system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1445system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1447system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 1448system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205 # average ReadReq mshr miss latency 1449system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946 # average ReadReq mshr miss latency 1450system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1451system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1452system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083 # average WriteLineReq mshr miss latency 1453system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083 # average WriteLineReq mshr miss latency 1454system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1455system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency 1456system.iocache.demand_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency 1457system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1458system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency 1459system.iocache.overall_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency 1460system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1461system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1462system.membus.trans_dist::ReadResp 534352 # Transaction distribution 1463system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1464system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1465system.membus.trans_dist::WritebackDirty 1399859 # Transaction distribution 1466system.membus.trans_dist::CleanEvict 242769 # Transaction distribution 1467system.membus.trans_dist::UpgradeReq 38707 # Transaction distribution 1468system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1469system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1470system.membus.trans_dist::ReadExReq 644117 # Transaction distribution 1471system.membus.trans_dist::ReadExResp 644117 # Transaction distribution 1472system.membus.trans_dist::ReadSharedReq 448346 # Transaction distribution 1473system.membus.trans_dist::InvalidateReq 642566 # Transaction distribution 1474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1477system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4378022 # Packet count per connected master and slave (bytes) 1478system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4507674 # Packet count per connected master and slave (bytes) 1479system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237045 # Packet count per connected master and slave (bytes) 1480system.membus.pkt_count_system.iocache.mem_side::total 237045 # Packet count per connected master and slave (bytes) 1481system.membus.pkt_count::total 4744719 # Packet count per connected master and slave (bytes) 1482system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1485system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155441452 # Cumulative packet size per connected master and slave (bytes) 1486system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155611858 # Cumulative packet size per connected master and slave (bytes) 1487system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7208704 # Cumulative packet size per connected master and slave (bytes) 1488system.membus.pkt_size_system.iocache.mem_side::total 7208704 # Cumulative packet size per connected master and slave (bytes) 1489system.membus.pkt_size::total 162820562 # Cumulative packet size per connected master and slave (bytes) 1490system.membus.snoops 3543 # Total snoops (count) 1491system.membus.snoop_fanout::samples 3536130 # Request fanout histogram 1492system.membus.snoop_fanout::mean 1 # Request fanout histogram 1493system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1494system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1495system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1496system.membus.snoop_fanout::1 3536130 100.00% 100.00% # Request fanout histogram 1497system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1498system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1499system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1500system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1501system.membus.snoop_fanout::total 3536130 # Request fanout histogram 1502system.membus.reqLayer0.occupancy 102490000 # Layer occupancy (ticks) 1503system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1504system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1505system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1506system.membus.reqLayer2.occupancy 5501500 # Layer occupancy (ticks) 1507system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1508system.membus.reqLayer5.occupancy 9311720798 # Layer occupancy (ticks) 1509system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1510system.membus.respLayer2.occupancy 6129482304 # Layer occupancy (ticks) 1511system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1512system.membus.respLayer3.occupancy 44955070 # Layer occupancy (ticks) 1513system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1514system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1515system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1516system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1517system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1518system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1519system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1520system.realview.ethernet.txBytes 966 # Bytes Transmitted 1521system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1522system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1523system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1524system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1525system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1526system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1527system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1528system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1529system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1530system.realview.ethernet.totPackets 3 # Total Packets 1531system.realview.ethernet.totBytes 966 # Total Bytes 1532system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1533system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1534system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1535system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1536system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1537system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1538system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1539system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1540system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1541system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1542system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1543system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1544system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1545system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1546system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1547system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1548system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1549system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1550system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1551system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1552system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1553system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1554system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1555system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1556system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1557system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1558system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1559system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1560system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1561system.realview.ethernet.droppedPackets 0 # number of packets dropped 1562system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1563system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1564system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1565system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1566 1567---------- End Simulation Statistics ---------- 1568