stats.txt revision 11680
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 51.688775 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 51688774990000 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711680SCurtis.Dunham@arm.comhost_inst_rate 210815 # Simulator instruction rate (inst/s) 811680SCurtis.Dunham@arm.comhost_op_rate 247704 # Simulator op (including micro ops) rate (op/s) 911680SCurtis.Dunham@arm.comhost_tick_rate 11507504763 # Simulator tick rate (ticks/s) 1011680SCurtis.Dunham@arm.comhost_mem_usage 684036 # Number of bytes of host memory used 1111680SCurtis.Dunham@arm.comhost_seconds 4491.74 # Real time elapsed on the host 1211680SCurtis.Dunham@arm.comsim_insts 946928269 # Number of instructions simulated 1311680SCurtis.Dunham@arm.comsim_ops 1112623169 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory 1811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory 1911680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory 2011680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory 2111680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory 2211680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 76755656 # Number of bytes read from this memory 2311680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory 2411680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory 2610636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 93636516 # Number of bytes written to this memory 2811680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory 2911680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory 3011680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory 3111680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory 3211680SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory 3311680SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory 3411680SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory 3510636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611680SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory 3711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s) 3811680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s) 3911680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s) 4011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s) 4111680SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s) 4211680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s) 4311680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s) 4411680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s) 4511680SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s) 4610892Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 4711680SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s) 4811680SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s) 4911680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s) 5011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s) 5111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s) 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s) 5311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s) 5411680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s) 5511680SCurtis.Dunham@arm.comsystem.physmem.readReqs 1199320 # Number of read requests accepted 5611680SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1465322 # Number of write requests accepted 5711680SCurtis.Dunham@arm.comsystem.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue 5811680SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue 5911680SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM 6011680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue 6111680SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM 6211680SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side 6311680SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side 6411680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue 6511680SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 6611336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 70144 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 74650 # Per bank write bursts 6911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 68418 # Per bank write bursts 7011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 68145 # Per bank write bursts 7111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 72367 # Per bank write bursts 7211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 76479 # Per bank write bursts 7311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 68140 # Per bank write bursts 7411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 71247 # Per bank write bursts 7511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 66581 # Per bank write bursts 7611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 125666 # Per bank write bursts 7711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 74635 # Per bank write bursts 7811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 76739 # Per bank write bursts 7911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 72169 # Per bank write bursts 8011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 75530 # Per bank write bursts 8111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 66172 # Per bank write bursts 8211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 71551 # Per bank write bursts 8311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 89120 # Per bank write bursts 8411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 91694 # Per bank write bursts 8511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 88427 # Per bank write bursts 8611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 87889 # Per bank write bursts 8711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 92386 # Per bank write bursts 8811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 94711 # Per bank write bursts 8911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 88472 # Per bank write bursts 9011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 91239 # Per bank write bursts 9111680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 88274 # Per bank write bursts 9211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 94990 # Per bank write bursts 9311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 92874 # Per bank write bursts 9411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 94799 # Per bank write bursts 9511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 93039 # Per bank write bursts 9611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 95949 # Per bank write bursts 9711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 87664 # Per bank write bursts 9811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 91512 # Per bank write bursts 9910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10011680SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 468 # Number of times write queue was full causing retry 10111680SCurtis.Dunham@arm.comsystem.physmem.totGap 51688773130000 # Total gap between requests 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10811680SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 1199305 # Read request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11511680SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1462749 # Write request sizes (log2) 11611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see 11711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see 11811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see 11911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see 12011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see 12111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see 12211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see 12311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see 12411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see 12511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see 12611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see 12711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see 12811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see 12911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see 13011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 13111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see 13211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see 13311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see 13411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see 13511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see 13611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 13711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see 16411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see 16511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see 16611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see 16711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see 16811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see 16911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see 17011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see 17111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see 17211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see 17311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see 17411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see 17511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see 17611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see 17711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see 17811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see 17911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see 18011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see 18111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see 18211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see 18311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see 18411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see 18511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see 18611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see 18711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see 18811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see 18911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see 19111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see 19211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see 19311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see 19411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see 19511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see 19611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see 19711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see 19811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see 19911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see 20011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see 20111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see 20211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see 20311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see 20411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see 20511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see 20611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see 20711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see 20811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see 20911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see 21011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see 21111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see 21211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation 21311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation 21411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation 21511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation 21611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation 21711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation 21811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation 21911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation 22011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation 22111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation 22211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation 22311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation 22411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation 22511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation 22611680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes 22711680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes 22811680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes 22911680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes 23011680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 23111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 23211353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 23311680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes 23411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads 23511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads 23611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads 23711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads 23811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads 23911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads 24011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads 24111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads 24211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads 24311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads 24411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads 24511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads 24611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads 24711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads 24811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads 24911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads 25011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads 25111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads 25211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads 25311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads 25411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads 25511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads 25611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads 25711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads 25811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads 25911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads 26011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads 26111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads 26211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads 26311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads 26411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads 26511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads 26611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads 26711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads 26811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads 26911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads 27011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads 27111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads 27211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads 27311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads 27411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads 27511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads 27611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads 27711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads 27811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads 27911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads 28011680SCurtis.Dunham@arm.comsystem.physmem.totQLat 38956691672 # Total ticks spent queuing 28111680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM 28211680SCurtis.Dunham@arm.comsystem.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers 28311680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst 28410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 28511680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst 28611680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s 28711680SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s 28811680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s 28911680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s 29010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 29111606Sandreas.sandberg@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 29211353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 29310892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 29411103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 29511680SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing 29611680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 929087 # Number of row buffer hits during reads 29711680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 1069644 # Number of row buffer hits during writes 29811680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads 29911680SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes 30011680SCurtis.Dunham@arm.comsystem.physmem.avgGap 19398017.87 # Average gap between requests 30111680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined 30211680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ) 30311680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ) 30411680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ) 30511680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ) 30611680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ) 30711680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ) 30811680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ) 30911680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ) 31011680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ) 31111680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ) 31211680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ) 31311680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 243.244086 # Core power per rank (mW) 31411680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank 31511680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states 31611680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states 31711680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states 31811680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states 31911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states 32011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states 32111680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ) 32211680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ) 32311680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ) 32411680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ) 32511680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ) 32611680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ) 32711680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ) 32811680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ) 32911680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ) 33011680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ) 33111680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ) 33211680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 243.324450 # Core power per rank (mW) 33311680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank 33411680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states 33511680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states 33611680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states 33711680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states 33811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states 33911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states 34011680SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 34110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 34210636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 34310515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 34410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 34510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 34610636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 34710636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 34810515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 34910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 35010636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 35110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 35210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 35310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 35410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 35510636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 35610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 35711680SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 35811680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 35911680SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 36010585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 36110585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 36210585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 36310585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 36410585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 36510585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 36611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 261505306 # Number of BP lookups 36711680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted 36811680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect 36911680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups 37011680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 130159045 # Number of BTB hits 37110585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 37211680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage 37311680SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target. 37411680SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions. 37511680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups. 37611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits. 37711680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses. 37811680SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches. 37910585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 38011680SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 38110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 40910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41011680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 41111680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 574319 # Table walker walks requested 41211680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors 41311680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate 41411680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate 41511680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency 41611680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency 41711680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency 41811680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency 41911680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency 42011680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency 42111680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency 42211680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency 42311680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency 42411680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency 42511680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency 42611680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency 42711680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency 42811680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency 42911680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 43011680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 43111680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 43211680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 43311680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency 43411680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution 43511680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution 43611680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution 43711680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated 43811680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated 43911680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated 44011680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst 44110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44211680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst 44311680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst 44410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44511680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst 44611680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst 44710585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 44810585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 44911680SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 182769858 # DTB read hits 45011680SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 473161 # DTB read misses 45111680SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 162201881 # DTB write hits 45211680SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 101158 # DTB write misses 45310585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 45410585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45511680SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID 45611680SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID 45711680SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB 45811680SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions 45911680SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch 46010585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46111680SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions 46211680SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 183243019 # DTB read accesses 46311680SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 162303039 # DTB write accesses 46410585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 46511680SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 344971739 # DTB hits 46611680SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 574319 # DTB misses 46711680SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 345546058 # DTB accesses 46811680SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 46910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 47810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 47910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 48610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 48710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 48810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 48910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 49510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 49610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 49710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 49811680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 49911680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 135751 # Table walker walks requested 50011680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors 50111680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate 50211680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate 50311680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency 50411680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency 50511680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency 50611680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency 50711680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency 50811680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency 50911680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency 51011680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency 51111680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency 51211680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency 51311680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency 51411680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency 51511680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency 51611680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency 51711680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency 51811680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency 51911680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency 52011680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52111680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency 52211680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution 52311680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution 52411680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution 52511680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated 52611680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated 52711680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated 52810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 52911680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst 53011680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst 53110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53211680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst 53311680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst 53411680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst 53511680SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 452655900 # ITB inst hits 53611680SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 135751 # ITB inst misses 53710585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 53810585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 53910585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 54010585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 54110585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 54210585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54311680SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID 54411680SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID 54511680SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB 54610585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54710585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 54810585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 54911680SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions 55010585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 55110585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 55211680SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 452791651 # ITB inst accesses 55311680SCurtis.Dunham@arm.comsystem.cpu.itb.hits 452655900 # DTB hits 55411680SCurtis.Dunham@arm.comsystem.cpu.itb.misses 135751 # DTB misses 55511680SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 452791651 # DTB accesses 55611680SCurtis.Dunham@arm.comsystem.cpu.numPwrStateTransitions 33180 # Number of power state transitions 55711680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state 55811680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state 55911680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state 56011680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state 56111680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state 56211530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 56311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 56411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 56511606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 56611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 56711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 56811530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 56911606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 57011606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 57111530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 57211570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 57311606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state 57411680SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state 57511680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states 57611680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states 57711680SCurtis.Dunham@arm.comsystem.cpu.numCycles 2530699433 # number of cpu cycles simulated 57810585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57910585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58011680SCurtis.Dunham@arm.comsystem.cpu.committedInsts 946928269 # Number of instructions committed 58111680SCurtis.Dunham@arm.comsystem.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed 58211680SCurtis.Dunham@arm.comsystem.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit 58311680SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching 58411680SCurtis.Dunham@arm.comsystem.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 58511680SCurtis.Dunham@arm.comsystem.cpu.cpi 2.672536 # CPI: cycles per instruction 58611680SCurtis.Dunham@arm.comsystem.cpu.ipc 0.374177 # IPC: instructions per cycle 58711441Sandreas.hansson@arm.comsystem.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 58811680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction 58911680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction 59011680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction 59111606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction 59211606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction 59311606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction 59411606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction 59511606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction 59611606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction 59711606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction 59811606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction 59911606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction 60011606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction 60111606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction 60211606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction 60311606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction 60411606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction 60511606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction 60611606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction 60711606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction 60811606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction 60911606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction 61011606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction 61111606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction 61211606Sandreas.sandberg@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction 61311680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 108989 0.01% 69.53% # Class of committed instruction 61411680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 61511680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 61611680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 61711680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 177312606 15.94% 85.47% # Class of committed instruction 61811680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 161648619 14.53% 100.00% # Class of committed instruction 61911441Sandreas.hansson@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 62011441Sandreas.hansson@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 62111680SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 1112623169 # Class of committed instruction 62210585Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 62311680SCurtis.Dunham@arm.comsystem.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed 62411680SCurtis.Dunham@arm.comsystem.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked 62511680SCurtis.Dunham@arm.comsystem.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped 62611680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 62711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 11091024 # number of replacements 62811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use 62911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks. 63011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks. 63111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks. 63211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. 63311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor 63411680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy 63511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy 63610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 63811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 63911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 64010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 64111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses 64211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses 64311680SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 64411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits 64511680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits 64611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits 64711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits 64811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits 64911680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits 65011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits 65111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits 65211680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits 65311680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits 65411680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits 65511680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits 65611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits 65711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits 65811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits 65911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 320875829 # number of overall hits 66011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses 66111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses 66211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses 66311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses 66411680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses 66511680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses 66611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses 66711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses 66811680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses 66911680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses 67011570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 67111570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 67211680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses 67311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses 67411680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses 67511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 13097731 # number of overall misses 67611680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles 67711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles 67811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles 67911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles 68011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles 68111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles 68211680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles 68311680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles 68411606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles 68511606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles 68611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 303646309500 # number of demand (read+write) miss cycles 68711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 303646309500 # number of demand (read+write) miss cycles 68811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 303646309500 # number of overall miss cycles 68911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 303646309500 # number of overall miss cycles 69011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 174693570 # number of ReadReq accesses(hits+misses) 69111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 174693570 # number of ReadReq accesses(hits+misses) 69211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 155704542 # number of WriteReq accesses(hits+misses) 69311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 155704542 # number of WriteReq accesses(hits+misses) 69411680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1994973 # number of SoftPFReq accesses(hits+misses) 69511680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1994973 # number of SoftPFReq accesses(hits+misses) 69611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1580475 # number of WriteLineReq accesses(hits+misses) 69711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1580475 # number of WriteLineReq accesses(hits+misses) 69811680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 4320727 # number of LoadLockedReq accesses(hits+misses) 69911680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 4320727 # number of LoadLockedReq accesses(hits+misses) 70011680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 4318997 # number of StoreCondReq accesses(hits+misses) 70111680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 4318997 # number of StoreCondReq accesses(hits+misses) 70211680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 331978587 # number of demand (read+write) accesses 70311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 331978587 # number of demand (read+write) accesses 70411680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 333973560 # number of overall (read+write) accesses 70511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 333973560 # number of overall (read+write) accesses 70611680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034878 # miss rate for ReadReq accesses 70711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.034878 # miss rate for ReadReq accesses 70811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027538 # miss rate for WriteReq accesses 70911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.027538 # miss rate for WriteReq accesses 71011680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738724 # miss rate for SoftPFReq accesses 71111680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.738724 # miss rate for SoftPFReq accesses 71211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786579 # miss rate for WriteLineReq accesses 71311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.786579 # miss rate for WriteLineReq accesses 71411680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072842 # miss rate for LoadLockedReq accesses 71511680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.072842 # miss rate for LoadLockedReq accesses 71611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 71711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 71811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.035014 # miss rate for demand accesses 71911680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.035014 # miss rate for demand accesses 72011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.039218 # miss rate for overall accesses 72111680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.039218 # miss rate for overall accesses 72211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733 # average ReadReq miss latency 72311680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733 # average ReadReq miss latency 72411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472 # average WriteReq miss latency 72511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472 # average WriteReq miss latency 72611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748 # average WriteLineReq miss latency 72711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748 # average WriteLineReq miss latency 72811680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349 # average LoadLockedReq miss latency 72911680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349 # average LoadLockedReq miss latency 73011606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 73111606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 73211680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719 # average overall miss latency 73311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 26122.368719 # average overall miss latency 73411680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054 # average overall miss latency 73511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 23183.123054 # average overall miss latency 73611680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked 73710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73811680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 73910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 74011680SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 19 # average number of cycles each access was blocked 74110585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74211680SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 8512101 # number of writebacks 74311680SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 8512101 # number of writebacks 74411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 311042 # number of ReadReq MSHR hits 74511680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 311042 # number of ReadReq MSHR hits 74611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1897692 # number of WriteReq MSHR hits 74711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1897692 # number of WriteReq MSHR hits 74811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits 74911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits 75011680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70889 # number of LoadLockedReq MSHR hits 75111680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 70889 # number of LoadLockedReq MSHR hits 75211680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2208886 # number of demand (read+write) MSHR hits 75311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2208886 # number of demand (read+write) MSHR hits 75411680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2208886 # number of overall MSHR hits 75511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2208886 # number of overall MSHR hits 75611680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5781994 # number of ReadReq MSHR misses 75711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5781994 # number of ReadReq MSHR misses 75811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2390100 # number of WriteReq MSHR misses 75911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2390100 # number of WriteReq MSHR misses 76011680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466271 # number of SoftPFReq MSHR misses 76111680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1466271 # number of SoftPFReq MSHR misses 76211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1243016 # number of WriteLineReq MSHR misses 76311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1243016 # number of WriteLineReq MSHR misses 76411680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 243840 # number of LoadLockedReq MSHR misses 76511680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 243840 # number of LoadLockedReq MSHR misses 76611570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 76711570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 76811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 9415110 # number of demand (read+write) MSHR misses 76911680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 9415110 # number of demand (read+write) MSHR misses 77011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 10881381 # number of overall MSHR misses 77111680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 10881381 # number of overall MSHR misses 77211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 77311680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable 77411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 77511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 77611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 77711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 77811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles 77911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles 78011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles 78111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles 78211680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles 78311680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles 78411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles 78511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles 78611680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles 78711680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles 78811606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles 78911606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles 79011680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles 79111680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles 79211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles 79311680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles 79411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles 79511680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles 79611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles 79711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles 79811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses 79911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses 80011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses 80111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses 80211680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses 80311680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses 80411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses 80511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses 80611680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses 80711680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses 80811441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 80911441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 81011680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses 81111680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses 81211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses 81311680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses 81411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency 81511680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency 81611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency 81711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency 81811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency 81911680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency 82011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency 82111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency 82211680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency 82311680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency 82411606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 82511606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 82611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency 82711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency 82811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency 82911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency 83011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency 83111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency 83211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency 83311680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency 83411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 83511680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 24547500 # number of replacements 83611680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use 83711680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks. 83811680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks. 83911680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks. 84011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit. 84111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor 84211680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy 84311680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy 84410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84511680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 84611680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id 84711680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id 84810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84911680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses 85011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 476870138 # Number of data accesses 85111680SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 85211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits 85311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits 85411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits 85511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits 85611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits 85711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 427774095 # number of overall hits 85811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses 85911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses 86011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses 86111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 24548022 # number of demand (read+write) misses 86211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 24548022 # number of overall misses 86311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 24548022 # number of overall misses 86411680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000 # number of ReadReq miss cycles 86511680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 329750158000 # number of ReadReq miss cycles 86611680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 329750158000 # number of demand (read+write) miss cycles 86711680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 329750158000 # number of demand (read+write) miss cycles 86811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 329750158000 # number of overall miss cycles 86911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 329750158000 # number of overall miss cycles 87011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 452322117 # number of ReadReq accesses(hits+misses) 87111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 452322117 # number of ReadReq accesses(hits+misses) 87211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 452322117 # number of demand (read+write) accesses 87311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 452322117 # number of demand (read+write) accesses 87411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 452322117 # number of overall (read+write) accesses 87511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 452322117 # number of overall (read+write) accesses 87611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses 87711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses 87811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses 87911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses 88011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses 88111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses 88211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619 # average ReadReq miss latency 88311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619 # average ReadReq miss latency 88411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency 88511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency 88611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency 88711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency 88810585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 88910585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 89210585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89310585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89411680SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 24547500 # number of writebacks 89511680SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 24547500 # number of writebacks 89611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 24548022 # number of ReadReq MSHR misses 89711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 24548022 # number of ReadReq MSHR misses 89811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 24548022 # number of demand (read+write) MSHR misses 89911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 24548022 # number of demand (read+write) MSHR misses 90011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 24548022 # number of overall MSHR misses 90111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 24548022 # number of overall MSHR misses 90211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable 90311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable 90411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses 90511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses 90611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000 # number of ReadReq MSHR miss cycles 90711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000 # number of ReadReq MSHR miss cycles 90811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000 # number of demand (read+write) MSHR miss cycles 90911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 305202137000 # number of demand (read+write) MSHR miss cycles 91011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000 # number of overall MSHR miss cycles 91111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 305202137000 # number of overall MSHR miss cycles 91211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles 91311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles 91411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles 91511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # number of overall MSHR uncacheable cycles 91611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses 91711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses 91811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses 91911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses 92011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses 92111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses 92211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660 # average ReadReq mshr miss latency 92311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660 # average ReadReq mshr miss latency 92411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency 92511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency 92611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency 92711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency 92811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average ReadReq mshr uncacheable latency 92911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757 # average ReadReq mshr uncacheable latency 93011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average overall mshr uncacheable latency 93111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757 # average overall mshr uncacheable latency 93211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 93311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 1591901 # number of replacements 93411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 65408.549959 # Cycle average of tags in use 93511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 69520908 # Total number of references to valid blocks. 93611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 1655396 # Sample count of references to valid blocks. 93711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 41.996542 # Average number of references to valid blocks. 93811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 6255171000 # Cycle when the warmup percentage was hit. 93911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9036.958133 # Average occupied blocks per requestor 94011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 433.683776 # Average occupied blocks per requestor 94111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 402.305370 # Average occupied blocks per requestor 94211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7871.756997 # Average occupied blocks per requestor 94311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683 # Average occupied blocks per requestor 94411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.137893 # Average percentage of cache occupancy 94511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006617 # Average percentage of cache occupancy 94611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006139 # Average percentage of cache occupancy 94711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.120113 # Average percentage of cache occupancy 94811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.727293 # Average percentage of cache occupancy 94911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998055 # Average percentage of cache occupancy 95011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id 95111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63224 # Occupied blocks per task id 95211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id 95311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 95411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 95511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 790 # Occupied blocks per task id 95611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5976 # Occupied blocks per task id 95711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 56108 # Occupied blocks per task id 95811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id 95911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.964722 # Percentage of cache occupancy per task id 96011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 582399864 # Number of tag accesses 96111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 582399864 # Number of data accesses 96211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 96311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921588 # number of ReadReq hits 96411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 261482 # number of ReadReq hits 96511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1183070 # number of ReadReq hits 96611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 8512101 # number of WritebackDirty hits 96711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 8512101 # number of WritebackDirty hits 96811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 24543775 # number of WritebackClean hits 96911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 24543775 # number of WritebackClean hits 97011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 29573 # number of UpgradeReq hits 97111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 29573 # number of UpgradeReq hits 97211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1660508 # number of ReadExReq hits 97311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1660508 # number of ReadExReq hits 97411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24440962 # number of ReadCleanReq hits 97511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 24440962 # number of ReadCleanReq hits 97611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 7164937 # number of ReadSharedReq hits 97711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 7164937 # number of ReadSharedReq hits 97811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 700668 # number of InvalidateReq hits 97911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 700668 # number of InvalidateReq hits 98011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 921588 # number of demand (read+write) hits 98111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 261482 # number of demand (read+write) hits 98211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 24440962 # number of demand (read+write) hits 98311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 8825445 # number of demand (read+write) hits 98411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 34449477 # number of demand (read+write) hits 98511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 921588 # number of overall hits 98611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 261482 # number of overall hits 98711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 24440962 # number of overall hits 98811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 8825445 # number of overall hits 98911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 34449477 # number of overall hits 99011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6273 # number of ReadReq misses 99111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5180 # number of ReadReq misses 99211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::total 11453 # number of ReadReq misses 99311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 4073 # number of UpgradeReq misses 99411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 4073 # number of UpgradeReq misses 99511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 99611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 99711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 696158 # number of ReadExReq misses 99811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 696158 # number of ReadExReq misses 99911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107059 # number of ReadCleanReq misses 100011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 107059 # number of ReadCleanReq misses 100111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 326956 # number of ReadSharedReq misses 100211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 326956 # number of ReadSharedReq misses 100311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 542348 # number of InvalidateReq misses 100411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 542348 # number of InvalidateReq misses 100511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 6273 # number of demand (read+write) misses 100611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5180 # number of demand (read+write) misses 100711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 107059 # number of demand (read+write) misses 100811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1023114 # number of demand (read+write) misses 100911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 1141626 # number of demand (read+write) misses 101011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 6273 # number of overall misses 101111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5180 # number of overall misses 101211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 107059 # number of overall misses 101311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1023114 # number of overall misses 101411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 1141626 # number of overall misses 101511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 939749000 # number of ReadReq miss cycles 101611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 683365000 # number of ReadReq miss cycles 101711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 1623114000 # number of ReadReq miss cycles 101811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72777000 # number of UpgradeReq miss cycles 101911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 72777000 # number of UpgradeReq miss cycles 102011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles 102111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles 102211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66999821500 # number of ReadExReq miss cycles 102311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 66999821500 # number of ReadExReq miss cycles 102411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11524194500 # number of ReadCleanReq miss cycles 102511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 11524194500 # number of ReadCleanReq miss cycles 102611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37120013000 # number of ReadSharedReq miss cycles 102711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 37120013000 # number of ReadSharedReq miss cycles 102811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 2135500 # number of InvalidateReq miss cycles 102911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::total 2135500 # number of InvalidateReq miss cycles 103011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 939749000 # number of demand (read+write) miss cycles 103111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 683365000 # number of demand (read+write) miss cycles 103211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11524194500 # number of demand (read+write) miss cycles 103311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 104119834500 # number of demand (read+write) miss cycles 103411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 117267143000 # number of demand (read+write) miss cycles 103511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 939749000 # number of overall miss cycles 103611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 683365000 # number of overall miss cycles 103711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11524194500 # number of overall miss cycles 103811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 104119834500 # number of overall miss cycles 103911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 117267143000 # number of overall miss cycles 104011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927861 # number of ReadReq accesses(hits+misses) 104111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 266662 # number of ReadReq accesses(hits+misses) 104211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1194523 # number of ReadReq accesses(hits+misses) 104311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 8512101 # number of WritebackDirty accesses(hits+misses) 104411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 8512101 # number of WritebackDirty accesses(hits+misses) 104511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 24543775 # number of WritebackClean accesses(hits+misses) 104611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 24543775 # number of WritebackClean accesses(hits+misses) 104711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 33646 # number of UpgradeReq accesses(hits+misses) 104811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 33646 # number of UpgradeReq accesses(hits+misses) 104911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 105011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 105111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2356666 # number of ReadExReq accesses(hits+misses) 105211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2356666 # number of ReadExReq accesses(hits+misses) 105311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24548021 # number of ReadCleanReq accesses(hits+misses) 105411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 24548021 # number of ReadCleanReq accesses(hits+misses) 105511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7491893 # number of ReadSharedReq accesses(hits+misses) 105611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 7491893 # number of ReadSharedReq accesses(hits+misses) 105711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1243016 # number of InvalidateReq accesses(hits+misses) 105811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1243016 # number of InvalidateReq accesses(hits+misses) 105911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 927861 # number of demand (read+write) accesses 106011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 266662 # number of demand (read+write) accesses 106111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 24548021 # number of demand (read+write) accesses 106211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 9848559 # number of demand (read+write) accesses 106311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 35591103 # number of demand (read+write) accesses 106411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 927861 # number of overall (read+write) accesses 106511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 266662 # number of overall (read+write) accesses 106611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 24548021 # number of overall (read+write) accesses 106711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 9848559 # number of overall (read+write) accesses 106811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 35591103 # number of overall (read+write) accesses 106911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006761 # miss rate for ReadReq accesses 107011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019425 # miss rate for ReadReq accesses 107111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.009588 # miss rate for ReadReq accesses 107211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.121055 # miss rate for UpgradeReq accesses 107311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.121055 # miss rate for UpgradeReq accesses 107410636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 107510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 107611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.295400 # miss rate for ReadExReq accesses 107711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.295400 # miss rate for ReadExReq accesses 107811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004361 # miss rate for ReadCleanReq accesses 107911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004361 # miss rate for ReadCleanReq accesses 108011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043641 # miss rate for ReadSharedReq accesses 108111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043641 # miss rate for ReadSharedReq accesses 108211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.436316 # miss rate for InvalidateReq accesses 108311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.436316 # miss rate for InvalidateReq accesses 108411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006761 # miss rate for demand accesses 108511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019425 # miss rate for demand accesses 108611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.004361 # miss rate for demand accesses 108711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.103885 # miss rate for demand accesses 108811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.032076 # miss rate for demand accesses 108911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006761 # miss rate for overall accesses 109011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019425 # miss rate for overall accesses 109111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.004361 # miss rate for overall accesses 109211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.103885 # miss rate for overall accesses 109311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.032076 # miss rate for overall accesses 109411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556 # average ReadReq miss latency 109511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174 # average ReadReq miss latency 109611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463 # average ReadReq miss latency 109711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150 # average UpgradeReq miss latency 109811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150 # average UpgradeReq miss latency 109911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 110011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency 110111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251 # average ReadExReq miss latency 110211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251 # average ReadExReq miss latency 110311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566 # average ReadCleanReq miss latency 110411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566 # average ReadCleanReq miss latency 110511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823 # average ReadSharedReq miss latency 110611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823 # average ReadSharedReq miss latency 110711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 3.937509 # average InvalidateReq miss latency 110811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 3.937509 # average InvalidateReq miss latency 110911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency 111011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency 111111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency 111211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency 111311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 102719.404604 # average overall miss latency 111411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency 111511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency 111611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency 111711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency 111811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 102719.404604 # average overall miss latency 111910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 112210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 112310585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112410585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 1356118 # number of writebacks 112611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 1356118 # number of writebacks 112710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 112810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 112911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 113011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 113110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 113211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 113311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 113410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 113511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 113611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 113711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6273 # number of ReadReq MSHR misses 113811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5180 # number of ReadReq MSHR misses 113911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 11453 # number of ReadReq MSHR misses 114011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 114111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 114211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4073 # number of UpgradeReq MSHR misses 114311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 4073 # number of UpgradeReq MSHR misses 114411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 114511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 114611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 696158 # number of ReadExReq MSHR misses 114711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 696158 # number of ReadExReq MSHR misses 114811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107056 # number of ReadCleanReq MSHR misses 114911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 107056 # number of ReadCleanReq MSHR misses 115011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 326935 # number of ReadSharedReq MSHR misses 115111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 326935 # number of ReadSharedReq MSHR misses 115211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 542348 # number of InvalidateReq MSHR misses 115311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::total 542348 # number of InvalidateReq MSHR misses 115411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6273 # number of demand (read+write) MSHR misses 115511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5180 # number of demand (read+write) MSHR misses 115611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 107056 # number of demand (read+write) MSHR misses 115711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1023093 # number of demand (read+write) MSHR misses 115811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 1141602 # number of demand (read+write) MSHR misses 115911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6273 # number of overall MSHR misses 116011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5180 # number of overall MSHR misses 116111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 107056 # number of overall MSHR misses 116211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1023093 # number of overall MSHR misses 116311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 1141602 # number of overall MSHR misses 116411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable 116511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 116611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 85987 # number of ReadReq MSHR uncacheable 116711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 116811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 116911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses 117011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 117111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 119694 # number of overall MSHR uncacheable misses 117211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 877019000 # number of ReadReq MSHR miss cycles 117311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 631565000 # number of ReadReq MSHR miss cycles 117411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1508584000 # number of ReadReq MSHR miss cycles 117511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77761500 # number of UpgradeReq MSHR miss cycles 117611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77761500 # number of UpgradeReq MSHR miss cycles 117711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles 117811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles 117911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60038241001 # number of ReadExReq MSHR miss cycles 118011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60038241001 # number of ReadExReq MSHR miss cycles 118111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10453433004 # number of ReadCleanReq MSHR miss cycles 118211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10453433004 # number of ReadCleanReq MSHR miss cycles 118311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33849413548 # number of ReadSharedReq MSHR miss cycles 118411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33849413548 # number of ReadSharedReq MSHR miss cycles 118511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11199554001 # number of InvalidateReq MSHR miss cycles 118611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11199554001 # number of InvalidateReq MSHR miss cycles 118711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 877019000 # number of demand (read+write) MSHR miss cycles 118811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 631565000 # number of demand (read+write) MSHR miss cycles 118911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10453433004 # number of demand (read+write) MSHR miss cycles 119011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93887654549 # number of demand (read+write) MSHR miss cycles 119111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 105849671553 # number of demand (read+write) MSHR miss cycles 119211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 877019000 # number of overall MSHR miss cycles 119311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 631565000 # number of overall MSHR miss cycles 119411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10453433004 # number of overall MSHR miss cycles 119511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93887654549 # number of overall MSHR miss cycles 119611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 105849671553 # number of overall MSHR miss cycles 119711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3611009000 # number of ReadReq MSHR uncacheable cycles 119811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809783000 # number of ReadReq MSHR uncacheable cycles 119911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420792000 # number of ReadReq MSHR uncacheable cycles 120011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3611009000 # number of overall MSHR uncacheable cycles 120111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809783000 # number of overall MSHR uncacheable cycles 120211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles 120311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses 120411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses 120511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses 120610892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 120710892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 120811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses 120911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses 121010636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 121110585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 121211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses 121311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses 121411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses 121511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses 121611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses 121711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses 121811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses 121911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses 122011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses 122111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses 122211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses 122311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses 122411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses 122511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses 122611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses 122711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses 122811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses 122911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses 123011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency 123111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency 123211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency 123311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency 123411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency 123511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 123611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 123711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency 123811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency 123911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency 124011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency 124111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency 124211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency 124311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency 124411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency 124511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency 124611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency 124711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency 124811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency 124911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency 125011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency 125111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency 125211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency 125311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency 125411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency 125511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency 125611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency 125711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency 125811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency 125911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency 126011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency 126111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter. 126211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data. 126311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 126411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter. 126511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 126611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 126711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 126811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution 126911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution 127011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution 127111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution 127211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution 127311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution 127411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution 127511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution 127611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 127711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution 127811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution 127911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution 128011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution 128111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution 128211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution 128311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution 128411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes) 128511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes) 128611680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes) 128711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes) 128811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes) 128911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes) 129011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes) 129111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes) 129211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes) 129311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes) 129411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 2114439 # Total snoops (count) 129511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes) 129611680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram 129711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram 129811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram 129910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 130011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram 130111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram 130211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 130310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 130411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 130511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 130611680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram 130711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks) 130810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 130911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks) 131010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 131111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks) 131210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 131311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks) 131410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 131511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks) 131610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 131711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks) 131810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 131911680SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 132011680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40325 # Transaction distribution 132111680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40325 # Transaction distribution 132210726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 132310892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 132410726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 132510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 132611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 132710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 132810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 132910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 133010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 133110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 133210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 133310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 133410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 133510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 133610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 133710726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 133811680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) 133911680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) 134010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 134110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 134211680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) 134310726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 134410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 134511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 134610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 134710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 134810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 134910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 135010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 135110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 135210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 135310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 135410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 135510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 135610726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 135711680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) 135811680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) 135910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 136010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 136111680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) 136211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks) 136310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 136411680SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 136510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 136611680SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) 136710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 136811680SCurtis.Dunham@arm.comsystem.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 136910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 137011680SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 137111245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 137211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 137310585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 137411680SCurtis.Dunham@arm.comsystem.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 137510585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 137611680SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 137710585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 137811680SCurtis.Dunham@arm.comsystem.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 137910585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 138011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 138110585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 138211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 138310585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 138411680SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks) 138510585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 138611680SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks) 138710585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 138811680SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks) 138910585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 139010726Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 139110585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 139211680SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) 139310585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 139410892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 139510585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 139611680SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 139711680SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115486 # number of replacements 139811680SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use 139910585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 140011680SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. 140110585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 140211680SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit. 140311680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor 140411680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor 140511680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy 140611680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy 140711680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy 140810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 140910585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 141010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 141111680SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1039893 # Number of tag accesses 141211680SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1039893 # Number of data accesses 141311680SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 141410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 141511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses 141611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8877 # number of ReadReq misses 141710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 141810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 141910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 142010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 142110585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 142211680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses 142311680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115544 # number of demand (read+write) misses 142410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 142511680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115504 # number of overall misses 142611680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115544 # number of overall misses 142711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles 142811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles 142911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles 143010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 143110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 143211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles 143311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles 143411680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles 143511680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles 143611680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles 143711680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles 143811680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles 143911680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles 144010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 144111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) 144211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) 144310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 144410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 144510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 144610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 144710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 144811680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses 144911680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses 145010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 145111680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses 145211680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses 145310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 145410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 145510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 145610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 145710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 145810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 145910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 146010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 146110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 146210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 146310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 146410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 146510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 146611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency 146711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency 146811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency 146910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 147010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 147111680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency 147211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency 147311680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 147411680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency 147511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency 147611680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 147711680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency 147811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency 147911680SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked 148010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 148111680SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked 148210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 148311680SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked 148410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 148511570SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106631 # number of writebacks 148611570SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106631 # number of writebacks 148710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 148811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses 148911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses 149010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 149110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 149210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 149310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 149410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 149511680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses 149611680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses 149710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 149811680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses 149911680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses 150011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles 150111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles 150211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles 150310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 150410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 150511680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles 150611680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles 150711680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles 150811680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles 150911680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles 151011680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles 151111680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles 151211680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles 151310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 151410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 151510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 151610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 151710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 151810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 151910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 152010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 152110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 152210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 152310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 152410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 152510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 152611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency 152711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency 152811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency 152910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 153010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 153111680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency 153211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency 153311680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 153411680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency 153511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency 153611680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 153711680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency 153811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency 153911680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter. 154011680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data. 154111680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 154211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 154311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 154411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 154511680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 154611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 85987 # Transaction distribution 154711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 540308 # Transaction distribution 154811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 33707 # Transaction distribution 154911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 33707 # Transaction distribution 155011680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution 155111680SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 243530 # Transaction distribution 155211680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 4703 # Transaction distribution 155311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 155411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 7 # Transaction distribution 155511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 695596 # Transaction distribution 155611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 695596 # Transaction distribution 155711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution 155811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 648947 # Transaction distribution 155910726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 156010515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 156111680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 156211680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes) 156311680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes) 156411680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes) 156511680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes) 156611680SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes) 156710726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 156810515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 156911680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 157011680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes) 157111680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes) 157211680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes) 157311680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes) 157411680SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes) 157511680SCurtis.Dunham@arm.comsystem.membus.snoops 2899 # Total snoops (count) 157611680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 185088 # Total snoop traffic (bytes) 157711680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 1923263 # Request fanout histogram 157811680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.016618 # Request fanout histogram 157911680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram 158010515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 158111680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram 158211680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram 158310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 158410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 158511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 158610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 158711680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 1923263 # Request fanout histogram 158811680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks) 158910515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 159011570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) 159110515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 159211680SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks) 159310515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 159411680SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks) 159510515SAli.Saidi@ARM.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 159611680SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks) 159710515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 159811680SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks) 159910515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 160011680SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160111680SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160211680SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160311680SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160411680SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160511680SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160611680SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 160711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 160811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 160911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 161011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 161111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 161211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 161311680SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 161411680SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 161510515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 161610515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 161710515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 161810515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 161910515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 162010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 162110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 162210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 162310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 162411138Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 162510515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 162610515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 162710515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 162811138Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 162910515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 163010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 163110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 163210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 163310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 163410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 163510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 163610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 163710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 163810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 163910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 164010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 164110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 164210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 164310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 164410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 164510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 164610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 164710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 164810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 164910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 165010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 165110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 165210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 165310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 165410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 165510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 165610515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 165711680SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 165811680SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 165911680SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166011680SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166111680SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166211680SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166311680SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 166511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 166611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 166711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 166811680SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 166911680SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167011680SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167111680SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167211680SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167311680SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167411680SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167511680SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167611680SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167711680SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167811680SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 167911680SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 168010515SAli.Saidi@ARM.com 168110515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1682