xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.667585                       # Number of seconds simulated
sim_ticks                                51667585479000                       # Number of ticks simulated
final_tick                               51667585479000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 173260                       # Simulator instruction rate (inst/s)
host_op_rate                                   203581                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9711995066                       # Simulator tick rate (ticks/s)
host_mem_usage                                 728604                       # Number of bytes of host memory used
host_seconds                                  5319.98                       # Real time elapsed on the host
sim_insts                                   921741550                       # Number of instructions simulated
sim_ops                                    1083047600                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       358592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       308608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10084224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94130760                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        400576                       # Number of bytes read from this memory
system.physmem.bytes_read::total            105282760                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10084224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10084224                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     87776448                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          87797028                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         5603                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         4822                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             157566                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1470806                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6259                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1645056                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1371507                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1374080                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           6940                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           5973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               195175                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1821853                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2037695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          195175                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             195175                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1698869                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1699267                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1698869                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          6940                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          5973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              195175                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1822252                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7753                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3736962                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1645056                       # Number of read requests accepted
system.physmem.writeReqs                      1374080                       # Number of write requests accepted
system.physmem.readBursts                     1645056                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1374080                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                105226304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     57280                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  87795840                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 105282760                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               87797028                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      895                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         144878                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               98762                       # Per bank write bursts
system.physmem.perBankRdBursts::1              104908                       # Per bank write bursts
system.physmem.perBankRdBursts::2              100268                       # Per bank write bursts
system.physmem.perBankRdBursts::3               95741                       # Per bank write bursts
system.physmem.perBankRdBursts::4              100817                       # Per bank write bursts
system.physmem.perBankRdBursts::5              109226                       # Per bank write bursts
system.physmem.perBankRdBursts::6               96584                       # Per bank write bursts
system.physmem.perBankRdBursts::7               96517                       # Per bank write bursts
system.physmem.perBankRdBursts::8               93312                       # Per bank write bursts
system.physmem.perBankRdBursts::9              154793                       # Per bank write bursts
system.physmem.perBankRdBursts::10              99831                       # Per bank write bursts
system.physmem.perBankRdBursts::11             102735                       # Per bank write bursts
system.physmem.perBankRdBursts::12              98206                       # Per bank write bursts
system.physmem.perBankRdBursts::13             101977                       # Per bank write bursts
system.physmem.perBankRdBursts::14              93251                       # Per bank write bursts
system.physmem.perBankRdBursts::15              97233                       # Per bank write bursts
system.physmem.perBankWrBursts::0               83938                       # Per bank write bursts
system.physmem.perBankWrBursts::1               86643                       # Per bank write bursts
system.physmem.perBankWrBursts::2               85449                       # Per bank write bursts
system.physmem.perBankWrBursts::3               83391                       # Per bank write bursts
system.physmem.perBankWrBursts::4               87884                       # Per bank write bursts
system.physmem.perBankWrBursts::5               92979                       # Per bank write bursts
system.physmem.perBankWrBursts::6               83797                       # Per bank write bursts
system.physmem.perBankWrBursts::7               84591                       # Per bank write bursts
system.physmem.perBankWrBursts::8               82134                       # Per bank write bursts
system.physmem.perBankWrBursts::9               88444                       # Per bank write bursts
system.physmem.perBankWrBursts::10              84764                       # Per bank write bursts
system.physmem.perBankWrBursts::11              87315                       # Per bank write bursts
system.physmem.perBankWrBursts::12              85408                       # Per bank write bursts
system.physmem.perBankWrBursts::13              87944                       # Per bank write bursts
system.physmem.perBankWrBursts::14              81647                       # Per bank write bursts
system.physmem.perBankWrBursts::15              85482                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    51667583532000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1645041                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1371507                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1321455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    316451                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       938                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       316                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       518                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       697                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       315                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      350                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      101                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    15056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    17226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    66293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    80848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    82840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    82796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    83570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    83932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    85472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    84523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    85247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    89567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    84372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    83217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    92227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    82440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    83507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    80252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      370                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      310                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       646368                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.625675                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.464471                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.594716                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         252807     39.11%     39.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       155954     24.13%     63.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        60049      9.29%     72.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        34895      5.40%     77.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        25863      4.00%     81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        18951      2.93%     84.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14056      2.17%     87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        13035      2.02%     89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        70758     10.95%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         646368                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         79614                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.651179                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      282.749901                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          79611    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           79614                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         79614                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.230763                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.794029                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.276538                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           77327     97.13%     97.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             304      0.38%     97.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              53      0.07%     97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             307      0.39%     97.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              57      0.07%     98.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             338      0.42%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             219      0.28%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              23      0.03%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              64      0.08%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             131      0.16%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              34      0.04%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              35      0.04%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             493      0.62%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              27      0.03%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              21      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             122      0.15%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            27      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           79614                       # Writes before turning the bus around for reads
system.physmem.totQLat                    26413369588                       # Total ticks spent queuing
system.physmem.totMemAccLat               57241388338                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8220805000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16064.95                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34814.95                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.04                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.70                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.04                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.70                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.46                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1338705                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1030897                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.42                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.15                       # Row buffer hit rate for writes
system.physmem.avgGap                     17113367.38                       # Average gap between requests
system.physmem.pageHitRate                      78.57                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2462533920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1343644500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6262011600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4462594560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3374675494320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1320469447905                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29842244670000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34551920396805                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.734956                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49644314314893                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1725294220000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    297976817607                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2424008160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1322623500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6562436400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4426734240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3374675494320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1320896835045                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29841869760750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34552177892415                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.739940                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49643648149046                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1725294220000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    298642969704                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               252423071                       # Number of BP lookups
system.cpu.branchPred.condPredicted         176427079                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          11938474                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            185221577                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               131501265                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.996731                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                30906734                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2133609                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    560833                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                560833                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        21083                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       178899                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       560833                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          560833    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       560833                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       199982                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 27029.240132                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 22851.547546                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20760.636291                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       197624     98.82%     98.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071            5      0.00%     98.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         2039      1.02%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143           52      0.03%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          109      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           52      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           79      0.04%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       199982                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples  -1571833592                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0     -1571833592    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total  -1571833592                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        178900     89.46%     89.46% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         21083     10.54%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       199983                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       560833                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       560833                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       199983                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       199983                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       760816                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    178232351                       # DTB read hits
system.cpu.dtb.read_misses                     463077                       # DTB read misses
system.cpu.dtb.write_hits                   157845440                       # DTB write hits
system.cpu.dtb.write_misses                     97756                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    77809                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1378                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  14628                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23069                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                178695428                       # DTB read accesses
system.cpu.dtb.write_accesses               157943196                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         336077791                       # DTB hits
system.cpu.dtb.misses                          560833                       # DTB misses
system.cpu.dtb.accesses                     336638624                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    134950                       # Table walker walks requested
system.cpu.itb.walker.walksLong                134950                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1074                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       117621                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       134950                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          134950    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       134950                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       118695                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 30170.011374                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 25640.228509                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 23413.242871                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       115997     97.73%     97.73% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071            4      0.00%     97.73% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         2500      2.11%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           50      0.04%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679          104      0.09%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       118695                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples  -1572850092                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     -1572850092    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total  -1572850092                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        117621     99.10%     99.10% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1074      0.90%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       118695                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       134950                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       134950                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118695                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       118695                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       253645                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    438786222                       # ITB inst hits
system.cpu.itb.inst_misses                     134950                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    55568                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    357024                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                438921172                       # ITB inst accesses
system.cpu.itb.hits                         438786222                       # DTB hits
system.cpu.itb.misses                          134950                       # DTB misses
system.cpu.itb.accesses                     438921172                       # DTB accesses
system.cpu.numCycles                       2561969113                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   921741550                       # Number of instructions committed
system.cpu.committedOps                    1083047600                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      92851518                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7622                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100774422273                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.779487                       # CPI: cycles per instruction
system.cpu.ipc                               0.359779                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    19360                       # number of quiesce instructions executed
system.cpu.tickCycles                      1740348403                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       821620710                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          10715341                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.930095                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           320246754                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          10715853                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.885325                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        7085883500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.930095                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1345291071                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1345291071                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    163948346                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       163948346                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    147386054                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      147386054                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       512627                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        512627                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       336269                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       336269                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3854490                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3854490                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4160967                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4160967                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     311334400                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        311334400                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    311847027                       # number of overall hits
system.cpu.dcache.overall_hits::total       311847027                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6367020                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6367020                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4130399                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4130399                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1400627                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1400627                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1238807                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1238807                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       308186                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       308186                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10497419                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10497419                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     11898046                       # number of overall misses
system.cpu.dcache.overall_misses::total      11898046                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 117617695000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 117617695000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 201217455000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 201217455000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84065023500                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  84065023500                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5131918500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   5131918500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 318835150000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 318835150000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 318835150000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 318835150000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    170315366                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    170315366                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    151516453                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    151516453                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1913254                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1913254                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1575076                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1575076                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4162676                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4162676                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4160969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4160969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    321831819                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    321831819                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    323745073                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    323745073                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037384                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037384                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027260                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027260                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732065                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.732065                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786506                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.786506                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074036                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074036                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032618                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032618                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.036751                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.036751                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18472.958307                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18472.958307                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48716.226931                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48716.226931                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67859.661352                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67859.661352                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16652.016964                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16652.016964                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30372.718284                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30372.718284                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26797.269905                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26797.269905                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8224375                       # number of writebacks
system.cpu.dcache.writebacks::total           8224375                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       782628                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       782628                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1821080                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1821080                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          142                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          142                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69834                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        69834                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2603708                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2603708                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2603708                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2603708                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5584392                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5584392                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2309319                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2309319                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1393093                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1393093                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1238665                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1238665                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       238352                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       238352                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7893711                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7893711                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9286804                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9286804                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96186724500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  96186724500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106755322500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 106755322500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26816989500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26816989500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  82819161500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  82819161500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3465009000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3465009000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202942047000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 202942047000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229759036500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 229759036500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830985000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830985000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5820481500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5820481500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11651466500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11651466500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032789                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032789                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015241                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015241                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728128                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728128                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786416                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786416                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057259                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057259                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024527                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024527                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028686                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028686                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17224.207129                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17224.207129                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46228.053595                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46228.053595                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19249.963570                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19249.963570                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66861.630465                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66861.630465                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14537.360710                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14537.360710                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25709.333291                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25709.333291                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24740.377475                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24740.377475                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173041.665430                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173041.665430                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172683.839672                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172683.839672                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172862.728662                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172862.728662                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24143027                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.872432                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           414273354                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24143539                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.158767                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       39477111500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.872432                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          115                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         462560451                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        462560451                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    414273354                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       414273354                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     414273354                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        414273354                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    414273354                       # number of overall hits
system.cpu.icache.overall_hits::total       414273354                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24143549                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24143549                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24143549                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24143549                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24143549                       # number of overall misses
system.cpu.icache.overall_misses::total      24143549                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 326781938000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 326781938000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 326781938000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 326781938000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 326781938000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 326781938000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    438416903                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    438416903                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    438416903                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    438416903                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    438416903                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    438416903                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055070                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.055070                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.055070                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.055070                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.055070                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.055070                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13534.958676                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13534.958676                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13534.958676                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13534.958676                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13534.958676                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13534.958676                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24143549                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24143549                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24143549                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24143549                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24143549                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24143549                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302638390000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 302638390000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302638390000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 302638390000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302638390000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 302638390000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746821500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746821500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746821500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   6746821500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055070                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055070                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055070                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.055070                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055070                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.055070                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12534.958717                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12534.958717                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12534.958717                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12534.958717                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12534.958717                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12534.958717                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.127703                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.127703                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.127703                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.127703                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1493610                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65243.274249                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           65796130                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1556709                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            42.266172                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      36608904000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36783.005624                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   344.357153                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   401.095680                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8076.862900                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19637.952892                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.561264                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005254                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006120                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123243                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.299651                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995533                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          261                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62838                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          259                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          440                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2477                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5563                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54301                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003983                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958832                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        572879965                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       572879965                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       917645                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       281080                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1198725                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8224375                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8224375                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10494                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10494                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1636293                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1636293                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24038260                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24038260                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6896602                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6896602                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       710760                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       710760                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       917645                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       281080                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24038260                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8532895                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        33769880                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       917645                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       281080                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24038260                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8532895                       # number of overall hits
system.cpu.l2cache.overall_hits::total       33769880                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5603                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4822                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        10425                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        37432                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        37432                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       625331                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       625331                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       105286                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       105286                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       319004                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       319004                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       527905                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       527905                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         5603                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         4822                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       105286                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       944335                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1060046                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         5603                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         4822                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       105286                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       944335                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1060046                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    765667000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    656318500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1421985500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1480581000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1480581000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  82954858000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  82954858000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  13909310000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  13909310000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  42957675000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  42957675000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  73230952500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  73230952500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    765667000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    656318500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  13909310000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 125912533000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 141243828500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    765667000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    656318500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  13909310000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 125912533000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 141243828500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       923248                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       285902                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1209150                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8224375                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8224375                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        47926                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        47926                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2261624                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2261624                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24143546                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24143546                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7215606                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7215606                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1238665                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1238665                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       923248                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       285902                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24143546                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9477230                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     34829926                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       923248                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       285902                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24143546                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9477230                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     34829926                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006069                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.016866                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.008622                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.781037                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.781037                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.276496                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.276496                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004361                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004361                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044210                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044210                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.426189                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.426189                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006069                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.016866                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004361                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.099643                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.030435                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006069                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.016866                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004361                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.099643                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.030435                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136653.043013                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136109.187059                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 136401.486811                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39553.884377                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39553.884377                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.517379                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.517379                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132109.777178                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132109.777178                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134661.869444                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134661.869444                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138719.944876                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138719.944876                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136653.043013                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136109.187059                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132109.777178                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133334.603716                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 133243.112563                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136653.043013                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136109.187059                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132109.777178                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133334.603716                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 133243.112563                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1264876                       # number of writebacks
system.cpu.l2cache.writebacks::total          1264876                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           25                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5603                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4822                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        10425                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1101                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1101                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37432                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        37432                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       625331                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       625331                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       105283                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       105283                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       318982                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       318982                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       527905                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       527905                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5603                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4822                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       105283                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       944313                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1060021                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5603                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4822                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       105283                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       944313                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1060021                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        86006                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119712                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    709637000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    608098500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1317735500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2648590000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2648590000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  76701548000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  76701548000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  12856217500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  12856217500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39765420000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39765420000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  67951902500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  67951902500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    709637000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    608098500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  12856217500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116466968000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 130640921000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    709637000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    608098500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  12856217500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116466968000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 130640921000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936031500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409709500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11345741000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5432237500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5432237500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936031500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10841947000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16777978500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006069                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016866                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008622                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.781037                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.781037                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.276496                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.276496                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004361                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044207                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044207                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.426189                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.426189                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006069                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016866                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.099640                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.030434                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006069                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016866                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.099640                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.030434                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126109.187059                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126401.486811                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.373370                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.373370                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122657.517379                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122657.517379                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122111.048317                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122111.048317                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124663.523334                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124663.523334                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128719.944876                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128719.944876                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126109.187059                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122111.048317                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123335.131466                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123243.710266                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126109.187059                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122111.048317                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123335.131466                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123243.710266                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160539.795828                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131918.017348                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161165.296980                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161165.296980                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160852.588164                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140152.854350                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     70464557                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     35605124                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4387                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2275                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2275                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq        1730195                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33090138                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      9595897                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict     26867205                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        47929                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        47931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2261624                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2261624                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24143549                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7224490                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1345329                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1238665                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72531044                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32377896                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       689100                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2164239                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         107762279                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1548534656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1133143634                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2287216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7385984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2691351490                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2160503                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     73254310                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.009691                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.097963                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           72544433     99.03%     99.03% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             709877      0.97%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       73254310                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    44006051993                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1484899                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36299896753                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14910158065                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     403245904                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1241004972                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40332                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40332                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231022                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231022                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353806                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334520                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334520                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492440                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           565934074                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115493                       # number of replacements
system.iocache.tags.tagsinuse               10.440039                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115509                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13160095445000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.520833                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.919206                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220052                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.432450                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652502                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039956                       # Number of tag accesses
system.iocache.tags.data_accesses             1039956                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8847                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8884                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8847                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8887                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8847                       # number of overall misses
system.iocache.overall_misses::total             8887                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1639357105                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1644426105                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13823164969                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13823164969                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1639357105                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1644777105                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1639357105                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1644777105                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8847                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8884                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8847                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8887                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8847                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8887                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 185300.904826                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 185099.741670                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129595.411470                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129595.411470                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 185300.904826                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 185076.753123                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 185300.904826                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 185076.753123                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32638                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3399                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.602236                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8847                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8884                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8847                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8887                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8847                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8887                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1197007105                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1200226105                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8489964969                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8489964969                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1197007105                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1200427105                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1197007105                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1200427105                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135300.904826                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135099.741670                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79595.411470                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79595.411470                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135300.904826                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 135076.753123                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135300.904826                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 135076.753123                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
system.membus.trans_dist::ReadResp             529580                       # Transaction distribution
system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
system.membus.trans_dist::Writeback           1371507                       # Transaction distribution
system.membus.trans_dist::CleanEvict           234789                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            38219                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           38221                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1152452                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1152452                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        443574                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4853436                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4983088                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341164                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341164                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5324252                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    185854828                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    186025234                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7224960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7224960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               193250194                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3290                       # Total snoops (count)
system.membus.snoop_fanout::samples           3469738                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3469738    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3469738                       # Request fanout histogram
system.membus.reqLayer0.occupancy           102307500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5483000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9286465077                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         8797329089                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228468079                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------