110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 51.643658 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 51643657651000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 51643657651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 290656 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 346501 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 16573581112 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 686852 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 3116.02 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 905689769 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 1079705427 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 481856 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 390720 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 7301696 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 78480968 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 396608 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 87051848 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 7301696 # Number of instructions bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 7301696 # Number of instructions bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 106840192 # Number of bytes written to this memory 2610636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 106860772 # Number of bytes written to this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 7529 # Number of read requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 6105 # Number of read requests responded to by this memory 3011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 114089 # Number of read requests responded to by this memory 3111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1226278 # Number of read requests responded to by this memory 3211860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6197 # Number of read requests responded to by this memory 3311860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1360198 # Number of read requests responded to by this memory 3411860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1669378 # Number of write requests responded to by this memory 3510636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1671951 # Number of write requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 9330 # Total read bandwidth from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 7566 # Total read bandwidth from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 141386 # Total read bandwidth from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 1519663 # Total read bandwidth from this memory (bytes/s) 4111860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 7680 # Total read bandwidth from this memory (bytes/s) 4211860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1685625 # Total read bandwidth from this memory (bytes/s) 4311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 141386 # Instruction read bandwidth from this memory (bytes/s) 4411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 141386 # Instruction read bandwidth from this memory (bytes/s) 4511860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2068796 # Write bandwidth from this memory (bytes/s) 4611860Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 4711860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2069194 # Write bandwidth from this memory (bytes/s) 4811860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2068796 # Total bandwidth to/from this memory (bytes/s) 4911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 9330 # Total bandwidth to/from this memory (bytes/s) 5011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 7566 # Total bandwidth to/from this memory (bytes/s) 5111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 141386 # Total bandwidth to/from this memory (bytes/s) 5211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 1520062 # Total bandwidth to/from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 7680 # Total bandwidth to/from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3754820 # Total bandwidth to/from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.physmem.readReqs 1360198 # Number of read requests accepted 5611860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1671951 # Number of write requests accepted 5711860Sandreas.hansson@arm.comsystem.physmem.readBursts 1360198 # Number of DRAM read bursts, including those serviced by the write queue 5811860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1671951 # Number of DRAM write bursts, including those merged in the write queue 5911860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 86990528 # Total number of bytes read from DRAM 6011860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 62144 # Total number of bytes read from write queue 6111860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 106858944 # Total number of bytes written to DRAM 6211860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 87051848 # Total read bytes from the system interface side 6311860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 106860772 # Total written bytes from the system interface side 6411860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 971 # Number of DRAM read bursts serviced by the write queue 6511860Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one 6611336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 83237 # Per bank write bursts 6811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 85225 # Per bank write bursts 6911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 82489 # Per bank write bursts 7011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 80125 # Per bank write bursts 7111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 87648 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 94125 # Per bank write bursts 7311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 89556 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 88166 # Per bank write bursts 7511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 78937 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 92012 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 85547 # Per bank write bursts 7811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 87304 # Per bank write bursts 7911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 77322 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 84061 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 80795 # Per bank write bursts 8211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 82678 # Per bank write bursts 8311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 101181 # Per bank write bursts 8411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 102649 # Per bank write bursts 8511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 102280 # Per bank write bursts 8611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 101626 # Per bank write bursts 8711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 106705 # Per bank write bursts 8811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 111943 # Per bank write bursts 8911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 107546 # Per bank write bursts 9011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 108809 # Per bank write bursts 9111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 101631 # Per bank write bursts 9211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 107791 # Per bank write bursts 9311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 102979 # Per bank write bursts 9411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 104017 # Per bank write bursts 9511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 98121 # Per bank write bursts 9611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 104909 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 102656 # Per bank write bursts 9811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 104828 # Per bank write bursts 9910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10011860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 458 # Number of times write queue was full causing retry 10111860Sandreas.hansson@arm.comsystem.physmem.totGap 51643655791000 # Total gap between requests 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10811860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1360183 # Read request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11511860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1669378 # Write request sizes (log2) 11611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1282957 # What read queue length does an incoming req see 11711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 70161 # What read queue length does an incoming req see 11811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 871 # What read queue length does an incoming req see 11911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see 12011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 12111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see 12211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see 12311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 445 # What read queue length does an incoming req see 12411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 945 # What read queue length does an incoming req see 12511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 570 # What read queue length does an incoming req see 12611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see 12711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 269 # What read queue length does an incoming req see 12811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see 12911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 159 # What read queue length does an incoming req see 13011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see 13111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see 13211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see 13311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see 13411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 13511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 78 # What read queue length does an incoming req see 13611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 13711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 31821 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 39955 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 90821 # What write queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 97628 # What write queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 100256 # What write queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 96883 # What write queue length does an incoming req see 16911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 101095 # What write queue length does an incoming req see 17011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 99439 # What write queue length does an incoming req see 17111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 101345 # What write queue length does an incoming req see 17211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 97950 # What write queue length does an incoming req see 17311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 101005 # What write queue length does an incoming req see 17411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 102593 # What write queue length does an incoming req see 17511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 99923 # What write queue length does an incoming req see 17611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 96951 # What write queue length does an incoming req see 17711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 96056 # What write queue length does an incoming req see 17811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 95043 # What write queue length does an incoming req see 17911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 92451 # What write queue length does an incoming req see 18011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 92535 # What write queue length does an incoming req see 18111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 18211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2382 # What write queue length does an incoming req see 18311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 2134 # What write queue length does an incoming req see 18411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1926 # What write queue length does an incoming req see 18511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1567 # What write queue length does an incoming req see 18611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 1406 # What write queue length does an incoming req see 18711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1261 # What write queue length does an incoming req see 18811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 1311 # What write queue length does an incoming req see 18911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1226 # What write queue length does an incoming req see 19011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1115 # What write queue length does an incoming req see 19111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 953 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1116 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 933 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 851 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 726 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 800 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 998 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 891 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 728 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 719 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 738 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 777 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 969 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 867 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 705 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 880 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1479 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1458 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 568 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 1009 # What write queue length does an incoming req see 21211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 752315 # Bytes accessed per row activation 21311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 257.670024 # Bytes accessed per row activation 21411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 155.219861 # Bytes accessed per row activation 21511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 291.691185 # Bytes accessed per row activation 21611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 319843 42.51% 42.51% # Bytes accessed per row activation 21711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 192789 25.63% 68.14% # Bytes accessed per row activation 21811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 70379 9.35% 77.50% # Bytes accessed per row activation 21911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 39533 5.25% 82.75% # Bytes accessed per row activation 22011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 27835 3.70% 86.45% # Bytes accessed per row activation 22111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 18762 2.49% 88.94% # Bytes accessed per row activation 22211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 14354 1.91% 90.85% # Bytes accessed per row activation 22311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 11626 1.55% 92.40% # Bytes accessed per row activation 22411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 57194 7.60% 100.00% # Bytes accessed per row activation 22511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 752315 # Bytes accessed per row activation 22611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 89671 # Reads before turning the bus around for writes 22711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 15.157342 # Reads before turning the bus around for writes 22811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 22.777727 # Reads before turning the bus around for writes 22911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-255 89658 99.99% 99.99% # Reads before turning the bus around for writes 23011860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::256-511 7 0.01% 99.99% # Reads before turning the bus around for writes 23111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-767 1 0.00% 99.99% # Reads before turning the bus around for writes 23211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 23311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes 23411860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes 23511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes 23611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 89671 # Reads before turning the bus around for writes 23711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 89671 # Writes before turning the bus around for reads 23811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 18.619966 # Writes before turning the bus around for reads 23911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.881543 # Writes before turning the bus around for reads 24011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.948219 # Writes before turning the bus around for reads 24111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 81046 90.38% 90.38% # Writes before turning the bus around for reads 24211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 5562 6.20% 96.58% # Writes before turning the bus around for reads 24311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 1304 1.45% 98.04% # Writes before turning the bus around for reads 24411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 395 0.44% 98.48% # Writes before turning the bus around for reads 24511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 213 0.24% 98.72% # Writes before turning the bus around for reads 24611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 159 0.18% 98.89% # Writes before turning the bus around for reads 24711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 654 0.73% 99.62% # Writes before turning the bus around for reads 24811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 203 0.23% 99.85% # Writes before turning the bus around for reads 24911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 30 0.03% 99.88% # Writes before turning the bus around for reads 25011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 3 0.00% 99.89% # Writes before turning the bus around for reads 25111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 5 0.01% 99.89% # Writes before turning the bus around for reads 25211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 17 0.02% 99.91% # Writes before turning the bus around for reads 25311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 4 0.00% 99.92% # Writes before turning the bus around for reads 25411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 4 0.00% 99.92% # Writes before turning the bus around for reads 25511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 32 0.04% 99.96% # Writes before turning the bus around for reads 25611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 13 0.01% 99.97% # Writes before turning the bus around for reads 25711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 6 0.01% 99.98% # Writes before turning the bus around for reads 25811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads 25911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 2 0.00% 99.98% # Writes before turning the bus around for reads 26011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 2 0.00% 99.98% # Writes before turning the bus around for reads 26111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 3 0.00% 99.99% # Writes before turning the bus around for reads 26211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads 26311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 10 0.01% 100.00% # Writes before turning the bus around for reads 26411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 89671 # Writes before turning the bus around for reads 26711860Sandreas.hansson@arm.comsystem.physmem.totQLat 40684785332 # Total ticks spent queuing 26811860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 66170291582 # Total ticks spent from burst creation until serviced by the DRAM 26911860Sandreas.hansson@arm.comsystem.physmem.totBusLat 6796135000 # Total ticks spent in databus transfers 27011860Sandreas.hansson@arm.comsystem.physmem.avgQLat 29932.30 # Average queueing delay per DRAM burst 27110515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27211860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 48682.30 # Average memory access latency per DRAM burst 27311860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s 27411860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.07 # Average achieved write bandwidth in MiByte/s 27511860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.69 # Average system read bandwidth in MiByte/s 27611860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.07 # Average system write bandwidth in MiByte/s 27710515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27811606Sandreas.sandberg@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 27911353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28011860Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 28111103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 28211860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing 28311860Sandreas.hansson@arm.comsystem.physmem.readRowHits 1052962 # Number of row buffer hits during reads 28411860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1223619 # Number of row buffer hits during writes 28511860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 77.47 # Row buffer hit rate for reads 28611860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes 28711860Sandreas.hansson@arm.comsystem.physmem.avgGap 17032031.01 # Average gap between requests 28811860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 28911860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 2732670780 # Energy for activate commands per rank (pJ) 29011860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1452445170 # Energy for precharge commands per rank (pJ) 29111860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4930676940 # Energy for read commands per rank (pJ) 29211860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4399097580 # Energy for write commands per rank (pJ) 29311860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 51881762400.000015 # Energy for refresh commands per rank (pJ) 29411860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 47976087180 # Energy for active background per rank (pJ) 29511860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 3104058720 # Energy for precharge background per rank (pJ) 29611860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 109980529290 # Energy for active power-down per rank (pJ) 29711860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 71485388640 # Energy for precharge power-down per rank (pJ) 29811860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 12273611587950 # Energy for self refresh per rank (pJ) 29911860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 12571576503750 # Total energy per rank (pJ) 30011860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 243.429243 # Core power per rank (mW) 30111860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 51530314812756 # Total Idle time Per DRAM Rank 30211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 5413929000 # Time in different power states 30311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 22045432000 # Time in different power states 30411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 51102968874750 # Time in different power states 30511860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 186159553736 # Time in different power states 30611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 85883432494 # Time in different power states 30711860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 241186429020 # Time in different power states 30811860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 2638872600 # Energy for activate commands per rank (pJ) 30911860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1402590255 # Energy for precharge commands per rank (pJ) 31011860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4774203840 # Energy for read commands per rank (pJ) 31111860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 4316585040 # Energy for write commands per rank (pJ) 31211860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 51214263360.000008 # Energy for refresh commands per rank (pJ) 31311860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 48316306500 # Energy for active background per rank (pJ) 31411860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 3067085280 # Energy for precharge background per rank (pJ) 31511860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 106463182980 # Energy for active power-down per rank (pJ) 31611860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 70942598400 # Energy for precharge power-down per rank (pJ) 31711860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 12275647651350 # Energy for self refresh per rank (pJ) 31811860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 12568805141895 # Total energy per rank (pJ) 31911860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 243.375580 # Core power per rank (mW) 32011860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 51529660585796 # Total Idle time Per DRAM Rank 32111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 5336166484 # Time in different power states 32211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 21762952000 # Time in different power states 32311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 51111446865750 # Time in different power states 32411860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 184746715790 # Time in different power states 32511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 86892179220 # Time in different power states 32611860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 233472771756 # Time in different power states 32711860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 32810636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 32910636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 33010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 33110515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 33210515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 33310636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 33410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 33510515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 33610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 33710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 33910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 34010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 34110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 34210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 34310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 34411860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 34511860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 34611860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 34710585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 34810585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 34910585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 35010585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 35110585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 35210585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 35311860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 230671595 # Number of BP lookups 35411860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 148977251 # Number of conditional branches predicted 35511860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12591272 # Number of conditional branches incorrect 35611860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 161205478 # Number of BTB lookups 35711860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 94166388 # Number of BTB hits 35810585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 35911860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 58.413888 # BTB Hit Percentage 36011860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 32707519 # Number of times the RAS was used to get a target. 36111860Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 2199358 # Number of incorrect RAS predictions. 36211860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 7428890 # Number of indirect predictor lookups. 36311860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 5357971 # Number of indirect target hits. 36411860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 2070919 # Number of indirect misses. 36511860Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 851352 # Number of mispredicted indirect branches. 36610585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 36711860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 36810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 39510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 39610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 39811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 612824 # Table walker walks requested 39911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 612824 # Table walker walks initiated with long descriptors 40011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 25045 # Level at which table walker walks with long descriptors terminate 40111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 213625 # Level at which table walker walks with long descriptors terminate 40211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 612824 # Table walker wait (enqueue to first request) latency 40311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 612824 100.00% 100.00% # Table walker wait (enqueue to first request) latency 40411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 612824 # Table walker wait (enqueue to first request) latency 40511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 238670 # Table walker service (enqueue to completion) latency 40611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 26656.848368 # Table walker service (enqueue to completion) latency 40711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207 # Table walker service (enqueue to completion) latency 40811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726 # Table walker service (enqueue to completion) latency 40911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 235680 98.75% 98.75% # Table walker service (enqueue to completion) latency 41011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 2495 1.05% 99.79% # Table walker service (enqueue to completion) latency 41111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 126 0.05% 99.85% # Table walker service (enqueue to completion) latency 41211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 157 0.07% 99.91% # Table walker service (enqueue to completion) latency 41311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.96% # Table walker service (enqueue to completion) latency 41411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.98% # Table walker service (enqueue to completion) latency 41511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.98% # Table walker service (enqueue to completion) latency 41611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency 41711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 41811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 28 0.01% 100.00% # Table walker service (enqueue to completion) latency 41911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 42011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 42111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 238670 # Table walker service (enqueue to completion) latency 42211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 411876000 # Table walker pending requests distribution 42311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 411876000 100.00% 100.00% # Table walker pending requests distribution 42411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 411876000 # Table walker pending requests distribution 42511860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 213626 89.51% 89.51% # Table walker page sizes translated 42611860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 25045 10.49% 100.00% # Table walker page sizes translated 42711860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 238671 # Table walker page sizes translated 42811860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 612824 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43011860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 612824 # Table walker requests started/completed, data/inst 43111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 238671 # Table walker requests started/completed, data/inst 43210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43311860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 238671 # Table walker requests started/completed, data/inst 43411860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 851495 # Table walker requests started/completed, data/inst 43510585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 43610585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 43711860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 191427667 # DTB read hits 43811860Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 503751 # DTB read misses 43911860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 170371453 # DTB write hits 44011860Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 109073 # DTB write misses 44110585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 44210585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44311860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID 44411860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID 44511860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 82805 # Number of entries that have been flushed from TLB 44611860Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 891 # Number of TLB faults due to alignment restrictions 44711860Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 16210 # Number of TLB faults due to prefetch 44810585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44911860Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 24062 # Number of TLB faults due to permissions restrictions 45011860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 191931418 # DTB read accesses 45111860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 170480526 # DTB write accesses 45210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 45311860Sandreas.hansson@arm.comsystem.cpu.dtb.hits 361799120 # DTB hits 45411860Sandreas.hansson@arm.comsystem.cpu.dtb.misses 612824 # DTB misses 45511860Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 362411944 # DTB accesses 45611860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 45710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 45810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 46210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 46510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 46610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 46810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 47210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 47610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 47710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 47810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 47910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 48611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 48711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 137744 # Table walker walks requested 48811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 137744 # Table walker walks initiated with long descriptors 48911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1060 # Level at which table walker walks with long descriptors terminate 49011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 119122 # Level at which table walker walks with long descriptors terminate 49111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 137744 # Table walker wait (enqueue to first request) latency 49211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 137744 100.00% 100.00% # Table walker wait (enqueue to first request) latency 49311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 137744 # Table walker wait (enqueue to first request) latency 49411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 120182 # Table walker service (enqueue to completion) latency 49511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 28731.482252 # Table walker service (enqueue to completion) latency 49611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 24330.551658 # Table walker service (enqueue to completion) latency 49711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 24049.037609 # Table walker service (enqueue to completion) latency 49811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 116919 97.28% 97.28% # Table walker service (enqueue to completion) latency 49911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 2876 2.39% 99.68% # Table walker service (enqueue to completion) latency 50011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 146 0.12% 99.80% # Table walker service (enqueue to completion) latency 50111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 107 0.09% 99.89% # Table walker service (enqueue to completion) latency 50211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 36 0.03% 99.92% # Table walker service (enqueue to completion) latency 50311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.94% # Table walker service (enqueue to completion) latency 50411860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.94% # Table walker service (enqueue to completion) latency 50511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.95% # Table walker service (enqueue to completion) latency 50611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 64 0.05% 100.00% # Table walker service (enqueue to completion) latency 50711860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 120182 # Table walker service (enqueue to completion) latency 50811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 411203500 # Table walker pending requests distribution 50911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 411203500 100.00% 100.00% # Table walker pending requests distribution 51011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 411203500 # Table walker pending requests distribution 51111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 119122 99.12% 99.12% # Table walker page sizes translated 51211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1060 0.88% 100.00% # Table walker page sizes translated 51311860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 120182 # Table walker page sizes translated 51410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 51511860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 137744 # Table walker requests started/completed, data/inst 51611860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 137744 # Table walker requests started/completed, data/inst 51710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51811860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120182 # Table walker requests started/completed, data/inst 51911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 120182 # Table walker requests started/completed, data/inst 52011860Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 257926 # Table walker requests started/completed, data/inst 52111860Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 367199991 # ITB inst hits 52211860Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 137744 # ITB inst misses 52310585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 52410585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 52510585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 52610585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 52710585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 52810585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52911860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID 53011860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID 53111860Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 59110 # Number of entries that have been flushed from TLB 53210585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 53310585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 53410585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 53511860Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 331525 # Number of TLB faults due to permissions restrictions 53610585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 53710585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 53811860Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 367337735 # ITB inst accesses 53911860Sandreas.hansson@arm.comsystem.cpu.itb.hits 367199991 # DTB hits 54011860Sandreas.hansson@arm.comsystem.cpu.itb.misses 137744 # DTB misses 54111860Sandreas.hansson@arm.comsystem.cpu.itb.accesses 367337735 # DTB accesses 54211860Sandreas.hansson@arm.comsystem.cpu.numPwrStateTransitions 33588 # Number of power state transitions 54311860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::samples 16794 # Distribution of time spent in the clock gated state 54411860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 3006267839.468917 # Distribution of time spent in the clock gated state 54511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 59370181603.459618 # Distribution of time spent in the clock gated state 54611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::underflows 7493 44.62% 44.62% # Distribution of time spent in the clock gated state 54711860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9266 55.17% 99.79% # Distribution of time spent in the clock gated state 54811530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 54911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.84% # Distribution of time spent in the clock gated state 55011860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 55111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 55211530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 55311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 55411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 55511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 55611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 55711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 55811570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 55911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988777658384 # Distribution of time spent in the clock gated state 56011860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::total 16794 # Distribution of time spent in the clock gated state 56111860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1156395554959 # Cumulative time (in ticks) in various power states 56211860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041 # Cumulative time (in ticks) in various power states 56311860Sandreas.hansson@arm.comsystem.cpu.numCycles 2312845645 # number of cpu cycles simulated 56410585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56510585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 56611860Sandreas.hansson@arm.comsystem.cpu.committedInsts 905689769 # Number of instructions committed 56711860Sandreas.hansson@arm.comsystem.cpu.committedOps 1079705427 # Number of ops (including micro ops) committed 56811860Sandreas.hansson@arm.comsystem.cpu.discardedOps 38872378 # Number of ops (including micro ops) which were discarded before commit 56911860Sandreas.hansson@arm.comsystem.cpu.numFetchSuspends 7934 # Number of times Execute suspended instruction fetching 57011860Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 100975614107 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57111860Sandreas.hansson@arm.comsystem.cpu.cpi 2.553684 # CPI: cycles per instruction 57211860Sandreas.hansson@arm.comsystem.cpu.ipc 0.391591 # IPC: instructions per cycle 57311441Sandreas.hansson@arm.comsystem.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 57411860Sandreas.hansson@arm.comsystem.cpu.op_class_0::IntAlu 721452382 66.82% 66.82% # Class of committed instruction 57511860Sandreas.hansson@arm.comsystem.cpu.op_class_0::IntMult 2371003 0.22% 67.04% # Class of committed instruction 57611860Sandreas.hansson@arm.comsystem.cpu.op_class_0::IntDiv 100622 0.01% 67.05% # Class of committed instruction 57711860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatAdd 8 0.00% 67.05% # Class of committed instruction 57811860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatCmp 13 0.00% 67.05% # Class of committed instruction 57911860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatCvt 21 0.00% 67.05% # Class of committed instruction 58011860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 67.05% # Class of committed instruction 58111860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 67.05% # Class of committed instruction 58211860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 67.05% # Class of committed instruction 58311860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 107773 0.01% 67.06% # Class of committed instruction 58411860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 67.06% # Class of committed instruction 58511860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 67.06% # Class of committed instruction 58611860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 67.06% # Class of committed instruction 58711860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 67.06% # Class of committed instruction 58811860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 67.06% # Class of committed instruction 58911860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 67.06% # Class of committed instruction 59011860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 67.06% # Class of committed instruction 59111860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 67.06% # Class of committed instruction 59211860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 67.06% # Class of committed instruction 59311860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 67.06% # Class of committed instruction 59411860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.06% # Class of committed instruction 59511860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 67.06% # Class of committed instruction 59611860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.06% # Class of committed instruction 59711860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.06% # Class of committed instruction 59811860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.06% # Class of committed instruction 59911860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.06% # Class of committed instruction 60011860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.06% # Class of committed instruction 60111860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.06% # Class of committed instruction 60211860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 67.06% # Class of committed instruction 60311860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.06% # Class of committed instruction 60411860Sandreas.hansson@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.06% # Class of committed instruction 60511860Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemRead 185747611 17.20% 84.26% # Class of committed instruction 60611860Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 169152555 15.67% 99.93% # Class of committed instruction 60711860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 112557 0.01% 99.94% # Class of committed instruction 60811860Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 660881 0.06% 100.00% # Class of committed instruction 60911441Sandreas.hansson@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 61011441Sandreas.hansson@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 61111860Sandreas.hansson@arm.comsystem.cpu.op_class_0::total 1079705427 # Class of committed instruction 61210585Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 61311860Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16794 # number of quiesce instructions executed 61411860Sandreas.hansson@arm.comsystem.cpu.tickCycles 1555844114 # Number of cycles that the object actually ticked 61511860Sandreas.hansson@arm.comsystem.cpu.idleCycles 757001531 # Total number of cycles that the object has spent stopped 61611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 61711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 11832637 # number of replacements 61811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.995677 # Cycle average of tags in use 61911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 345046750 # Total number of references to valid blocks. 62011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 11833149 # Sample count of references to valid blocks. 62111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 29.159335 # Average number of references to valid blocks. 62211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 456752500 # Cycle when the warmup percentage was hit. 62311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.995677 # Average occupied blocks per requestor 62411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 62511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999992 # Average percentage of cache occupancy 62610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 62711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 62811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id 62911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 63011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 63110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1449239878 # Number of tag accesses 63311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1449239878 # Number of data accesses 63411860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 63511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 176307264 # number of ReadReq hits 63611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 176307264 # number of ReadReq hits 63711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 158900158 # number of WriteReq hits 63811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 158900158 # number of WriteReq hits 63911860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 537417 # number of SoftPFReq hits 64011860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 537417 # number of SoftPFReq hits 64111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 337852 # number of WriteLineReq hits 64211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 337852 # number of WriteLineReq hits 64311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4300418 # number of LoadLockedReq hits 64411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 4300418 # number of LoadLockedReq hits 64511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 4627725 # number of StoreCondReq hits 64611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 4627725 # number of StoreCondReq hits 64711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 335545274 # number of demand (read+write) hits 64811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 335545274 # number of demand (read+write) hits 64911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 336082691 # number of overall hits 65011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 336082691 # number of overall hits 65111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 6490291 # number of ReadReq misses 65211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 6490291 # number of ReadReq misses 65311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 4646590 # number of WriteReq misses 65411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 4646590 # number of WriteReq misses 65511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1620869 # number of SoftPFReq misses 65611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1620869 # number of SoftPFReq misses 65711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1254011 # number of WriteLineReq misses 65811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1254011 # number of WriteLineReq misses 65911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 329077 # number of LoadLockedReq misses 66011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 329077 # number of LoadLockedReq misses 66111570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 66211570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 66311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 12390892 # number of demand (read+write) misses 66411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 12390892 # number of demand (read+write) misses 66511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 14011761 # number of overall misses 66611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 14011761 # number of overall misses 66711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 114759870500 # number of ReadReq miss cycles 66811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 114759870500 # number of ReadReq miss cycles 66911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 196713087999 # number of WriteReq miss cycles 67011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 196713087999 # number of WriteReq miss cycles 67111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27879484500 # number of WriteLineReq miss cycles 67211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 27879484500 # number of WriteLineReq miss cycles 67311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5348350500 # number of LoadLockedReq miss cycles 67411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 5348350500 # number of LoadLockedReq miss cycles 67511606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles 67611606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles 67711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 339352442999 # number of demand (read+write) miss cycles 67811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 339352442999 # number of demand (read+write) miss cycles 67911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 339352442999 # number of overall miss cycles 68011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 339352442999 # number of overall miss cycles 68111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 182797555 # number of ReadReq accesses(hits+misses) 68211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 182797555 # number of ReadReq accesses(hits+misses) 68311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 163546748 # number of WriteReq accesses(hits+misses) 68411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 163546748 # number of WriteReq accesses(hits+misses) 68511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2158286 # number of SoftPFReq accesses(hits+misses) 68611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2158286 # number of SoftPFReq accesses(hits+misses) 68711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1591863 # number of WriteLineReq accesses(hits+misses) 68811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1591863 # number of WriteLineReq accesses(hits+misses) 68911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 4629495 # number of LoadLockedReq accesses(hits+misses) 69011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 4629495 # number of LoadLockedReq accesses(hits+misses) 69111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 4627726 # number of StoreCondReq accesses(hits+misses) 69211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 4627726 # number of StoreCondReq accesses(hits+misses) 69311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 347936166 # number of demand (read+write) accesses 69411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 347936166 # number of demand (read+write) accesses 69511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 350094452 # number of overall (read+write) accesses 69611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 350094452 # number of overall (read+write) accesses 69711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035505 # miss rate for ReadReq accesses 69811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.035505 # miss rate for ReadReq accesses 69911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028411 # miss rate for WriteReq accesses 70011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.028411 # miss rate for WriteReq accesses 70111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750998 # miss rate for SoftPFReq accesses 70211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.750998 # miss rate for SoftPFReq accesses 70311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787763 # miss rate for WriteLineReq accesses 70411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.787763 # miss rate for WriteLineReq accesses 70511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.071083 # miss rate for LoadLockedReq accesses 70611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.071083 # miss rate for LoadLockedReq accesses 70711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 70811441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 70911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.035613 # miss rate for demand accesses 71011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.035613 # miss rate for demand accesses 71111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.040023 # miss rate for overall accesses 71211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.040023 # miss rate for overall accesses 71311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.775825 # average ReadReq miss latency 71411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17681.775825 # average ReadReq miss latency 71511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42334.935512 # average WriteReq miss latency 71611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 42334.935512 # average WriteReq miss latency 71711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22232.248760 # average WriteLineReq miss latency 71811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 22232.248760 # average WriteLineReq miss latency 71911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16252.580703 # average LoadLockedReq miss latency 72011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16252.580703 # average LoadLockedReq miss latency 72111606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 72211606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 72311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 27387.248876 # average overall miss latency 72411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 27387.248876 # average overall miss latency 72511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 24219.114428 # average overall miss latency 72611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 24219.114428 # average overall miss latency 72711860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked 72810585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72911860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 73010585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 73111860Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked 73210585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73311860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 9058668 # number of writebacks 73411860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 9058668 # number of writebacks 73511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 331345 # number of ReadReq MSHR hits 73611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 331345 # number of ReadReq MSHR hits 73711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 2059664 # number of WriteReq MSHR hits 73811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 2059664 # number of WriteReq MSHR hits 73911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 161 # number of WriteLineReq MSHR hits 74011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 161 # number of WriteLineReq MSHR hits 74111860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 73138 # number of LoadLockedReq MSHR hits 74211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 73138 # number of LoadLockedReq MSHR hits 74311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2391170 # number of demand (read+write) MSHR hits 74411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2391170 # number of demand (read+write) MSHR hits 74511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2391170 # number of overall MSHR hits 74611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2391170 # number of overall MSHR hits 74711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 6158946 # number of ReadReq MSHR misses 74811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 6158946 # number of ReadReq MSHR misses 74911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2586926 # number of WriteReq MSHR misses 75011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2586926 # number of WriteReq MSHR misses 75111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1613436 # number of SoftPFReq MSHR misses 75211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1613436 # number of SoftPFReq MSHR misses 75311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1253850 # number of WriteLineReq MSHR misses 75411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1253850 # number of WriteLineReq MSHR misses 75511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 255939 # number of LoadLockedReq MSHR misses 75611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 255939 # number of LoadLockedReq MSHR misses 75711570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 75811570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 75911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 9999722 # number of demand (read+write) MSHR misses 76011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 9999722 # number of demand (read+write) MSHR misses 76111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 11613158 # number of overall MSHR misses 76211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 11613158 # number of overall MSHR misses 76311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable 76411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33608 # number of ReadReq MSHR uncacheable 76511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable 76611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable 76711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses 76811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67228 # number of overall MSHR uncacheable misses 76911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 101472833000 # number of ReadReq MSHR miss cycles 77011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 101472833000 # number of ReadReq MSHR miss cycles 77111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102652778000 # number of WriteReq MSHR miss cycles 77211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 102652778000 # number of WriteReq MSHR miss cycles 77311860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 27900020500 # number of SoftPFReq MSHR miss cycles 77411860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 27900020500 # number of SoftPFReq MSHR miss cycles 77511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26619580500 # number of WriteLineReq MSHR miss cycles 77611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26619580500 # number of WriteLineReq MSHR miss cycles 77711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3678632000 # number of LoadLockedReq MSHR miss cycles 77811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3678632000 # number of LoadLockedReq MSHR miss cycles 77911606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles 78011606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles 78111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 230745191500 # number of demand (read+write) MSHR miss cycles 78211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 230745191500 # number of demand (read+write) MSHR miss cycles 78311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 258645212000 # number of overall MSHR miss cycles 78411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 258645212000 # number of overall MSHR miss cycles 78511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6209488500 # number of ReadReq MSHR uncacheable cycles 78611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6209488500 # number of ReadReq MSHR uncacheable cycles 78711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6209488500 # number of overall MSHR uncacheable cycles 78811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 6209488500 # number of overall MSHR uncacheable cycles 78911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033693 # mshr miss rate for ReadReq accesses 79011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033693 # mshr miss rate for ReadReq accesses 79111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015818 # mshr miss rate for WriteReq accesses 79211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015818 # mshr miss rate for WriteReq accesses 79311860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.747554 # mshr miss rate for SoftPFReq accesses 79411860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.747554 # mshr miss rate for SoftPFReq accesses 79511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787662 # mshr miss rate for WriteLineReq accesses 79611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787662 # mshr miss rate for WriteLineReq accesses 79711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.055284 # mshr miss rate for LoadLockedReq accesses 79811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055284 # mshr miss rate for LoadLockedReq accesses 79911441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 80011441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 80111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028740 # mshr miss rate for demand accesses 80211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.028740 # mshr miss rate for demand accesses 80311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.033171 # mshr miss rate for overall accesses 80411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.033171 # mshr miss rate for overall accesses 80511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553 # average ReadReq mshr miss latency 80611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553 # average ReadReq mshr miss latency 80711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39681.373955 # average WriteReq mshr miss latency 80811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39681.373955 # average WriteReq mshr miss latency 80911860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17292.300717 # average SoftPFReq mshr miss latency 81011860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717 # average SoftPFReq mshr miss latency 81111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153 # average WriteLineReq mshr miss latency 81211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153 # average WriteLineReq mshr miss latency 81311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14373.081086 # average LoadLockedReq mshr miss latency 81411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14373.081086 # average LoadLockedReq mshr miss latency 81511606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 81611606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 81711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23075.160639 # average overall mshr miss latency 81811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639 # average overall mshr miss latency 81911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22271.737972 # average overall mshr miss latency 82011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22271.737972 # average overall mshr miss latency 82111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184762.214354 # average ReadReq mshr uncacheable latency 82211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184762.214354 # average ReadReq mshr uncacheable latency 82311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92364.617421 # average overall mshr uncacheable latency 82411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421 # average overall mshr uncacheable latency 82511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 82611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 25121901 # number of replacements 82711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.967924 # Cycle average of tags in use 82811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 341735076 # Total number of references to valid blocks. 82911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 25122413 # Sample count of references to valid blocks. 83011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 13.602797 # Average number of references to valid blocks. 83111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 17226930500 # Cycle when the warmup percentage was hit. 83211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.967924 # Average occupied blocks per requestor 83311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999937 # Average percentage of cache occupancy 83411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999937 # Average percentage of cache occupancy 83510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 83611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 83711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 83811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 83910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 391979921 # Number of tag accesses 84111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 391979921 # Number of data accesses 84211860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 84311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 341735076 # number of ReadReq hits 84411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 341735076 # number of ReadReq hits 84511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 341735076 # number of demand (read+write) hits 84611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 341735076 # number of demand (read+write) hits 84711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 341735076 # number of overall hits 84811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 341735076 # number of overall hits 84911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 25122423 # number of ReadReq misses 85011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 25122423 # number of ReadReq misses 85111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 25122423 # number of demand (read+write) misses 85211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 25122423 # number of demand (read+write) misses 85311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 25122423 # number of overall misses 85411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 25122423 # number of overall misses 85511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 337360587000 # number of ReadReq miss cycles 85611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 337360587000 # number of ReadReq miss cycles 85711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 337360587000 # number of demand (read+write) miss cycles 85811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 337360587000 # number of demand (read+write) miss cycles 85911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 337360587000 # number of overall miss cycles 86011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 337360587000 # number of overall miss cycles 86111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 366857499 # number of ReadReq accesses(hits+misses) 86211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 366857499 # number of ReadReq accesses(hits+misses) 86311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 366857499 # number of demand (read+write) accesses 86411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 366857499 # number of demand (read+write) accesses 86511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 366857499 # number of overall (read+write) accesses 86611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 366857499 # number of overall (read+write) accesses 86711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.068480 # miss rate for ReadReq accesses 86811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.068480 # miss rate for ReadReq accesses 86911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.068480 # miss rate for demand accesses 87011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.068480 # miss rate for demand accesses 87111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.068480 # miss rate for overall accesses 87211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.068480 # miss rate for overall accesses 87311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13428.664385 # average ReadReq miss latency 87411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13428.664385 # average ReadReq miss latency 87511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency 87611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13428.664385 # average overall miss latency 87711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency 87811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13428.664385 # average overall miss latency 87910585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 88010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 88310585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 88410585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88511860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 25121901 # number of writebacks 88611860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 25121901 # number of writebacks 88711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 25122423 # number of ReadReq MSHR misses 88811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 25122423 # number of ReadReq MSHR misses 88911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 25122423 # number of demand (read+write) MSHR misses 89011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 25122423 # number of demand (read+write) MSHR misses 89111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 25122423 # number of overall MSHR misses 89211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 25122423 # number of overall MSHR misses 89311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable 89411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 4291 # number of ReadReq MSHR uncacheable 89511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses 89611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 4291 # number of overall MSHR uncacheable misses 89711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312238165000 # number of ReadReq MSHR miss cycles 89811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 312238165000 # number of ReadReq MSHR miss cycles 89911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 312238165000 # number of demand (read+write) MSHR miss cycles 90011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 312238165000 # number of demand (read+write) MSHR miss cycles 90111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 312238165000 # number of overall MSHR miss cycles 90211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 312238165000 # number of overall MSHR miss cycles 90311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 366344000 # number of ReadReq MSHR uncacheable cycles 90411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 366344000 # number of ReadReq MSHR uncacheable cycles 90511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 366344000 # number of overall MSHR uncacheable cycles 90611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 366344000 # number of overall MSHR uncacheable cycles 90711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for ReadReq accesses 90811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.068480 # mshr miss rate for ReadReq accesses 90911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for demand accesses 91011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses 91111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for overall accesses 91211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses 91311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12428.664425 # average ReadReq mshr miss latency 91411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12428.664425 # average ReadReq mshr miss latency 91511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency 91611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency 91711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency 91811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency 91911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average ReadReq mshr uncacheable latency 92011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85374.970869 # average ReadReq mshr uncacheable latency 92111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average overall mshr uncacheable latency 92211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85374.970869 # average overall mshr uncacheable latency 92311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 92411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1823253 # number of replacements 92511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65445.001874 # Cycle average of tags in use 92611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 72021344 # Total number of references to valid blocks. 92711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1886697 # Sample count of references to valid blocks. 92811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 38.173244 # Average number of references to valid blocks. 92911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 2050526000 # Cycle when the warmup percentage was hit. 93011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9044.623983 # Average occupied blocks per requestor 93111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 456.585654 # Average occupied blocks per requestor 93211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 458.430752 # Average occupied blocks per requestor 93311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7955.769070 # Average occupied blocks per requestor 93411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 47529.592416 # Average occupied blocks per requestor 93511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.138010 # Average percentage of cache occupancy 93611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006967 # Average percentage of cache occupancy 93711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006995 # Average percentage of cache occupancy 93811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.121395 # Average percentage of cache occupancy 93911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.725244 # Average percentage of cache occupancy 94011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998611 # Average percentage of cache occupancy 94111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id 94211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63208 # Occupied blocks per task id 94311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 94411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id 94511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 94611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 94711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id 94811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5962 # Occupied blocks per task id 94911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 56005 # Occupied blocks per task id 95011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 95111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.964478 # Percentage of cache occupancy per task id 95211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 604501194 # Number of tag accesses 95311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 604501194 # Number of data accesses 95411860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 95511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1016248 # number of ReadReq hits 95611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 265268 # number of ReadReq hits 95711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1281516 # number of ReadReq hits 95811860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 9058668 # number of WritebackDirty hits 95911860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 9058668 # number of WritebackDirty hits 96011860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 25118324 # number of WritebackClean hits 96111860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 25118324 # number of WritebackClean hits 96211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 31922 # number of UpgradeReq hits 96311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 31922 # number of UpgradeReq hits 96411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1691397 # number of ReadExReq hits 96511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1691397 # number of ReadExReq hits 96611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 25012596 # number of ReadCleanReq hits 96711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 25012596 # number of ReadCleanReq hits 96811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 7660453 # number of ReadSharedReq hits 96911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 7660453 # number of ReadSharedReq hits 97011860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 687915 # number of InvalidateReq hits 97111860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 687915 # number of InvalidateReq hits 97211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 1016248 # number of demand (read+write) hits 97311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 265268 # number of demand (read+write) hits 97411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 25012596 # number of demand (read+write) hits 97511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 9351850 # number of demand (read+write) hits 97611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 35645962 # number of demand (read+write) hits 97711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 1016248 # number of overall hits 97811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 265268 # number of overall hits 97911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 25012596 # number of overall hits 98011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 9351850 # number of overall hits 98111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 35645962 # number of overall hits 98211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7529 # number of ReadReq misses 98311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6105 # number of ReadReq misses 98411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 13634 # number of ReadReq misses 98511860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 3989 # number of UpgradeReq misses 98611860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 3989 # number of UpgradeReq misses 98711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 98811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 98911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 859845 # number of ReadExReq misses 99011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 859845 # number of ReadExReq misses 99111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 109826 # number of ReadCleanReq misses 99211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 109826 # number of ReadCleanReq misses 99311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 367641 # number of ReadSharedReq misses 99411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 367641 # number of ReadSharedReq misses 99511860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 565935 # number of InvalidateReq misses 99611860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 565935 # number of InvalidateReq misses 99711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7529 # number of demand (read+write) misses 99811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 6105 # number of demand (read+write) misses 99911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 109826 # number of demand (read+write) misses 100011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1227486 # number of demand (read+write) misses 100111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1350946 # number of demand (read+write) misses 100211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7529 # number of overall misses 100311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 6105 # number of overall misses 100411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 109826 # number of overall misses 100511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1227486 # number of overall misses 100611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1350946 # number of overall misses 100711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 877005000 # number of ReadReq miss cycles 100811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 644825000 # number of ReadReq miss cycles 100911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 1521830000 # number of ReadReq miss cycles 101011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72113000 # number of UpgradeReq miss cycles 101111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 72113000 # number of UpgradeReq miss cycles 101211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles 101311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles 101411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80528268500 # number of ReadExReq miss cycles 101511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 80528268500 # number of ReadExReq miss cycles 101611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11692993000 # number of ReadCleanReq miss cycles 101711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 11692993000 # number of ReadCleanReq miss cycles 101811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40327835000 # number of ReadSharedReq miss cycles 101911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 40327835000 # number of ReadSharedReq miss cycles 102011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 877005000 # number of demand (read+write) miss cycles 102111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 644825000 # number of demand (read+write) miss cycles 102211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11692993000 # number of demand (read+write) miss cycles 102311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 120856103500 # number of demand (read+write) miss cycles 102411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 134070926500 # number of demand (read+write) miss cycles 102511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 877005000 # number of overall miss cycles 102611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 644825000 # number of overall miss cycles 102711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11692993000 # number of overall miss cycles 102811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 120856103500 # number of overall miss cycles 102911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 134070926500 # number of overall miss cycles 103011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1023777 # number of ReadReq accesses(hits+misses) 103111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 271373 # number of ReadReq accesses(hits+misses) 103211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1295150 # number of ReadReq accesses(hits+misses) 103311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 9058668 # number of WritebackDirty accesses(hits+misses) 103411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 9058668 # number of WritebackDirty accesses(hits+misses) 103511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 25118324 # number of WritebackClean accesses(hits+misses) 103611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 25118324 # number of WritebackClean accesses(hits+misses) 103711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 35911 # number of UpgradeReq accesses(hits+misses) 103811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 35911 # number of UpgradeReq accesses(hits+misses) 103911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 104011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 104111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2551242 # number of ReadExReq accesses(hits+misses) 104211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2551242 # number of ReadExReq accesses(hits+misses) 104311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25122422 # number of ReadCleanReq accesses(hits+misses) 104411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 25122422 # number of ReadCleanReq accesses(hits+misses) 104511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8028094 # number of ReadSharedReq accesses(hits+misses) 104611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 8028094 # number of ReadSharedReq accesses(hits+misses) 104711860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253850 # number of InvalidateReq accesses(hits+misses) 104811860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1253850 # number of InvalidateReq accesses(hits+misses) 104911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 1023777 # number of demand (read+write) accesses 105011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 271373 # number of demand (read+write) accesses 105111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 25122422 # number of demand (read+write) accesses 105211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 10579336 # number of demand (read+write) accesses 105311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 36996908 # number of demand (read+write) accesses 105411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 1023777 # number of overall (read+write) accesses 105511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 271373 # number of overall (read+write) accesses 105611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 25122422 # number of overall (read+write) accesses 105711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 10579336 # number of overall (read+write) accesses 105811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 36996908 # number of overall (read+write) accesses 105911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007354 # miss rate for ReadReq accesses 106011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses 106111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.010527 # miss rate for ReadReq accesses 106211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.111080 # miss rate for UpgradeReq accesses 106311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.111080 # miss rate for UpgradeReq accesses 106410636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 106510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 106611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.337030 # miss rate for ReadExReq accesses 106711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.337030 # miss rate for ReadExReq accesses 106811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004372 # miss rate for ReadCleanReq accesses 106911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004372 # miss rate for ReadCleanReq accesses 107011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045794 # miss rate for ReadSharedReq accesses 107111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045794 # miss rate for ReadSharedReq accesses 107211860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.451358 # miss rate for InvalidateReq accesses 107311860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.451358 # miss rate for InvalidateReq accesses 107411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007354 # miss rate for demand accesses 107511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses 107611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.004372 # miss rate for demand accesses 107711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.116027 # miss rate for demand accesses 107811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.036515 # miss rate for demand accesses 107911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007354 # miss rate for overall accesses 108011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses 108111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.004372 # miss rate for overall accesses 108211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.116027 # miss rate for overall accesses 108311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.036515 # miss rate for overall accesses 108411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 116483.596759 # average ReadReq miss latency 108511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 105622.440622 # average ReadReq miss latency 108611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 111620.214170 # average ReadReq miss latency 108711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18077.964402 # average UpgradeReq miss latency 108811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18077.964402 # average UpgradeReq miss latency 108911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 109011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency 109111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93654.401084 # average ReadExReq miss latency 109211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 93654.401084 # average ReadExReq miss latency 109311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106468.349935 # average ReadCleanReq miss latency 109411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106468.349935 # average ReadCleanReq miss latency 109511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109693.518949 # average ReadSharedReq miss latency 109611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109693.518949 # average ReadSharedReq miss latency 109711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 116483.596759 # average overall miss latency 109811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 105622.440622 # average overall miss latency 109911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106468.349935 # average overall miss latency 110011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 98458.233740 # average overall miss latency 110111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 99242.254317 # average overall miss latency 110211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 116483.596759 # average overall miss latency 110311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 105622.440622 # average overall miss latency 110411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106468.349935 # average overall miss latency 110511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 98458.233740 # average overall miss latency 110611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 99242.254317 # average overall miss latency 110710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 110910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111311860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 1562747 # number of writebacks 111411860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 1562747 # number of writebacks 111511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 111611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 111711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 111811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits 111911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 112011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 112111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 112211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 112311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 112411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 112511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7529 # number of ReadReq MSHR misses 112611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6105 # number of ReadReq MSHR misses 112711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 13634 # number of ReadReq MSHR misses 112811860Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 112911860Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 113011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3989 # number of UpgradeReq MSHR misses 113111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 3989 # number of UpgradeReq MSHR misses 113211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 113311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 113411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 859845 # number of ReadExReq MSHR misses 113511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 859845 # number of ReadExReq MSHR misses 113611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 109824 # number of ReadCleanReq MSHR misses 113711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 109824 # number of ReadCleanReq MSHR misses 113811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 367619 # number of ReadSharedReq MSHR misses 113911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 367619 # number of ReadSharedReq MSHR misses 114011860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 565935 # number of InvalidateReq MSHR misses 114111860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::total 565935 # number of InvalidateReq MSHR misses 114211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7529 # number of demand (read+write) MSHR misses 114311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6105 # number of demand (read+write) MSHR misses 114411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 109824 # number of demand (read+write) MSHR misses 114511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1227464 # number of demand (read+write) MSHR misses 114611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 1350922 # number of demand (read+write) MSHR misses 114711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7529 # number of overall MSHR misses 114811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6105 # number of overall MSHR misses 114911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 109824 # number of overall MSHR misses 115011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1227464 # number of overall MSHR misses 115111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 1350922 # number of overall MSHR misses 115211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable 115311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable 115411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 37899 # number of ReadReq MSHR uncacheable 115511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable 115611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable 115711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses 115811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses 115911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 71519 # number of overall MSHR uncacheable misses 116011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 801715000 # number of ReadReq MSHR miss cycles 116111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 583775000 # number of ReadReq MSHR miss cycles 116211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1385490000 # number of ReadReq MSHR miss cycles 116311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76139500 # number of UpgradeReq MSHR miss cycles 116411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76139500 # number of UpgradeReq MSHR miss cycles 116511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles 116611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles 116711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 71929817502 # number of ReadExReq MSHR miss cycles 116811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 71929817502 # number of ReadExReq MSHR miss cycles 116911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10594574503 # number of ReadCleanReq MSHR miss cycles 117011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10594574503 # number of ReadCleanReq MSHR miss cycles 117111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36650353047 # number of ReadSharedReq MSHR miss cycles 117211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36650353047 # number of ReadSharedReq MSHR miss cycles 117311860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11657372001 # number of InvalidateReq MSHR miss cycles 117411860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11657372001 # number of InvalidateReq MSHR miss cycles 117511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 801715000 # number of demand (read+write) MSHR miss cycles 117611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 583775000 # number of demand (read+write) MSHR miss cycles 117711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10594574503 # number of demand (read+write) MSHR miss cycles 117811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108580170549 # number of demand (read+write) MSHR miss cycles 117911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 120560235052 # number of demand (read+write) MSHR miss cycles 118011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 801715000 # number of overall MSHR miss cycles 118111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 583775000 # number of overall MSHR miss cycles 118211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10594574503 # number of overall MSHR miss cycles 118311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549 # number of overall MSHR miss cycles 118411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 120560235052 # number of overall MSHR miss cycles 118511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 299820000 # number of ReadReq MSHR uncacheable cycles 118611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5789264500 # number of ReadReq MSHR uncacheable cycles 118711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6089084500 # number of ReadReq MSHR uncacheable cycles 118811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 299820000 # number of overall MSHR uncacheable cycles 118911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5789264500 # number of overall MSHR uncacheable cycles 119011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 6089084500 # number of overall MSHR uncacheable cycles 119111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for ReadReq accesses 119211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for ReadReq accesses 119311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadReq accesses 119410892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 119510892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 119611860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111080 # mshr miss rate for UpgradeReq accesses 119711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111080 # mshr miss rate for UpgradeReq accesses 119810636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 119910585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 120011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.337030 # mshr miss rate for ReadExReq accesses 120111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.337030 # mshr miss rate for ReadExReq accesses 120211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for ReadCleanReq accesses 120311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004372 # mshr miss rate for ReadCleanReq accesses 120411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045792 # mshr miss rate for ReadSharedReq accesses 120511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045792 # mshr miss rate for ReadSharedReq accesses 120611860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.451358 # mshr miss rate for InvalidateReq accesses 120711860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.451358 # mshr miss rate for InvalidateReq accesses 120811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for demand accesses 120911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for demand accesses 121011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for demand accesses 121111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for demand accesses 121211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.036514 # mshr miss rate for demand accesses 121311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for overall accesses 121411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for overall accesses 121511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for overall accesses 121611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for overall accesses 121711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.036514 # mshr miss rate for overall accesses 121811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average ReadReq mshr miss latency 121911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average ReadReq mshr miss latency 122011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170 # average ReadReq mshr miss latency 122111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254 # average UpgradeReq mshr miss latency 122211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254 # average UpgradeReq mshr miss latency 122311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 122411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 122511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923 # average ReadExReq mshr miss latency 122611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923 # average ReadExReq mshr miss latency 122711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525 # average ReadCleanReq mshr miss latency 122811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525 # average ReadCleanReq mshr miss latency 122911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130 # average ReadSharedReq mshr miss latency 123011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130 # average ReadSharedReq mshr miss latency 123111860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150 # average InvalidateReq mshr miss latency 123211860Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150 # average InvalidateReq mshr miss latency 123311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency 123411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency 123511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency 123611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency 123711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency 123811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency 123911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency 124011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency 124111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency 124211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency 124311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average ReadReq mshr uncacheable latency 124411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756 # average ReadReq mshr uncacheable latency 124511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369 # average ReadReq mshr uncacheable latency 124611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average overall mshr uncacheable latency 124711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558 # average overall mshr uncacheable latency 124811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524 # average overall mshr uncacheable latency 124911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 74678701 # Total number of requests made to the snoop filter. 125011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 37723093 # Number of requests hitting in the snoop filter with a single holder of the requested data. 125111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4208 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 125211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1985 # Total number of snoops made to the snoop filter. 125311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1985 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 125411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 125511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 125611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1826986 # Transaction distribution 125711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 34978302 # Transaction distribution 125811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33620 # Transaction distribution 125911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33620 # Transaction distribution 126011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 10621415 # Transaction distribution 126111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 25121901 # Transaction distribution 126211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 3034475 # Transaction distribution 126311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 35914 # Transaction distribution 126411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 126511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 35915 # Transaction distribution 126611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2551242 # Transaction distribution 126711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2551242 # Transaction distribution 126811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 25122423 # Transaction distribution 126911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 8030982 # Transaction distribution 127011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1284314 # Transaction distribution 127111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1253880 # Transaction distribution 127211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75375327 # Packet count per connected master and slave (bytes) 127311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35706122 # Packet count per connected master and slave (bytes) 127411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 683214 # Packet count per connected master and slave (bytes) 127511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2401023 # Packet count per connected master and slave (bytes) 127611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 114165686 # Packet count per connected master and slave (bytes) 127711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3215911232 # Cumulative packet size per connected master and slave (bytes) 127811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1257073518 # Cumulative packet size per connected master and slave (bytes) 127911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2170984 # Cumulative packet size per connected master and slave (bytes) 128011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 8190216 # Cumulative packet size per connected master and slave (bytes) 128111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 4483345950 # Cumulative packet size per connected master and slave (bytes) 128211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 2351379 # Total snoops (count) 128311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 104018568 # Total snoop traffic (bytes) 128411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 40708735 # Request fanout histogram 128511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.018149 # Request fanout histogram 128611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.133491 # Request fanout histogram 128710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 128811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 39969899 98.19% 98.19% # Request fanout histogram 128911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 738836 1.81% 100.00% # Request fanout histogram 129011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 129110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 129211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 129311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 129411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 40708735 # Request fanout histogram 129511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 72100713496 # Layer occupancy (ticks) 129610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 129711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1533365 # Layer occupancy (ticks) 129810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 129911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 37694541038 # Layer occupancy (ticks) 130010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 130111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 16565349400 # Layer occupancy (ticks) 130210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 130311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 411872936 # Layer occupancy (ticks) 130410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 130511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1377265960 # Layer occupancy (ticks) 130610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 130711860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 130811860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40237 # Transaction distribution 130911860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40237 # Transaction distribution 131011860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136485 # Transaction distribution 131111860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136485 # Transaction distribution 131211860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) 131310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 131411245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 131510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 131610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 131710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 131810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 131910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 132010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 132110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 132210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 132310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 132410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 132511860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) 132611860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) 132711860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) 132810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 132910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 133011860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353444 # Packet count per connected master and slave (bytes) 133111860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) 133210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 133311245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 133410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 133510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 133610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 133710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 133810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 133910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 134010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 134110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 134210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 134310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 134411860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) 134511860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) 134611860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) 134710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 134810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 134911860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) 135011860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 37126500 # Layer occupancy (ticks) 135110585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 135211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 135310585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 135411860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) 135510585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 135611860Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 135710585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 135811680SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 135911245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 136011680SCurtis.Dunham@arm.comsystem.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 136110585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 136211680SCurtis.Dunham@arm.comsystem.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 136310585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 136411680SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 136510585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 136611860Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 136710585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 136811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 136910585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 137011860Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 137110585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 137211860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25225000 # Layer occupancy (ticks) 137310585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 137411860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36490500 # Layer occupancy (ticks) 137510585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 137611860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 569036756 # Layer occupancy (ticks) 137710585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 137811860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) 137910585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 138011860Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) 138110585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 138210892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 138310585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 138411860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 138511860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115484 # number of replacements 138611860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.444243 # Cycle average of tags in use 138710585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 138811860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 138910585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 139011860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13137487927000 # Cycle when the warmup percentage was hit. 139111860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 5.867221 # Average occupied blocks per requestor 139211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 4.577022 # Average occupied blocks per requestor 139311860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.366701 # Average percentage of cache occupancy 139411860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.286064 # Average percentage of cache occupancy 139511860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.652765 # Average percentage of cache occupancy 139610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 139710585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 139810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 139911860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039875 # Number of tag accesses 140011860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039875 # Number of data accesses 140111860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 140210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 140311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses 140411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8875 # number of ReadReq misses 140510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 140610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 140710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 140810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 140910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 141011860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115502 # number of demand (read+write) misses 141111860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115542 # number of demand (read+write) misses 141210585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 141311860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115502 # number of overall misses 141411860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115542 # number of overall misses 141511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 141611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 2014766150 # number of ReadReq miss cycles 141711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 2019852150 # number of ReadReq miss cycles 141810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 141910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 142011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13376583606 # number of WriteLineReq miss cycles 142111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13376583606 # number of WriteLineReq miss cycles 142211860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 142311860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15391349756 # number of demand (read+write) miss cycles 142411860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15396786756 # number of demand (read+write) miss cycles 142511860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 142611860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15391349756 # number of overall miss cycles 142711860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15396786756 # number of overall miss cycles 142810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 142911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) 143011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) 143110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 143210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 143310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 143410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 143510585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 143611860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115502 # number of demand (read+write) accesses 143711860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115542 # number of demand (read+write) accesses 143810585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 143911860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115502 # number of overall (read+write) accesses 144011860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115542 # number of overall (read+write) accesses 144110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 144210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 144310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 144410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 144510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 144610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 144710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 144810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 144910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 145010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 145110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 145210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 145310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 145411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 145511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936 # average ReadReq miss latency 145611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 227588.974648 # average ReadReq miss latency 145710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 145810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 145911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521 # average WriteLineReq miss latency 146011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125408.606521 # average WriteLineReq miss latency 146111860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 146211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency 146311860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 133257.055928 # average overall miss latency 146411860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 146511860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency 146611860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 133257.055928 # average overall miss latency 146711860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 51744 # number of cycles access was blocked 146810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 146911860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3369 # number of cycles access was blocked 147010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 147111860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 15.358860 # average number of cycles each access was blocked 147210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 147311570SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106631 # number of writebacks 147411570SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106631 # number of writebacks 147510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 147611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses 147711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses 147810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 147910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 148010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 148110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 148210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 148311860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115502 # number of demand (read+write) MSHR misses 148411860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115542 # number of demand (read+write) MSHR misses 148510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 148611860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115502 # number of overall MSHR misses 148711860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115542 # number of overall MSHR misses 148811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 148911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1572866150 # number of ReadReq MSHR miss cycles 149011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1576102150 # number of ReadReq MSHR miss cycles 149110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 149210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 149311860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8037847459 # number of WriteLineReq MSHR miss cycles 149411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8037847459 # number of WriteLineReq MSHR miss cycles 149511860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 149611860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9610713609 # number of demand (read+write) MSHR miss cycles 149711860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9614150609 # number of demand (read+write) MSHR miss cycles 149811860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 149911860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9610713609 # number of overall MSHR miss cycles 150011860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9614150609 # number of overall MSHR miss cycles 150110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 150210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 150310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 150410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 150510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 150610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 150710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 150810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 150910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 151010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 151110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 151210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 151310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 151411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 151511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936 # average ReadReq mshr miss latency 151611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648 # average ReadReq mshr miss latency 151710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 151810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 151911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846 # average WriteLineReq mshr miss latency 152011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846 # average WriteLineReq mshr miss latency 152111860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 152211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency 152311860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency 152411860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 152511860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency 152611860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency 152711860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 3974449 # Total number of requests made to the snoop filter. 152811860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 1973040 # Number of requests hitting in the snoop filter with a single holder of the requested data. 152911860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 153011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 153111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 153211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 153311860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 153411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 37899 # Transaction distribution 153511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 537851 # Transaction distribution 153611860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33620 # Transaction distribution 153711860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33620 # Transaction distribution 153811860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1669378 # Transaction distribution 153911860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 268224 # Transaction distribution 154011860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 4552 # Transaction distribution 154111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 154211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 7 # Transaction distribution 154311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 859285 # Transaction distribution 154411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 859285 # Transaction distribution 154511860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 499952 # Transaction distribution 154611860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 672599 # Transaction distribution 154711860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 30234 # Transaction distribution 154811860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) 154910515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 155011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6910 # Packet count per connected master and slave (bytes) 155111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5106407 # Packet count per connected master and slave (bytes) 155211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 5235709 # Packet count per connected master and slave (bytes) 155311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237223 # Packet count per connected master and slave (bytes) 155411860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237223 # Packet count per connected master and slave (bytes) 155511860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5472932 # Packet count per connected master and slave (bytes) 155611860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) 155710515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 155811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13820 # Cumulative packet size per connected master and slave (bytes) 155911860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186691628 # Cumulative packet size per connected master and slave (bytes) 156011860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 186861678 # Cumulative packet size per connected master and slave (bytes) 156111860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220992 # Cumulative packet size per connected master and slave (bytes) 156211860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7220992 # Cumulative packet size per connected master and slave (bytes) 156311860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 194082670 # Cumulative packet size per connected master and slave (bytes) 156411860Sandreas.hansson@arm.comsystem.membus.snoops 33575 # Total snoops (count) 156511860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 213376 # Total snoop traffic (bytes) 156611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2107909 # Request fanout histogram 156711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.016147 # Request fanout histogram 156811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.126040 # Request fanout histogram 156910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 157011860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2073873 98.39% 98.39% # Request fanout histogram 157111860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 34036 1.61% 100.00% # Request fanout histogram 157210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 157310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 157411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 157510515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 157611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2107909 # Request fanout histogram 157711860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 99276000 # Layer occupancy (ticks) 157810515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 157911570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) 158010515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 158111860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5601000 # Layer occupancy (ticks) 158210515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 158311860Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 10934593718 # Layer occupancy (ticks) 158410515SAli.Saidi@ARM.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 158511860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 7287611424 # Layer occupancy (ticks) 158610515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 158711860Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 76573457 # Layer occupancy (ticks) 158810515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 158911860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159011860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159111860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159211860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159311860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159411860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159511860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 159611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 159711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 159811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 159911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 160011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 160111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 160211860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 160311860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 160410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 160510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 160610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 160710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 160810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 160910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 161010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 161110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 161210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 161311138Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 161410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 161510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 161610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 161711138Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 161810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 161910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 162010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 162110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 162210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 162310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 162410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 162510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 162610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 162710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 162810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 162910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 163010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 163110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 163210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 163310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 163410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 163510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 163610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 163710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 163810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 163910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 164010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 164110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 164210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 164310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 164410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 164510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 164611860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 164711860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 164811860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 164911860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165011860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165111860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165211860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 165411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 165511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 165611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 165711860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165811860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 165911860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166011860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166111860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166211860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166311860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166411860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166511860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166611860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166711860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166811860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 166910515SAli.Saidi@ARM.com 167010515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1671