stats.txt revision 11754
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311754Sandreas.hansson@arm.comsim_seconds 47.356210 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 47356210126000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 47356210126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 269105 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 316551 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 14489745940 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 771556 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 3268.26 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 879504495 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 1034569807 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 139968 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 127936 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 7960960 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 14481160 # Number of bytes read from this memory 2111754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 15033920 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 105216 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 97088 # Number of bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3386304 # Number of bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 9267600 # Number of bytes read from this memory 2611754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 11152448 # Number of bytes read from this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 451392 # Number of bytes read from this memory 2811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 62203992 # Number of bytes read from this memory 2911754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 7960960 # Number of instructions bytes read from this memory 3011754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3386304 # Number of instructions bytes read from this memory 3111754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 11347264 # Number of instructions bytes read from this memory 3211754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 74964928 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 74985512 # Number of bytes written to this memory 3611754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2187 # Number of read requests responded to by this memory 3711754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1999 # Number of read requests responded to by this memory 3811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 124390 # Number of read requests responded to by this memory 3911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 226281 # Number of read requests responded to by this memory 4011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 234905 # Number of read requests responded to by this memory 4111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1644 # Number of read requests responded to by this memory 4211754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1517 # Number of read requests responded to by this memory 4311754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 52911 # Number of read requests responded to by this memory 4411754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 144819 # Number of read requests responded to by this memory 4511754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 174257 # Number of read requests responded to by this memory 4611754Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 7053 # Number of read requests responded to by this memory 4711754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 971963 # Number of read requests responded to by this memory 4811754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1171327 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1173901 # Number of write requests responded to by this memory 5211754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2702 # Total read bandwidth from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 168108 # Total read bandwidth from this memory (bytes/s) 5511754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 305792 # Total read bandwidth from this memory (bytes/s) 5611754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 317465 # Total read bandwidth from this memory (bytes/s) 5711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2222 # Total read bandwidth from this memory (bytes/s) 5811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2050 # Total read bandwidth from this memory (bytes/s) 5911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 71507 # Total read bandwidth from this memory (bytes/s) 6011754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 195700 # Total read bandwidth from this memory (bytes/s) 6111754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 235501 # Total read bandwidth from this memory (bytes/s) 6211754Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9532 # Total read bandwidth from this memory (bytes/s) 6311754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1313534 # Total read bandwidth from this memory (bytes/s) 6411754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 168108 # Instruction read bandwidth from this memory (bytes/s) 6511754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 71507 # Instruction read bandwidth from this memory (bytes/s) 6611754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 239615 # Instruction read bandwidth from this memory (bytes/s) 6711754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1583001 # Write bandwidth from this memory (bytes/s) 6811754Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6910636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1583436 # Write bandwidth from this memory (bytes/s) 7111754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1583001 # Total bandwidth to/from this memory (bytes/s) 7211754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) 7311754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2702 # Total bandwidth to/from this memory (bytes/s) 7411754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 168108 # Total bandwidth to/from this memory (bytes/s) 7511754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 306227 # Total bandwidth to/from this memory (bytes/s) 7611754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 317465 # Total bandwidth to/from this memory (bytes/s) 7711754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2222 # Total bandwidth to/from this memory (bytes/s) 7811754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2050 # Total bandwidth to/from this memory (bytes/s) 7911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 71507 # Total bandwidth to/from this memory (bytes/s) 8011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 195700 # Total bandwidth to/from this memory (bytes/s) 8111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 235501 # Total bandwidth to/from this memory (bytes/s) 8211754Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9532 # Total bandwidth to/from this memory (bytes/s) 8311754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2896970 # Total bandwidth to/from this memory (bytes/s) 8411754Sandreas.hansson@arm.comsystem.physmem.readReqs 971963 # Number of read requests accepted 8511754Sandreas.hansson@arm.comsystem.physmem.writeReqs 1173901 # Number of write requests accepted 8611754Sandreas.hansson@arm.comsystem.physmem.readBursts 971963 # Number of DRAM read bursts, including those serviced by the write queue 8711754Sandreas.hansson@arm.comsystem.physmem.writeBursts 1173901 # Number of DRAM write bursts, including those merged in the write queue 8811754Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 62180096 # Total number of bytes read from DRAM 8911754Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 25536 # Total number of bytes read from write queue 9011754Sandreas.hansson@arm.comsystem.physmem.bytesWritten 74984000 # Total number of bytes written to DRAM 9111754Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 62203992 # Total read bytes from the system interface side 9211754Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 74985512 # Total written bytes from the system interface side 9311754Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 399 # Number of DRAM read bursts serviced by the write queue 9411754Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 55033 # Per bank write bursts 9711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 62597 # Per bank write bursts 9811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 50092 # Per bank write bursts 9911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 57292 # Per bank write bursts 10011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 55886 # Per bank write bursts 10111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 65305 # Per bank write bursts 10211754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 62171 # Per bank write bursts 10311754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 60911 # Per bank write bursts 10411754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 55564 # Per bank write bursts 10511754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 110087 # Per bank write bursts 10611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 50665 # Per bank write bursts 10711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 58731 # Per bank write bursts 10811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 55379 # Per bank write bursts 10911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 59204 # Per bank write bursts 11011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 58833 # Per bank write bursts 11111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 53814 # Per bank write bursts 11211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 70729 # Per bank write bursts 11311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 73923 # Per bank write bursts 11411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 67641 # Per bank write bursts 11511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 73309 # Per bank write bursts 11611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 73460 # Per bank write bursts 11711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 77994 # Per bank write bursts 11811754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 75119 # Per bank write bursts 11911754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 77047 # Per bank write bursts 12011754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 72172 # Per bank write bursts 12111754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 76177 # Per bank write bursts 12211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 69310 # Per bank write bursts 12311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 74055 # Per bank write bursts 12411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 71196 # Per bank write bursts 12511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 73730 # Per bank write bursts 12611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 72781 # Per bank write bursts 12711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 72982 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911754Sandreas.hansson@arm.comsystem.physmem.numWrRetry 338 # Number of times write queue was full causing retry 13011754Sandreas.hansson@arm.comsystem.physmem.totGap 47356208030500 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711754Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 971933 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411754Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1171327 # Write request sizes (log2) 14511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 599542 # What read queue length does an incoming req see 14611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 159109 # What read queue length does an incoming req see 14711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 46981 # What read queue length does an incoming req see 14811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 36741 # What read queue length does an incoming req see 14911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 28369 # What read queue length does an incoming req see 15011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 25953 # What read queue length does an incoming req see 15111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 23819 # What read queue length does an incoming req see 15211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 21360 # What read queue length does an incoming req see 15311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 18806 # What read queue length does an incoming req see 15411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 4598 # What read queue length does an incoming req see 15511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1833 # What read queue length does an incoming req see 15611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1239 # What read queue length does an incoming req see 15711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 994 # What read queue length does an incoming req see 15811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see 15911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see 16011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 339 # What read queue length does an incoming req see 16111754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see 16211754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 244 # What read queue length does an incoming req see 16311754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see 16511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see 16611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see 16711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 16811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 16911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 24305 # What write queue length does an incoming req see 19311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 32346 # What write queue length does an incoming req see 19411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 48833 # What write queue length does an incoming req see 19511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 56114 # What write queue length does an incoming req see 19611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 61688 # What write queue length does an incoming req see 19711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 64343 # What write queue length does an incoming req see 19811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 66279 # What write queue length does an incoming req see 19911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 68229 # What write queue length does an incoming req see 20011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 71242 # What write queue length does an incoming req see 20111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 71432 # What write queue length does an incoming req see 20211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 74216 # What write queue length does an incoming req see 20311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 76183 # What write queue length does an incoming req see 20411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 73010 # What write queue length does an incoming req see 20511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 71262 # What write queue length does an incoming req see 20611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 72325 # What write queue length does an incoming req see 20711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 75575 # What write queue length does an incoming req see 20811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 67464 # What write queue length does an incoming req see 20911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 63552 # What write queue length does an incoming req see 21011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 4902 # What write queue length does an incoming req see 21111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 3071 # What write queue length does an incoming req see 21211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 2501 # What write queue length does an incoming req see 21311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1943 # What write queue length does an incoming req see 21411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1570 # What write queue length does an incoming req see 21511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 1445 # What write queue length does an incoming req see 21611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1223 # What write queue length does an incoming req see 21711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see 21811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 888 # What write queue length does an incoming req see 21911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 894 # What write queue length does an incoming req see 22011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 765 # What write queue length does an incoming req see 22111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 736 # What write queue length does an incoming req see 22211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 628 # What write queue length does an incoming req see 22311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 732 # What write queue length does an incoming req see 22411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 601 # What write queue length does an incoming req see 22511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 589 # What write queue length does an incoming req see 22611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 546 # What write queue length does an incoming req see 22711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 578 # What write queue length does an incoming req see 22811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 547 # What write queue length does an incoming req see 22911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 623 # What write queue length does an incoming req see 23011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 600 # What write queue length does an incoming req see 23111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 597 # What write queue length does an incoming req see 23211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 584 # What write queue length does an incoming req see 23311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 815 # What write queue length does an incoming req see 23411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 810 # What write queue length does an incoming req see 23511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 531 # What write queue length does an incoming req see 23611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 839 # What write queue length does an incoming req see 23711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 762 # What write queue length does an incoming req see 23811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 764 # What write queue length does an incoming req see 23911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 423 # What write queue length does an incoming req see 24011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 769 # What write queue length does an incoming req see 24111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 927860 # Bytes accessed per row activation 24211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 147.827612 # Bytes accessed per row activation 24311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 99.770435 # Bytes accessed per row activation 24411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 195.442358 # Bytes accessed per row activation 24511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 609464 65.68% 65.68% # Bytes accessed per row activation 24611754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 190800 20.56% 86.25% # Bytes accessed per row activation 24711754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 46263 4.99% 91.23% # Bytes accessed per row activation 24811754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 21195 2.28% 93.52% # Bytes accessed per row activation 24911754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 15500 1.67% 95.19% # Bytes accessed per row activation 25011754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 9774 1.05% 96.24% # Bytes accessed per row activation 25111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 7067 0.76% 97.00% # Bytes accessed per row activation 25211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 5586 0.60% 97.61% # Bytes accessed per row activation 25311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22211 2.39% 100.00% # Bytes accessed per row activation 25411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 927860 # Bytes accessed per row activation 25511754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 57099 # Reads before turning the bus around for writes 25611754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 17.014939 # Reads before turning the bus around for writes 25711754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 164.898277 # Reads before turning the bus around for writes 25811754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 57097 100.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26111754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 57099 # Reads before turning the bus around for writes 26211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 57099 # Writes before turning the bus around for reads 26311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 20.519186 # Writes before turning the bus around for reads 26411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.696547 # Writes before turning the bus around for reads 26511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 14.054604 # Writes before turning the bus around for reads 26611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 49168 86.11% 86.11% # Writes before turning the bus around for reads 26711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 2307 4.04% 90.15% # Writes before turning the bus around for reads 26811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 623 1.09% 91.24% # Writes before turning the bus around for reads 26911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 607 1.06% 92.30% # Writes before turning the bus around for reads 27011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 970 1.70% 94.00% # Writes before turning the bus around for reads 27111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 377 0.66% 94.66% # Writes before turning the bus around for reads 27211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 342 0.60% 95.26% # Writes before turning the bus around for reads 27311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 248 0.43% 95.70% # Writes before turning the bus around for reads 27411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 171 0.30% 96.00% # Writes before turning the bus around for reads 27511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 147 0.26% 96.25% # Writes before turning the bus around for reads 27611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 125 0.22% 96.47% # Writes before turning the bus around for reads 27711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 141 0.25% 96.72% # Writes before turning the bus around for reads 27811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 491 0.86% 97.58% # Writes before turning the bus around for reads 27911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 181 0.32% 97.90% # Writes before turning the bus around for reads 28011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 140 0.25% 98.14% # Writes before turning the bus around for reads 28111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 149 0.26% 98.40% # Writes before turning the bus around for reads 28211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 103 0.18% 98.58% # Writes before turning the bus around for reads 28311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 79 0.14% 98.72% # Writes before turning the bus around for reads 28411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 87 0.15% 98.87% # Writes before turning the bus around for reads 28511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 90 0.16% 99.03% # Writes before turning the bus around for reads 28611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 76 0.13% 99.16% # Writes before turning the bus around for reads 28711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 61 0.11% 99.27% # Writes before turning the bus around for reads 28811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 62 0.11% 99.38% # Writes before turning the bus around for reads 28911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 70 0.12% 99.50% # Writes before turning the bus around for reads 29011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 41 0.07% 99.57% # Writes before turning the bus around for reads 29111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 40 0.07% 99.64% # Writes before turning the bus around for reads 29211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 42 0.07% 99.72% # Writes before turning the bus around for reads 29311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 34 0.06% 99.78% # Writes before turning the bus around for reads 29411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 42 0.07% 99.85% # Writes before turning the bus around for reads 29511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 20 0.04% 99.89% # Writes before turning the bus around for reads 29611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads 29711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 13 0.02% 99.93% # Writes before turning the bus around for reads 29811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 6 0.01% 99.94% # Writes before turning the bus around for reads 29911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 4 0.01% 99.95% # Writes before turning the bus around for reads 30011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.95% # Writes before turning the bus around for reads 30111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 4 0.01% 99.96% # Writes before turning the bus around for reads 30211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 2 0.00% 99.96% # Writes before turning the bus around for reads 30311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads 30411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 5 0.01% 99.97% # Writes before turning the bus around for reads 30511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads 30611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads 30711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads 30811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 6 0.01% 99.99% # Writes before turning the bus around for reads 30911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads 31011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads 31111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 57099 # Writes before turning the bus around for reads 31211754Sandreas.hansson@arm.comsystem.physmem.totQLat 49354955217 # Total ticks spent queuing 31311754Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 67571780217 # Total ticks spent from burst creation until serviced by the DRAM 31411754Sandreas.hansson@arm.comsystem.physmem.totBusLat 4857820000 # Total ticks spent in databus transfers 31511754Sandreas.hansson@arm.comsystem.physmem.avgQLat 50799.49 # Average queueing delay per DRAM burst 31610515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31711754Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 69549.49 # Average memory access latency per DRAM burst 31811754Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.31 # Average DRAM read bandwidth in MiByte/s 31911754Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 32011754Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.31 # Average system read bandwidth in MiByte/s 32111754Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 32210515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32311680SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32411353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32511441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32611754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 32711754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 22.53 # Average write queue length when enqueuing 32811754Sandreas.hansson@arm.comsystem.physmem.readRowHits 725116 # Number of row buffer hits during reads 32911754Sandreas.hansson@arm.comsystem.physmem.writeRowHits 490210 # Number of row buffer hits during writes 33011754Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.63 # Row buffer hit rate for reads 33111754Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 41.84 # Row buffer hit rate for writes 33211754Sandreas.hansson@arm.comsystem.physmem.avgGap 22068597.09 # Average gap between requests 33311754Sandreas.hansson@arm.comsystem.physmem.pageHitRate 56.71 # Row buffer hit rate, read and write combined 33411754Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3347988840 # Energy for activate commands per rank (pJ) 33511754Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1779490680 # Energy for precharge commands per rank (pJ) 33611754Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3350709180 # Energy for read commands per rank (pJ) 33711754Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3075738840 # Energy for write commands per rank (pJ) 33811754Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 40224500160.000008 # Energy for refresh commands per rank (pJ) 33911754Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 43885079760 # Energy for active background per rank (pJ) 34011754Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 2109996960 # Energy for precharge background per rank (pJ) 34111754Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 79595636190 # Energy for active power-down per rank (pJ) 34211754Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 56472597600 # Energy for precharge power-down per rank (pJ) 34311754Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 11270458828185 # Energy for self refresh per rank (pJ) 34411754Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 11504320668105 # Total energy per rank (pJ) 34511754Sandreas.hansson@arm.comsystem.physmem_0.averagePower 242.931616 # Core power per rank (mW) 34611754Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 47254429054365 # Total Idle time Per DRAM Rank 34711754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3740889550 # Time in different power states 34811754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 17088544000 # Time in different power states 34911754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 46932815651000 # Time in different power states 35011754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 147063936092 # Time in different power states 35111754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 80948731835 # Time in different power states 35211754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 174552373523 # Time in different power states 35311754Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3276952980 # Energy for activate commands per rank (pJ) 35411754Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1741738020 # Energy for precharge commands per rank (pJ) 35511754Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3586257780 # Energy for read commands per rank (pJ) 35611754Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3040143660 # Energy for write commands per rank (pJ) 35711754Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 38004420480.000008 # Energy for refresh commands per rank (pJ) 35811754Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 43585213590 # Energy for active background per rank (pJ) 35911754Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1995622560 # Energy for precharge background per rank (pJ) 36011754Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 72860280210 # Energy for active power-down per rank (pJ) 36111754Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 53203975680 # Energy for precharge power-down per rank (pJ) 36211754Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 11275978868760 # Energy for self refresh per rank (pJ) 36311754Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 11497290812280 # Total energy per rank (pJ) 36411754Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.783170 # Core power per rank (mW) 36511754Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 47255392508641 # Total Idle time Per DRAM Rank 36611754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3486165610 # Time in different power states 36711754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 16146094000 # Time in different power states 36811754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 46957059679500 # Time in different power states 36911754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 138551420004 # Time in different power states 37011754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 81185307499 # Time in different power states 37111754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 159781459387 # Time in different power states 37211754Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 37310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 37511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 37610636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 37711570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 37911570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 38011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 38110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 38210636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 38311570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 38410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 38511570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 38610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 38710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 38811754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) 38910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 39011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 39110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 39211754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) 39311570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 39410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 39510636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 39611754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) 39710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 39811570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 39911754Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 40011754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 40111754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 40210585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 40310585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 40410585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 40511606Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 40611606Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 40711606Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 40811754Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 135721275 # Number of BP lookups 40911754Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 95221356 # Number of conditional branches predicted 41011754Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6297780 # Number of conditional branches incorrect 41111754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 101561419 # Number of BTB lookups 41211754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 70514394 # Number of BTB hits 41310585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 41411754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 69.430296 # BTB Hit Percentage 41511754Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 16061922 # Number of times the RAS was used to get a target. 41611754Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1062204 # Number of incorrect RAS predictions. 41711754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectLookups 3676908 # Number of indirect predictor lookups. 41811754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectHits 2416966 # Number of indirect target hits. 41911754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectMisses 1259942 # Number of indirect misses. 42011754Sandreas.hansson@arm.comsystem.cpu0.branchPredindirectMispredicted 447333 # Number of mispredicted indirect branches. 42110515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 42211754Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 42310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 42410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 42710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 42810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 43610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 43710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 43810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 43910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 44010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 44110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 44210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 44310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 44410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 44510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 44610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 44710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 44810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 44910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 45010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 45110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 45211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 45311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 280305 # Table walker walks requested 45411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 280305 # Table walker walks initiated with long descriptors 45511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9673 # Level at which table walker walks with long descriptors terminate 45611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80745 # Level at which table walker walks with long descriptors terminate 45711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 280305 # Table walker wait (enqueue to first request) latency 45811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 280305 100.00% 100.00% # Table walker wait (enqueue to first request) latency 45911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 280305 # Table walker wait (enqueue to first request) latency 46011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 90418 # Table walker service (enqueue to completion) latency 46111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099 # Table walker service (enqueue to completion) latency 46211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848 # Table walker service (enqueue to completion) latency 46311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973 # Table walker service (enqueue to completion) latency 46411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 89075 98.51% 98.51% # Table walker service (enqueue to completion) latency 46511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 1011 1.12% 99.63% # Table walker service (enqueue to completion) latency 46611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 175 0.19% 99.83% # Table walker service (enqueue to completion) latency 46711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency 46811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 41 0.05% 99.94% # Table walker service (enqueue to completion) latency 46911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency 47011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.97% # Table walker service (enqueue to completion) latency 47111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 47211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 47311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 21 0.02% 100.00% # Table walker service (enqueue to completion) latency 47411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 90418 # Table walker service (enqueue to completion) latency 47511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution 47611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution 47711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution 47811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 80745 89.30% 89.30% # Table walker page sizes translated 47911754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9673 10.70% 100.00% # Table walker page sizes translated 48011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 90418 # Table walker page sizes translated 48111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 280305 # Table walker requests started/completed, data/inst 48210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 280305 # Table walker requests started/completed, data/inst 48411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90418 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90418 # Table walker requests started/completed, data/inst 48711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 370723 # Table walker requests started/completed, data/inst 48810585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 48910585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 49011754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 85620412 # DTB read hits 49111754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 232360 # DTB read misses 49211754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 76323418 # DTB write hits 49311754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 47945 # DTB write misses 49411441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 49510585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49611754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 49711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 49811754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 37568 # Number of entries that have been flushed from TLB 49911754Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 2099 # Number of TLB faults due to alignment restrictions 50011754Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 10030 # Number of TLB faults due to prefetch 50110585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 50211754Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 11718 # Number of TLB faults due to permissions restrictions 50311754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 85852772 # DTB read accesses 50411754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 76371363 # DTB write accesses 50510585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 50611754Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 161943830 # DTB hits 50711754Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 280305 # DTB misses 50811754Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 162224135 # DTB accesses 50911754Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 51010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 51110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 51210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 51310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 51410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 51610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 51710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 52410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 52510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 53110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 53210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 53310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 53410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 53510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 53610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 53710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 53810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 53911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 54011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 68220 # Table walker walks requested 54111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 68220 # Table walker walks initiated with long descriptors 54211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 613 # Level at which table walker walks with long descriptors terminate 54311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 59689 # Level at which table walker walks with long descriptors terminate 54411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 68220 # Table walker wait (enqueue to first request) latency 54511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 68220 100.00% 100.00% # Table walker wait (enqueue to first request) latency 54611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 68220 # Table walker wait (enqueue to first request) latency 54711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 60302 # Table walker service (enqueue to completion) latency 54811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26595.826009 # Table walker service (enqueue to completion) latency 54911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451 # Table walker service (enqueue to completion) latency 55011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701 # Table walker service (enqueue to completion) latency 55111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 58891 97.66% 97.66% # Table walker service (enqueue to completion) latency 55211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 1009 1.67% 99.33% # Table walker service (enqueue to completion) latency 55311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 274 0.45% 99.79% # Table walker service (enqueue to completion) latency 55411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.12% 99.91% # Table walker service (enqueue to completion) latency 55511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.93% # Table walker service (enqueue to completion) latency 55611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.95% # Table walker service (enqueue to completion) latency 55711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.96% # Table walker service (enqueue to completion) latency 55811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.96% # Table walker service (enqueue to completion) latency 55911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency 56011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 56111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 60302 # Table walker service (enqueue to completion) latency 56211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution 56311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution 56411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution 56511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 59689 98.98% 98.98% # Table walker page sizes translated 56611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 613 1.02% 100.00% # Table walker page sizes translated 56711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 60302 # Table walker page sizes translated 56810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68220 # Table walker requests started/completed, data/inst 57011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 68220 # Table walker requests started/completed, data/inst 57110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 57211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60302 # Table walker requests started/completed, data/inst 57311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 60302 # Table walker requests started/completed, data/inst 57411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 128522 # Table walker requests started/completed, data/inst 57511754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 240780512 # ITB inst hits 57611754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 68220 # ITB inst misses 57710585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 57810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 57910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 58010585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 58111441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 58210585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58311754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 58411680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 58511754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 26473 # Number of entries that have been flushed from TLB 58610585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58710585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58810585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58911754Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 160298 # Number of TLB faults due to permissions restrictions 59010585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 59110585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 59211754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 240848732 # ITB inst accesses 59311754Sandreas.hansson@arm.comsystem.cpu0.itb.hits 240780512 # DTB hits 59411754Sandreas.hansson@arm.comsystem.cpu0.itb.misses 68220 # DTB misses 59511754Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 240848732 # DTB accesses 59611754Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 27604 # Number of power state transitions 59711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13802 # Distribution of time spent in the clock gated state 59811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3395512179.708375 # Distribution of time spent in the clock gated state 59911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 87569621243.897629 # Distribution of time spent in the clock gated state 60011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3847 27.87% 27.87% # Distribution of time spent in the clock gated state 60111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9929 71.94% 99.81% # Distribution of time spent in the clock gated state 60211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 60311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 60411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 60511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 60611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 60711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 60811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 60911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 61011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 61111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 61211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7470353787292 # Distribution of time spent in the clock gated state 61311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 13802 # Distribution of time spent in the clock gated state 61411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 491351021665 # Cumulative time (in ticks) in various power states 61511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335 # Cumulative time (in ticks) in various power states 61611754Sandreas.hansson@arm.comsystem.cpu0.numCycles 982743358 # number of cpu cycles simulated 61710585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61810585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61911754Sandreas.hansson@arm.comsystem.cpu0.committedInsts 443442317 # Number of instructions committed 62011754Sandreas.hansson@arm.comsystem.cpu0.committedOps 521139520 # Number of ops (including micro ops) committed 62111754Sandreas.hansson@arm.comsystem.cpu0.discardedOps 46171758 # Number of ops (including micro ops) which were discarded before commit 62211754Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 4942 # Number of times Execute suspended instruction fetching 62311754Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93730487058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 62411754Sandreas.hansson@arm.comsystem.cpu0.cpi 2.216170 # CPI: cycles per instruction 62511754Sandreas.hansson@arm.comsystem.cpu0.ipc 0.451229 # IPC: instructions per cycle 62611754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62711754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntAlu 361587453 69.38% 69.38% # Class of committed instruction 62811754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntMult 1073144 0.21% 69.59% # Class of committed instruction 62911754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntDiv 57197 0.01% 69.60% # Class of committed instruction 63011754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatAdd 8 0.00% 69.60% # Class of committed instruction 63111754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatCmp 13 0.00% 69.60% # Class of committed instruction 63211754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatCvt 21 0.00% 69.60% # Class of committed instruction 63311754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction 63411754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.60% # Class of committed instruction 63511754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction 63611754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMisc 48874 0.01% 69.61% # Class of committed instruction 63711754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 63811754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 63911754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 64011754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 64111754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 64211754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 64311754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 64411754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 64511754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 64611754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 64711754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 64811754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 64911754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 65011754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 65111754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 65211754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 65311754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 65411754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.61% # Class of committed instruction 65511754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction 65611754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction 65711754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction 65811754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::MemRead 82336787 15.80% 85.41% # Class of committed instruction 65911754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::MemWrite 75604792 14.51% 99.92% # Class of committed instruction 66011754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMemRead 54276 0.01% 99.93% # Class of committed instruction 66111754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMemWrite 376955 0.07% 100.00% # Class of committed instruction 66211441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 66311441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 66411754Sandreas.hansson@arm.comsystem.cpu0.op_class_0::total 521139520 # Class of committed instruction 66510585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 66611754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13802 # number of quiesce instructions executed 66711754Sandreas.hansson@arm.comsystem.cpu0.tickCycles 716804238 # Number of cycles that the object actually ticked 66811754Sandreas.hansson@arm.comsystem.cpu0.idleCycles 265939120 # Total number of cycles that the object has spent stopped 66911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 67011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5714630 # number of replacements 67111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 503.374360 # Cycle average of tags in use 67211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 153605175 # Total number of references to valid blocks. 67311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5715141 # Sample count of references to valid blocks. 67411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 26.876883 # Average number of references to valid blocks. 67511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. 67611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 503.374360 # Average occupied blocks per requestor 67711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.983153 # Average percentage of cache occupancy 67811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.983153 # Average percentage of cache occupancy 67911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 68011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 68111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 68211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 68311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 68411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 326958988 # Number of tag accesses 68511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 326958988 # Number of data accesses 68611754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 68711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 78624149 # number of ReadReq hits 68811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 78624149 # number of ReadReq hits 68911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 70655306 # number of WriteReq hits 69011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 70655306 # number of WriteReq hits 69111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 268473 # number of SoftPFReq hits 69211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 268473 # number of SoftPFReq hits 69311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 172491 # number of WriteLineReq hits 69411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 172491 # number of WriteLineReq hits 69511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1691736 # number of LoadLockedReq hits 69611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1691736 # number of LoadLockedReq hits 69711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1666426 # number of StoreCondReq hits 69811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1666426 # number of StoreCondReq hits 69911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 149451946 # number of demand (read+write) hits 70011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 149451946 # number of demand (read+write) hits 70111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 149720419 # number of overall hits 70211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 149720419 # number of overall hits 70311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3212821 # number of ReadReq misses 70411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3212821 # number of ReadReq misses 70511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2434459 # number of WriteReq misses 70611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2434459 # number of WriteReq misses 70711754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 667240 # number of SoftPFReq misses 70811754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 667240 # number of SoftPFReq misses 70911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 831306 # number of WriteLineReq misses 71011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 831306 # number of WriteLineReq misses 71111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163515 # number of LoadLockedReq misses 71211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 163515 # number of LoadLockedReq misses 71311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 187633 # number of StoreCondReq misses 71411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 187633 # number of StoreCondReq misses 71511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 6478586 # number of demand (read+write) misses 71611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6478586 # number of demand (read+write) misses 71711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 7145826 # number of overall misses 71811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 7145826 # number of overall misses 71911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52300502500 # number of ReadReq miss cycles 72011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52300502500 # number of ReadReq miss cycles 72111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52442906000 # number of WriteReq miss cycles 72211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 52442906000 # number of WriteReq miss cycles 72311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26430842500 # number of WriteLineReq miss cycles 72411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 26430842500 # number of WriteLineReq miss cycles 72511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2572412500 # number of LoadLockedReq miss cycles 72611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2572412500 # number of LoadLockedReq miss cycles 72711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4480220000 # number of StoreCondReq miss cycles 72811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4480220000 # number of StoreCondReq miss cycles 72911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2147000 # number of StoreCondFailReq miss cycles 73011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2147000 # number of StoreCondFailReq miss cycles 73111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000 # number of demand (read+write) miss cycles 73211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 131174251000 # number of demand (read+write) miss cycles 73311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000 # number of overall miss cycles 73411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 131174251000 # number of overall miss cycles 73511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 81836970 # number of ReadReq accesses(hits+misses) 73611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 81836970 # number of ReadReq accesses(hits+misses) 73711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 73089765 # number of WriteReq accesses(hits+misses) 73811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 73089765 # number of WriteReq accesses(hits+misses) 73911754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935713 # number of SoftPFReq accesses(hits+misses) 74011754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 935713 # number of SoftPFReq accesses(hits+misses) 74111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1003797 # number of WriteLineReq accesses(hits+misses) 74211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1003797 # number of WriteLineReq accesses(hits+misses) 74311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1855251 # number of LoadLockedReq accesses(hits+misses) 74411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1855251 # number of LoadLockedReq accesses(hits+misses) 74511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1854059 # number of StoreCondReq accesses(hits+misses) 74611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1854059 # number of StoreCondReq accesses(hits+misses) 74711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 155930532 # number of demand (read+write) accesses 74811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 155930532 # number of demand (read+write) accesses 74911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 156866245 # number of overall (read+write) accesses 75011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 156866245 # number of overall (read+write) accesses 75111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039259 # miss rate for ReadReq accesses 75211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.039259 # miss rate for ReadReq accesses 75311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033308 # miss rate for WriteReq accesses 75411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses 75511754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713082 # miss rate for SoftPFReq accesses 75611754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.713082 # miss rate for SoftPFReq accesses 75711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.828161 # miss rate for WriteLineReq accesses 75811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.828161 # miss rate for WriteLineReq accesses 75911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088136 # miss rate for LoadLockedReq accesses 76011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088136 # miss rate for LoadLockedReq accesses 76111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101201 # miss rate for StoreCondReq accesses 76211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.101201 # miss rate for StoreCondReq accesses 76311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses 76411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses 76511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.045554 # miss rate for overall accesses 76611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.045554 # miss rate for overall accesses 76711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461 # average ReadReq miss latency 76811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461 # average ReadReq miss latency 76911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830 # average WriteReq miss latency 77011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830 # average WriteReq miss latency 77111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320 # average WriteLineReq miss latency 77211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320 # average WriteLineReq miss latency 77311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486 # average LoadLockedReq miss latency 77411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486 # average LoadLockedReq miss latency 77511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511 # average StoreCondReq miss latency 77611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511 # average StoreCondReq miss latency 77710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143 # average overall miss latency 78011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20247.358143 # average overall miss latency 78111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334 # average overall miss latency 78211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 18356.765334 # average overall miss latency 78310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 78410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78510585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78710585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78810585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78911754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5714633 # number of writebacks 79011754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5714633 # number of writebacks 79111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202792 # number of ReadReq MSHR hits 79211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 202792 # number of ReadReq MSHR hits 79311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1014502 # number of WriteReq MSHR hits 79411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1014502 # number of WriteReq MSHR hits 79511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 93 # number of WriteLineReq MSHR hits 79611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 93 # number of WriteLineReq MSHR hits 79711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43372 # number of LoadLockedReq MSHR hits 79811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 43372 # number of LoadLockedReq MSHR hits 79911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 49 # number of StoreCondReq MSHR hits 80011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 49 # number of StoreCondReq MSHR hits 80111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1217387 # number of demand (read+write) MSHR hits 80211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1217387 # number of demand (read+write) MSHR hits 80311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1217387 # number of overall MSHR hits 80411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1217387 # number of overall MSHR hits 80511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3010029 # number of ReadReq MSHR misses 80611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3010029 # number of ReadReq MSHR misses 80711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419957 # number of WriteReq MSHR misses 80811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1419957 # number of WriteReq MSHR misses 80911754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664995 # number of SoftPFReq MSHR misses 81011754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 664995 # number of SoftPFReq MSHR misses 81111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 831213 # number of WriteLineReq MSHR misses 81211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 831213 # number of WriteLineReq MSHR misses 81311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120143 # number of LoadLockedReq MSHR misses 81411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 120143 # number of LoadLockedReq MSHR misses 81511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187584 # number of StoreCondReq MSHR misses 81611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 187584 # number of StoreCondReq MSHR misses 81711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5261199 # number of demand (read+write) MSHR misses 81811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5261199 # number of demand (read+write) MSHR misses 81911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5926194 # number of overall MSHR misses 82011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5926194 # number of overall MSHR misses 82111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 82211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 31550 # number of ReadReq MSHR uncacheable 82311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 82411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable 82511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 82611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 62751 # number of overall MSHR uncacheable misses 82711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44196910500 # number of ReadReq MSHR miss cycles 82811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 44196910500 # number of ReadReq MSHR miss cycles 82911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29509664500 # number of WriteReq MSHR miss cycles 83011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 29509664500 # number of WriteReq MSHR miss cycles 83111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16065417000 # number of SoftPFReq MSHR miss cycles 83211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16065417000 # number of SoftPFReq MSHR miss cycles 83311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25593186000 # number of WriteLineReq MSHR miss cycles 83411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25593186000 # number of WriteLineReq MSHR miss cycles 83511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1671520500 # number of LoadLockedReq MSHR miss cycles 83611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1671520500 # number of LoadLockedReq MSHR miss cycles 83711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4291457000 # number of StoreCondReq MSHR miss cycles 83811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4291457000 # number of StoreCondReq MSHR miss cycles 83911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1958500 # number of StoreCondFailReq MSHR miss cycles 84011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1958500 # number of StoreCondFailReq MSHR miss cycles 84111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99299761000 # number of demand (read+write) MSHR miss cycles 84211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 99299761000 # number of demand (read+write) MSHR miss cycles 84311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000 # number of overall MSHR miss cycles 84411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 115365178000 # number of overall MSHR miss cycles 84511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6087891000 # number of ReadReq MSHR uncacheable cycles 84611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6087891000 # number of ReadReq MSHR uncacheable cycles 84711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6087891000 # number of overall MSHR uncacheable cycles 84811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6087891000 # number of overall MSHR uncacheable cycles 84911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036781 # mshr miss rate for ReadReq accesses 85011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036781 # mshr miss rate for ReadReq accesses 85111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019428 # mshr miss rate for WriteReq accesses 85211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019428 # mshr miss rate for WriteReq accesses 85311754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710683 # mshr miss rate for SoftPFReq accesses 85411754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710683 # mshr miss rate for SoftPFReq accesses 85511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.828069 # mshr miss rate for WriteLineReq accesses 85611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.828069 # mshr miss rate for WriteLineReq accesses 85711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064758 # mshr miss rate for LoadLockedReq accesses 85811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064758 # mshr miss rate for LoadLockedReq accesses 85911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101175 # mshr miss rate for StoreCondReq accesses 86011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101175 # mshr miss rate for StoreCondReq accesses 86111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033741 # mshr miss rate for demand accesses 86211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.033741 # mshr miss rate for demand accesses 86311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037779 # mshr miss rate for overall accesses 86411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.037779 # mshr miss rate for overall accesses 86511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504 # average ReadReq mshr miss latency 86611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504 # average ReadReq mshr miss latency 86711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190 # average WriteReq mshr miss latency 86811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190 # average WriteReq mshr miss latency 86911754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449 # average SoftPFReq mshr miss latency 87011754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449 # average SoftPFReq mshr miss latency 87111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698 # average WriteLineReq mshr miss latency 87211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698 # average WriteLineReq mshr miss latency 87311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130 # average LoadLockedReq mshr miss latency 87411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130 # average LoadLockedReq mshr miss latency 87511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537 # average StoreCondReq mshr miss latency 87611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537 # average StoreCondReq mshr miss latency 87710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 87810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 87911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296 # average overall mshr miss latency 88011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296 # average overall mshr miss latency 88111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149 # average overall mshr miss latency 88211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149 # average overall mshr miss latency 88311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087 # average ReadReq mshr uncacheable latency 88411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087 # average ReadReq mshr uncacheable latency 88511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185 # average overall mshr uncacheable latency 88611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185 # average overall mshr uncacheable latency 88711754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 88811754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9611464 # number of replacements 88911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.928699 # Cycle average of tags in use 89011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 231001616 # Total number of references to valid blocks. 89111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9611976 # Sample count of references to valid blocks. 89211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 24.032688 # Average number of references to valid blocks. 89311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 22883257000 # Cycle when the warmup percentage was hit. 89411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928699 # Average occupied blocks per requestor 89511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy 89611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy 89710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89811754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 89911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 426 # Occupied blocks per task id 90011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 90110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 90211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 490839190 # Number of tag accesses 90311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 490839190 # Number of data accesses 90411754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 90511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 231001616 # number of ReadReq hits 90611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 231001616 # number of ReadReq hits 90711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 231001616 # number of demand (read+write) hits 90811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 231001616 # number of demand (read+write) hits 90911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 231001616 # number of overall hits 91011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 231001616 # number of overall hits 91111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9611986 # number of ReadReq misses 91211754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9611986 # number of ReadReq misses 91311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9611986 # number of demand (read+write) misses 91411754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9611986 # number of demand (read+write) misses 91511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9611986 # number of overall misses 91611754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9611986 # number of overall misses 91711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98657772000 # number of ReadReq miss cycles 91811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 98657772000 # number of ReadReq miss cycles 91911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 98657772000 # number of demand (read+write) miss cycles 92011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 98657772000 # number of demand (read+write) miss cycles 92111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 98657772000 # number of overall miss cycles 92211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 98657772000 # number of overall miss cycles 92311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 240613602 # number of ReadReq accesses(hits+misses) 92411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 240613602 # number of ReadReq accesses(hits+misses) 92511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 240613602 # number of demand (read+write) accesses 92611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 240613602 # number of demand (read+write) accesses 92711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 240613602 # number of overall (read+write) accesses 92811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 240613602 # number of overall (read+write) accesses 92911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039948 # miss rate for ReadReq accesses 93011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.039948 # miss rate for ReadReq accesses 93111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.039948 # miss rate for demand accesses 93211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.039948 # miss rate for demand accesses 93311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.039948 # miss rate for overall accesses 93411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.039948 # miss rate for overall accesses 93511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173 # average ReadReq miss latency 93611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173 # average ReadReq miss latency 93711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency 93811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10264.036173 # average overall miss latency 93911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency 94011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10264.036173 # average overall miss latency 94110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 94210585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94310585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94410585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 94510585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 94610585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 94711754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 9611464 # number of writebacks 94811754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 9611464 # number of writebacks 94911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9611986 # number of ReadReq MSHR misses 95011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9611986 # number of ReadReq MSHR misses 95111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9611986 # number of demand (read+write) MSHR misses 95211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9611986 # number of demand (read+write) MSHR misses 95311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9611986 # number of overall MSHR misses 95411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9611986 # number of overall MSHR misses 95511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 95611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable 95711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 95811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses 95911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93851779000 # number of ReadReq MSHR miss cycles 96011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 93851779000 # number of ReadReq MSHR miss cycles 96111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93851779000 # number of demand (read+write) MSHR miss cycles 96211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 93851779000 # number of demand (read+write) MSHR miss cycles 96311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93851779000 # number of overall MSHR miss cycles 96411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 93851779000 # number of overall MSHR miss cycles 96511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles 96611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles 96711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles 96811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles 96911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for ReadReq accesses 97011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039948 # mshr miss rate for ReadReq accesses 97111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for demand accesses 97211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.039948 # mshr miss rate for demand accesses 97311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for overall accesses 97411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.039948 # mshr miss rate for overall accesses 97511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average ReadReq mshr miss latency 97611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9764.036173 # average ReadReq mshr miss latency 97711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency 97811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency 97911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency 98011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency 98111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency 98211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency 98311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency 98411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency 98511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 98611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7434042 # number of hwpf issued 98711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7435434 # number of prefetch candidates identified 98811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1234 # number of redundant prefetches already in prefetch queue 98910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 99010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 99111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 974582 # number of prefetches not generated due to page crossing 99211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 99311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2611270 # number of replacements 99411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15687.218696 # Cycle average of tags in use 99511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 13797239 # Total number of references to valid blocks. 99611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2627042 # Sample count of references to valid blocks. 99711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.252005 # Average number of references to valid blocks. 99811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit. 99911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15319.283860 # Average occupied blocks per requestor 100011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.805682 # Average occupied blocks per requestor 100111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.313962 # Average occupied blocks per requestor 100211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 298.815192 # Average occupied blocks per requestor 100311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.935015 # Average percentage of cache occupancy 100411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002613 # Average percentage of cache occupancy 100511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001606 # Average percentage of cache occupancy 100611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018238 # Average percentage of cache occupancy 100711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.957472 # Average percentage of cache occupancy 100811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 263 # Occupied blocks per task id 100911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id 101011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id 101111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 82 # Occupied blocks per task id 101211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 89 # Occupied blocks per task id 101311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id 101411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id 101511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id 101611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id 101711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 101811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 101911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2136 # Occupied blocks per task id 102011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5462 # Occupied blocks per task id 102111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5455 # Occupied blocks per task id 102211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2257 # Occupied blocks per task id 102311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016052 # Percentage of cache occupancy per task id 102411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id 102511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id 102611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 526460646 # Number of tag accesses 102711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 526460646 # Number of data accesses 102811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 102911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522971 # number of ReadReq hits 103011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 177971 # number of ReadReq hits 103111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 700942 # number of ReadReq hits 103211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3820006 # number of WritebackDirty hits 103311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3820006 # number of WritebackDirty hits 103411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11503050 # number of WritebackClean hits 103511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 11503050 # number of WritebackClean hits 103611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 900259 # number of ReadExReq hits 103711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 900259 # number of ReadExReq hits 103811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8923530 # number of ReadCleanReq hits 103911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 8923530 # number of ReadCleanReq hits 104011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2824509 # number of ReadSharedReq hits 104111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2824509 # number of ReadSharedReq hits 104211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229490 # number of InvalidateReq hits 104311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 229490 # number of InvalidateReq hits 104411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522971 # number of demand (read+write) hits 104511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 177971 # number of demand (read+write) hits 104611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 8923530 # number of demand (read+write) hits 104711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3724768 # number of demand (read+write) hits 104811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 13349240 # number of demand (read+write) hits 104911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522971 # number of overall hits 105011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 177971 # number of overall hits 105111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 8923530 # number of overall hits 105211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3724768 # number of overall hits 105311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 13349240 # number of overall hits 105411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20616 # number of ReadReq misses 105511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9971 # number of ReadReq misses 105611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 30587 # number of ReadReq misses 105711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242554 # number of UpgradeReq misses 105811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 242554 # number of UpgradeReq misses 105911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187582 # number of SCUpgradeReq misses 106011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 187582 # number of SCUpgradeReq misses 106111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 106211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 106311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 283527 # number of ReadExReq misses 106411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 283527 # number of ReadExReq misses 106511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688455 # number of ReadCleanReq misses 106611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 688455 # number of ReadCleanReq misses 106711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 970291 # number of ReadSharedReq misses 106811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 970291 # number of ReadSharedReq misses 106911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601723 # number of InvalidateReq misses 107011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 601723 # number of InvalidateReq misses 107111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20616 # number of demand (read+write) misses 107211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 9971 # number of demand (read+write) misses 107311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 688455 # number of demand (read+write) misses 107411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1253818 # number of demand (read+write) misses 107511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1972860 # number of demand (read+write) misses 107611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20616 # number of overall misses 107711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 9971 # number of overall misses 107811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 688455 # number of overall misses 107911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1253818 # number of overall misses 108011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1972860 # number of overall misses 108111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 693953500 # number of ReadReq miss cycles 108211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 416737500 # number of ReadReq miss cycles 108311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1110691000 # number of ReadReq miss cycles 108411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 877430000 # number of UpgradeReq miss cycles 108511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 877430000 # number of UpgradeReq miss cycles 108611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 285529500 # number of SCUpgradeReq miss cycles 108711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 285529500 # number of SCUpgradeReq miss cycles 108811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1883000 # number of SCUpgradeFailReq miss cycles 108911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1883000 # number of SCUpgradeFailReq miss cycles 109011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15417318498 # number of ReadExReq miss cycles 109111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 15417318498 # number of ReadExReq miss cycles 109211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25525674000 # number of ReadCleanReq miss cycles 109311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 25525674000 # number of ReadCleanReq miss cycles 109411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37603567991 # number of ReadSharedReq miss cycles 109511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 37603567991 # number of ReadSharedReq miss cycles 109611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles 109711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles 109811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 693953500 # number of demand (read+write) miss cycles 109911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 416737500 # number of demand (read+write) miss cycles 110011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 25525674000 # number of demand (read+write) miss cycles 110111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 53020886489 # number of demand (read+write) miss cycles 110211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 79657251489 # number of demand (read+write) miss cycles 110311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 693953500 # number of overall miss cycles 110411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 416737500 # number of overall miss cycles 110511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 25525674000 # number of overall miss cycles 110611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 53020886489 # number of overall miss cycles 110711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 79657251489 # number of overall miss cycles 110811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 543587 # number of ReadReq accesses(hits+misses) 110911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 187942 # number of ReadReq accesses(hits+misses) 111011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 731529 # number of ReadReq accesses(hits+misses) 111111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3820006 # number of WritebackDirty accesses(hits+misses) 111211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3820006 # number of WritebackDirty accesses(hits+misses) 111311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11503050 # number of WritebackClean accesses(hits+misses) 111411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11503050 # number of WritebackClean accesses(hits+misses) 111511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242554 # number of UpgradeReq accesses(hits+misses) 111611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 242554 # number of UpgradeReq accesses(hits+misses) 111711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187582 # number of SCUpgradeReq accesses(hits+misses) 111811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 187582 # number of SCUpgradeReq accesses(hits+misses) 111911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 112011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 112111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183786 # number of ReadExReq accesses(hits+misses) 112211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1183786 # number of ReadExReq accesses(hits+misses) 112311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9611985 # number of ReadCleanReq accesses(hits+misses) 112411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9611985 # number of ReadCleanReq accesses(hits+misses) 112511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3794800 # number of ReadSharedReq accesses(hits+misses) 112611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3794800 # number of ReadSharedReq accesses(hits+misses) 112711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831213 # number of InvalidateReq accesses(hits+misses) 112811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 831213 # number of InvalidateReq accesses(hits+misses) 112911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 543587 # number of demand (read+write) accesses 113011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 187942 # number of demand (read+write) accesses 113111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9611985 # number of demand (read+write) accesses 113211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4978586 # number of demand (read+write) accesses 113311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 15322100 # number of demand (read+write) accesses 113411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 543587 # number of overall (read+write) accesses 113511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 187942 # number of overall (read+write) accesses 113611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9611985 # number of overall (read+write) accesses 113711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4978586 # number of overall (read+write) accesses 113811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 15322100 # number of overall (read+write) accesses 113911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for ReadReq accesses 114011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053054 # miss rate for ReadReq accesses 114111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.041812 # miss rate for ReadReq accesses 114211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 114311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 114411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 114511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 114610636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 114710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 114811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.239509 # miss rate for ReadExReq accesses 114911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.239509 # miss rate for ReadExReq accesses 115011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071625 # miss rate for ReadCleanReq accesses 115111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071625 # miss rate for ReadCleanReq accesses 115211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255690 # miss rate for ReadSharedReq accesses 115311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255690 # miss rate for ReadSharedReq accesses 115411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.723910 # miss rate for InvalidateReq accesses 115511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.723910 # miss rate for InvalidateReq accesses 115611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for demand accesses 115711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053054 # miss rate for demand accesses 115811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071625 # miss rate for demand accesses 115911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251842 # miss rate for demand accesses 116011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.128759 # miss rate for demand accesses 116111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for overall accesses 116211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053054 # miss rate for overall accesses 116311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071625 # miss rate for overall accesses 116411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251842 # miss rate for overall accesses 116511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.128759 # miss rate for overall accesses 116611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average ReadReq miss latency 116711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41794.955371 # average ReadReq miss latency 116811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 36312.518390 # average ReadReq miss latency 116911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3617.462503 # average UpgradeReq miss latency 117011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3617.462503 # average UpgradeReq miss latency 117111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1522.158309 # average SCUpgradeReq miss latency 117211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1522.158309 # average SCUpgradeReq miss latency 117311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency 117411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency 117511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54376.897079 # average ReadExReq miss latency 117611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54376.897079 # average ReadExReq miss latency 117711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37076.750114 # average ReadCleanReq miss latency 117811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37076.750114 # average ReadCleanReq miss latency 117911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38754.938458 # average ReadSharedReq miss latency 118011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38754.938458 # average ReadSharedReq miss latency 118111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.172837 # average InvalidateReq miss latency 118211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.172837 # average InvalidateReq miss latency 118311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency 118411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency 118511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency 118611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency 118711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 40376.535329 # average overall miss latency 118811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency 118911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency 119011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency 119111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency 119211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 40376.535329 # average overall miss latency 119311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 119410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 119610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 119711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked 119810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.unused_prefetches 44451 # number of HardPF blocks evicted w/o reference 120011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1620068 # number of writebacks 120111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1620068 # number of writebacks 120211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits 120311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 98 # number of ReadReq MSHR hits 120411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits 120511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8857 # number of ReadExReq MSHR hits 120611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 8857 # number of ReadExReq MSHR hits 120711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits 120811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 120911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 996 # number of ReadSharedReq MSHR hits 121011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 996 # number of ReadSharedReq MSHR hits 121111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 121211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 121311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits 121411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 98 # number of demand (read+write) MSHR hits 121511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits 121611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 9853 # number of demand (read+write) MSHR hits 121711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 9980 # number of demand (read+write) MSHR hits 121811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits 121911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 98 # number of overall MSHR hits 122011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits 122111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 9853 # number of overall MSHR hits 122211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 9980 # number of overall MSHR hits 122311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20593 # number of ReadReq MSHR misses 122411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9873 # number of ReadReq MSHR misses 122511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 30466 # number of ReadReq MSHR misses 122611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of HardPFReq MSHR misses 122711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 782341 # number of HardPFReq MSHR misses 122811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242554 # number of UpgradeReq MSHR misses 122911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 242554 # number of UpgradeReq MSHR misses 123011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187582 # number of SCUpgradeReq MSHR misses 123111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187582 # number of SCUpgradeReq MSHR misses 123211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 123311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 123411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274670 # number of ReadExReq MSHR misses 123511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 274670 # number of ReadExReq MSHR misses 123611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688449 # number of ReadCleanReq MSHR misses 123711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688449 # number of ReadCleanReq MSHR misses 123811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 969295 # number of ReadSharedReq MSHR misses 123911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 969295 # number of ReadSharedReq MSHR misses 124011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601721 # number of InvalidateReq MSHR misses 124111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 601721 # number of InvalidateReq MSHR misses 124211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20593 # number of demand (read+write) MSHR misses 124311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9873 # number of demand (read+write) MSHR misses 124411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688449 # number of demand (read+write) MSHR misses 124511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243965 # number of demand (read+write) MSHR misses 124611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1962880 # number of demand (read+write) MSHR misses 124711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20593 # number of overall MSHR misses 124811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9873 # number of overall MSHR misses 124911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688449 # number of overall MSHR misses 125011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243965 # number of overall MSHR misses 125111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of overall MSHR misses 125211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2745221 # number of overall MSHR misses 125311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 125411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 125511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83834 # number of ReadReq MSHR uncacheable 125611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 125711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable 125811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 125911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 126011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115035 # number of overall MSHR uncacheable misses 126111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of ReadReq MSHR miss cycles 126211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 355875500 # number of ReadReq MSHR miss cycles 126311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 925633500 # number of ReadReq MSHR miss cycles 126411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of HardPFReq MSHR miss cycles 126511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38599728272 # number of HardPFReq MSHR miss cycles 126611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4476827494 # number of UpgradeReq MSHR miss cycles 126711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4476827494 # number of UpgradeReq MSHR miss cycles 126811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2879854497 # number of SCUpgradeReq MSHR miss cycles 126911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2879854497 # number of SCUpgradeReq MSHR miss cycles 127011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1583000 # number of SCUpgradeFailReq MSHR miss cycles 127111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1583000 # number of SCUpgradeFailReq MSHR miss cycles 127211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12562742498 # number of ReadExReq MSHR miss cycles 127311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12562742498 # number of ReadExReq MSHR miss cycles 127411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21394767500 # number of ReadCleanReq MSHR miss cycles 127511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21394767500 # number of ReadCleanReq MSHR miss cycles 127611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31646923991 # number of ReadSharedReq MSHR miss cycles 127711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31646923991 # number of ReadSharedReq MSHR miss cycles 127811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19132934000 # number of InvalidateReq MSHR miss cycles 127911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19132934000 # number of InvalidateReq MSHR miss cycles 128011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of demand (read+write) MSHR miss cycles 128111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 355875500 # number of demand (read+write) MSHR miss cycles 128211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21394767500 # number of demand (read+write) MSHR miss cycles 128311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44209666489 # number of demand (read+write) MSHR miss cycles 128411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 66530067489 # number of demand (read+write) MSHR miss cycles 128511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of overall MSHR miss cycles 128611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 355875500 # number of overall MSHR miss cycles 128711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21394767500 # number of overall MSHR miss cycles 128811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44209666489 # number of overall MSHR miss cycles 128911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of overall MSHR miss cycles 129011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 105129795761 # number of overall MSHR miss cycles 129111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles 129211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5835246500 # number of ReadReq MSHR uncacheable cycles 129311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10578580500 # number of ReadReq MSHR uncacheable cycles 129411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles 129511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5835246500 # number of overall MSHR uncacheable cycles 129611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10578580500 # number of overall MSHR uncacheable cycles 129711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for ReadReq accesses 129811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for ReadReq accesses 129911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041647 # mshr miss rate for ReadReq accesses 130010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 130110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 130211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 130311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 130411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 130511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 130610636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 130710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 130811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.232027 # mshr miss rate for ReadExReq accesses 130911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.232027 # mshr miss rate for ReadExReq accesses 131011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for ReadCleanReq accesses 131111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071624 # mshr miss rate for ReadCleanReq accesses 131211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255427 # mshr miss rate for ReadSharedReq accesses 131311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255427 # mshr miss rate for ReadSharedReq accesses 131411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.723907 # mshr miss rate for InvalidateReq accesses 131511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.723907 # mshr miss rate for InvalidateReq accesses 131611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for demand accesses 131711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for demand accesses 131811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for demand accesses 131911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for demand accesses 132011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.128108 # mshr miss rate for demand accesses 132111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for overall accesses 132211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for overall accesses 132311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for overall accesses 132411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for overall accesses 132510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 132611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.179167 # mshr miss rate for overall accesses 132711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average ReadReq mshr miss latency 132811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average ReadReq mshr miss latency 132911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370 # average ReadReq mshr miss latency 133011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average HardPFReq mshr miss latency 133111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608 # average HardPFReq mshr miss latency 133211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285 # average UpgradeReq mshr miss latency 133311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285 # average UpgradeReq mshr miss latency 133411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820 # average SCUpgradeReq mshr miss latency 133511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820 # average SCUpgradeReq mshr miss latency 133611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 791500 # average SCUpgradeFailReq mshr miss latency 133711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 791500 # average SCUpgradeFailReq mshr miss latency 133811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095 # average ReadExReq mshr miss latency 133911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095 # average ReadExReq mshr miss latency 134011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average ReadCleanReq mshr miss latency 134111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582 # average ReadCleanReq mshr miss latency 134211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572 # average ReadSharedReq mshr miss latency 134311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572 # average ReadSharedReq mshr miss latency 134411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884 # average InvalidateReq mshr miss latency 134511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884 # average InvalidateReq mshr miss latency 134611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency 134711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency 134811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency 134911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency 135011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396 # average overall mshr miss latency 135111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency 135211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency 135311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency 135411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency 135511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average overall mshr miss latency 135611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374 # average overall mshr miss latency 135711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency 135811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483 # average ReadReq mshr uncacheable latency 135911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437 # average ReadReq mshr uncacheable latency 136011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency 136111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175 # average overall mshr uncacheable latency 136211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796 # average overall mshr uncacheable latency 136311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 31463839 # Total number of requests made to the snoop filter. 136411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16044170 # Number of requests hitting in the snoop filter with a single holder of the requested data. 136511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3048 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 136611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 652134 # Total number of snoops made to the snoop filter. 136711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 652077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 136811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 57 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 136911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 137011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 887708 # Transaction distribution 137111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14387458 # Transaction distribution 137211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 31201 # Transaction distribution 137311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 31200 # Transaction distribution 137411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5457517 # Transaction distribution 137511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11506087 # Transaction distribution 137611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1359708 # Transaction distribution 137711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 999352 # Transaction distribution 137811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 137911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 454749 # Transaction distribution 138011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343952 # Transaction distribution 138111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 493156 # Transaction distribution 138211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 138311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 138411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1220335 # Transaction distribution 138511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1191280 # Transaction distribution 138611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9611986 # Transaction distribution 138711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4900402 # Transaction distribution 138811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 909564 # Transaction distribution 138911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 832554 # Transaction distribution 139011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28940003 # Packet count per connected master and slave (bytes) 139111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18484921 # Packet count per connected master and slave (bytes) 139211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391848 # Packet count per connected master and slave (bytes) 139311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1143553 # Packet count per connected master and slave (bytes) 139411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 48960325 # Packet count per connected master and slave (bytes) 139511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1233646912 # Cumulative packet size per connected master and slave (bytes) 139611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690994144 # Cumulative packet size per connected master and slave (bytes) 139711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1503536 # Cumulative packet size per connected master and slave (bytes) 139811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4348696 # Cumulative packet size per connected master and slave (bytes) 139911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1930493288 # Cumulative packet size per connected master and slave (bytes) 140011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 5822948 # Total snoops (count) 140111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 111810824 # Total snoop traffic (bytes) 140211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 22356517 # Request fanout histogram 140311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.042093 # Request fanout histogram 140411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.200815 # Request fanout histogram 140510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 140611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 21415512 95.79% 95.79% # Request fanout histogram 140711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 940948 4.21% 100.00% # Request fanout histogram 140811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 57 0.00% 100.00% # Request fanout histogram 140910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 141011138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 141110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 141211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 22356517 # Request fanout histogram 141311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 31390166976 # Layer occupancy (ticks) 141411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 141511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 183129639 # Layer occupancy (ticks) 141610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 141711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14498904485 # Layer occupancy (ticks) 141810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 141911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8149348322 # Layer occupancy (ticks) 142010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 142111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 204016279 # Layer occupancy (ticks) 142210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 142311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 600088255 # Layer occupancy (ticks) 142410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 142511754Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 132997996 # Number of BP lookups 142611754Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 94215152 # Number of conditional branches predicted 142711754Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6033479 # Number of conditional branches incorrect 142811754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 99520242 # Number of BTB lookups 142911754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 69476937 # Number of BTB hits 143010585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 143111754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 69.811865 # BTB Hit Percentage 143211754Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 15575496 # Number of times the RAS was used to get a target. 143311754Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1022946 # Number of incorrect RAS predictions. 143411754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectLookups 3462102 # Number of indirect predictor lookups. 143511754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectHits 2360825 # Number of indirect target hits. 143611754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectMisses 1101277 # Number of indirect misses. 143711754Sandreas.hansson@arm.comsystem.cpu1.branchPredindirectMispredicted 401735 # Number of mispredicted indirect branches. 143811754Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 143910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 144010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 144110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 144310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 144410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 144610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 144710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 145010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 145110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 145210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 145310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 146010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 146110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 146210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 146410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 146510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 146610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 146710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 146911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 271949 # Table walker walks requested 147011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 271949 # Table walker walks initiated with long descriptors 147111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9428 # Level at which table walker walks with long descriptors terminate 147211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76874 # Level at which table walker walks with long descriptors terminate 147311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 271949 # Table walker wait (enqueue to first request) latency 147411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 271949 100.00% 100.00% # Table walker wait (enqueue to first request) latency 147511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 271949 # Table walker wait (enqueue to first request) latency 147611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 86302 # Table walker service (enqueue to completion) latency 147711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504 # Table walker service (enqueue to completion) latency 147811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810 # Table walker service (enqueue to completion) latency 147911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024 # Table walker service (enqueue to completion) latency 148011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 85344 98.89% 98.89% # Table walker service (enqueue to completion) latency 148111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 718 0.83% 99.72% # Table walker service (enqueue to completion) latency 148211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 138 0.16% 99.88% # Table walker service (enqueue to completion) latency 148311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency 148411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 32 0.04% 99.96% # Table walker service (enqueue to completion) latency 148511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency 148611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 148711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 148811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 148911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 86302 # Table walker service (enqueue to completion) latency 149011754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 114608944 # Table walker pending requests distribution 149111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 114608944 100.00% 100.00% # Table walker pending requests distribution 149211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 114608944 # Table walker pending requests distribution 149311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 76874 89.08% 89.08% # Table walker page sizes translated 149411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 9428 10.92% 100.00% # Table walker page sizes translated 149511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 86302 # Table walker page sizes translated 149611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271949 # Table walker requests started/completed, data/inst 149710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 149811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271949 # Table walker requests started/completed, data/inst 149911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86302 # Table walker requests started/completed, data/inst 150010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 150111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86302 # Table walker requests started/completed, data/inst 150211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 358251 # Table walker requests started/completed, data/inst 150310585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 150410585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 150511754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 86154833 # DTB read hits 150611754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 225974 # DTB read misses 150711754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 74805729 # DTB write hits 150811754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 45975 # DTB write misses 150911441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 151010585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151111754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 151211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 151311754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 36571 # Number of entries that have been flushed from TLB 151411754Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1221 # Number of TLB faults due to alignment restrictions 151511754Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 7188 # Number of TLB faults due to prefetch 151610585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 151711754Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10263 # Number of TLB faults due to permissions restrictions 151811754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 86380807 # DTB read accesses 151911754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 74851704 # DTB write accesses 152010585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 152111754Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 160960562 # DTB hits 152211754Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 271949 # DTB misses 152311754Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 161232511 # DTB accesses 152411754Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 152510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 152610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 152910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 153010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 153110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 153210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 153310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 153410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 153510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 153610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 153710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 153810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 153910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 154010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 154110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 154210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 154310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 154410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 154510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 154610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 154710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 154910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 155010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 155110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 155210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 155310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 155411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 155511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 60899 # Table walker walks requested 155611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 60899 # Table walker walks initiated with long descriptors 155711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 513 # Level at which table walker walks with long descriptors terminate 155811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 50941 # Level at which table walker walks with long descriptors terminate 155911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60899 # Table walker wait (enqueue to first request) latency 156011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60899 100.00% 100.00% # Table walker wait (enqueue to first request) latency 156111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60899 # Table walker wait (enqueue to first request) latency 156211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 51454 # Table walker service (enqueue to completion) latency 156311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25618.018036 # Table walker service (enqueue to completion) latency 156411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553 # Table walker service (enqueue to completion) latency 156511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181 # Table walker service (enqueue to completion) latency 156611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 50489 98.12% 98.12% # Table walker service (enqueue to completion) latency 156711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 670 1.30% 99.43% # Table walker service (enqueue to completion) latency 156811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.41% 99.84% # Table walker service (enqueue to completion) latency 156911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 46 0.09% 99.93% # Table walker service (enqueue to completion) latency 157011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.95% # Table walker service (enqueue to completion) latency 157111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency 157211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 157311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 157411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 13 0.03% 100.00% # Table walker service (enqueue to completion) latency 157511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 157611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 51454 # Table walker service (enqueue to completion) latency 157711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 113972444 # Table walker pending requests distribution 157811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 113972444 100.00% 100.00% # Table walker pending requests distribution 157911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 113972444 # Table walker pending requests distribution 158011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 50941 99.00% 99.00% # Table walker page sizes translated 158111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 513 1.00% 100.00% # Table walker page sizes translated 158211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 51454 # Table walker page sizes translated 158310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 158411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60899 # Table walker requests started/completed, data/inst 158511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60899 # Table walker requests started/completed, data/inst 158610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51454 # Table walker requests started/completed, data/inst 158811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 51454 # Table walker requests started/completed, data/inst 158911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 112353 # Table walker requests started/completed, data/inst 159011754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 236231380 # ITB inst hits 159111754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 60899 # ITB inst misses 159210585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 159310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 159410585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 159510585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 159611441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 159710585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159811754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 159911680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 160011754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 26538 # Number of entries that have been flushed from TLB 160110585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 160210585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 160310585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 160411754Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 178013 # Number of TLB faults due to permissions restrictions 160510585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 160610585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 160711754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 236292279 # ITB inst accesses 160811754Sandreas.hansson@arm.comsystem.cpu1.itb.hits 236231380 # DTB hits 160911754Sandreas.hansson@arm.comsystem.cpu1.itb.misses 60899 # DTB misses 161011754Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 236292279 # DTB accesses 161111754Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 9440 # Number of power state transitions 161211754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 4720 # Distribution of time spent in the clock gated state 161311754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 9937322156.794067 # Distribution of time spent in the clock gated state 161411754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 214697400239.899719 # Distribution of time spent in the clock gated state 161511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3380 71.61% 71.61% # Distribution of time spent in the clock gated state 161611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1320 27.97% 99.58% # Distribution of time spent in the clock gated state 161711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.11% 99.68% # Distribution of time spent in the clock gated state 161811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state 161911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.75% # Distribution of time spent in the clock gated state 162011754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 162111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 162211754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.21% 100.00% # Distribution of time spent in the clock gated state 162311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 162411754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813594348000 # Distribution of time spent in the clock gated state 162511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 4720 # Distribution of time spent in the clock gated state 162611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 452049545932 # Cumulative time (in ticks) in various power states 162711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068 # Cumulative time (in ticks) in various power states 162811754Sandreas.hansson@arm.comsystem.cpu1.numCycles 904105497 # number of cpu cycles simulated 162910585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 163010585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 163111754Sandreas.hansson@arm.comsystem.cpu1.committedInsts 436062178 # Number of instructions committed 163211754Sandreas.hansson@arm.comsystem.cpu1.committedOps 513430287 # Number of ops (including micro ops) committed 163311754Sandreas.hansson@arm.comsystem.cpu1.discardedOps 45590191 # Number of ops (including micro ops) which were discarded before commit 163411754Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching 163511754Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93808990671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 163611754Sandreas.hansson@arm.comsystem.cpu1.cpi 2.073341 # CPI: cycles per instruction 163711754Sandreas.hansson@arm.comsystem.cpu1.ipc 0.482313 # IPC: instructions per cycle 163811754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 163911754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntAlu 354600208 69.06% 69.06% # Class of committed instruction 164011754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntMult 1143323 0.22% 69.29% # Class of committed instruction 164111754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntDiv 59569 0.01% 69.30% # Class of committed instruction 164211754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction 164311754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction 164411754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction 164511754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction 164611754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.30% # Class of committed instruction 164711754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction 164811754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMisc 63096 0.01% 69.31% # Class of committed instruction 164911754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction 165011754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction 165111754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction 165211754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction 165311754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction 165411754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction 165511754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction 165611754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction 165711754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction 165811754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction 165911754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction 166011754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction 166111754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction 166211754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction 166311754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction 166411754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction 166511754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction 166611754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.31% # Class of committed instruction 166711754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction 166811754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction 166911754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction 167011754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::MemRead 82989666 16.16% 85.48% # Class of committed instruction 167111754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::MemWrite 74191847 14.45% 99.93% # Class of committed instruction 167211754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMemRead 64253 0.01% 99.94% # Class of committed instruction 167311754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMemWrite 318324 0.06% 100.00% # Class of committed instruction 167411441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 167511441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 167611754Sandreas.hansson@arm.comsystem.cpu1.op_class_0::total 513430287 # Class of committed instruction 167710585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 167811754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 4720 # number of quiesce instructions executed 167911754Sandreas.hansson@arm.comsystem.cpu1.tickCycles 704305988 # Number of cycles that the object actually ticked 168011754Sandreas.hansson@arm.comsystem.cpu1.idleCycles 199799509 # Total number of cycles that the object has spent stopped 168111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 168211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5048947 # number of replacements 168311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 416.228585 # Cycle average of tags in use 168411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 153590869 # Total number of references to valid blocks. 168511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5049459 # Sample count of references to valid blocks. 168611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 30.417292 # Average number of references to valid blocks. 168711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8378525599500 # Cycle when the warmup percentage was hit. 168811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 416.228585 # Average occupied blocks per requestor 168911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.812946 # Average percentage of cache occupancy 169011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.812946 # Average percentage of cache occupancy 169111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 169211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 169311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 169411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 169511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 169611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 324622701 # Number of tag accesses 169711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 324622701 # Number of data accesses 169811754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 169911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 79356977 # number of ReadReq hits 170011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 79356977 # number of ReadReq hits 170111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 69837106 # number of WriteReq hits 170211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 69837106 # number of WriteReq hits 170311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 233112 # number of SoftPFReq hits 170411754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 233112 # number of SoftPFReq hits 170511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 147127 # number of WriteLineReq hits 170611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 147127 # number of WriteLineReq hits 170711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782955 # number of LoadLockedReq hits 170811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1782955 # number of LoadLockedReq hits 170911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1749534 # number of StoreCondReq hits 171011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1749534 # number of StoreCondReq hits 171111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 149341210 # number of demand (read+write) hits 171211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 149341210 # number of demand (read+write) hits 171311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 149574322 # number of overall hits 171411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 149574322 # number of overall hits 171511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3104936 # number of ReadReq misses 171611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3104936 # number of ReadReq misses 171711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2154320 # number of WriteReq misses 171811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2154320 # number of WriteReq misses 171911754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 600203 # number of SoftPFReq misses 172011754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 600203 # number of SoftPFReq misses 172111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 416637 # number of WriteLineReq misses 172211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 416637 # number of WriteLineReq misses 172311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162547 # number of LoadLockedReq misses 172411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 162547 # number of LoadLockedReq misses 172511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 194652 # number of StoreCondReq misses 172611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 194652 # number of StoreCondReq misses 172711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5675893 # number of demand (read+write) misses 172811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5675893 # number of demand (read+write) misses 172911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6276096 # number of overall misses 173011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6276096 # number of overall misses 173111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47629871000 # number of ReadReq miss cycles 173211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 47629871000 # number of ReadReq miss cycles 173311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40774475000 # number of WriteReq miss cycles 173411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 40774475000 # number of WriteReq miss cycles 173511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9727566000 # number of WriteLineReq miss cycles 173611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 9727566000 # number of WriteLineReq miss cycles 173711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2415502000 # number of LoadLockedReq miss cycles 173811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2415502000 # number of LoadLockedReq miss cycles 173911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4643846000 # number of StoreCondReq miss cycles 174011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4643846000 # number of StoreCondReq miss cycles 174111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2158500 # number of StoreCondFailReq miss cycles 174211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2158500 # number of StoreCondFailReq miss cycles 174311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 98131912000 # number of demand (read+write) miss cycles 174411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 98131912000 # number of demand (read+write) miss cycles 174511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 98131912000 # number of overall miss cycles 174611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 98131912000 # number of overall miss cycles 174711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 82461913 # number of ReadReq accesses(hits+misses) 174811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 82461913 # number of ReadReq accesses(hits+misses) 174911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 71991426 # number of WriteReq accesses(hits+misses) 175011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 71991426 # number of WriteReq accesses(hits+misses) 175111754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833315 # number of SoftPFReq accesses(hits+misses) 175211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 833315 # number of SoftPFReq accesses(hits+misses) 175311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 563764 # number of WriteLineReq accesses(hits+misses) 175411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 563764 # number of WriteLineReq accesses(hits+misses) 175511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945502 # number of LoadLockedReq accesses(hits+misses) 175611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1945502 # number of LoadLockedReq accesses(hits+misses) 175711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944186 # number of StoreCondReq accesses(hits+misses) 175811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1944186 # number of StoreCondReq accesses(hits+misses) 175911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 155017103 # number of demand (read+write) accesses 176011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 155017103 # number of demand (read+write) accesses 176111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 155850418 # number of overall (read+write) accesses 176211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 155850418 # number of overall (read+write) accesses 176311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037653 # miss rate for ReadReq accesses 176411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037653 # miss rate for ReadReq accesses 176511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029925 # miss rate for WriteReq accesses 176611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.029925 # miss rate for WriteReq accesses 176711754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.720259 # miss rate for SoftPFReq accesses 176811754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.720259 # miss rate for SoftPFReq accesses 176911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739027 # miss rate for WriteLineReq accesses 177011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.739027 # miss rate for WriteLineReq accesses 177111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083550 # miss rate for LoadLockedReq accesses 177211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083550 # miss rate for LoadLockedReq accesses 177311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100120 # miss rate for StoreCondReq accesses 177411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.100120 # miss rate for StoreCondReq accesses 177511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.036615 # miss rate for demand accesses 177611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.036615 # miss rate for demand accesses 177711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.040270 # miss rate for overall accesses 177811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.040270 # miss rate for overall accesses 177911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199 # average ReadReq miss latency 178011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199 # average ReadReq miss latency 178111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345 # average WriteReq miss latency 178211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345 # average WriteReq miss latency 178311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765 # average WriteLineReq miss latency 178411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765 # average WriteLineReq miss latency 178511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628 # average LoadLockedReq miss latency 178611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628 # average LoadLockedReq miss latency 178711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746 # average StoreCondReq miss latency 178811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746 # average StoreCondReq miss latency 178910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 179010585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 179111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291 # average overall miss latency 179211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17289.246291 # average overall miss latency 179311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740 # average overall miss latency 179411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15635.820740 # average overall miss latency 179510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179610585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179710585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 179810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 179910585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180010585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180111754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5048949 # number of writebacks 180211754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5048949 # number of writebacks 180311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 157294 # number of ReadReq MSHR hits 180411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 157294 # number of ReadReq MSHR hits 180511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 878635 # number of WriteReq MSHR hits 180611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 878635 # number of WriteReq MSHR hits 180711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 59 # number of WriteLineReq MSHR hits 180811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 59 # number of WriteLineReq MSHR hits 180911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39126 # number of LoadLockedReq MSHR hits 181011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 39126 # number of LoadLockedReq MSHR hits 181111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 65 # number of StoreCondReq MSHR hits 181211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits 181311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1035988 # number of demand (read+write) MSHR hits 181411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1035988 # number of demand (read+write) MSHR hits 181511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1035988 # number of overall MSHR hits 181611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1035988 # number of overall MSHR hits 181711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2947642 # number of ReadReq MSHR misses 181811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2947642 # number of ReadReq MSHR misses 181911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1275685 # number of WriteReq MSHR misses 182011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1275685 # number of WriteReq MSHR misses 182111754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599894 # number of SoftPFReq MSHR misses 182211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 599894 # number of SoftPFReq MSHR misses 182311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 416578 # number of WriteLineReq MSHR misses 182411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 416578 # number of WriteLineReq MSHR misses 182511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123421 # number of LoadLockedReq MSHR misses 182611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 123421 # number of LoadLockedReq MSHR misses 182711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194587 # number of StoreCondReq MSHR misses 182811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 194587 # number of StoreCondReq MSHR misses 182911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4639905 # number of demand (read+write) MSHR misses 183011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4639905 # number of demand (read+write) MSHR misses 183111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5239799 # number of overall MSHR misses 183211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5239799 # number of overall MSHR misses 183311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable 183411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 6968 # number of ReadReq MSHR uncacheable 183511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 183611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable 183711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses 183811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 14155 # number of overall MSHR uncacheable misses 183911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41244047000 # number of ReadReq MSHR miss cycles 184011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 41244047000 # number of ReadReq MSHR miss cycles 184111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23526690000 # number of WriteReq MSHR miss cycles 184211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 23526690000 # number of WriteReq MSHR miss cycles 184311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13870615000 # number of SoftPFReq MSHR miss cycles 184411754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13870615000 # number of SoftPFReq MSHR miss cycles 184511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9306680500 # number of WriteLineReq MSHR miss cycles 184611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9306680500 # number of WriteLineReq MSHR miss cycles 184711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1636714500 # number of LoadLockedReq MSHR miss cycles 184811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1636714500 # number of LoadLockedReq MSHR miss cycles 184911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4447799000 # number of StoreCondReq MSHR miss cycles 185011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4447799000 # number of StoreCondReq MSHR miss cycles 185111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1876000 # number of StoreCondFailReq MSHR miss cycles 185211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1876000 # number of StoreCondFailReq MSHR miss cycles 185311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74077417500 # number of demand (read+write) MSHR miss cycles 185411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 74077417500 # number of demand (read+write) MSHR miss cycles 185511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87948032500 # number of overall MSHR miss cycles 185611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 87948032500 # number of overall MSHR miss cycles 185711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 882714500 # number of ReadReq MSHR uncacheable cycles 185811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 882714500 # number of ReadReq MSHR uncacheable cycles 185911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 882714500 # number of overall MSHR uncacheable cycles 186011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 882714500 # number of overall MSHR uncacheable cycles 186111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035745 # mshr miss rate for ReadReq accesses 186211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035745 # mshr miss rate for ReadReq accesses 186311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017720 # mshr miss rate for WriteReq accesses 186411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 186511754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.719889 # mshr miss rate for SoftPFReq accesses 186611754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.719889 # mshr miss rate for SoftPFReq accesses 186711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738923 # mshr miss rate for WriteLineReq accesses 186811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738923 # mshr miss rate for WriteLineReq accesses 186911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063439 # mshr miss rate for LoadLockedReq accesses 187011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063439 # mshr miss rate for LoadLockedReq accesses 187111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100087 # mshr miss rate for StoreCondReq accesses 187211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100087 # mshr miss rate for StoreCondReq accesses 187311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses 187411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses 187511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033621 # mshr miss rate for overall accesses 187611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.033621 # mshr miss rate for overall accesses 187711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169 # average ReadReq mshr miss latency 187811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169 # average ReadReq mshr miss latency 187911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614 # average WriteReq mshr miss latency 188011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614 # average WriteReq mshr miss latency 188111754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514 # average SoftPFReq mshr miss latency 188211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514 # average SoftPFReq mshr miss latency 188311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320 # average WriteLineReq mshr miss latency 188411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320 # average WriteLineReq mshr miss latency 188511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881 # average LoadLockedReq mshr miss latency 188611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881 # average LoadLockedReq mshr miss latency 188711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944 # average StoreCondReq mshr miss latency 188811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944 # average StoreCondReq mshr miss latency 188910636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 189010585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 189111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544 # average overall mshr miss latency 189211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544 # average overall mshr miss latency 189311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505 # average overall mshr miss latency 189411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505 # average overall mshr miss latency 189511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419 # average ReadReq mshr uncacheable latency 189611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419 # average ReadReq mshr uncacheable latency 189711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624 # average overall mshr uncacheable latency 189811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624 # average overall mshr uncacheable latency 189911754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 190011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9106015 # number of replacements 190111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 507.214941 # Cycle average of tags in use 190211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 226941610 # Total number of references to valid blocks. 190311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9106527 # Sample count of references to valid blocks. 190411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 24.920764 # Average number of references to valid blocks. 190511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8368863514500 # Cycle when the warmup percentage was hit. 190611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.214941 # Average occupied blocks per requestor 190711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990654 # Average percentage of cache occupancy 190811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990654 # Average percentage of cache occupancy 190910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 191011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id 191111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 191211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 191310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 191411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 481202803 # Number of tag accesses 191511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 481202803 # Number of data accesses 191611754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 191711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 226941610 # number of ReadReq hits 191811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 226941610 # number of ReadReq hits 191911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 226941610 # number of demand (read+write) hits 192011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 226941610 # number of demand (read+write) hits 192111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 226941610 # number of overall hits 192211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 226941610 # number of overall hits 192311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9106528 # number of ReadReq misses 192411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9106528 # number of ReadReq misses 192511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9106528 # number of demand (read+write) misses 192611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9106528 # number of demand (read+write) misses 192711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9106528 # number of overall misses 192811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9106528 # number of overall misses 192911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93334039500 # number of ReadReq miss cycles 193011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 93334039500 # number of ReadReq miss cycles 193111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 93334039500 # number of demand (read+write) miss cycles 193211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 93334039500 # number of demand (read+write) miss cycles 193311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 93334039500 # number of overall miss cycles 193411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 93334039500 # number of overall miss cycles 193511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 236048138 # number of ReadReq accesses(hits+misses) 193611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 236048138 # number of ReadReq accesses(hits+misses) 193711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 236048138 # number of demand (read+write) accesses 193811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 236048138 # number of demand (read+write) accesses 193911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 236048138 # number of overall (read+write) accesses 194011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 236048138 # number of overall (read+write) accesses 194111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038579 # miss rate for ReadReq accesses 194211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.038579 # miss rate for ReadReq accesses 194311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.038579 # miss rate for demand accesses 194411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.038579 # miss rate for demand accesses 194511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.038579 # miss rate for overall accesses 194611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.038579 # miss rate for overall accesses 194711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510 # average ReadReq miss latency 194811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510 # average ReadReq miss latency 194911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency 195011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10249.135510 # average overall miss latency 195111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency 195211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10249.135510 # average overall miss latency 195310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 195410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 195710585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 195810585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 195911754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 9106015 # number of writebacks 196011754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 9106015 # number of writebacks 196111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9106528 # number of ReadReq MSHR misses 196211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9106528 # number of ReadReq MSHR misses 196311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9106528 # number of demand (read+write) MSHR misses 196411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9106528 # number of demand (read+write) MSHR misses 196511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9106528 # number of overall MSHR misses 196611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9106528 # number of overall MSHR misses 196711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 196811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 196911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 197011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 197111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88780776000 # number of ReadReq MSHR miss cycles 197211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 88780776000 # number of ReadReq MSHR miss cycles 197311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88780776000 # number of demand (read+write) MSHR miss cycles 197411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 88780776000 # number of demand (read+write) MSHR miss cycles 197511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88780776000 # number of overall MSHR miss cycles 197611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 88780776000 # number of overall MSHR miss cycles 197711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9602500 # number of ReadReq MSHR uncacheable cycles 197811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9602500 # number of ReadReq MSHR uncacheable cycles 197911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9602500 # number of overall MSHR uncacheable cycles 198011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 9602500 # number of overall MSHR uncacheable cycles 198111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for ReadReq accesses 198211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038579 # mshr miss rate for ReadReq accesses 198311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for demand accesses 198411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses 198511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for overall accesses 198611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses 198711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average ReadReq mshr miss latency 198811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9749.135565 # average ReadReq mshr miss latency 198911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency 199011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency 199111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency 199211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency 199311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average ReadReq mshr uncacheable latency 199411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368 # average ReadReq mshr uncacheable latency 199511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average overall mshr uncacheable latency 199611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368 # average overall mshr uncacheable latency 199711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 199811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7104941 # number of hwpf issued 199911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7105044 # number of prefetch candidates identified 200011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue 200110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 200210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 200311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 891372 # number of prefetches not generated due to page crossing 200411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 200511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2193537 # number of replacements 200611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13101.642441 # Cycle average of tags in use 200711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 12964075 # Total number of references to valid blocks. 200811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2209317 # Sample count of references to valid blocks. 200911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.867911 # Average number of references to valid blocks. 201011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 201111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283 # Average occupied blocks per requestor 201211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 29.247108 # Average occupied blocks per requestor 201311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.647207 # Average occupied blocks per requestor 201411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 236.020843 # Average occupied blocks per requestor 201511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.782454 # Average percentage of cache occupancy 201611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001785 # Average percentage of cache occupancy 201711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001016 # Average percentage of cache occupancy 201811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014406 # Average percentage of cache occupancy 201911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.799661 # Average percentage of cache occupancy 202011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 358 # Occupied blocks per task id 202111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 202211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15375 # Occupied blocks per task id 202311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 202411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 202511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id 202611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 74 # Occupied blocks per task id 202711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 202811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 202911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 203011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 203111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 203211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1753 # Occupied blocks per task id 203311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6630 # Occupied blocks per task id 203411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5167 # Occupied blocks per task id 203511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id 203611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021851 # Percentage of cache occupancy per task id 203711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id 203811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.938416 # Percentage of cache occupancy per task id 203911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 486850576 # Number of tag accesses 204011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 486850576 # Number of data accesses 204111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 204211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 506555 # number of ReadReq hits 204311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 152150 # number of ReadReq hits 204411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 658705 # number of ReadReq hits 204511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3098065 # number of WritebackDirty hits 204611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3098065 # number of WritebackDirty hits 204711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 11055157 # number of WritebackClean hits 204811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 11055157 # number of WritebackClean hits 204911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits 205011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 205111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 205211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 205311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 815552 # number of ReadExReq hits 205411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 815552 # number of ReadExReq hits 205511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8406399 # number of ReadCleanReq hits 205611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8406399 # number of ReadCleanReq hits 205711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2722472 # number of ReadSharedReq hits 205811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2722472 # number of ReadSharedReq hits 205911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 157346 # number of InvalidateReq hits 206011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 157346 # number of InvalidateReq hits 206111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 506555 # number of demand (read+write) hits 206211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 152150 # number of demand (read+write) hits 206311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8406399 # number of demand (read+write) hits 206411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3538024 # number of demand (read+write) hits 206511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 12603128 # number of demand (read+write) hits 206611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 506555 # number of overall hits 206711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 152150 # number of overall hits 206811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8406399 # number of overall hits 206911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3538024 # number of overall hits 207011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 12603128 # number of overall hits 207111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20442 # number of ReadReq misses 207211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9977 # number of ReadReq misses 207311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 30419 # number of ReadReq misses 207411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 207511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 207611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 219088 # number of UpgradeReq misses 207711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 219088 # number of UpgradeReq misses 207811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194583 # number of SCUpgradeReq misses 207911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 194583 # number of SCUpgradeReq misses 208011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 208111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 208211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 241398 # number of ReadExReq misses 208311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 241398 # number of ReadExReq misses 208411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700129 # number of ReadCleanReq misses 208511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 700129 # number of ReadCleanReq misses 208611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 948287 # number of ReadSharedReq misses 208711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 948287 # number of ReadSharedReq misses 208811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 259232 # number of InvalidateReq misses 208911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 259232 # number of InvalidateReq misses 209011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20442 # number of demand (read+write) misses 209111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9977 # number of demand (read+write) misses 209211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 700129 # number of demand (read+write) misses 209311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1189685 # number of demand (read+write) misses 209411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1920233 # number of demand (read+write) misses 209511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20442 # number of overall misses 209611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9977 # number of overall misses 209711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 700129 # number of overall misses 209811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1189685 # number of overall misses 209911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1920233 # number of overall misses 210011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 617018000 # number of ReadReq miss cycles 210111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 362407000 # number of ReadReq miss cycles 210211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 979425000 # number of ReadReq miss cycles 210311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 937065000 # number of UpgradeReq miss cycles 210411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 937065000 # number of UpgradeReq miss cycles 210511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273754000 # number of SCUpgradeReq miss cycles 210611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273754000 # number of SCUpgradeReq miss cycles 210711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1804499 # number of SCUpgradeFailReq miss cycles 210811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1804499 # number of SCUpgradeFailReq miss cycles 210911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10806413996 # number of ReadExReq miss cycles 211011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 10806413996 # number of ReadExReq miss cycles 211111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24362152500 # number of ReadCleanReq miss cycles 211211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 24362152500 # number of ReadCleanReq miss cycles 211311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33291553995 # number of ReadSharedReq miss cycles 211411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 33291553995 # number of ReadSharedReq miss cycles 211511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 509000 # number of InvalidateReq miss cycles 211611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 509000 # number of InvalidateReq miss cycles 211711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 617018000 # number of demand (read+write) miss cycles 211811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 362407000 # number of demand (read+write) miss cycles 211911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 24362152500 # number of demand (read+write) miss cycles 212011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 44097967991 # number of demand (read+write) miss cycles 212111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 69439545491 # number of demand (read+write) miss cycles 212211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 617018000 # number of overall miss cycles 212311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 362407000 # number of overall miss cycles 212411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 24362152500 # number of overall miss cycles 212511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 44097967991 # number of overall miss cycles 212611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 69439545491 # number of overall miss cycles 212711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 526997 # number of ReadReq accesses(hits+misses) 212811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 162127 # number of ReadReq accesses(hits+misses) 212911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 689124 # number of ReadReq accesses(hits+misses) 213011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3098065 # number of WritebackDirty accesses(hits+misses) 213111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3098065 # number of WritebackDirty accesses(hits+misses) 213211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 11055158 # number of WritebackClean accesses(hits+misses) 213311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 11055158 # number of WritebackClean accesses(hits+misses) 213411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219089 # number of UpgradeReq accesses(hits+misses) 213511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 219089 # number of UpgradeReq accesses(hits+misses) 213611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194584 # number of SCUpgradeReq accesses(hits+misses) 213711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 194584 # number of SCUpgradeReq accesses(hits+misses) 213811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 213911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 214011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1056950 # number of ReadExReq accesses(hits+misses) 214111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1056950 # number of ReadExReq accesses(hits+misses) 214211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9106528 # number of ReadCleanReq accesses(hits+misses) 214311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9106528 # number of ReadCleanReq accesses(hits+misses) 214411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3670759 # number of ReadSharedReq accesses(hits+misses) 214511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3670759 # number of ReadSharedReq accesses(hits+misses) 214611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416578 # number of InvalidateReq accesses(hits+misses) 214711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 416578 # number of InvalidateReq accesses(hits+misses) 214811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 526997 # number of demand (read+write) accesses 214911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 162127 # number of demand (read+write) accesses 215011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9106528 # number of demand (read+write) accesses 215111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4727709 # number of demand (read+write) accesses 215211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 14523361 # number of demand (read+write) accesses 215311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 526997 # number of overall (read+write) accesses 215411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 162127 # number of overall (read+write) accesses 215511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9106528 # number of overall (read+write) accesses 215611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4727709 # number of overall (read+write) accesses 215711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 14523361 # number of overall (read+write) accesses 215811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for ReadReq accesses 215911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061538 # miss rate for ReadReq accesses 216011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.044142 # miss rate for ReadReq accesses 216111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 216211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 216311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for UpgradeReq accesses 216411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999995 # miss rate for UpgradeReq accesses 216511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses 216611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 216710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 216810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 216911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228391 # miss rate for ReadExReq accesses 217011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.228391 # miss rate for ReadExReq accesses 217111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076882 # miss rate for ReadCleanReq accesses 217211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076882 # miss rate for ReadCleanReq accesses 217311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258335 # miss rate for ReadSharedReq accesses 217411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258335 # miss rate for ReadSharedReq accesses 217511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622289 # miss rate for InvalidateReq accesses 217611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622289 # miss rate for InvalidateReq accesses 217711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for demand accesses 217811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061538 # miss rate for demand accesses 217911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076882 # miss rate for demand accesses 218011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251641 # miss rate for demand accesses 218111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.132217 # miss rate for demand accesses 218211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for overall accesses 218311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061538 # miss rate for overall accesses 218411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076882 # miss rate for overall accesses 218511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251641 # miss rate for overall accesses 218611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.132217 # miss rate for overall accesses 218711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average ReadReq miss latency 218811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36324.245765 # average ReadReq miss latency 218911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 32197.804004 # average ReadReq miss latency 219011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4277.116958 # average UpgradeReq miss latency 219111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4277.116958 # average UpgradeReq miss latency 219211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1406.875215 # average SCUpgradeReq miss latency 219311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1406.875215 # average SCUpgradeReq miss latency 219411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 601499.666667 # average SCUpgradeFailReq miss latency 219511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601499.666667 # average SCUpgradeFailReq miss latency 219611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44765.963247 # average ReadExReq miss latency 219711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44765.963247 # average ReadExReq miss latency 219811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34796.662472 # average ReadCleanReq miss latency 219911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34796.662472 # average ReadCleanReq miss latency 220011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35107.044592 # average ReadSharedReq miss latency 220111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35107.044592 # average ReadSharedReq miss latency 220211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1.963492 # average InvalidateReq miss latency 220311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1.963492 # average InvalidateReq miss latency 220411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency 220511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency 220611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency 220711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency 220811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 36162.041529 # average overall miss latency 220911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency 221011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency 221111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency 221211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency 221311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 36162.041529 # average overall miss latency 221411441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 221510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 221611441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 221710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 221811441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.unused_prefetches 43998 # number of HardPF blocks evicted w/o reference 222111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1082545 # number of writebacks 222211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1082545 # number of writebacks 222311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 17 # number of ReadReq MSHR hits 222411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 90 # number of ReadReq MSHR hits 222511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 222611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6036 # number of ReadExReq MSHR hits 222711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 6036 # number of ReadExReq MSHR hits 222811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 222911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 223011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 724 # number of ReadSharedReq MSHR hits 223111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 724 # number of ReadSharedReq MSHR hits 223211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits 223311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 223411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 17 # number of demand (read+write) MSHR hits 223511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 90 # number of demand (read+write) MSHR hits 223611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 223711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 6760 # number of demand (read+write) MSHR hits 223811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 6871 # number of demand (read+write) MSHR hits 223911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 17 # number of overall MSHR hits 224011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 90 # number of overall MSHR hits 224111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 224211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 6760 # number of overall MSHR hits 224311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 6871 # number of overall MSHR hits 224411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20425 # number of ReadReq MSHR misses 224511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9887 # number of ReadReq MSHR misses 224611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 30312 # number of ReadReq MSHR misses 224711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 224811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 224911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of HardPFReq MSHR misses 225011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 721434 # number of HardPFReq MSHR misses 225111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 219088 # number of UpgradeReq MSHR misses 225211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 219088 # number of UpgradeReq MSHR misses 225311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194583 # number of SCUpgradeReq MSHR misses 225411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194583 # number of SCUpgradeReq MSHR misses 225511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 225611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 225711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235362 # number of ReadExReq MSHR misses 225811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 235362 # number of ReadExReq MSHR misses 225911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700125 # number of ReadCleanReq MSHR misses 226011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700125 # number of ReadCleanReq MSHR misses 226111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 947563 # number of ReadSharedReq MSHR misses 226211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 947563 # number of ReadSharedReq MSHR misses 226311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 259229 # number of InvalidateReq MSHR misses 226411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 259229 # number of InvalidateReq MSHR misses 226511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20425 # number of demand (read+write) MSHR misses 226611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9887 # number of demand (read+write) MSHR misses 226711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700125 # number of demand (read+write) MSHR misses 226811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1182925 # number of demand (read+write) MSHR misses 226911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1913362 # number of demand (read+write) MSHR misses 227011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20425 # number of overall MSHR misses 227111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9887 # number of overall MSHR misses 227211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700125 # number of overall MSHR misses 227311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1182925 # number of overall MSHR misses 227411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of overall MSHR misses 227511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2634796 # number of overall MSHR misses 227611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 227711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable 227811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7063 # number of ReadReq MSHR uncacheable 227911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 228011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable 228111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 228211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses 228311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14250 # number of overall MSHR uncacheable misses 228411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of ReadReq MSHR miss cycles 228511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 301606000 # number of ReadReq MSHR miss cycles 228611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 795670000 # number of ReadReq MSHR miss cycles 228711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of HardPFReq MSHR miss cycles 228811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29780460685 # number of HardPFReq MSHR miss cycles 228911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4150846499 # number of UpgradeReq MSHR miss cycles 229011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4150846499 # number of UpgradeReq MSHR miss cycles 229111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2983943996 # number of SCUpgradeReq MSHR miss cycles 229211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2983943996 # number of SCUpgradeReq MSHR miss cycles 229311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1522499 # number of SCUpgradeFailReq MSHR miss cycles 229411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1522499 # number of SCUpgradeFailReq MSHR miss cycles 229511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8542642996 # number of ReadExReq MSHR miss cycles 229611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8542642996 # number of ReadExReq MSHR miss cycles 229711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20161321500 # number of ReadCleanReq MSHR miss cycles 229811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20161321500 # number of ReadCleanReq MSHR miss cycles 229911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27488554995 # number of ReadSharedReq MSHR miss cycles 230011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27488554995 # number of ReadSharedReq MSHR miss cycles 230111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6032275000 # number of InvalidateReq MSHR miss cycles 230211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6032275000 # number of InvalidateReq MSHR miss cycles 230311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of demand (read+write) MSHR miss cycles 230411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 301606000 # number of demand (read+write) MSHR miss cycles 230511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20161321500 # number of demand (read+write) MSHR miss cycles 230611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36031197991 # number of demand (read+write) MSHR miss cycles 230711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 56988189491 # number of demand (read+write) MSHR miss cycles 230811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of overall MSHR miss cycles 230911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 301606000 # number of overall MSHR miss cycles 231011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20161321500 # number of overall MSHR miss cycles 231111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36031197991 # number of overall MSHR miss cycles 231211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of overall MSHR miss cycles 231311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 86768650176 # number of overall MSHR miss cycles 231411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8842500 # number of ReadReq MSHR uncacheable cycles 231511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 826904500 # number of ReadReq MSHR uncacheable cycles 231611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 835747000 # number of ReadReq MSHR uncacheable cycles 231711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8842500 # number of overall MSHR uncacheable cycles 231811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 826904500 # number of overall MSHR uncacheable cycles 231911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 835747000 # number of overall MSHR uncacheable cycles 232011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for ReadReq accesses 232111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for ReadReq accesses 232211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043986 # mshr miss rate for ReadReq accesses 232311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 232411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 232510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 232610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 232711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for UpgradeReq accesses 232811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for UpgradeReq accesses 232911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 233011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 233110636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 233210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 233311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222680 # mshr miss rate for ReadExReq accesses 233411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222680 # mshr miss rate for ReadExReq accesses 233511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for ReadCleanReq accesses 233611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076882 # mshr miss rate for ReadCleanReq accesses 233711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258138 # mshr miss rate for ReadSharedReq accesses 233811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258138 # mshr miss rate for ReadSharedReq accesses 233911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.622282 # mshr miss rate for InvalidateReq accesses 234011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.622282 # mshr miss rate for InvalidateReq accesses 234111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for demand accesses 234211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for demand accesses 234311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for demand accesses 234411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for demand accesses 234511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.131744 # mshr miss rate for demand accesses 234611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for overall accesses 234711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for overall accesses 234811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for overall accesses 234911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for overall accesses 235010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 235111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.181418 # mshr miss rate for overall accesses 235211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average ReadReq mshr miss latency 235311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average ReadReq mshr miss latency 235411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195 # average ReadReq mshr miss latency 235511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average HardPFReq mshr miss latency 235611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876 # average HardPFReq mshr miss latency 235711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968 # average UpgradeReq mshr miss latency 235811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968 # average UpgradeReq mshr miss latency 235911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361 # average SCUpgradeReq mshr miss latency 236011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361 # average SCUpgradeReq mshr miss latency 236111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667 # average SCUpgradeFailReq mshr miss latency 236211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667 # average SCUpgradeFailReq mshr miss latency 236311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406 # average ReadExReq mshr miss latency 236411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406 # average ReadExReq mshr miss latency 236511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average ReadCleanReq mshr miss latency 236611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581 # average ReadCleanReq mshr miss latency 236711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661 # average ReadSharedReq mshr miss latency 236811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661 # average ReadSharedReq mshr miss latency 236911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377 # average InvalidateReq mshr miss latency 237011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377 # average InvalidateReq mshr miss latency 237111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency 237211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency 237311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency 237411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency 237511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781 # average overall mshr miss latency 237611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency 237711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency 237811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency 237911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency 238011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average overall mshr miss latency 238111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565 # average overall mshr miss latency 238211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average ReadReq mshr uncacheable latency 238311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548 # average ReadReq mshr uncacheable latency 238411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240 # average ReadReq mshr uncacheable latency 238511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average overall mshr uncacheable latency 238611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220 # average overall mshr uncacheable latency 238711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281 # average overall mshr uncacheable latency 238811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 29139456 # Total number of requests made to the snoop filter. 238911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 14890637 # Number of requests hitting in the snoop filter with a single holder of the requested data. 239011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1736 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 239111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 592017 # Total number of snoops made to the snoop filter. 239211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 591980 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 239311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 37 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 239411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 239511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 780515 # Transaction distribution 239611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13649954 # Transaction distribution 239711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 7187 # Transaction distribution 239811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 7187 # Transaction distribution 239911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4195318 # Transaction distribution 240011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 11056894 # Transaction distribution 240111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1429217 # Transaction distribution 240211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 912059 # Transaction distribution 240311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 240411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 423433 # Transaction distribution 240511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346671 # Transaction distribution 240611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 478761 # Transaction distribution 240711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 240811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 240911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1089502 # Transaction distribution 241011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1063784 # Transaction distribution 241111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9106528 # Transaction distribution 241211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4703864 # Transaction distribution 241311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 480825 # Transaction distribution 241411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 417736 # Transaction distribution 241511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27319260 # Packet count per connected master and slave (bytes) 241611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16358508 # Packet count per connected master and slave (bytes) 241711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 344119 # Packet count per connected master and slave (bytes) 241811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1118457 # Packet count per connected master and slave (bytes) 241911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 45140344 # Packet count per connected master and slave (bytes) 242011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1165608768 # Cumulative packet size per connected master and slave (bytes) 242111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 632082996 # Cumulative packet size per connected master and slave (bytes) 242211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1297016 # Cumulative packet size per connected master and slave (bytes) 242311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4215976 # Cumulative packet size per connected master and slave (bytes) 242411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1803204756 # Cumulative packet size per connected master and slave (bytes) 242511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5174570 # Total snoops (count) 242611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 77236160 # Total snoop traffic (bytes) 242711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 20377107 # Request fanout histogram 242811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.044844 # Request fanout histogram 242911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.206971 # Request fanout histogram 243010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 243111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 19463345 95.52% 95.52% # Request fanout histogram 243211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 913725 4.48% 100.00% # Request fanout histogram 243311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 37 0.00% 100.00% # Request fanout histogram 243410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 243511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 243610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 243711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 20377107 # Request fanout histogram 243811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 28962136490 # Layer occupancy (ticks) 243911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 244011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 181919759 # Layer occupancy (ticks) 244110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 244211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13662646557 # Layer occupancy (ticks) 244310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 244411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7521057995 # Layer occupancy (ticks) 244510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 244611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 182080323 # Layer occupancy (ticks) 244710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 244811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 591562794 # Layer occupancy (ticks) 244910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 245011754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 245111754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40336 # Transaction distribution 245211754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40336 # Transaction distribution 245311754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136646 # Transaction distribution 245411754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136645 # Transaction distribution 245511754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47799 # Packet count per connected master and slave (bytes) 245610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 245711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 245810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 245910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 246010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 246110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 246210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 246310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 246410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 246510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 246611680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 246710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 246811754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122681 # Packet count per connected master and slave (bytes) 246911754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) 247011754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) 247110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 247210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 247311754Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353963 # Packet count per connected master and slave (bytes) 247411754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) 247510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 247611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 247710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 247810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 247910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 248010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 248110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 248210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 248310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 248410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 248511680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 248610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 248711754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) 248811754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) 248911754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) 249010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 249110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 249211754Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496722 # Cumulative packet size per connected master and slave (bytes) 249311754Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 42736003 # Layer occupancy (ticks) 249410585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 249511754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 249610585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 249711754Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 316501 # Layer occupancy (ticks) 249810585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 249911754Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 250010585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 250111754Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 250211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 250311754Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 250410585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 250511606Sandreas.sandberg@arm.comsystem.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 250610585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 250711754Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 250810585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 250911754Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 251010585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 251111754Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) 251210585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 251311754Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 251410585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 251511754Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25813003 # Layer occupancy (ticks) 251610585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 251711754Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 34441500 # Layer occupancy (ticks) 251810585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 251911754Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 569849738 # Layer occupancy (ticks) 252010585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 252111754Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92766000 # Layer occupancy (ticks) 252210585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 252311754Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) 252410585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 252510892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 252610585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 252711754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 252811754Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115581 # number of replacements 252911754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.283387 # Cycle average of tags in use 253011336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 253111754Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. 253211336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 253311754Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9167357489000 # Cycle when the warmup percentage was hit. 253411754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.841167 # Average occupied blocks per requestor 253511754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.442220 # Average occupied blocks per requestor 253611754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240073 # Average percentage of cache occupancy 253711754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465139 # Average percentage of cache occupancy 253811754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705212 # Average percentage of cache occupancy 253910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 254010827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 254110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 254211754Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040766 # Number of tag accesses 254311754Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040766 # Number of data accesses 254411754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 254510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 254611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses 254711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8910 # number of ReadReq misses 254810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 254910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 255011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 255111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 255210585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 255311754Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115601 # number of demand (read+write) misses 255411754Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115641 # number of demand (read+write) misses 255510585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 255611754Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115601 # number of overall misses 255711754Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115641 # number of overall misses 255811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5212500 # number of ReadReq miss cycles 255911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1870801980 # number of ReadReq miss cycles 256011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1876014480 # number of ReadReq miss cycles 256110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 256210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 256311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13212782258 # number of WriteLineReq miss cycles 256411754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13212782258 # number of WriteLineReq miss cycles 256511754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5581500 # number of demand (read+write) miss cycles 256611754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15083584238 # number of demand (read+write) miss cycles 256711754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15089165738 # number of demand (read+write) miss cycles 256811754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5581500 # number of overall miss cycles 256911754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15083584238 # number of overall miss cycles 257011754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15089165738 # number of overall miss cycles 257110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 257211754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) 257311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) 257410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 257510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 257611606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 257711606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 257810585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 257911754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115601 # number of demand (read+write) accesses 258011754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115641 # number of demand (read+write) accesses 258110585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 258211754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115601 # number of overall (read+write) accesses 258311754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115641 # number of overall (read+write) accesses 258410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 258510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 258610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 258710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 258810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 258911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 259011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 259110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 259210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 259310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 259410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 259510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 259610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 259711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378 # average ReadReq miss latency 259811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009 # average ReadReq miss latency 259911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 210551.569024 # average ReadReq miss latency 260010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 260110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 260211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445 # average WriteLineReq miss latency 260311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 123798.649445 # average WriteLineReq miss latency 260411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency 260511754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency 260611754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 130482.836866 # average overall miss latency 260711754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency 260811754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency 260911754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 130482.836866 # average overall miss latency 261011754Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 43615 # number of cycles access was blocked 261110585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 261211754Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 261310585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 261411754Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 12.338048 # average number of cycles each access was blocked 261510585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 261611680SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106693 # number of writebacks 261711680SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106693 # number of writebacks 261810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 261911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses 262011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses 262110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 262210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 262311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 262411606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 262510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 262611754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115601 # number of demand (read+write) MSHR misses 262711754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115641 # number of demand (read+write) MSHR misses 262810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 262911754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115601 # number of overall MSHR misses 263011754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115641 # number of overall MSHR misses 263111754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3362500 # number of ReadReq MSHR miss cycles 263211754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1427151980 # number of ReadReq MSHR miss cycles 263311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1430514480 # number of ReadReq MSHR miss cycles 263410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 263510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 263611754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7870696448 # number of WriteLineReq MSHR miss cycles 263711754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7870696448 # number of WriteLineReq MSHR miss cycles 263811754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3581500 # number of demand (read+write) MSHR miss cycles 263911754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9297848428 # number of demand (read+write) MSHR miss cycles 264011754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9301429928 # number of demand (read+write) MSHR miss cycles 264111754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3581500 # number of overall MSHR miss cycles 264211754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9297848428 # number of overall MSHR miss cycles 264311754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9301429928 # number of overall MSHR miss cycles 264410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 264510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 264610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 264710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 264810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 264911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 265011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 265110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 265210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 265310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 265410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 265510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 265610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 265711754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378 # average ReadReq mshr miss latency 265811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160842.103009 # average ReadReq mshr miss latency 265911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 160551.569024 # average ReadReq mshr miss latency 266010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 266110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 266211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73745.375609 # average WriteLineReq mshr miss latency 266311754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 73745.375609 # average WriteLineReq mshr miss latency 266411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency 266511754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency 266611754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency 266711754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency 266811754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency 266911754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency 267011754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 267111754Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1414426 # number of replacements 267211754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65137.583571 # Cycle average of tags in use 267311754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6994560 # Total number of references to valid blocks. 267411754Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1476169 # Sample count of references to valid blocks. 267511754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.738319 # Average number of references to valid blocks. 267611680SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. 267711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 11569.884492 # Average occupied blocks per requestor 267811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 195.527132 # Average occupied blocks per requestor 267911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 189.575172 # Average occupied blocks per requestor 268011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5571.537349 # Average occupied blocks per requestor 268111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 16752.169298 # Average occupied blocks per requestor 268211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274 # Average occupied blocks per requestor 268311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 243.722413 # Average occupied blocks per requestor 268411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 247.067471 # Average occupied blocks per requestor 268511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3668.697792 # Average occupied blocks per requestor 268611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 7415.172357 # Average occupied blocks per requestor 268711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9157.755820 # Average occupied blocks per requestor 268811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.176542 # Average percentage of cache occupancy 268911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002984 # Average percentage of cache occupancy 269011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002893 # Average percentage of cache occupancy 269111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.085015 # Average percentage of cache occupancy 269211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.255618 # Average percentage of cache occupancy 269311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.154518 # Average percentage of cache occupancy 269411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.003719 # Average percentage of cache occupancy 269511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.003770 # Average percentage of cache occupancy 269611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.055980 # Average percentage of cache occupancy 269711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.113147 # Average percentage of cache occupancy 269811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.139736 # Average percentage of cache occupancy 269911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.993921 # Average percentage of cache occupancy 270011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10627 # Occupied blocks per task id 270111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 250 # Occupied blocks per task id 270211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50866 # Occupied blocks per task id 270311754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 270411754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 125 # Occupied blocks per task id 270511754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 764 # Occupied blocks per task id 270611754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9737 # Occupied blocks per task id 270711754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id 270811754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 270911754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 271011754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 271111754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id 271211754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4265 # Occupied blocks per task id 271311754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 44783 # Occupied blocks per task id 271411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.162155 # Percentage of cache occupancy per task id 271511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003815 # Percentage of cache occupancy per task id 271611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.776154 # Percentage of cache occupancy per task id 271711754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 76792424 # Number of tag accesses 271811754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 76792424 # Number of data accesses 271911754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 272011754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2702608 # number of WritebackDirty hits 272111754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2702608 # number of WritebackDirty hits 272211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 192434 # number of UpgradeReq hits 272311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 150964 # number of UpgradeReq hits 272411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 343398 # number of UpgradeReq hits 272511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 50257 # number of SCUpgradeReq hits 272611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 52778 # number of SCUpgradeReq hits 272711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 103035 # number of SCUpgradeReq hits 272811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 55782 # number of ReadExReq hits 272911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 52105 # number of ReadExReq hits 273011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 107887 # number of ReadExReq hits 273111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13231 # number of ReadSharedReq hits 273211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5451 # number of ReadSharedReq hits 273311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 616225 # number of ReadSharedReq hits 273411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 581799 # number of ReadSharedReq hits 273511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 304510 # number of ReadSharedReq hits 273611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10640 # number of ReadSharedReq hits 273711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4481 # number of ReadSharedReq hits 273811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 647147 # number of ReadSharedReq hits 273911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 570987 # number of ReadSharedReq hits 274011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 311044 # number of ReadSharedReq hits 274111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 3065515 # number of ReadSharedReq hits 274211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 124497 # number of InvalidateReq hits 274311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 122676 # number of InvalidateReq hits 274411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 247173 # number of InvalidateReq hits 274511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 13231 # number of demand (read+write) hits 274611754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5451 # number of demand (read+write) hits 274711754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 616225 # number of demand (read+write) hits 274811754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 637581 # number of demand (read+write) hits 274911754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 304510 # number of demand (read+write) hits 275011754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 10640 # number of demand (read+write) hits 275111754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4481 # number of demand (read+write) hits 275211754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 647147 # number of demand (read+write) hits 275311754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 623092 # number of demand (read+write) hits 275411754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 311044 # number of demand (read+write) hits 275511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3173402 # number of demand (read+write) hits 275611754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 13231 # number of overall hits 275711754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5451 # number of overall hits 275811754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 616225 # number of overall hits 275911754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 637581 # number of overall hits 276011754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 304510 # number of overall hits 276111754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 10640 # number of overall hits 276211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4481 # number of overall hits 276311754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 647147 # number of overall hits 276411754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 623092 # number of overall hits 276511754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 311044 # number of overall hits 276611754Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3173402 # number of overall hits 276711754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 19140 # number of UpgradeReq misses 276811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 25859 # number of UpgradeReq misses 276911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 44999 # number of UpgradeReq misses 277011754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 523 # number of SCUpgradeReq misses 277111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 682 # number of SCUpgradeReq misses 277211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses 277311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 81279 # number of ReadExReq misses 277411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 45582 # number of ReadExReq misses 277511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 126861 # number of ReadExReq misses 277611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq misses 277711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1999 # number of ReadSharedReq misses 277811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 72224 # number of ReadSharedReq misses 277911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 145719 # number of ReadSharedReq misses 278011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq misses 278111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq misses 278211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1517 # number of ReadSharedReq misses 278311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 52978 # number of ReadSharedReq misses 278411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 99810 # number of ReadSharedReq misses 278511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq misses 278611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 787476 # number of ReadSharedReq misses 278711754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 432248 # number of InvalidateReq misses 278811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 85316 # number of InvalidateReq misses 278911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 517564 # number of InvalidateReq misses 279011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2187 # number of demand (read+write) misses 279111754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1999 # number of demand (read+write) misses 279211754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 72224 # number of demand (read+write) misses 279311754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 226998 # number of demand (read+write) misses 279411754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) misses 279511754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1644 # number of demand (read+write) misses 279611754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1517 # number of demand (read+write) misses 279711754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 52978 # number of demand (read+write) misses 279811754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 145392 # number of demand (read+write) misses 279911754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) misses 280011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 914337 # number of demand (read+write) misses 280111754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2187 # number of overall misses 280211754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1999 # number of overall misses 280311754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 72224 # number of overall misses 280411754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 226998 # number of overall misses 280511754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 234962 # number of overall misses 280611754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1644 # number of overall misses 280711754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1517 # number of overall misses 280811754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 52978 # number of overall misses 280911754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 145392 # number of overall misses 281011754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 174436 # number of overall misses 281111754Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 914337 # number of overall misses 281211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 159938500 # number of UpgradeReq miss cycles 281311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 143600000 # number of UpgradeReq miss cycles 281411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 303538500 # number of UpgradeReq miss cycles 281511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 6591000 # number of SCUpgradeReq miss cycles 281611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 8923000 # number of SCUpgradeReq miss cycles 281711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 15514000 # number of SCUpgradeReq miss cycles 281811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 8642428000 # number of ReadExReq miss cycles 281911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4940577000 # number of ReadExReq miss cycles 282011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 13583005000 # number of ReadExReq miss cycles 282111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 231505500 # number of ReadSharedReq miss cycles 282211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 211185500 # number of ReadSharedReq miss cycles 282311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 7798644500 # number of ReadSharedReq miss cycles 282411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15829133000 # number of ReadSharedReq miss cycles 282511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of ReadSharedReq miss cycles 282611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 165185000 # number of ReadSharedReq miss cycles 282711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 157137500 # number of ReadSharedReq miss cycles 282811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6014742000 # number of ReadSharedReq miss cycles 282911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 11671652500 # number of ReadSharedReq miss cycles 283011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of ReadSharedReq miss cycles 283111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 99292357724 # number of ReadSharedReq miss cycles 283211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 231505500 # number of demand (read+write) miss cycles 283311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 211185500 # number of demand (read+write) miss cycles 283411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 7798644500 # number of demand (read+write) miss cycles 283511754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 24471561000 # number of demand (read+write) miss cycles 283611754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of demand (read+write) miss cycles 283711754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 165185000 # number of demand (read+write) miss cycles 283811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 157137500 # number of demand (read+write) miss cycles 283911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6014742000 # number of demand (read+write) miss cycles 284011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 16612229500 # number of demand (read+write) miss cycles 284111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of demand (read+write) miss cycles 284211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 112875362724 # number of demand (read+write) miss cycles 284311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 231505500 # number of overall miss cycles 284411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 211185500 # number of overall miss cycles 284511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 7798644500 # number of overall miss cycles 284611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 24471561000 # number of overall miss cycles 284711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of overall miss cycles 284811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 165185000 # number of overall miss cycles 284911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 157137500 # number of overall miss cycles 285011754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6014742000 # number of overall miss cycles 285111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 16612229500 # number of overall miss cycles 285211754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of overall miss cycles 285311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 112875362724 # number of overall miss cycles 285411754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2702608 # number of WritebackDirty accesses(hits+misses) 285511754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2702608 # number of WritebackDirty accesses(hits+misses) 285611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 211574 # number of UpgradeReq accesses(hits+misses) 285711754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 176823 # number of UpgradeReq accesses(hits+misses) 285811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 388397 # number of UpgradeReq accesses(hits+misses) 285911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 50780 # number of SCUpgradeReq accesses(hits+misses) 286011754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 53460 # number of SCUpgradeReq accesses(hits+misses) 286111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 104240 # number of SCUpgradeReq accesses(hits+misses) 286211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 137061 # number of ReadExReq accesses(hits+misses) 286311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 97687 # number of ReadExReq accesses(hits+misses) 286411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 234748 # number of ReadExReq accesses(hits+misses) 286511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15418 # number of ReadSharedReq accesses(hits+misses) 286611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7450 # number of ReadSharedReq accesses(hits+misses) 286711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 688449 # number of ReadSharedReq accesses(hits+misses) 286811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 727518 # number of ReadSharedReq accesses(hits+misses) 286911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 539472 # number of ReadSharedReq accesses(hits+misses) 287011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12284 # number of ReadSharedReq accesses(hits+misses) 287111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5998 # number of ReadSharedReq accesses(hits+misses) 287211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 700125 # number of ReadSharedReq accesses(hits+misses) 287311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 670797 # number of ReadSharedReq accesses(hits+misses) 287411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 485480 # number of ReadSharedReq accesses(hits+misses) 287511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3852991 # number of ReadSharedReq accesses(hits+misses) 287611754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 556745 # number of InvalidateReq accesses(hits+misses) 287711754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 207992 # number of InvalidateReq accesses(hits+misses) 287811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 764737 # number of InvalidateReq accesses(hits+misses) 287911754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 15418 # number of demand (read+write) accesses 288011754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7450 # number of demand (read+write) accesses 288111754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 688449 # number of demand (read+write) accesses 288211754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 864579 # number of demand (read+write) accesses 288311754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 539472 # number of demand (read+write) accesses 288411754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 12284 # number of demand (read+write) accesses 288511754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5998 # number of demand (read+write) accesses 288611754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 700125 # number of demand (read+write) accesses 288711754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 768484 # number of demand (read+write) accesses 288811754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 485480 # number of demand (read+write) accesses 288911754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4087739 # number of demand (read+write) accesses 289011754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 15418 # number of overall (read+write) accesses 289111754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7450 # number of overall (read+write) accesses 289211754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 688449 # number of overall (read+write) accesses 289311754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 864579 # number of overall (read+write) accesses 289411754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 539472 # number of overall (read+write) accesses 289511754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 12284 # number of overall (read+write) accesses 289611754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5998 # number of overall (read+write) accesses 289711754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 700125 # number of overall (read+write) accesses 289811754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 768484 # number of overall (read+write) accesses 289911754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 485480 # number of overall (read+write) accesses 290011754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4087739 # number of overall (read+write) accesses 290111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.090465 # miss rate for UpgradeReq accesses 290211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.146242 # miss rate for UpgradeReq accesses 290311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.115858 # miss rate for UpgradeReq accesses 290411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010299 # miss rate for SCUpgradeReq accesses 290511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012757 # miss rate for SCUpgradeReq accesses 290611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.011560 # miss rate for SCUpgradeReq accesses 290711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.593013 # miss rate for ReadExReq accesses 290811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.466613 # miss rate for ReadExReq accesses 290911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.540414 # miss rate for ReadExReq accesses 291011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for ReadSharedReq accesses 291111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.268322 # miss rate for ReadSharedReq accesses 291211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104908 # miss rate for ReadSharedReq accesses 291311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200296 # miss rate for ReadSharedReq accesses 291411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for ReadSharedReq accesses 291511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for ReadSharedReq accesses 291611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.252918 # miss rate for ReadSharedReq accesses 291711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses 291811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.148793 # miss rate for ReadSharedReq accesses 291911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for ReadSharedReq accesses 292011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.204380 # miss rate for ReadSharedReq accesses 292111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.776384 # miss rate for InvalidateReq accesses 292211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.410189 # miss rate for InvalidateReq accesses 292311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.676787 # miss rate for InvalidateReq accesses 292411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for demand accesses 292511754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.268322 # miss rate for demand accesses 292611754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.104908 # miss rate for demand accesses 292711754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.262553 # miss rate for demand accesses 292811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for demand accesses 292911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for demand accesses 293011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.252918 # miss rate for demand accesses 293111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses 293211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.189193 # miss rate for demand accesses 293311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for demand accesses 293411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.223678 # miss rate for demand accesses 293511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for overall accesses 293611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.268322 # miss rate for overall accesses 293711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.104908 # miss rate for overall accesses 293811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.262553 # miss rate for overall accesses 293911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for overall accesses 294011754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for overall accesses 294111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.252918 # miss rate for overall accesses 294211754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses 294311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.189193 # miss rate for overall accesses 294411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for overall accesses 294511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.223678 # miss rate for overall accesses 294611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 8356.243469 # average UpgradeReq miss latency 294711754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5553.192312 # average UpgradeReq miss latency 294811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6745.449899 # average UpgradeReq miss latency 294911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12602.294455 # average SCUpgradeReq miss latency 295011754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13083.577713 # average SCUpgradeReq miss latency 295111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 12874.688797 # average SCUpgradeReq miss latency 295211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 106330.392844 # average ReadExReq miss latency 295311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 108388.771884 # average ReadExReq miss latency 295411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 107069.982106 # average ReadExReq miss latency 295511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average ReadSharedReq miss latency 295611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105645.572786 # average ReadSharedReq miss latency 295711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107978.573604 # average ReadSharedReq miss latency 295811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 108627.790473 # average ReadSharedReq miss latency 295911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average ReadSharedReq miss latency 296011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average ReadSharedReq miss latency 296111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103584.377060 # average ReadSharedReq miss latency 296211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113532.824946 # average ReadSharedReq miss latency 296311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116938.708546 # average ReadSharedReq miss latency 296411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average ReadSharedReq miss latency 296511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 126089.376342 # average ReadSharedReq miss latency 296611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency 296711754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency 296811754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency 296911754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency 297011754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency 297111754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency 297211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency 297311754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency 297411754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency 297511754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency 297611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 123450.503178 # average overall miss latency 297711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency 297811754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency 297911754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency 298011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency 298111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency 298211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency 298311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency 298411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency 298511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency 298611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency 298711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 123450.503178 # average overall miss latency 298811754Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 159 # number of cycles access was blocked 298910515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 299011754Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 6 # number of cycles access was blocked 299110515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 299211754Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked 299310515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 299411754Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1064634 # number of writebacks 299511754Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1064634 # number of writebacks 299611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 107 # number of ReadSharedReq MSHR hits 299711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 22 # number of ReadSharedReq MSHR hits 299811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 137 # number of ReadSharedReq MSHR hits 299911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits 300011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 289 # number of ReadSharedReq MSHR hits 300111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 107 # number of demand (read+write) MSHR hits 300211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits 300311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 137 # number of demand (read+write) MSHR hits 300411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits 300511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits 300611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 107 # number of overall MSHR hits 300711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits 300811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 137 # number of overall MSHR hits 300911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits 301011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 289 # number of overall MSHR hits 301111754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 58693 # number of CleanEvict MSHR misses 301211754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 58693 # number of CleanEvict MSHR misses 301311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 19140 # number of UpgradeReq MSHR misses 301411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 25859 # number of UpgradeReq MSHR misses 301511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 44999 # number of UpgradeReq MSHR misses 301611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 523 # number of SCUpgradeReq MSHR misses 301711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 682 # number of SCUpgradeReq MSHR misses 301811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1205 # number of SCUpgradeReq MSHR misses 301911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 81279 # number of ReadExReq MSHR misses 302011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 45582 # number of ReadExReq MSHR misses 302111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 126861 # number of ReadExReq MSHR misses 302211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq MSHR misses 302311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1999 # number of ReadSharedReq MSHR misses 302411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72117 # number of ReadSharedReq MSHR misses 302511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 145697 # number of ReadSharedReq MSHR misses 302611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq MSHR misses 302711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq MSHR misses 302811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1517 # number of ReadSharedReq MSHR misses 302911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 52841 # number of ReadSharedReq MSHR misses 303011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 99787 # number of ReadSharedReq MSHR misses 303111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq MSHR misses 303211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 787187 # number of ReadSharedReq MSHR misses 303311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 432248 # number of InvalidateReq MSHR misses 303411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 85316 # number of InvalidateReq MSHR misses 303511754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 517564 # number of InvalidateReq MSHR misses 303611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 2187 # number of demand (read+write) MSHR misses 303711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1999 # number of demand (read+write) MSHR misses 303811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 72117 # number of demand (read+write) MSHR misses 303911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 226976 # number of demand (read+write) MSHR misses 304011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) MSHR misses 304111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1644 # number of demand (read+write) MSHR misses 304211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1517 # number of demand (read+write) MSHR misses 304311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 52841 # number of demand (read+write) MSHR misses 304411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 145369 # number of demand (read+write) MSHR misses 304511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) MSHR misses 304611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 914048 # number of demand (read+write) MSHR misses 304711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 2187 # number of overall MSHR misses 304811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1999 # number of overall MSHR misses 304911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 72117 # number of overall MSHR misses 305011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 226976 # number of overall MSHR misses 305111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of overall MSHR misses 305211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1644 # number of overall MSHR misses 305311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1517 # number of overall MSHR misses 305411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 52841 # number of overall MSHR misses 305511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 145369 # number of overall MSHR misses 305611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of overall MSHR misses 305711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 914048 # number of overall MSHR misses 305811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 305911754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 306011570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 306111754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 6966 # number of ReadReq MSHR uncacheable 306211754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 90895 # number of ReadReq MSHR uncacheable 306311754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 306411754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 306511754Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38388 # number of WriteReq MSHR uncacheable 306611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 306711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 306811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 306911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 14153 # number of overall MSHR uncacheable misses 307011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 129283 # number of overall MSHR uncacheable misses 307111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 389704500 # number of UpgradeReq MSHR miss cycles 307211754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 525466000 # number of UpgradeReq MSHR miss cycles 307311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 915170500 # number of UpgradeReq MSHR miss cycles 307411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12566500 # number of SCUpgradeReq MSHR miss cycles 307511754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16471000 # number of SCUpgradeReq MSHR miss cycles 307611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 29037500 # number of SCUpgradeReq MSHR miss cycles 307711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7829611555 # number of ReadExReq MSHR miss cycles 307811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4484731054 # number of ReadExReq MSHR miss cycles 307911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 12314342609 # number of ReadExReq MSHR miss cycles 308011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of ReadSharedReq MSHR miss cycles 308111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 191194502 # number of ReadSharedReq MSHR miss cycles 308211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7068927036 # number of ReadSharedReq MSHR miss cycles 308311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14369749705 # number of ReadSharedReq MSHR miss cycles 308411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of ReadSharedReq MSHR miss cycles 308511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of ReadSharedReq MSHR miss cycles 308611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141966502 # number of ReadSharedReq MSHR miss cycles 308711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5474322057 # number of ReadSharedReq MSHR miss cycles 308811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10671015209 # number of ReadSharedReq MSHR miss cycles 308911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of ReadSharedReq MSHR miss cycles 309011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 91394456852 # number of ReadSharedReq MSHR miss cycles 309111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8929441001 # number of InvalidateReq MSHR miss cycles 309211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1642247000 # number of InvalidateReq MSHR miss cycles 309311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 10571688001 # number of InvalidateReq MSHR miss cycles 309411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of demand (read+write) MSHR miss cycles 309511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 191194502 # number of demand (read+write) MSHR miss cycles 309611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 7068927036 # number of demand (read+write) MSHR miss cycles 309711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 22199361260 # number of demand (read+write) MSHR miss cycles 309811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of demand (read+write) MSHR miss cycles 309911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of demand (read+write) MSHR miss cycles 310011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141966502 # number of demand (read+write) MSHR miss cycles 310111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 5474322057 # number of demand (read+write) MSHR miss cycles 310211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 15155746263 # number of demand (read+write) MSHR miss cycles 310311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of demand (read+write) MSHR miss cycles 310411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 103708799461 # number of demand (read+write) MSHR miss cycles 310511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of overall MSHR miss cycles 310611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 191194502 # number of overall MSHR miss cycles 310711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 7068927036 # number of overall MSHR miss cycles 310811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 22199361260 # number of overall MSHR miss cycles 310911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of overall MSHR miss cycles 311011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of overall MSHR miss cycles 311111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141966502 # number of overall MSHR miss cycles 311211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 5474322057 # number of overall MSHR miss cycles 311311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 15155746263 # number of overall MSHR miss cycles 311411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of overall MSHR miss cycles 311511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 103708799461 # number of overall MSHR miss cycles 311611680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles 311711754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5267143505 # number of ReadReq MSHR uncacheable cycles 311811754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6847500 # number of ReadReq MSHR uncacheable cycles 311911754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 701418504 # number of ReadReq MSHR uncacheable cycles 312011754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 9620779009 # number of ReadReq MSHR uncacheable cycles 312111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles 312211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 5267143505 # number of overall MSHR uncacheable cycles 312311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6847500 # number of overall MSHR uncacheable cycles 312411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 701418504 # number of overall MSHR uncacheable cycles 312511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 9620779009 # number of overall MSHR uncacheable cycles 312610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 312710892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 312811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090465 # mshr miss rate for UpgradeReq accesses 312911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.146242 # mshr miss rate for UpgradeReq accesses 313011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.115858 # mshr miss rate for UpgradeReq accesses 313111754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010299 # mshr miss rate for SCUpgradeReq accesses 313211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012757 # mshr miss rate for SCUpgradeReq accesses 313311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011560 # mshr miss rate for SCUpgradeReq accesses 313411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593013 # mshr miss rate for ReadExReq accesses 313511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466613 # mshr miss rate for ReadExReq accesses 313611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.540414 # mshr miss rate for ReadExReq accesses 313711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for ReadSharedReq accesses 313811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for ReadSharedReq accesses 313911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for ReadSharedReq accesses 314011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200266 # mshr miss rate for ReadSharedReq accesses 314111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for ReadSharedReq accesses 314211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for ReadSharedReq accesses 314311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for ReadSharedReq accesses 314411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for ReadSharedReq accesses 314511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.148759 # mshr miss rate for ReadSharedReq accesses 314611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for ReadSharedReq accesses 314711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.204305 # mshr miss rate for ReadSharedReq accesses 314811754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.776384 # mshr miss rate for InvalidateReq accesses 314911754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.410189 # mshr miss rate for InvalidateReq accesses 315011754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.676787 # mshr miss rate for InvalidateReq accesses 315111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for demand accesses 315211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for demand accesses 315311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for demand accesses 315411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for demand accesses 315511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for demand accesses 315611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for demand accesses 315711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for demand accesses 315811754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for demand accesses 315911754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for demand accesses 316011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for demand accesses 316111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.223607 # mshr miss rate for demand accesses 316211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for overall accesses 316311754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for overall accesses 316411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for overall accesses 316511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for overall accesses 316611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for overall accesses 316711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for overall accesses 316811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for overall accesses 316911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for overall accesses 317011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for overall accesses 317111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for overall accesses 317211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.223607 # mshr miss rate for overall accesses 317311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20360.736677 # average UpgradeReq mshr miss latency 317411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.430024 # average UpgradeReq mshr miss latency 317511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20337.574168 # average UpgradeReq mshr miss latency 317611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24027.724665 # average SCUpgradeReq mshr miss latency 317711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24151.026393 # average SCUpgradeReq mshr miss latency 317811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24097.510373 # average SCUpgradeReq mshr miss latency 317911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 96330.067484 # average ReadExReq mshr miss latency 318011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98388.202668 # average ReadExReq mshr miss latency 318111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 97069.569127 # average ReadExReq mshr miss latency 318211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average ReadSharedReq mshr miss latency 318311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average ReadSharedReq mshr miss latency 318411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average ReadSharedReq mshr miss latency 318511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 98627.629292 # average ReadSharedReq mshr miss latency 318611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average ReadSharedReq mshr miss latency 318711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average ReadSharedReq mshr miss latency 318811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average ReadSharedReq mshr miss latency 318911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average ReadSharedReq mshr miss latency 319011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106937.929881 # average ReadSharedReq mshr miss latency 319111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average ReadSharedReq mshr miss latency 319211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116102.599321 # average ReadSharedReq mshr miss latency 319311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20658.143013 # average InvalidateReq mshr miss latency 319411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19248.991983 # average InvalidateReq mshr miss latency 319511754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20425.856514 # average InvalidateReq mshr miss latency 319611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency 319711754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency 319811754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency 319911754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency 320011754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency 320111754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency 320211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency 320311754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency 320411754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency 320511754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency 320611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency 320711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency 320811754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency 320911754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency 321011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency 321111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency 321211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency 321311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency 321411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency 321511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency 321611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency 321711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency 321811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency 321911754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410 # average ReadReq mshr uncacheable latency 322011754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average ReadReq mshr uncacheable latency 322111754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485 # average ReadReq mshr uncacheable latency 322211754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070 # average ReadReq mshr uncacheable latency 322311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency 322411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268 # average overall mshr uncacheable latency 322511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average overall mshr uncacheable latency 322611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939 # average overall mshr uncacheable latency 322711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597 # average overall mshr uncacheable latency 322811754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 3622014 # Total number of requests made to the snoop filter. 322911754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2135906 # Number of requests hitting in the snoop filter with a single holder of the requested data. 323011754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 2993 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 323111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 323211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 323311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 323411754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 323511754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 90895 # Transaction distribution 323611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 886992 # Transaction distribution 323711754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38388 # Transaction distribution 323811754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38387 # Transaction distribution 323911754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1171327 # Transaction distribution 324011754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 257625 # Transaction distribution 324111754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 339183 # Transaction distribution 324211754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 279038 # Transaction distribution 324311680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 24 # Transaction distribution 324411754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 324511754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 141595 # Transaction distribution 324611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 126059 # Transaction distribution 324711754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 796097 # Transaction distribution 324811754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 636810 # Transaction distribution 324911754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 29788 # Transaction distribution 325011754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122681 # Packet count per connected master and slave (bytes) 325111570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 325211754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25906 # Packet count per connected master and slave (bytes) 325311754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4412900 # Packet count per connected master and slave (bytes) 325411754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4561541 # Packet count per connected master and slave (bytes) 325511754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238275 # Packet count per connected master and slave (bytes) 325611754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238275 # Packet count per connected master and slave (bytes) 325711754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4799816 # Packet count per connected master and slave (bytes) 325811754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) 325911570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 326011754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51812 # Cumulative packet size per connected master and slave (bytes) 326111754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129909760 # Cumulative packet size per connected master and slave (bytes) 326211754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 130118772 # Cumulative packet size per connected master and slave (bytes) 326311754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279744 # Cumulative packet size per connected master and slave (bytes) 326411754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7279744 # Cumulative packet size per connected master and slave (bytes) 326511754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 137398516 # Cumulative packet size per connected master and slave (bytes) 326611754Sandreas.hansson@arm.comsystem.membus.snoops 631660 # Total snoops (count) 326711754Sandreas.hansson@arm.comsystem.membus.snoopTraffic 165184 # Total snoop traffic (bytes) 326811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2322011 # Request fanout histogram 326911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.014128 # Request fanout histogram 327011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.118018 # Request fanout histogram 327110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 327211754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2289206 98.59% 98.59% # Request fanout histogram 327311754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 32805 1.41% 100.00% # Request fanout histogram 327410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 327510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 327611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 327710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 327811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2322011 # Request fanout histogram 327911754Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 103411493 # Layer occupancy (ticks) 328010585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 328111570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 328210585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 328311754Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21687499 # Layer occupancy (ticks) 328410585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 328511754Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 8057234059 # Layer occupancy (ticks) 328610585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 328711754Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 5202386097 # Layer occupancy (ticks) 328810585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 328911754Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 79808698 # Layer occupancy (ticks) 329010585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 329111754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329211754Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329311754Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329411754Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329511754Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329611754Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329711754Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 329811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 329911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 330011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 330111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 330211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 330311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 330411754Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 330511754Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 330610515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 330710515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 330810515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 330910515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 331010515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 331110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 331210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 331310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 331410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 331511201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 331610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 331710515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 331810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 331911201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 332010515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 332110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 332210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 332310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 332410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 332510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 332610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 332710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 332810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 332910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 333010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 333110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 333210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 333310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 333410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 333510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 333610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 333710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 333810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 333910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 334010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 334110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 334210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 334310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 334410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 334510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 334610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 334710515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 334811754Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 334911754Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335011754Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335111754Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335211754Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335311754Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335411754Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 335511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 335611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 335711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 335811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 335911754Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336011754Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336111754Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336211754Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336311754Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336411754Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336511754Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336611754Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336711754Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336811754Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 336911754Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 337011754Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 337111754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12161965 # Total number of requests made to the snoop filter. 337211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6407928 # Number of requests hitting in the snoop filter with a single holder of the requested data. 337311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2357892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 337411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 209457 # Total number of snoops made to the snoop filter. 337511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 187271 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 337611754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 22186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 337711754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 337811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 90897 # Transaction distribution 337911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4728170 # Transaction distribution 338011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38388 # Transaction distribution 338111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38387 # Transaction distribution 338211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3767242 # Transaction distribution 338311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 338411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2958537 # Transaction distribution 338511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 681779 # Transaction distribution 338611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 382073 # Transaction distribution 338711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1063852 # Transaction distribution 338811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution 338911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 339011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 289918 # Transaction distribution 339111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 289918 # Transaction distribution 339211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4637675 # Transaction distribution 339311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 890912 # Transaction distribution 339411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 871981 # Transaction distribution 339511754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9721848 # Packet count per connected master and slave (bytes) 339611754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8056306 # Packet count per connected master and slave (bytes) 339711754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 17778154 # Packet count per connected master and slave (bytes) 339811754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 242672912 # Cumulative packet size per connected master and slave (bytes) 339911754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 195596708 # Cumulative packet size per connected master and slave (bytes) 340011754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 438269620 # Cumulative packet size per connected master and slave (bytes) 340111754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 2964469 # Total snoops (count) 340211754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 121867728 # Total snoop traffic (bytes) 340311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 8426211 # Request fanout histogram 340411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.390204 # Request fanout histogram 340511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.493164 # Request fanout histogram 340610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 340711754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5160452 61.24% 61.24% # Request fanout histogram 340811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3243573 38.49% 99.74% # Request fanout histogram 340911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 22186 0.26% 100.00% # Request fanout histogram 341010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 341111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 341210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 341311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 8426211 # Request fanout histogram 341411754Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 9265268057 # Layer occupancy (ticks) 341510515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 341611754Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 8336972 # Layer occupancy (ticks) 341710515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 341811754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4478456950 # Layer occupancy (ticks) 341910515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 342011754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4027071928 # Layer occupancy (ticks) 342110515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 342210515SAli.Saidi@ARM.com 342310515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3424