stats.txt revision 11754
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.356210 # Number of seconds simulated 4sim_ticks 47356210126000 # Number of ticks simulated 5final_tick 47356210126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 269105 # Simulator instruction rate (inst/s) 8host_op_rate 316551 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14489745940 # Simulator tick rate (ticks/s) 10host_mem_usage 771556 # Number of bytes of host memory used 11host_seconds 3268.26 # Real time elapsed on the host 12sim_insts 879504495 # Number of instructions simulated 13sim_ops 1034569807 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 139968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 127936 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7960960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 14481160 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 15033920 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 105216 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 97088 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3386304 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9267600 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 11152448 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 451392 # Number of bytes read from this memory 28system.physmem.bytes_read::total 62203992 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 7960960 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3386304 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 11347264 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 74964928 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 74985512 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 2187 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1999 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 124390 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 226281 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 234905 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1644 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1517 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 52911 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 144819 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 174257 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 7053 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 971963 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1171327 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1173901 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2702 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 168108 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 305792 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 317465 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2222 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2050 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 71507 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 195700 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 235501 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9532 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1313534 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 168108 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 71507 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 239615 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1583001 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1583436 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1583001 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2702 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 168108 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 306227 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 317465 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2222 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2050 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 71507 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 195700 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 235501 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9532 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2896970 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 971963 # Number of read requests accepted 85system.physmem.writeReqs 1173901 # Number of write requests accepted 86system.physmem.readBursts 971963 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1173901 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 62180096 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 25536 # Total number of bytes read from write queue 90system.physmem.bytesWritten 74984000 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 62203992 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 74985512 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 399 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 55033 # Per bank write bursts 97system.physmem.perBankRdBursts::1 62597 # Per bank write bursts 98system.physmem.perBankRdBursts::2 50092 # Per bank write bursts 99system.physmem.perBankRdBursts::3 57292 # Per bank write bursts 100system.physmem.perBankRdBursts::4 55886 # Per bank write bursts 101system.physmem.perBankRdBursts::5 65305 # Per bank write bursts 102system.physmem.perBankRdBursts::6 62171 # Per bank write bursts 103system.physmem.perBankRdBursts::7 60911 # Per bank write bursts 104system.physmem.perBankRdBursts::8 55564 # Per bank write bursts 105system.physmem.perBankRdBursts::9 110087 # Per bank write bursts 106system.physmem.perBankRdBursts::10 50665 # Per bank write bursts 107system.physmem.perBankRdBursts::11 58731 # Per bank write bursts 108system.physmem.perBankRdBursts::12 55379 # Per bank write bursts 109system.physmem.perBankRdBursts::13 59204 # Per bank write bursts 110system.physmem.perBankRdBursts::14 58833 # Per bank write bursts 111system.physmem.perBankRdBursts::15 53814 # Per bank write bursts 112system.physmem.perBankWrBursts::0 70729 # Per bank write bursts 113system.physmem.perBankWrBursts::1 73923 # Per bank write bursts 114system.physmem.perBankWrBursts::2 67641 # Per bank write bursts 115system.physmem.perBankWrBursts::3 73309 # Per bank write bursts 116system.physmem.perBankWrBursts::4 73460 # Per bank write bursts 117system.physmem.perBankWrBursts::5 77994 # Per bank write bursts 118system.physmem.perBankWrBursts::6 75119 # Per bank write bursts 119system.physmem.perBankWrBursts::7 77047 # Per bank write bursts 120system.physmem.perBankWrBursts::8 72172 # Per bank write bursts 121system.physmem.perBankWrBursts::9 76177 # Per bank write bursts 122system.physmem.perBankWrBursts::10 69310 # Per bank write bursts 123system.physmem.perBankWrBursts::11 74055 # Per bank write bursts 124system.physmem.perBankWrBursts::12 71196 # Per bank write bursts 125system.physmem.perBankWrBursts::13 73730 # Per bank write bursts 126system.physmem.perBankWrBursts::14 72781 # Per bank write bursts 127system.physmem.perBankWrBursts::15 72982 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 338 # Number of times write queue was full causing retry 130system.physmem.totGap 47356208030500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 971933 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1171327 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 599542 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 159109 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 46981 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 36741 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28369 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25953 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 23819 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 21360 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 18806 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 4598 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1833 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 1239 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 994 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 339 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 244 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 24305 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 32346 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 48833 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 56114 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 61688 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 64343 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 66279 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 68229 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 71242 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 71432 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 74216 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 76183 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 73010 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 71262 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 72325 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 75575 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 67464 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 63552 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 4902 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 3071 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 2501 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1943 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1570 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 1445 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1223 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 888 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 894 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 765 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 736 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 628 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 732 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 601 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 589 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 546 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 578 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 547 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 623 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 600 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 597 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 584 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 815 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 810 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 531 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 839 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 762 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 764 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 423 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 769 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 927860 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 147.827612 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 99.770435 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 195.442358 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 609464 65.68% 65.68% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 190800 20.56% 86.25% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 46263 4.99% 91.23% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 21195 2.28% 93.52% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 15500 1.67% 95.19% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9774 1.05% 96.24% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 7067 0.76% 97.00% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5586 0.60% 97.61% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 22211 2.39% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 927860 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 57099 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.014939 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 164.898277 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 57097 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 57099 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 57099 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.519186 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.696547 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 14.054604 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 49168 86.11% 86.11% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 2307 4.04% 90.15% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 623 1.09% 91.24% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 607 1.06% 92.30% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 970 1.70% 94.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 377 0.66% 94.66% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 342 0.60% 95.26% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 248 0.43% 95.70% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 171 0.30% 96.00% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 147 0.26% 96.25% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 125 0.22% 96.47% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 141 0.25% 96.72% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 491 0.86% 97.58% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 181 0.32% 97.90% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 140 0.25% 98.14% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 149 0.26% 98.40% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 103 0.18% 98.58% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 79 0.14% 98.72% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 87 0.15% 98.87% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 90 0.16% 99.03% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 76 0.13% 99.16% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 61 0.11% 99.27% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 62 0.11% 99.38% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 70 0.12% 99.50% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 41 0.07% 99.57% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 40 0.07% 99.64% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 42 0.07% 99.72% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 34 0.06% 99.78% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 42 0.07% 99.85% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::132-135 20 0.04% 99.89% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::140-143 13 0.02% 99.93% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::144-147 6 0.01% 99.94% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::148-151 4 0.01% 99.95% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::152-155 2 0.00% 99.95% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::156-159 4 0.01% 99.96% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::160-163 2 0.00% 99.96% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::172-175 5 0.01% 99.97% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::188-191 6 0.01% 99.99% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::total 57099 # Writes before turning the bus around for reads 312system.physmem.totQLat 49354955217 # Total ticks spent queuing 313system.physmem.totMemAccLat 67571780217 # Total ticks spent from burst creation until serviced by the DRAM 314system.physmem.totBusLat 4857820000 # Total ticks spent in databus transfers 315system.physmem.avgQLat 50799.49 # Average queueing delay per DRAM burst 316system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 317system.physmem.avgMemAccLat 69549.49 # Average memory access latency per DRAM burst 318system.physmem.avgRdBW 1.31 # Average DRAM read bandwidth in MiByte/s 319system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 320system.physmem.avgRdBWSys 1.31 # Average system read bandwidth in MiByte/s 321system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 322system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 323system.physmem.busUtil 0.02 # Data bus utilization in percentage 324system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 325system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 326system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 327system.physmem.avgWrQLen 22.53 # Average write queue length when enqueuing 328system.physmem.readRowHits 725116 # Number of row buffer hits during reads 329system.physmem.writeRowHits 490210 # Number of row buffer hits during writes 330system.physmem.readRowHitRate 74.63 # Row buffer hit rate for reads 331system.physmem.writeRowHitRate 41.84 # Row buffer hit rate for writes 332system.physmem.avgGap 22068597.09 # Average gap between requests 333system.physmem.pageHitRate 56.71 # Row buffer hit rate, read and write combined 334system.physmem_0.actEnergy 3347988840 # Energy for activate commands per rank (pJ) 335system.physmem_0.preEnergy 1779490680 # Energy for precharge commands per rank (pJ) 336system.physmem_0.readEnergy 3350709180 # Energy for read commands per rank (pJ) 337system.physmem_0.writeEnergy 3075738840 # Energy for write commands per rank (pJ) 338system.physmem_0.refreshEnergy 40224500160.000008 # Energy for refresh commands per rank (pJ) 339system.physmem_0.actBackEnergy 43885079760 # Energy for active background per rank (pJ) 340system.physmem_0.preBackEnergy 2109996960 # Energy for precharge background per rank (pJ) 341system.physmem_0.actPowerDownEnergy 79595636190 # Energy for active power-down per rank (pJ) 342system.physmem_0.prePowerDownEnergy 56472597600 # Energy for precharge power-down per rank (pJ) 343system.physmem_0.selfRefreshEnergy 11270458828185 # Energy for self refresh per rank (pJ) 344system.physmem_0.totalEnergy 11504320668105 # Total energy per rank (pJ) 345system.physmem_0.averagePower 242.931616 # Core power per rank (mW) 346system.physmem_0.totalIdleTime 47254429054365 # Total Idle time Per DRAM Rank 347system.physmem_0.memoryStateTime::IDLE 3740889550 # Time in different power states 348system.physmem_0.memoryStateTime::REF 17088544000 # Time in different power states 349system.physmem_0.memoryStateTime::SREF 46932815651000 # Time in different power states 350system.physmem_0.memoryStateTime::PRE_PDN 147063936092 # Time in different power states 351system.physmem_0.memoryStateTime::ACT 80948731835 # Time in different power states 352system.physmem_0.memoryStateTime::ACT_PDN 174552373523 # Time in different power states 353system.physmem_1.actEnergy 3276952980 # Energy for activate commands per rank (pJ) 354system.physmem_1.preEnergy 1741738020 # Energy for precharge commands per rank (pJ) 355system.physmem_1.readEnergy 3586257780 # Energy for read commands per rank (pJ) 356system.physmem_1.writeEnergy 3040143660 # Energy for write commands per rank (pJ) 357system.physmem_1.refreshEnergy 38004420480.000008 # Energy for refresh commands per rank (pJ) 358system.physmem_1.actBackEnergy 43585213590 # Energy for active background per rank (pJ) 359system.physmem_1.preBackEnergy 1995622560 # Energy for precharge background per rank (pJ) 360system.physmem_1.actPowerDownEnergy 72860280210 # Energy for active power-down per rank (pJ) 361system.physmem_1.prePowerDownEnergy 53203975680 # Energy for precharge power-down per rank (pJ) 362system.physmem_1.selfRefreshEnergy 11275978868760 # Energy for self refresh per rank (pJ) 363system.physmem_1.totalEnergy 11497290812280 # Total energy per rank (pJ) 364system.physmem_1.averagePower 242.783170 # Core power per rank (mW) 365system.physmem_1.totalIdleTime 47255392508641 # Total Idle time Per DRAM Rank 366system.physmem_1.memoryStateTime::IDLE 3486165610 # Time in different power states 367system.physmem_1.memoryStateTime::REF 16146094000 # Time in different power states 368system.physmem_1.memoryStateTime::SREF 46957059679500 # Time in different power states 369system.physmem_1.memoryStateTime::PRE_PDN 138551420004 # Time in different power states 370system.physmem_1.memoryStateTime::ACT 81185307499 # Time in different power states 371system.physmem_1.memoryStateTime::ACT_PDN 159781459387 # Time in different power states 372system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 373system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 374system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 375system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 376system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 377system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 378system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 379system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 380system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 381system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 382system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 383system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 384system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 385system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 386system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 387system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 388system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) 389system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 390system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 391system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 392system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) 393system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 394system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 395system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 396system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) 397system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 398system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 399system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 400system.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 401system.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 402system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 403system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 404system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 405system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 406system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 407system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 408system.cpu0.branchPred.lookups 135721275 # Number of BP lookups 409system.cpu0.branchPred.condPredicted 95221356 # Number of conditional branches predicted 410system.cpu0.branchPred.condIncorrect 6297780 # Number of conditional branches incorrect 411system.cpu0.branchPred.BTBLookups 101561419 # Number of BTB lookups 412system.cpu0.branchPred.BTBHits 70514394 # Number of BTB hits 413system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 414system.cpu0.branchPred.BTBHitPct 69.430296 # BTB Hit Percentage 415system.cpu0.branchPred.usedRAS 16061922 # Number of times the RAS was used to get a target. 416system.cpu0.branchPred.RASInCorrect 1062204 # Number of incorrect RAS predictions. 417system.cpu0.branchPred.indirectLookups 3676908 # Number of indirect predictor lookups. 418system.cpu0.branchPred.indirectHits 2416966 # Number of indirect target hits. 419system.cpu0.branchPred.indirectMisses 1259942 # Number of indirect misses. 420system.cpu0.branchPredindirectMispredicted 447333 # Number of mispredicted indirect branches. 421system.cpu_clk_domain.clock 500 # Clock period in ticks 422system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 423system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 424system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 425system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 427system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 428system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 430system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 431system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 432system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 433system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 434system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 435system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 436system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 437system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 438system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 439system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 440system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 441system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 442system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 443system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 444system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 446system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 447system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 448system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 449system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 450system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 451system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 452system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 453system.cpu0.dtb.walker.walks 280305 # Table walker walks requested 454system.cpu0.dtb.walker.walksLong 280305 # Table walker walks initiated with long descriptors 455system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9673 # Level at which table walker walks with long descriptors terminate 456system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80745 # Level at which table walker walks with long descriptors terminate 457system.cpu0.dtb.walker.walkWaitTime::samples 280305 # Table walker wait (enqueue to first request) latency 458system.cpu0.dtb.walker.walkWaitTime::0 280305 100.00% 100.00% # Table walker wait (enqueue to first request) latency 459system.cpu0.dtb.walker.walkWaitTime::total 280305 # Table walker wait (enqueue to first request) latency 460system.cpu0.dtb.walker.walkCompletionTime::samples 90418 # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099 # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848 # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973 # Table walker service (enqueue to completion) latency 464system.cpu0.dtb.walker.walkCompletionTime::0-65535 89075 98.51% 98.51% # Table walker service (enqueue to completion) latency 465system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1011 1.12% 99.63% # Table walker service (enqueue to completion) latency 466system.cpu0.dtb.walker.walkCompletionTime::131072-196607 175 0.19% 99.83% # Table walker service (enqueue to completion) latency 467system.cpu0.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency 468system.cpu0.dtb.walker.walkCompletionTime::262144-327679 41 0.05% 99.94% # Table walker service (enqueue to completion) latency 469system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency 470system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.97% # Table walker service (enqueue to completion) latency 471system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 472system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 473system.cpu0.dtb.walker.walkCompletionTime::589824-655359 21 0.02% 100.00% # Table walker service (enqueue to completion) latency 474system.cpu0.dtb.walker.walkCompletionTime::total 90418 # Table walker service (enqueue to completion) latency 475system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution 476system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution 477system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution 478system.cpu0.dtb.walker.walkPageSizes::4K 80745 89.30% 89.30% # Table walker page sizes translated 479system.cpu0.dtb.walker.walkPageSizes::2M 9673 10.70% 100.00% # Table walker page sizes translated 480system.cpu0.dtb.walker.walkPageSizes::total 90418 # Table walker page sizes translated 481system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 280305 # Table walker requests started/completed, data/inst 482system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 483system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 280305 # Table walker requests started/completed, data/inst 484system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90418 # Table walker requests started/completed, data/inst 485system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90418 # Table walker requests started/completed, data/inst 487system.cpu0.dtb.walker.walkRequestOrigin::total 370723 # Table walker requests started/completed, data/inst 488system.cpu0.dtb.inst_hits 0 # ITB inst hits 489system.cpu0.dtb.inst_misses 0 # ITB inst misses 490system.cpu0.dtb.read_hits 85620412 # DTB read hits 491system.cpu0.dtb.read_misses 232360 # DTB read misses 492system.cpu0.dtb.write_hits 76323418 # DTB write hits 493system.cpu0.dtb.write_misses 47945 # DTB write misses 494system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 495system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 496system.cpu0.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 497system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 498system.cpu0.dtb.flush_entries 37568 # Number of entries that have been flushed from TLB 499system.cpu0.dtb.align_faults 2099 # Number of TLB faults due to alignment restrictions 500system.cpu0.dtb.prefetch_faults 10030 # Number of TLB faults due to prefetch 501system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 502system.cpu0.dtb.perms_faults 11718 # Number of TLB faults due to permissions restrictions 503system.cpu0.dtb.read_accesses 85852772 # DTB read accesses 504system.cpu0.dtb.write_accesses 76371363 # DTB write accesses 505system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 506system.cpu0.dtb.hits 161943830 # DTB hits 507system.cpu0.dtb.misses 280305 # DTB misses 508system.cpu0.dtb.accesses 162224135 # DTB accesses 509system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 510system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 512system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 513system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 514system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 515system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 516system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 517system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 518system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 519system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 520system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 521system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 522system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 523system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 524system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 525system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 526system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 527system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 528system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 529system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 530system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 531system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 532system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 533system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 534system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 535system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 536system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 537system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 538system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 539system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 540system.cpu0.itb.walker.walks 68220 # Table walker walks requested 541system.cpu0.itb.walker.walksLong 68220 # Table walker walks initiated with long descriptors 542system.cpu0.itb.walker.walksLongTerminationLevel::Level2 613 # Level at which table walker walks with long descriptors terminate 543system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59689 # Level at which table walker walks with long descriptors terminate 544system.cpu0.itb.walker.walkWaitTime::samples 68220 # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::0 68220 100.00% 100.00% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::total 68220 # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkCompletionTime::samples 60302 # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::mean 26595.826009 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451 # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::0-65535 58891 97.66% 97.66% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::65536-131071 1009 1.67% 99.33% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::131072-196607 274 0.45% 99.79% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.12% 99.91% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.93% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.95% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.96% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.96% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::total 60302 # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution 565system.cpu0.itb.walker.walkPageSizes::4K 59689 98.98% 98.98% # Table walker page sizes translated 566system.cpu0.itb.walker.walkPageSizes::2M 613 1.02% 100.00% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::total 60302 # Table walker page sizes translated 568system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68220 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68220 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60302 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60302 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin::total 128522 # Table walker requests started/completed, data/inst 575system.cpu0.itb.inst_hits 240780512 # ITB inst hits 576system.cpu0.itb.inst_misses 68220 # ITB inst misses 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 585system.cpu0.itb.flush_entries 26473 # Number of entries that have been flushed from TLB 586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 160298 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 240848732 # ITB inst accesses 593system.cpu0.itb.hits 240780512 # DTB hits 594system.cpu0.itb.misses 68220 # DTB misses 595system.cpu0.itb.accesses 240848732 # DTB accesses 596system.cpu0.numPwrStateTransitions 27604 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 13802 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 3395512179.708375 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 87569621243.897629 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 3847 27.87% 27.87% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 9929 71.94% 99.81% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::max_value 7470353787292 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateClkGateDist::total 13802 # Distribution of time spent in the clock gated state 614system.cpu0.pwrStateResidencyTicks::ON 491351021665 # Cumulative time (in ticks) in various power states 615system.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335 # Cumulative time (in ticks) in various power states 616system.cpu0.numCycles 982743358 # number of cpu cycles simulated 617system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 618system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 619system.cpu0.committedInsts 443442317 # Number of instructions committed 620system.cpu0.committedOps 521139520 # Number of ops (including micro ops) committed 621system.cpu0.discardedOps 46171758 # Number of ops (including micro ops) which were discarded before commit 622system.cpu0.numFetchSuspends 4942 # Number of times Execute suspended instruction fetching 623system.cpu0.quiesceCycles 93730487058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 624system.cpu0.cpi 2.216170 # CPI: cycles per instruction 625system.cpu0.ipc 0.451229 # IPC: instructions per cycle 626system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 627system.cpu0.op_class_0::IntAlu 361587453 69.38% 69.38% # Class of committed instruction 628system.cpu0.op_class_0::IntMult 1073144 0.21% 69.59% # Class of committed instruction 629system.cpu0.op_class_0::IntDiv 57197 0.01% 69.60% # Class of committed instruction 630system.cpu0.op_class_0::FloatAdd 8 0.00% 69.60% # Class of committed instruction 631system.cpu0.op_class_0::FloatCmp 13 0.00% 69.60% # Class of committed instruction 632system.cpu0.op_class_0::FloatCvt 21 0.00% 69.60% # Class of committed instruction 633system.cpu0.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction 634system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.60% # Class of committed instruction 635system.cpu0.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction 636system.cpu0.op_class_0::FloatMisc 48874 0.01% 69.61% # Class of committed instruction 637system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 638system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 639system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 640system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 641system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 642system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 643system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 644system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 645system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 646system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 647system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 648system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 649system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 650system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 651system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 652system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 653system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 654system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.61% # Class of committed instruction 655system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction 656system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction 657system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction 658system.cpu0.op_class_0::MemRead 82336787 15.80% 85.41% # Class of committed instruction 659system.cpu0.op_class_0::MemWrite 75604792 14.51% 99.92% # Class of committed instruction 660system.cpu0.op_class_0::FloatMemRead 54276 0.01% 99.93% # Class of committed instruction 661system.cpu0.op_class_0::FloatMemWrite 376955 0.07% 100.00% # Class of committed instruction 662system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 663system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 664system.cpu0.op_class_0::total 521139520 # Class of committed instruction 665system.cpu0.kern.inst.arm 0 # number of arm instructions executed 666system.cpu0.kern.inst.quiesce 13802 # number of quiesce instructions executed 667system.cpu0.tickCycles 716804238 # Number of cycles that the object actually ticked 668system.cpu0.idleCycles 265939120 # Total number of cycles that the object has spent stopped 669system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 670system.cpu0.dcache.tags.replacements 5714630 # number of replacements 671system.cpu0.dcache.tags.tagsinuse 503.374360 # Cycle average of tags in use 672system.cpu0.dcache.tags.total_refs 153605175 # Total number of references to valid blocks. 673system.cpu0.dcache.tags.sampled_refs 5715141 # Sample count of references to valid blocks. 674system.cpu0.dcache.tags.avg_refs 26.876883 # Average number of references to valid blocks. 675system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. 676system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.374360 # Average occupied blocks per requestor 677system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983153 # Average percentage of cache occupancy 678system.cpu0.dcache.tags.occ_percent::total 0.983153 # Average percentage of cache occupancy 679system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 680system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 681system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 682system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 683system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 684system.cpu0.dcache.tags.tag_accesses 326958988 # Number of tag accesses 685system.cpu0.dcache.tags.data_accesses 326958988 # Number of data accesses 686system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 687system.cpu0.dcache.ReadReq_hits::cpu0.data 78624149 # number of ReadReq hits 688system.cpu0.dcache.ReadReq_hits::total 78624149 # number of ReadReq hits 689system.cpu0.dcache.WriteReq_hits::cpu0.data 70655306 # number of WriteReq hits 690system.cpu0.dcache.WriteReq_hits::total 70655306 # number of WriteReq hits 691system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268473 # number of SoftPFReq hits 692system.cpu0.dcache.SoftPFReq_hits::total 268473 # number of SoftPFReq hits 693system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172491 # number of WriteLineReq hits 694system.cpu0.dcache.WriteLineReq_hits::total 172491 # number of WriteLineReq hits 695system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1691736 # number of LoadLockedReq hits 696system.cpu0.dcache.LoadLockedReq_hits::total 1691736 # number of LoadLockedReq hits 697system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1666426 # number of StoreCondReq hits 698system.cpu0.dcache.StoreCondReq_hits::total 1666426 # number of StoreCondReq hits 699system.cpu0.dcache.demand_hits::cpu0.data 149451946 # number of demand (read+write) hits 700system.cpu0.dcache.demand_hits::total 149451946 # number of demand (read+write) hits 701system.cpu0.dcache.overall_hits::cpu0.data 149720419 # number of overall hits 702system.cpu0.dcache.overall_hits::total 149720419 # number of overall hits 703system.cpu0.dcache.ReadReq_misses::cpu0.data 3212821 # number of ReadReq misses 704system.cpu0.dcache.ReadReq_misses::total 3212821 # number of ReadReq misses 705system.cpu0.dcache.WriteReq_misses::cpu0.data 2434459 # number of WriteReq misses 706system.cpu0.dcache.WriteReq_misses::total 2434459 # number of WriteReq misses 707system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667240 # number of SoftPFReq misses 708system.cpu0.dcache.SoftPFReq_misses::total 667240 # number of SoftPFReq misses 709system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831306 # number of WriteLineReq misses 710system.cpu0.dcache.WriteLineReq_misses::total 831306 # number of WriteLineReq misses 711system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163515 # number of LoadLockedReq misses 712system.cpu0.dcache.LoadLockedReq_misses::total 163515 # number of LoadLockedReq misses 713system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187633 # number of StoreCondReq misses 714system.cpu0.dcache.StoreCondReq_misses::total 187633 # number of StoreCondReq misses 715system.cpu0.dcache.demand_misses::cpu0.data 6478586 # number of demand (read+write) misses 716system.cpu0.dcache.demand_misses::total 6478586 # number of demand (read+write) misses 717system.cpu0.dcache.overall_misses::cpu0.data 7145826 # number of overall misses 718system.cpu0.dcache.overall_misses::total 7145826 # number of overall misses 719system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52300502500 # number of ReadReq miss cycles 720system.cpu0.dcache.ReadReq_miss_latency::total 52300502500 # number of ReadReq miss cycles 721system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52442906000 # number of WriteReq miss cycles 722system.cpu0.dcache.WriteReq_miss_latency::total 52442906000 # number of WriteReq miss cycles 723system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26430842500 # number of WriteLineReq miss cycles 724system.cpu0.dcache.WriteLineReq_miss_latency::total 26430842500 # number of WriteLineReq miss cycles 725system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2572412500 # number of LoadLockedReq miss cycles 726system.cpu0.dcache.LoadLockedReq_miss_latency::total 2572412500 # number of LoadLockedReq miss cycles 727system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4480220000 # number of StoreCondReq miss cycles 728system.cpu0.dcache.StoreCondReq_miss_latency::total 4480220000 # number of StoreCondReq miss cycles 729system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2147000 # number of StoreCondFailReq miss cycles 730system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2147000 # number of StoreCondFailReq miss cycles 731system.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000 # number of demand (read+write) miss cycles 732system.cpu0.dcache.demand_miss_latency::total 131174251000 # number of demand (read+write) miss cycles 733system.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000 # number of overall miss cycles 734system.cpu0.dcache.overall_miss_latency::total 131174251000 # number of overall miss cycles 735system.cpu0.dcache.ReadReq_accesses::cpu0.data 81836970 # number of ReadReq accesses(hits+misses) 736system.cpu0.dcache.ReadReq_accesses::total 81836970 # number of ReadReq accesses(hits+misses) 737system.cpu0.dcache.WriteReq_accesses::cpu0.data 73089765 # number of WriteReq accesses(hits+misses) 738system.cpu0.dcache.WriteReq_accesses::total 73089765 # number of WriteReq accesses(hits+misses) 739system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935713 # number of SoftPFReq accesses(hits+misses) 740system.cpu0.dcache.SoftPFReq_accesses::total 935713 # number of SoftPFReq accesses(hits+misses) 741system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1003797 # number of WriteLineReq accesses(hits+misses) 742system.cpu0.dcache.WriteLineReq_accesses::total 1003797 # number of WriteLineReq accesses(hits+misses) 743system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1855251 # number of LoadLockedReq accesses(hits+misses) 744system.cpu0.dcache.LoadLockedReq_accesses::total 1855251 # number of LoadLockedReq accesses(hits+misses) 745system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1854059 # number of StoreCondReq accesses(hits+misses) 746system.cpu0.dcache.StoreCondReq_accesses::total 1854059 # number of StoreCondReq accesses(hits+misses) 747system.cpu0.dcache.demand_accesses::cpu0.data 155930532 # number of demand (read+write) accesses 748system.cpu0.dcache.demand_accesses::total 155930532 # number of demand (read+write) accesses 749system.cpu0.dcache.overall_accesses::cpu0.data 156866245 # number of overall (read+write) accesses 750system.cpu0.dcache.overall_accesses::total 156866245 # number of overall (read+write) accesses 751system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039259 # miss rate for ReadReq accesses 752system.cpu0.dcache.ReadReq_miss_rate::total 0.039259 # miss rate for ReadReq accesses 753system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033308 # miss rate for WriteReq accesses 754system.cpu0.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses 755system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713082 # miss rate for SoftPFReq accesses 756system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713082 # miss rate for SoftPFReq accesses 757system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.828161 # miss rate for WriteLineReq accesses 758system.cpu0.dcache.WriteLineReq_miss_rate::total 0.828161 # miss rate for WriteLineReq accesses 759system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088136 # miss rate for LoadLockedReq accesses 760system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088136 # miss rate for LoadLockedReq accesses 761system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101201 # miss rate for StoreCondReq accesses 762system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101201 # miss rate for StoreCondReq accesses 763system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses 764system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses 765system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045554 # miss rate for overall accesses 766system.cpu0.dcache.overall_miss_rate::total 0.045554 # miss rate for overall accesses 767system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461 # average ReadReq miss latency 768system.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461 # average ReadReq miss latency 769system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830 # average WriteReq miss latency 770system.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830 # average WriteReq miss latency 771system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320 # average WriteLineReq miss latency 772system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320 # average WriteLineReq miss latency 773system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486 # average LoadLockedReq miss latency 774system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486 # average LoadLockedReq miss latency 775system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511 # average StoreCondReq miss latency 776system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511 # average StoreCondReq miss latency 777system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 778system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 779system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143 # average overall miss latency 780system.cpu0.dcache.demand_avg_miss_latency::total 20247.358143 # average overall miss latency 781system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334 # average overall miss latency 782system.cpu0.dcache.overall_avg_miss_latency::total 18356.765334 # average overall miss latency 783system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 784system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 785system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 786system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 787system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 788system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 789system.cpu0.dcache.writebacks::writebacks 5714633 # number of writebacks 790system.cpu0.dcache.writebacks::total 5714633 # number of writebacks 791system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202792 # number of ReadReq MSHR hits 792system.cpu0.dcache.ReadReq_mshr_hits::total 202792 # number of ReadReq MSHR hits 793system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1014502 # number of WriteReq MSHR hits 794system.cpu0.dcache.WriteReq_mshr_hits::total 1014502 # number of WriteReq MSHR hits 795system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 93 # number of WriteLineReq MSHR hits 796system.cpu0.dcache.WriteLineReq_mshr_hits::total 93 # number of WriteLineReq MSHR hits 797system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43372 # number of LoadLockedReq MSHR hits 798system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43372 # number of LoadLockedReq MSHR hits 799system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 49 # number of StoreCondReq MSHR hits 800system.cpu0.dcache.StoreCondReq_mshr_hits::total 49 # number of StoreCondReq MSHR hits 801system.cpu0.dcache.demand_mshr_hits::cpu0.data 1217387 # number of demand (read+write) MSHR hits 802system.cpu0.dcache.demand_mshr_hits::total 1217387 # number of demand (read+write) MSHR hits 803system.cpu0.dcache.overall_mshr_hits::cpu0.data 1217387 # number of overall MSHR hits 804system.cpu0.dcache.overall_mshr_hits::total 1217387 # number of overall MSHR hits 805system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3010029 # number of ReadReq MSHR misses 806system.cpu0.dcache.ReadReq_mshr_misses::total 3010029 # number of ReadReq MSHR misses 807system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419957 # number of WriteReq MSHR misses 808system.cpu0.dcache.WriteReq_mshr_misses::total 1419957 # number of WriteReq MSHR misses 809system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664995 # number of SoftPFReq MSHR misses 810system.cpu0.dcache.SoftPFReq_mshr_misses::total 664995 # number of SoftPFReq MSHR misses 811system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 831213 # number of WriteLineReq MSHR misses 812system.cpu0.dcache.WriteLineReq_mshr_misses::total 831213 # number of WriteLineReq MSHR misses 813system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120143 # number of LoadLockedReq MSHR misses 814system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120143 # number of LoadLockedReq MSHR misses 815system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187584 # number of StoreCondReq MSHR misses 816system.cpu0.dcache.StoreCondReq_mshr_misses::total 187584 # number of StoreCondReq MSHR misses 817system.cpu0.dcache.demand_mshr_misses::cpu0.data 5261199 # number of demand (read+write) MSHR misses 818system.cpu0.dcache.demand_mshr_misses::total 5261199 # number of demand (read+write) MSHR misses 819system.cpu0.dcache.overall_mshr_misses::cpu0.data 5926194 # number of overall MSHR misses 820system.cpu0.dcache.overall_mshr_misses::total 5926194 # number of overall MSHR misses 821system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 822system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31550 # number of ReadReq MSHR uncacheable 823system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 824system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable 825system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 826system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62751 # number of overall MSHR uncacheable misses 827system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44196910500 # number of ReadReq MSHR miss cycles 828system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44196910500 # number of ReadReq MSHR miss cycles 829system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29509664500 # number of WriteReq MSHR miss cycles 830system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29509664500 # number of WriteReq MSHR miss cycles 831system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16065417000 # number of SoftPFReq MSHR miss cycles 832system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16065417000 # number of SoftPFReq MSHR miss cycles 833system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25593186000 # number of WriteLineReq MSHR miss cycles 834system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25593186000 # number of WriteLineReq MSHR miss cycles 835system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1671520500 # number of LoadLockedReq MSHR miss cycles 836system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1671520500 # number of LoadLockedReq MSHR miss cycles 837system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4291457000 # number of StoreCondReq MSHR miss cycles 838system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4291457000 # number of StoreCondReq MSHR miss cycles 839system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1958500 # number of StoreCondFailReq MSHR miss cycles 840system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1958500 # number of StoreCondFailReq MSHR miss cycles 841system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99299761000 # number of demand (read+write) MSHR miss cycles 842system.cpu0.dcache.demand_mshr_miss_latency::total 99299761000 # number of demand (read+write) MSHR miss cycles 843system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000 # number of overall MSHR miss cycles 844system.cpu0.dcache.overall_mshr_miss_latency::total 115365178000 # number of overall MSHR miss cycles 845system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6087891000 # number of ReadReq MSHR uncacheable cycles 846system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6087891000 # number of ReadReq MSHR uncacheable cycles 847system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6087891000 # number of overall MSHR uncacheable cycles 848system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6087891000 # number of overall MSHR uncacheable cycles 849system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036781 # mshr miss rate for ReadReq accesses 850system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036781 # mshr miss rate for ReadReq accesses 851system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019428 # mshr miss rate for WriteReq accesses 852system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019428 # mshr miss rate for WriteReq accesses 853system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710683 # mshr miss rate for SoftPFReq accesses 854system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710683 # mshr miss rate for SoftPFReq accesses 855system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.828069 # mshr miss rate for WriteLineReq accesses 856system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.828069 # mshr miss rate for WriteLineReq accesses 857system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064758 # mshr miss rate for LoadLockedReq accesses 858system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064758 # mshr miss rate for LoadLockedReq accesses 859system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101175 # mshr miss rate for StoreCondReq accesses 860system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101175 # mshr miss rate for StoreCondReq accesses 861system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033741 # mshr miss rate for demand accesses 862system.cpu0.dcache.demand_mshr_miss_rate::total 0.033741 # mshr miss rate for demand accesses 863system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037779 # mshr miss rate for overall accesses 864system.cpu0.dcache.overall_mshr_miss_rate::total 0.037779 # mshr miss rate for overall accesses 865system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504 # average ReadReq mshr miss latency 866system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504 # average ReadReq mshr miss latency 867system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190 # average WriteReq mshr miss latency 868system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190 # average WriteReq mshr miss latency 869system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449 # average SoftPFReq mshr miss latency 870system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449 # average SoftPFReq mshr miss latency 871system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698 # average WriteLineReq mshr miss latency 872system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698 # average WriteLineReq mshr miss latency 873system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130 # average LoadLockedReq mshr miss latency 874system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130 # average LoadLockedReq mshr miss latency 875system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537 # average StoreCondReq mshr miss latency 876system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537 # average StoreCondReq mshr miss latency 877system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 878system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 879system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296 # average overall mshr miss latency 880system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296 # average overall mshr miss latency 881system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149 # average overall mshr miss latency 882system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149 # average overall mshr miss latency 883system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087 # average ReadReq mshr uncacheable latency 884system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087 # average ReadReq mshr uncacheable latency 885system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185 # average overall mshr uncacheable latency 886system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185 # average overall mshr uncacheable latency 887system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 888system.cpu0.icache.tags.replacements 9611464 # number of replacements 889system.cpu0.icache.tags.tagsinuse 511.928699 # Cycle average of tags in use 890system.cpu0.icache.tags.total_refs 231001616 # Total number of references to valid blocks. 891system.cpu0.icache.tags.sampled_refs 9611976 # Sample count of references to valid blocks. 892system.cpu0.icache.tags.avg_refs 24.032688 # Average number of references to valid blocks. 893system.cpu0.icache.tags.warmup_cycle 22883257000 # Cycle when the warmup percentage was hit. 894system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928699 # Average occupied blocks per requestor 895system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy 896system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy 897system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 898system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 899system.cpu0.icache.tags.age_task_id_blocks_1024::1 426 # Occupied blocks per task id 900system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 901system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 902system.cpu0.icache.tags.tag_accesses 490839190 # Number of tag accesses 903system.cpu0.icache.tags.data_accesses 490839190 # Number of data accesses 904system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 905system.cpu0.icache.ReadReq_hits::cpu0.inst 231001616 # number of ReadReq hits 906system.cpu0.icache.ReadReq_hits::total 231001616 # number of ReadReq hits 907system.cpu0.icache.demand_hits::cpu0.inst 231001616 # number of demand (read+write) hits 908system.cpu0.icache.demand_hits::total 231001616 # number of demand (read+write) hits 909system.cpu0.icache.overall_hits::cpu0.inst 231001616 # number of overall hits 910system.cpu0.icache.overall_hits::total 231001616 # number of overall hits 911system.cpu0.icache.ReadReq_misses::cpu0.inst 9611986 # number of ReadReq misses 912system.cpu0.icache.ReadReq_misses::total 9611986 # number of ReadReq misses 913system.cpu0.icache.demand_misses::cpu0.inst 9611986 # number of demand (read+write) misses 914system.cpu0.icache.demand_misses::total 9611986 # number of demand (read+write) misses 915system.cpu0.icache.overall_misses::cpu0.inst 9611986 # number of overall misses 916system.cpu0.icache.overall_misses::total 9611986 # number of overall misses 917system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98657772000 # number of ReadReq miss cycles 918system.cpu0.icache.ReadReq_miss_latency::total 98657772000 # number of ReadReq miss cycles 919system.cpu0.icache.demand_miss_latency::cpu0.inst 98657772000 # number of demand (read+write) miss cycles 920system.cpu0.icache.demand_miss_latency::total 98657772000 # number of demand (read+write) miss cycles 921system.cpu0.icache.overall_miss_latency::cpu0.inst 98657772000 # number of overall miss cycles 922system.cpu0.icache.overall_miss_latency::total 98657772000 # number of overall miss cycles 923system.cpu0.icache.ReadReq_accesses::cpu0.inst 240613602 # number of ReadReq accesses(hits+misses) 924system.cpu0.icache.ReadReq_accesses::total 240613602 # number of ReadReq accesses(hits+misses) 925system.cpu0.icache.demand_accesses::cpu0.inst 240613602 # number of demand (read+write) accesses 926system.cpu0.icache.demand_accesses::total 240613602 # number of demand (read+write) accesses 927system.cpu0.icache.overall_accesses::cpu0.inst 240613602 # number of overall (read+write) accesses 928system.cpu0.icache.overall_accesses::total 240613602 # number of overall (read+write) accesses 929system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039948 # miss rate for ReadReq accesses 930system.cpu0.icache.ReadReq_miss_rate::total 0.039948 # miss rate for ReadReq accesses 931system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039948 # miss rate for demand accesses 932system.cpu0.icache.demand_miss_rate::total 0.039948 # miss rate for demand accesses 933system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039948 # miss rate for overall accesses 934system.cpu0.icache.overall_miss_rate::total 0.039948 # miss rate for overall accesses 935system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173 # average ReadReq miss latency 936system.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173 # average ReadReq miss latency 937system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency 938system.cpu0.icache.demand_avg_miss_latency::total 10264.036173 # average overall miss latency 939system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency 940system.cpu0.icache.overall_avg_miss_latency::total 10264.036173 # average overall miss latency 941system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 942system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 943system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 944system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 945system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 946system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 947system.cpu0.icache.writebacks::writebacks 9611464 # number of writebacks 948system.cpu0.icache.writebacks::total 9611464 # number of writebacks 949system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9611986 # number of ReadReq MSHR misses 950system.cpu0.icache.ReadReq_mshr_misses::total 9611986 # number of ReadReq MSHR misses 951system.cpu0.icache.demand_mshr_misses::cpu0.inst 9611986 # number of demand (read+write) MSHR misses 952system.cpu0.icache.demand_mshr_misses::total 9611986 # number of demand (read+write) MSHR misses 953system.cpu0.icache.overall_mshr_misses::cpu0.inst 9611986 # number of overall MSHR misses 954system.cpu0.icache.overall_mshr_misses::total 9611986 # number of overall MSHR misses 955system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 956system.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable 957system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 958system.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses 959system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93851779000 # number of ReadReq MSHR miss cycles 960system.cpu0.icache.ReadReq_mshr_miss_latency::total 93851779000 # number of ReadReq MSHR miss cycles 961system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93851779000 # number of demand (read+write) MSHR miss cycles 962system.cpu0.icache.demand_mshr_miss_latency::total 93851779000 # number of demand (read+write) MSHR miss cycles 963system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93851779000 # number of overall MSHR miss cycles 964system.cpu0.icache.overall_mshr_miss_latency::total 93851779000 # number of overall MSHR miss cycles 965system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles 966system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles 967system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles 968system.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles 969system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for ReadReq accesses 970system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039948 # mshr miss rate for ReadReq accesses 971system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for demand accesses 972system.cpu0.icache.demand_mshr_miss_rate::total 0.039948 # mshr miss rate for demand accesses 973system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for overall accesses 974system.cpu0.icache.overall_mshr_miss_rate::total 0.039948 # mshr miss rate for overall accesses 975system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average ReadReq mshr miss latency 976system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9764.036173 # average ReadReq mshr miss latency 977system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency 978system.cpu0.icache.demand_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency 979system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency 980system.cpu0.icache.overall_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency 981system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency 982system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency 983system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency 984system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency 985system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 986system.cpu0.l2cache.prefetcher.num_hwpf_issued 7434042 # number of hwpf issued 987system.cpu0.l2cache.prefetcher.pfIdentified 7435434 # number of prefetch candidates identified 988system.cpu0.l2cache.prefetcher.pfBufferHit 1234 # number of redundant prefetches already in prefetch queue 989system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 990system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 991system.cpu0.l2cache.prefetcher.pfSpanPage 974582 # number of prefetches not generated due to page crossing 992system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 993system.cpu0.l2cache.tags.replacements 2611270 # number of replacements 994system.cpu0.l2cache.tags.tagsinuse 15687.218696 # Cycle average of tags in use 995system.cpu0.l2cache.tags.total_refs 13797239 # Total number of references to valid blocks. 996system.cpu0.l2cache.tags.sampled_refs 2627042 # Sample count of references to valid blocks. 997system.cpu0.l2cache.tags.avg_refs 5.252005 # Average number of references to valid blocks. 998system.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit. 999system.cpu0.l2cache.tags.occ_blocks::writebacks 15319.283860 # Average occupied blocks per requestor 1000system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.805682 # Average occupied blocks per requestor 1001system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.313962 # Average occupied blocks per requestor 1002system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 298.815192 # Average occupied blocks per requestor 1003system.cpu0.l2cache.tags.occ_percent::writebacks 0.935015 # Average percentage of cache occupancy 1004system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002613 # Average percentage of cache occupancy 1005system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001606 # Average percentage of cache occupancy 1006system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018238 # Average percentage of cache occupancy 1007system.cpu0.l2cache.tags.occ_percent::total 0.957472 # Average percentage of cache occupancy 1008system.cpu0.l2cache.tags.occ_task_id_blocks::1022 263 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 82 # Occupied blocks per task id 1012system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 89 # Occupied blocks per task id 1013system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id 1014system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id 1015system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id 1016system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id 1017system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 1018system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 1019system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2136 # Occupied blocks per task id 1020system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5462 # Occupied blocks per task id 1021system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5455 # Occupied blocks per task id 1022system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2257 # Occupied blocks per task id 1023system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016052 # Percentage of cache occupancy per task id 1024system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id 1025system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id 1026system.cpu0.l2cache.tags.tag_accesses 526460646 # Number of tag accesses 1027system.cpu0.l2cache.tags.data_accesses 526460646 # Number of data accesses 1028system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1029system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522971 # number of ReadReq hits 1030system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 177971 # number of ReadReq hits 1031system.cpu0.l2cache.ReadReq_hits::total 700942 # number of ReadReq hits 1032system.cpu0.l2cache.WritebackDirty_hits::writebacks 3820006 # number of WritebackDirty hits 1033system.cpu0.l2cache.WritebackDirty_hits::total 3820006 # number of WritebackDirty hits 1034system.cpu0.l2cache.WritebackClean_hits::writebacks 11503050 # number of WritebackClean hits 1035system.cpu0.l2cache.WritebackClean_hits::total 11503050 # number of WritebackClean hits 1036system.cpu0.l2cache.ReadExReq_hits::cpu0.data 900259 # number of ReadExReq hits 1037system.cpu0.l2cache.ReadExReq_hits::total 900259 # number of ReadExReq hits 1038system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8923530 # number of ReadCleanReq hits 1039system.cpu0.l2cache.ReadCleanReq_hits::total 8923530 # number of ReadCleanReq hits 1040system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2824509 # number of ReadSharedReq hits 1041system.cpu0.l2cache.ReadSharedReq_hits::total 2824509 # number of ReadSharedReq hits 1042system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229490 # number of InvalidateReq hits 1043system.cpu0.l2cache.InvalidateReq_hits::total 229490 # number of InvalidateReq hits 1044system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522971 # number of demand (read+write) hits 1045system.cpu0.l2cache.demand_hits::cpu0.itb.walker 177971 # number of demand (read+write) hits 1046system.cpu0.l2cache.demand_hits::cpu0.inst 8923530 # number of demand (read+write) hits 1047system.cpu0.l2cache.demand_hits::cpu0.data 3724768 # number of demand (read+write) hits 1048system.cpu0.l2cache.demand_hits::total 13349240 # number of demand (read+write) hits 1049system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522971 # number of overall hits 1050system.cpu0.l2cache.overall_hits::cpu0.itb.walker 177971 # number of overall hits 1051system.cpu0.l2cache.overall_hits::cpu0.inst 8923530 # number of overall hits 1052system.cpu0.l2cache.overall_hits::cpu0.data 3724768 # number of overall hits 1053system.cpu0.l2cache.overall_hits::total 13349240 # number of overall hits 1054system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20616 # number of ReadReq misses 1055system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9971 # number of ReadReq misses 1056system.cpu0.l2cache.ReadReq_misses::total 30587 # number of ReadReq misses 1057system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242554 # number of UpgradeReq misses 1058system.cpu0.l2cache.UpgradeReq_misses::total 242554 # number of UpgradeReq misses 1059system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187582 # number of SCUpgradeReq misses 1060system.cpu0.l2cache.SCUpgradeReq_misses::total 187582 # number of SCUpgradeReq misses 1061system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1062system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1063system.cpu0.l2cache.ReadExReq_misses::cpu0.data 283527 # number of ReadExReq misses 1064system.cpu0.l2cache.ReadExReq_misses::total 283527 # number of ReadExReq misses 1065system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688455 # number of ReadCleanReq misses 1066system.cpu0.l2cache.ReadCleanReq_misses::total 688455 # number of ReadCleanReq misses 1067system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 970291 # number of ReadSharedReq misses 1068system.cpu0.l2cache.ReadSharedReq_misses::total 970291 # number of ReadSharedReq misses 1069system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601723 # number of InvalidateReq misses 1070system.cpu0.l2cache.InvalidateReq_misses::total 601723 # number of InvalidateReq misses 1071system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20616 # number of demand (read+write) misses 1072system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9971 # number of demand (read+write) misses 1073system.cpu0.l2cache.demand_misses::cpu0.inst 688455 # number of demand (read+write) misses 1074system.cpu0.l2cache.demand_misses::cpu0.data 1253818 # number of demand (read+write) misses 1075system.cpu0.l2cache.demand_misses::total 1972860 # number of demand (read+write) misses 1076system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20616 # number of overall misses 1077system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9971 # number of overall misses 1078system.cpu0.l2cache.overall_misses::cpu0.inst 688455 # number of overall misses 1079system.cpu0.l2cache.overall_misses::cpu0.data 1253818 # number of overall misses 1080system.cpu0.l2cache.overall_misses::total 1972860 # number of overall misses 1081system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 693953500 # number of ReadReq miss cycles 1082system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 416737500 # number of ReadReq miss cycles 1083system.cpu0.l2cache.ReadReq_miss_latency::total 1110691000 # number of ReadReq miss cycles 1084system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 877430000 # number of UpgradeReq miss cycles 1085system.cpu0.l2cache.UpgradeReq_miss_latency::total 877430000 # number of UpgradeReq miss cycles 1086system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 285529500 # number of SCUpgradeReq miss cycles 1087system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 285529500 # number of SCUpgradeReq miss cycles 1088system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1883000 # number of SCUpgradeFailReq miss cycles 1089system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1883000 # number of SCUpgradeFailReq miss cycles 1090system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15417318498 # number of ReadExReq miss cycles 1091system.cpu0.l2cache.ReadExReq_miss_latency::total 15417318498 # number of ReadExReq miss cycles 1092system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25525674000 # number of ReadCleanReq miss cycles 1093system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25525674000 # number of ReadCleanReq miss cycles 1094system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37603567991 # number of ReadSharedReq miss cycles 1095system.cpu0.l2cache.ReadSharedReq_miss_latency::total 37603567991 # number of ReadSharedReq miss cycles 1096system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles 1097system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles 1098system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 693953500 # number of demand (read+write) miss cycles 1099system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 416737500 # number of demand (read+write) miss cycles 1100system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25525674000 # number of demand (read+write) miss cycles 1101system.cpu0.l2cache.demand_miss_latency::cpu0.data 53020886489 # number of demand (read+write) miss cycles 1102system.cpu0.l2cache.demand_miss_latency::total 79657251489 # number of demand (read+write) miss cycles 1103system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 693953500 # number of overall miss cycles 1104system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 416737500 # number of overall miss cycles 1105system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25525674000 # number of overall miss cycles 1106system.cpu0.l2cache.overall_miss_latency::cpu0.data 53020886489 # number of overall miss cycles 1107system.cpu0.l2cache.overall_miss_latency::total 79657251489 # number of overall miss cycles 1108system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 543587 # number of ReadReq accesses(hits+misses) 1109system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 187942 # number of ReadReq accesses(hits+misses) 1110system.cpu0.l2cache.ReadReq_accesses::total 731529 # number of ReadReq accesses(hits+misses) 1111system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3820006 # number of WritebackDirty accesses(hits+misses) 1112system.cpu0.l2cache.WritebackDirty_accesses::total 3820006 # number of WritebackDirty accesses(hits+misses) 1113system.cpu0.l2cache.WritebackClean_accesses::writebacks 11503050 # number of WritebackClean accesses(hits+misses) 1114system.cpu0.l2cache.WritebackClean_accesses::total 11503050 # number of WritebackClean accesses(hits+misses) 1115system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242554 # number of UpgradeReq accesses(hits+misses) 1116system.cpu0.l2cache.UpgradeReq_accesses::total 242554 # number of UpgradeReq accesses(hits+misses) 1117system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187582 # number of SCUpgradeReq accesses(hits+misses) 1118system.cpu0.l2cache.SCUpgradeReq_accesses::total 187582 # number of SCUpgradeReq accesses(hits+misses) 1119system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1120system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1121system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183786 # number of ReadExReq accesses(hits+misses) 1122system.cpu0.l2cache.ReadExReq_accesses::total 1183786 # number of ReadExReq accesses(hits+misses) 1123system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9611985 # number of ReadCleanReq accesses(hits+misses) 1124system.cpu0.l2cache.ReadCleanReq_accesses::total 9611985 # number of ReadCleanReq accesses(hits+misses) 1125system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3794800 # number of ReadSharedReq accesses(hits+misses) 1126system.cpu0.l2cache.ReadSharedReq_accesses::total 3794800 # number of ReadSharedReq accesses(hits+misses) 1127system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831213 # number of InvalidateReq accesses(hits+misses) 1128system.cpu0.l2cache.InvalidateReq_accesses::total 831213 # number of InvalidateReq accesses(hits+misses) 1129system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 543587 # number of demand (read+write) accesses 1130system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 187942 # number of demand (read+write) accesses 1131system.cpu0.l2cache.demand_accesses::cpu0.inst 9611985 # number of demand (read+write) accesses 1132system.cpu0.l2cache.demand_accesses::cpu0.data 4978586 # number of demand (read+write) accesses 1133system.cpu0.l2cache.demand_accesses::total 15322100 # number of demand (read+write) accesses 1134system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 543587 # number of overall (read+write) accesses 1135system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 187942 # number of overall (read+write) accesses 1136system.cpu0.l2cache.overall_accesses::cpu0.inst 9611985 # number of overall (read+write) accesses 1137system.cpu0.l2cache.overall_accesses::cpu0.data 4978586 # number of overall (read+write) accesses 1138system.cpu0.l2cache.overall_accesses::total 15322100 # number of overall (read+write) accesses 1139system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for ReadReq accesses 1140system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053054 # miss rate for ReadReq accesses 1141system.cpu0.l2cache.ReadReq_miss_rate::total 0.041812 # miss rate for ReadReq accesses 1142system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1143system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1144system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1145system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1147system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1148system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.239509 # miss rate for ReadExReq accesses 1149system.cpu0.l2cache.ReadExReq_miss_rate::total 0.239509 # miss rate for ReadExReq accesses 1150system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071625 # miss rate for ReadCleanReq accesses 1151system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071625 # miss rate for ReadCleanReq accesses 1152system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255690 # miss rate for ReadSharedReq accesses 1153system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255690 # miss rate for ReadSharedReq accesses 1154system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.723910 # miss rate for InvalidateReq accesses 1155system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.723910 # miss rate for InvalidateReq accesses 1156system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for demand accesses 1157system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053054 # miss rate for demand accesses 1158system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071625 # miss rate for demand accesses 1159system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251842 # miss rate for demand accesses 1160system.cpu0.l2cache.demand_miss_rate::total 0.128759 # miss rate for demand accesses 1161system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for overall accesses 1162system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053054 # miss rate for overall accesses 1163system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071625 # miss rate for overall accesses 1164system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251842 # miss rate for overall accesses 1165system.cpu0.l2cache.overall_miss_rate::total 0.128759 # miss rate for overall accesses 1166system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average ReadReq miss latency 1167system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41794.955371 # average ReadReq miss latency 1168system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36312.518390 # average ReadReq miss latency 1169system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3617.462503 # average UpgradeReq miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3617.462503 # average UpgradeReq miss latency 1171system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1522.158309 # average SCUpgradeReq miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1522.158309 # average SCUpgradeReq miss latency 1173system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency 1175system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54376.897079 # average ReadExReq miss latency 1176system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54376.897079 # average ReadExReq miss latency 1177system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37076.750114 # average ReadCleanReq miss latency 1178system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37076.750114 # average ReadCleanReq miss latency 1179system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38754.938458 # average ReadSharedReq miss latency 1180system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38754.938458 # average ReadSharedReq miss latency 1181system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.172837 # average InvalidateReq miss latency 1182system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.172837 # average InvalidateReq miss latency 1183system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency 1184system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency 1185system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency 1186system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency 1187system.cpu0.l2cache.demand_avg_miss_latency::total 40376.535329 # average overall miss latency 1188system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency 1189system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency 1190system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency 1191system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency 1192system.cpu0.l2cache.overall_avg_miss_latency::total 40376.535329 # average overall miss latency 1193system.cpu0.l2cache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 1194system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1195system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1196system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1197system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked 1198system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1199system.cpu0.l2cache.unused_prefetches 44451 # number of HardPF blocks evicted w/o reference 1200system.cpu0.l2cache.writebacks::writebacks 1620068 # number of writebacks 1201system.cpu0.l2cache.writebacks::total 1620068 # number of writebacks 1202system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits 1203system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 98 # number of ReadReq MSHR hits 1204system.cpu0.l2cache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits 1205system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8857 # number of ReadExReq MSHR hits 1206system.cpu0.l2cache.ReadExReq_mshr_hits::total 8857 # number of ReadExReq MSHR hits 1207system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits 1208system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 1209system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 996 # number of ReadSharedReq MSHR hits 1210system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 996 # number of ReadSharedReq MSHR hits 1211system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 1212system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 1213system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits 1214system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 98 # number of demand (read+write) MSHR hits 1215system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits 1216system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9853 # number of demand (read+write) MSHR hits 1217system.cpu0.l2cache.demand_mshr_hits::total 9980 # number of demand (read+write) MSHR hits 1218system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits 1219system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 98 # number of overall MSHR hits 1220system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits 1221system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9853 # number of overall MSHR hits 1222system.cpu0.l2cache.overall_mshr_hits::total 9980 # number of overall MSHR hits 1223system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20593 # number of ReadReq MSHR misses 1224system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9873 # number of ReadReq MSHR misses 1225system.cpu0.l2cache.ReadReq_mshr_misses::total 30466 # number of ReadReq MSHR misses 1226system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of HardPFReq MSHR misses 1227system.cpu0.l2cache.HardPFReq_mshr_misses::total 782341 # number of HardPFReq MSHR misses 1228system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242554 # number of UpgradeReq MSHR misses 1229system.cpu0.l2cache.UpgradeReq_mshr_misses::total 242554 # number of UpgradeReq MSHR misses 1230system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187582 # number of SCUpgradeReq MSHR misses 1231system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187582 # number of SCUpgradeReq MSHR misses 1232system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1233system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1234system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274670 # number of ReadExReq MSHR misses 1235system.cpu0.l2cache.ReadExReq_mshr_misses::total 274670 # number of ReadExReq MSHR misses 1236system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688449 # number of ReadCleanReq MSHR misses 1237system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688449 # number of ReadCleanReq MSHR misses 1238system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 969295 # number of ReadSharedReq MSHR misses 1239system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 969295 # number of ReadSharedReq MSHR misses 1240system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601721 # number of InvalidateReq MSHR misses 1241system.cpu0.l2cache.InvalidateReq_mshr_misses::total 601721 # number of InvalidateReq MSHR misses 1242system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20593 # number of demand (read+write) MSHR misses 1243system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9873 # number of demand (read+write) MSHR misses 1244system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688449 # number of demand (read+write) MSHR misses 1245system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243965 # number of demand (read+write) MSHR misses 1246system.cpu0.l2cache.demand_mshr_misses::total 1962880 # number of demand (read+write) MSHR misses 1247system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20593 # number of overall MSHR misses 1248system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9873 # number of overall MSHR misses 1249system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688449 # number of overall MSHR misses 1250system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243965 # number of overall MSHR misses 1251system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of overall MSHR misses 1252system.cpu0.l2cache.overall_mshr_misses::total 2745221 # number of overall MSHR misses 1253system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 1254system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 1255system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83834 # number of ReadReq MSHR uncacheable 1256system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 1257system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable 1258system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 1259system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 1260system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115035 # number of overall MSHR uncacheable misses 1261system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of ReadReq MSHR miss cycles 1262system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 355875500 # number of ReadReq MSHR miss cycles 1263system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 925633500 # number of ReadReq MSHR miss cycles 1264system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of HardPFReq MSHR miss cycles 1265system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38599728272 # number of HardPFReq MSHR miss cycles 1266system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4476827494 # number of UpgradeReq MSHR miss cycles 1267system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4476827494 # number of UpgradeReq MSHR miss cycles 1268system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2879854497 # number of SCUpgradeReq MSHR miss cycles 1269system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2879854497 # number of SCUpgradeReq MSHR miss cycles 1270system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1583000 # number of SCUpgradeFailReq MSHR miss cycles 1271system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1583000 # number of SCUpgradeFailReq MSHR miss cycles 1272system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12562742498 # number of ReadExReq MSHR miss cycles 1273system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12562742498 # number of ReadExReq MSHR miss cycles 1274system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21394767500 # number of ReadCleanReq MSHR miss cycles 1275system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21394767500 # number of ReadCleanReq MSHR miss cycles 1276system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31646923991 # number of ReadSharedReq MSHR miss cycles 1277system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31646923991 # number of ReadSharedReq MSHR miss cycles 1278system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19132934000 # number of InvalidateReq MSHR miss cycles 1279system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19132934000 # number of InvalidateReq MSHR miss cycles 1280system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of demand (read+write) MSHR miss cycles 1281system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 355875500 # number of demand (read+write) MSHR miss cycles 1282system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21394767500 # number of demand (read+write) MSHR miss cycles 1283system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44209666489 # number of demand (read+write) MSHR miss cycles 1284system.cpu0.l2cache.demand_mshr_miss_latency::total 66530067489 # number of demand (read+write) MSHR miss cycles 1285system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of overall MSHR miss cycles 1286system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 355875500 # number of overall MSHR miss cycles 1287system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21394767500 # number of overall MSHR miss cycles 1288system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44209666489 # number of overall MSHR miss cycles 1289system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of overall MSHR miss cycles 1290system.cpu0.l2cache.overall_mshr_miss_latency::total 105129795761 # number of overall MSHR miss cycles 1291system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles 1292system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5835246500 # number of ReadReq MSHR uncacheable cycles 1293system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10578580500 # number of ReadReq MSHR uncacheable cycles 1294system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles 1295system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5835246500 # number of overall MSHR uncacheable cycles 1296system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10578580500 # number of overall MSHR uncacheable cycles 1297system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for ReadReq accesses 1298system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for ReadReq accesses 1299system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041647 # mshr miss rate for ReadReq accesses 1300system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1301system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1302system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1303system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1304system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1305system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1306system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1307system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1308system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.232027 # mshr miss rate for ReadExReq accesses 1309system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.232027 # mshr miss rate for ReadExReq accesses 1310system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for ReadCleanReq accesses 1311system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071624 # mshr miss rate for ReadCleanReq accesses 1312system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255427 # mshr miss rate for ReadSharedReq accesses 1313system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255427 # mshr miss rate for ReadSharedReq accesses 1314system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.723907 # mshr miss rate for InvalidateReq accesses 1315system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.723907 # mshr miss rate for InvalidateReq accesses 1316system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for demand accesses 1317system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for demand accesses 1318system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for demand accesses 1319system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for demand accesses 1320system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128108 # mshr miss rate for demand accesses 1321system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for overall accesses 1322system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for overall accesses 1323system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for overall accesses 1324system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for overall accesses 1325system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1326system.cpu0.l2cache.overall_mshr_miss_rate::total 0.179167 # mshr miss rate for overall accesses 1327system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average ReadReq mshr miss latency 1328system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average ReadReq mshr miss latency 1329system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370 # average ReadReq mshr miss latency 1330system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average HardPFReq mshr miss latency 1331system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608 # average HardPFReq mshr miss latency 1332system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285 # average UpgradeReq mshr miss latency 1333system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285 # average UpgradeReq mshr miss latency 1334system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820 # average SCUpgradeReq mshr miss latency 1335system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820 # average SCUpgradeReq mshr miss latency 1336system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 791500 # average SCUpgradeFailReq mshr miss latency 1337system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 791500 # average SCUpgradeFailReq mshr miss latency 1338system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095 # average ReadExReq mshr miss latency 1339system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095 # average ReadExReq mshr miss latency 1340system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average ReadCleanReq mshr miss latency 1341system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582 # average ReadCleanReq mshr miss latency 1342system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572 # average ReadSharedReq mshr miss latency 1343system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572 # average ReadSharedReq mshr miss latency 1344system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884 # average InvalidateReq mshr miss latency 1345system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884 # average InvalidateReq mshr miss latency 1346system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency 1347system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency 1348system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency 1349system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency 1350system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396 # average overall mshr miss latency 1351system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency 1352system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency 1353system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency 1354system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency 1355system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average overall mshr miss latency 1356system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374 # average overall mshr miss latency 1357system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency 1358system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483 # average ReadReq mshr uncacheable latency 1359system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437 # average ReadReq mshr uncacheable latency 1360system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency 1361system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175 # average overall mshr uncacheable latency 1362system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796 # average overall mshr uncacheable latency 1363system.cpu0.toL2Bus.snoop_filter.tot_requests 31463839 # Total number of requests made to the snoop filter. 1364system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16044170 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1365system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3048 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1366system.cpu0.toL2Bus.snoop_filter.tot_snoops 652134 # Total number of snoops made to the snoop filter. 1367system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 652077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1368system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 57 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1369system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1370system.cpu0.toL2Bus.trans_dist::ReadReq 887708 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::ReadResp 14387458 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::WriteReq 31201 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::WriteResp 31200 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::WritebackDirty 5457517 # Transaction distribution 1375system.cpu0.toL2Bus.trans_dist::WritebackClean 11506087 # Transaction distribution 1376system.cpu0.toL2Bus.trans_dist::CleanEvict 1359708 # Transaction distribution 1377system.cpu0.toL2Bus.trans_dist::HardPFReq 999352 # Transaction distribution 1378system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1379system.cpu0.toL2Bus.trans_dist::UpgradeReq 454749 # Transaction distribution 1380system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343952 # Transaction distribution 1381system.cpu0.toL2Bus.trans_dist::UpgradeResp 493156 # Transaction distribution 1382system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 1383system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 1384system.cpu0.toL2Bus.trans_dist::ReadExReq 1220335 # Transaction distribution 1385system.cpu0.toL2Bus.trans_dist::ReadExResp 1191280 # Transaction distribution 1386system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9611986 # Transaction distribution 1387system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4900402 # Transaction distribution 1388system.cpu0.toL2Bus.trans_dist::InvalidateReq 909564 # Transaction distribution 1389system.cpu0.toL2Bus.trans_dist::InvalidateResp 832554 # Transaction distribution 1390system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28940003 # Packet count per connected master and slave (bytes) 1391system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18484921 # Packet count per connected master and slave (bytes) 1392system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391848 # Packet count per connected master and slave (bytes) 1393system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1143553 # Packet count per connected master and slave (bytes) 1394system.cpu0.toL2Bus.pkt_count::total 48960325 # Packet count per connected master and slave (bytes) 1395system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1233646912 # Cumulative packet size per connected master and slave (bytes) 1396system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690994144 # Cumulative packet size per connected master and slave (bytes) 1397system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1503536 # Cumulative packet size per connected master and slave (bytes) 1398system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4348696 # Cumulative packet size per connected master and slave (bytes) 1399system.cpu0.toL2Bus.pkt_size::total 1930493288 # Cumulative packet size per connected master and slave (bytes) 1400system.cpu0.toL2Bus.snoops 5822948 # Total snoops (count) 1401system.cpu0.toL2Bus.snoopTraffic 111810824 # Total snoop traffic (bytes) 1402system.cpu0.toL2Bus.snoop_fanout::samples 22356517 # Request fanout histogram 1403system.cpu0.toL2Bus.snoop_fanout::mean 0.042093 # Request fanout histogram 1404system.cpu0.toL2Bus.snoop_fanout::stdev 0.200815 # Request fanout histogram 1405system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1406system.cpu0.toL2Bus.snoop_fanout::0 21415512 95.79% 95.79% # Request fanout histogram 1407system.cpu0.toL2Bus.snoop_fanout::1 940948 4.21% 100.00% # Request fanout histogram 1408system.cpu0.toL2Bus.snoop_fanout::2 57 0.00% 100.00% # Request fanout histogram 1409system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1410system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1411system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1412system.cpu0.toL2Bus.snoop_fanout::total 22356517 # Request fanout histogram 1413system.cpu0.toL2Bus.reqLayer0.occupancy 31390166976 # Layer occupancy (ticks) 1414system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1415system.cpu0.toL2Bus.snoopLayer0.occupancy 183129639 # Layer occupancy (ticks) 1416system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1417system.cpu0.toL2Bus.respLayer0.occupancy 14498904485 # Layer occupancy (ticks) 1418system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1419system.cpu0.toL2Bus.respLayer1.occupancy 8149348322 # Layer occupancy (ticks) 1420system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1421system.cpu0.toL2Bus.respLayer2.occupancy 204016279 # Layer occupancy (ticks) 1422system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1423system.cpu0.toL2Bus.respLayer3.occupancy 600088255 # Layer occupancy (ticks) 1424system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1425system.cpu1.branchPred.lookups 132997996 # Number of BP lookups 1426system.cpu1.branchPred.condPredicted 94215152 # Number of conditional branches predicted 1427system.cpu1.branchPred.condIncorrect 6033479 # Number of conditional branches incorrect 1428system.cpu1.branchPred.BTBLookups 99520242 # Number of BTB lookups 1429system.cpu1.branchPred.BTBHits 69476937 # Number of BTB hits 1430system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1431system.cpu1.branchPred.BTBHitPct 69.811865 # BTB Hit Percentage 1432system.cpu1.branchPred.usedRAS 15575496 # Number of times the RAS was used to get a target. 1433system.cpu1.branchPred.RASInCorrect 1022946 # Number of incorrect RAS predictions. 1434system.cpu1.branchPred.indirectLookups 3462102 # Number of indirect predictor lookups. 1435system.cpu1.branchPred.indirectHits 2360825 # Number of indirect target hits. 1436system.cpu1.branchPred.indirectMisses 1101277 # Number of indirect misses. 1437system.cpu1.branchPredindirectMispredicted 401735 # Number of mispredicted indirect branches. 1438system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1439system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1440system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1441system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1442system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1443system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1444system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1445system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1446system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1447system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1448system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1449system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1450system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1451system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1452system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1453system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1454system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1455system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1456system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1457system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1458system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1459system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1460system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1461system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1462system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1463system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1464system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1465system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1466system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1467system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1468system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1469system.cpu1.dtb.walker.walks 271949 # Table walker walks requested 1470system.cpu1.dtb.walker.walksLong 271949 # Table walker walks initiated with long descriptors 1471system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9428 # Level at which table walker walks with long descriptors terminate 1472system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76874 # Level at which table walker walks with long descriptors terminate 1473system.cpu1.dtb.walker.walkWaitTime::samples 271949 # Table walker wait (enqueue to first request) latency 1474system.cpu1.dtb.walker.walkWaitTime::0 271949 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1475system.cpu1.dtb.walker.walkWaitTime::total 271949 # Table walker wait (enqueue to first request) latency 1476system.cpu1.dtb.walker.walkCompletionTime::samples 86302 # Table walker service (enqueue to completion) latency 1477system.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504 # Table walker service (enqueue to completion) latency 1478system.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810 # Table walker service (enqueue to completion) latency 1479system.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024 # Table walker service (enqueue to completion) latency 1480system.cpu1.dtb.walker.walkCompletionTime::0-65535 85344 98.89% 98.89% # Table walker service (enqueue to completion) latency 1481system.cpu1.dtb.walker.walkCompletionTime::65536-131071 718 0.83% 99.72% # Table walker service (enqueue to completion) latency 1482system.cpu1.dtb.walker.walkCompletionTime::131072-196607 138 0.16% 99.88% # Table walker service (enqueue to completion) latency 1483system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency 1484system.cpu1.dtb.walker.walkCompletionTime::262144-327679 32 0.04% 99.96% # Table walker service (enqueue to completion) latency 1485system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency 1486system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1487system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1488system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 1489system.cpu1.dtb.walker.walkCompletionTime::total 86302 # Table walker service (enqueue to completion) latency 1490system.cpu1.dtb.walker.walksPending::samples 114608944 # Table walker pending requests distribution 1491system.cpu1.dtb.walker.walksPending::0 114608944 100.00% 100.00% # Table walker pending requests distribution 1492system.cpu1.dtb.walker.walksPending::total 114608944 # Table walker pending requests distribution 1493system.cpu1.dtb.walker.walkPageSizes::4K 76874 89.08% 89.08% # Table walker page sizes translated 1494system.cpu1.dtb.walker.walkPageSizes::2M 9428 10.92% 100.00% # Table walker page sizes translated 1495system.cpu1.dtb.walker.walkPageSizes::total 86302 # Table walker page sizes translated 1496system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271949 # Table walker requests started/completed, data/inst 1497system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1498system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271949 # Table walker requests started/completed, data/inst 1499system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86302 # Table walker requests started/completed, data/inst 1500system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1501system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86302 # Table walker requests started/completed, data/inst 1502system.cpu1.dtb.walker.walkRequestOrigin::total 358251 # Table walker requests started/completed, data/inst 1503system.cpu1.dtb.inst_hits 0 # ITB inst hits 1504system.cpu1.dtb.inst_misses 0 # ITB inst misses 1505system.cpu1.dtb.read_hits 86154833 # DTB read hits 1506system.cpu1.dtb.read_misses 225974 # DTB read misses 1507system.cpu1.dtb.write_hits 74805729 # DTB write hits 1508system.cpu1.dtb.write_misses 45975 # DTB write misses 1509system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1510system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1511system.cpu1.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 1512system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 1513system.cpu1.dtb.flush_entries 36571 # Number of entries that have been flushed from TLB 1514system.cpu1.dtb.align_faults 1221 # Number of TLB faults due to alignment restrictions 1515system.cpu1.dtb.prefetch_faults 7188 # Number of TLB faults due to prefetch 1516system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1517system.cpu1.dtb.perms_faults 10263 # Number of TLB faults due to permissions restrictions 1518system.cpu1.dtb.read_accesses 86380807 # DTB read accesses 1519system.cpu1.dtb.write_accesses 74851704 # DTB write accesses 1520system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1521system.cpu1.dtb.hits 160960562 # DTB hits 1522system.cpu1.dtb.misses 271949 # DTB misses 1523system.cpu1.dtb.accesses 161232511 # DTB accesses 1524system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1525system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1526system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1527system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1528system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1529system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1530system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1531system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1532system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1533system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1534system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1535system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1536system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1537system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1538system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1539system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1540system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1541system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1542system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1543system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1544system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1545system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1546system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1547system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1548system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1549system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1550system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1551system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1552system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1553system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1554system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1555system.cpu1.itb.walker.walks 60899 # Table walker walks requested 1556system.cpu1.itb.walker.walksLong 60899 # Table walker walks initiated with long descriptors 1557system.cpu1.itb.walker.walksLongTerminationLevel::Level2 513 # Level at which table walker walks with long descriptors terminate 1558system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50941 # Level at which table walker walks with long descriptors terminate 1559system.cpu1.itb.walker.walkWaitTime::samples 60899 # Table walker wait (enqueue to first request) latency 1560system.cpu1.itb.walker.walkWaitTime::0 60899 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1561system.cpu1.itb.walker.walkWaitTime::total 60899 # Table walker wait (enqueue to first request) latency 1562system.cpu1.itb.walker.walkCompletionTime::samples 51454 # Table walker service (enqueue to completion) latency 1563system.cpu1.itb.walker.walkCompletionTime::mean 25618.018036 # Table walker service (enqueue to completion) latency 1564system.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553 # Table walker service (enqueue to completion) latency 1565system.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181 # Table walker service (enqueue to completion) latency 1566system.cpu1.itb.walker.walkCompletionTime::0-65535 50489 98.12% 98.12% # Table walker service (enqueue to completion) latency 1567system.cpu1.itb.walker.walkCompletionTime::65536-131071 670 1.30% 99.43% # Table walker service (enqueue to completion) latency 1568system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.41% 99.84% # Table walker service (enqueue to completion) latency 1569system.cpu1.itb.walker.walkCompletionTime::196608-262143 46 0.09% 99.93% # Table walker service (enqueue to completion) latency 1570system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.95% # Table walker service (enqueue to completion) latency 1571system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency 1572system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 1573system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 1574system.cpu1.itb.walker.walkCompletionTime::589824-655359 13 0.03% 100.00% # Table walker service (enqueue to completion) latency 1575system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1576system.cpu1.itb.walker.walkCompletionTime::total 51454 # Table walker service (enqueue to completion) latency 1577system.cpu1.itb.walker.walksPending::samples 113972444 # Table walker pending requests distribution 1578system.cpu1.itb.walker.walksPending::0 113972444 100.00% 100.00% # Table walker pending requests distribution 1579system.cpu1.itb.walker.walksPending::total 113972444 # Table walker pending requests distribution 1580system.cpu1.itb.walker.walkPageSizes::4K 50941 99.00% 99.00% # Table walker page sizes translated 1581system.cpu1.itb.walker.walkPageSizes::2M 513 1.00% 100.00% # Table walker page sizes translated 1582system.cpu1.itb.walker.walkPageSizes::total 51454 # Table walker page sizes translated 1583system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1584system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60899 # Table walker requests started/completed, data/inst 1585system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60899 # Table walker requests started/completed, data/inst 1586system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1587system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51454 # Table walker requests started/completed, data/inst 1588system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51454 # Table walker requests started/completed, data/inst 1589system.cpu1.itb.walker.walkRequestOrigin::total 112353 # Table walker requests started/completed, data/inst 1590system.cpu1.itb.inst_hits 236231380 # ITB inst hits 1591system.cpu1.itb.inst_misses 60899 # ITB inst misses 1592system.cpu1.itb.read_hits 0 # DTB read hits 1593system.cpu1.itb.read_misses 0 # DTB read misses 1594system.cpu1.itb.write_hits 0 # DTB write hits 1595system.cpu1.itb.write_misses 0 # DTB write misses 1596system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1597system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1598system.cpu1.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID 1599system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 1600system.cpu1.itb.flush_entries 26538 # Number of entries that have been flushed from TLB 1601system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1602system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1603system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1604system.cpu1.itb.perms_faults 178013 # Number of TLB faults due to permissions restrictions 1605system.cpu1.itb.read_accesses 0 # DTB read accesses 1606system.cpu1.itb.write_accesses 0 # DTB write accesses 1607system.cpu1.itb.inst_accesses 236292279 # ITB inst accesses 1608system.cpu1.itb.hits 236231380 # DTB hits 1609system.cpu1.itb.misses 60899 # DTB misses 1610system.cpu1.itb.accesses 236292279 # DTB accesses 1611system.cpu1.numPwrStateTransitions 9440 # Number of power state transitions 1612system.cpu1.pwrStateClkGateDist::samples 4720 # Distribution of time spent in the clock gated state 1613system.cpu1.pwrStateClkGateDist::mean 9937322156.794067 # Distribution of time spent in the clock gated state 1614system.cpu1.pwrStateClkGateDist::stdev 214697400239.899719 # Distribution of time spent in the clock gated state 1615system.cpu1.pwrStateClkGateDist::underflows 3380 71.61% 71.61% # Distribution of time spent in the clock gated state 1616system.cpu1.pwrStateClkGateDist::1000-5e+10 1320 27.97% 99.58% # Distribution of time spent in the clock gated state 1617system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.11% 99.68% # Distribution of time spent in the clock gated state 1618system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state 1619system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.75% # Distribution of time spent in the clock gated state 1620system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 1621system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 1622system.cpu1.pwrStateClkGateDist::overflows 10 0.21% 100.00% # Distribution of time spent in the clock gated state 1623system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1624system.cpu1.pwrStateClkGateDist::max_value 11813594348000 # Distribution of time spent in the clock gated state 1625system.cpu1.pwrStateClkGateDist::total 4720 # Distribution of time spent in the clock gated state 1626system.cpu1.pwrStateResidencyTicks::ON 452049545932 # Cumulative time (in ticks) in various power states 1627system.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068 # Cumulative time (in ticks) in various power states 1628system.cpu1.numCycles 904105497 # number of cpu cycles simulated 1629system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1630system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1631system.cpu1.committedInsts 436062178 # Number of instructions committed 1632system.cpu1.committedOps 513430287 # Number of ops (including micro ops) committed 1633system.cpu1.discardedOps 45590191 # Number of ops (including micro ops) which were discarded before commit 1634system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching 1635system.cpu1.quiesceCycles 93808990671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1636system.cpu1.cpi 2.073341 # CPI: cycles per instruction 1637system.cpu1.ipc 0.482313 # IPC: instructions per cycle 1638system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 1639system.cpu1.op_class_0::IntAlu 354600208 69.06% 69.06% # Class of committed instruction 1640system.cpu1.op_class_0::IntMult 1143323 0.22% 69.29% # Class of committed instruction 1641system.cpu1.op_class_0::IntDiv 59569 0.01% 69.30% # Class of committed instruction 1642system.cpu1.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction 1643system.cpu1.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction 1644system.cpu1.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction 1645system.cpu1.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction 1646system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.30% # Class of committed instruction 1647system.cpu1.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction 1648system.cpu1.op_class_0::FloatMisc 63096 0.01% 69.31% # Class of committed instruction 1649system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction 1650system.cpu1.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction 1651system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction 1652system.cpu1.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction 1653system.cpu1.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction 1654system.cpu1.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction 1655system.cpu1.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction 1656system.cpu1.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction 1657system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction 1658system.cpu1.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction 1659system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction 1660system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction 1661system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction 1662system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction 1663system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction 1664system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction 1665system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction 1666system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.31% # Class of committed instruction 1667system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction 1668system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction 1669system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction 1670system.cpu1.op_class_0::MemRead 82989666 16.16% 85.48% # Class of committed instruction 1671system.cpu1.op_class_0::MemWrite 74191847 14.45% 99.93% # Class of committed instruction 1672system.cpu1.op_class_0::FloatMemRead 64253 0.01% 99.94% # Class of committed instruction 1673system.cpu1.op_class_0::FloatMemWrite 318324 0.06% 100.00% # Class of committed instruction 1674system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1675system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1676system.cpu1.op_class_0::total 513430287 # Class of committed instruction 1677system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1678system.cpu1.kern.inst.quiesce 4720 # number of quiesce instructions executed 1679system.cpu1.tickCycles 704305988 # Number of cycles that the object actually ticked 1680system.cpu1.idleCycles 199799509 # Total number of cycles that the object has spent stopped 1681system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1682system.cpu1.dcache.tags.replacements 5048947 # number of replacements 1683system.cpu1.dcache.tags.tagsinuse 416.228585 # Cycle average of tags in use 1684system.cpu1.dcache.tags.total_refs 153590869 # Total number of references to valid blocks. 1685system.cpu1.dcache.tags.sampled_refs 5049459 # Sample count of references to valid blocks. 1686system.cpu1.dcache.tags.avg_refs 30.417292 # Average number of references to valid blocks. 1687system.cpu1.dcache.tags.warmup_cycle 8378525599500 # Cycle when the warmup percentage was hit. 1688system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.228585 # Average occupied blocks per requestor 1689system.cpu1.dcache.tags.occ_percent::cpu1.data 0.812946 # Average percentage of cache occupancy 1690system.cpu1.dcache.tags.occ_percent::total 0.812946 # Average percentage of cache occupancy 1691system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1692system.cpu1.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 1693system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 1694system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 1695system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1696system.cpu1.dcache.tags.tag_accesses 324622701 # Number of tag accesses 1697system.cpu1.dcache.tags.data_accesses 324622701 # Number of data accesses 1698system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1699system.cpu1.dcache.ReadReq_hits::cpu1.data 79356977 # number of ReadReq hits 1700system.cpu1.dcache.ReadReq_hits::total 79356977 # number of ReadReq hits 1701system.cpu1.dcache.WriteReq_hits::cpu1.data 69837106 # number of WriteReq hits 1702system.cpu1.dcache.WriteReq_hits::total 69837106 # number of WriteReq hits 1703system.cpu1.dcache.SoftPFReq_hits::cpu1.data 233112 # number of SoftPFReq hits 1704system.cpu1.dcache.SoftPFReq_hits::total 233112 # number of SoftPFReq hits 1705system.cpu1.dcache.WriteLineReq_hits::cpu1.data 147127 # number of WriteLineReq hits 1706system.cpu1.dcache.WriteLineReq_hits::total 147127 # number of WriteLineReq hits 1707system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782955 # number of LoadLockedReq hits 1708system.cpu1.dcache.LoadLockedReq_hits::total 1782955 # number of LoadLockedReq hits 1709system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1749534 # number of StoreCondReq hits 1710system.cpu1.dcache.StoreCondReq_hits::total 1749534 # number of StoreCondReq hits 1711system.cpu1.dcache.demand_hits::cpu1.data 149341210 # number of demand (read+write) hits 1712system.cpu1.dcache.demand_hits::total 149341210 # number of demand (read+write) hits 1713system.cpu1.dcache.overall_hits::cpu1.data 149574322 # number of overall hits 1714system.cpu1.dcache.overall_hits::total 149574322 # number of overall hits 1715system.cpu1.dcache.ReadReq_misses::cpu1.data 3104936 # number of ReadReq misses 1716system.cpu1.dcache.ReadReq_misses::total 3104936 # number of ReadReq misses 1717system.cpu1.dcache.WriteReq_misses::cpu1.data 2154320 # number of WriteReq misses 1718system.cpu1.dcache.WriteReq_misses::total 2154320 # number of WriteReq misses 1719system.cpu1.dcache.SoftPFReq_misses::cpu1.data 600203 # number of SoftPFReq misses 1720system.cpu1.dcache.SoftPFReq_misses::total 600203 # number of SoftPFReq misses 1721system.cpu1.dcache.WriteLineReq_misses::cpu1.data 416637 # number of WriteLineReq misses 1722system.cpu1.dcache.WriteLineReq_misses::total 416637 # number of WriteLineReq misses 1723system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162547 # number of LoadLockedReq misses 1724system.cpu1.dcache.LoadLockedReq_misses::total 162547 # number of LoadLockedReq misses 1725system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194652 # number of StoreCondReq misses 1726system.cpu1.dcache.StoreCondReq_misses::total 194652 # number of StoreCondReq misses 1727system.cpu1.dcache.demand_misses::cpu1.data 5675893 # number of demand (read+write) misses 1728system.cpu1.dcache.demand_misses::total 5675893 # number of demand (read+write) misses 1729system.cpu1.dcache.overall_misses::cpu1.data 6276096 # number of overall misses 1730system.cpu1.dcache.overall_misses::total 6276096 # number of overall misses 1731system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47629871000 # number of ReadReq miss cycles 1732system.cpu1.dcache.ReadReq_miss_latency::total 47629871000 # number of ReadReq miss cycles 1733system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40774475000 # number of WriteReq miss cycles 1734system.cpu1.dcache.WriteReq_miss_latency::total 40774475000 # number of WriteReq miss cycles 1735system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9727566000 # number of WriteLineReq miss cycles 1736system.cpu1.dcache.WriteLineReq_miss_latency::total 9727566000 # number of WriteLineReq miss cycles 1737system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2415502000 # number of LoadLockedReq miss cycles 1738system.cpu1.dcache.LoadLockedReq_miss_latency::total 2415502000 # number of LoadLockedReq miss cycles 1739system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4643846000 # number of StoreCondReq miss cycles 1740system.cpu1.dcache.StoreCondReq_miss_latency::total 4643846000 # number of StoreCondReq miss cycles 1741system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2158500 # number of StoreCondFailReq miss cycles 1742system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2158500 # number of StoreCondFailReq miss cycles 1743system.cpu1.dcache.demand_miss_latency::cpu1.data 98131912000 # number of demand (read+write) miss cycles 1744system.cpu1.dcache.demand_miss_latency::total 98131912000 # number of demand (read+write) miss cycles 1745system.cpu1.dcache.overall_miss_latency::cpu1.data 98131912000 # number of overall miss cycles 1746system.cpu1.dcache.overall_miss_latency::total 98131912000 # number of overall miss cycles 1747system.cpu1.dcache.ReadReq_accesses::cpu1.data 82461913 # number of ReadReq accesses(hits+misses) 1748system.cpu1.dcache.ReadReq_accesses::total 82461913 # number of ReadReq accesses(hits+misses) 1749system.cpu1.dcache.WriteReq_accesses::cpu1.data 71991426 # number of WriteReq accesses(hits+misses) 1750system.cpu1.dcache.WriteReq_accesses::total 71991426 # number of WriteReq accesses(hits+misses) 1751system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833315 # number of SoftPFReq accesses(hits+misses) 1752system.cpu1.dcache.SoftPFReq_accesses::total 833315 # number of SoftPFReq accesses(hits+misses) 1753system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 563764 # number of WriteLineReq accesses(hits+misses) 1754system.cpu1.dcache.WriteLineReq_accesses::total 563764 # number of WriteLineReq accesses(hits+misses) 1755system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945502 # number of LoadLockedReq accesses(hits+misses) 1756system.cpu1.dcache.LoadLockedReq_accesses::total 1945502 # number of LoadLockedReq accesses(hits+misses) 1757system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944186 # number of StoreCondReq accesses(hits+misses) 1758system.cpu1.dcache.StoreCondReq_accesses::total 1944186 # number of StoreCondReq accesses(hits+misses) 1759system.cpu1.dcache.demand_accesses::cpu1.data 155017103 # number of demand (read+write) accesses 1760system.cpu1.dcache.demand_accesses::total 155017103 # number of demand (read+write) accesses 1761system.cpu1.dcache.overall_accesses::cpu1.data 155850418 # number of overall (read+write) accesses 1762system.cpu1.dcache.overall_accesses::total 155850418 # number of overall (read+write) accesses 1763system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037653 # miss rate for ReadReq accesses 1764system.cpu1.dcache.ReadReq_miss_rate::total 0.037653 # miss rate for ReadReq accesses 1765system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029925 # miss rate for WriteReq accesses 1766system.cpu1.dcache.WriteReq_miss_rate::total 0.029925 # miss rate for WriteReq accesses 1767system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.720259 # miss rate for SoftPFReq accesses 1768system.cpu1.dcache.SoftPFReq_miss_rate::total 0.720259 # miss rate for SoftPFReq accesses 1769system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739027 # miss rate for WriteLineReq accesses 1770system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739027 # miss rate for WriteLineReq accesses 1771system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083550 # miss rate for LoadLockedReq accesses 1772system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083550 # miss rate for LoadLockedReq accesses 1773system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100120 # miss rate for StoreCondReq accesses 1774system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100120 # miss rate for StoreCondReq accesses 1775system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036615 # miss rate for demand accesses 1776system.cpu1.dcache.demand_miss_rate::total 0.036615 # miss rate for demand accesses 1777system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040270 # miss rate for overall accesses 1778system.cpu1.dcache.overall_miss_rate::total 0.040270 # miss rate for overall accesses 1779system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199 # average ReadReq miss latency 1780system.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199 # average ReadReq miss latency 1781system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345 # average WriteReq miss latency 1782system.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345 # average WriteReq miss latency 1783system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765 # average WriteLineReq miss latency 1784system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765 # average WriteLineReq miss latency 1785system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628 # average LoadLockedReq miss latency 1786system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628 # average LoadLockedReq miss latency 1787system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746 # average StoreCondReq miss latency 1788system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746 # average StoreCondReq miss latency 1789system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1790system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1791system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291 # average overall miss latency 1792system.cpu1.dcache.demand_avg_miss_latency::total 17289.246291 # average overall miss latency 1793system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740 # average overall miss latency 1794system.cpu1.dcache.overall_avg_miss_latency::total 15635.820740 # average overall miss latency 1795system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1796system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1797system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1798system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1799system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1800system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1801system.cpu1.dcache.writebacks::writebacks 5048949 # number of writebacks 1802system.cpu1.dcache.writebacks::total 5048949 # number of writebacks 1803system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 157294 # number of ReadReq MSHR hits 1804system.cpu1.dcache.ReadReq_mshr_hits::total 157294 # number of ReadReq MSHR hits 1805system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 878635 # number of WriteReq MSHR hits 1806system.cpu1.dcache.WriteReq_mshr_hits::total 878635 # number of WriteReq MSHR hits 1807system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 59 # number of WriteLineReq MSHR hits 1808system.cpu1.dcache.WriteLineReq_mshr_hits::total 59 # number of WriteLineReq MSHR hits 1809system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39126 # number of LoadLockedReq MSHR hits 1810system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39126 # number of LoadLockedReq MSHR hits 1811system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 65 # number of StoreCondReq MSHR hits 1812system.cpu1.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits 1813system.cpu1.dcache.demand_mshr_hits::cpu1.data 1035988 # number of demand (read+write) MSHR hits 1814system.cpu1.dcache.demand_mshr_hits::total 1035988 # number of demand (read+write) MSHR hits 1815system.cpu1.dcache.overall_mshr_hits::cpu1.data 1035988 # number of overall MSHR hits 1816system.cpu1.dcache.overall_mshr_hits::total 1035988 # number of overall MSHR hits 1817system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2947642 # number of ReadReq MSHR misses 1818system.cpu1.dcache.ReadReq_mshr_misses::total 2947642 # number of ReadReq MSHR misses 1819system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1275685 # number of WriteReq MSHR misses 1820system.cpu1.dcache.WriteReq_mshr_misses::total 1275685 # number of WriteReq MSHR misses 1821system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599894 # number of SoftPFReq MSHR misses 1822system.cpu1.dcache.SoftPFReq_mshr_misses::total 599894 # number of SoftPFReq MSHR misses 1823system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 416578 # number of WriteLineReq MSHR misses 1824system.cpu1.dcache.WriteLineReq_mshr_misses::total 416578 # number of WriteLineReq MSHR misses 1825system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123421 # number of LoadLockedReq MSHR misses 1826system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123421 # number of LoadLockedReq MSHR misses 1827system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194587 # number of StoreCondReq MSHR misses 1828system.cpu1.dcache.StoreCondReq_mshr_misses::total 194587 # number of StoreCondReq MSHR misses 1829system.cpu1.dcache.demand_mshr_misses::cpu1.data 4639905 # number of demand (read+write) MSHR misses 1830system.cpu1.dcache.demand_mshr_misses::total 4639905 # number of demand (read+write) MSHR misses 1831system.cpu1.dcache.overall_mshr_misses::cpu1.data 5239799 # number of overall MSHR misses 1832system.cpu1.dcache.overall_mshr_misses::total 5239799 # number of overall MSHR misses 1833system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable 1834system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6968 # number of ReadReq MSHR uncacheable 1835system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 1836system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable 1837system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses 1838system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14155 # number of overall MSHR uncacheable misses 1839system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41244047000 # number of ReadReq MSHR miss cycles 1840system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41244047000 # number of ReadReq MSHR miss cycles 1841system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23526690000 # number of WriteReq MSHR miss cycles 1842system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23526690000 # number of WriteReq MSHR miss cycles 1843system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13870615000 # number of SoftPFReq MSHR miss cycles 1844system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13870615000 # number of SoftPFReq MSHR miss cycles 1845system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9306680500 # number of WriteLineReq MSHR miss cycles 1846system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9306680500 # number of WriteLineReq MSHR miss cycles 1847system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1636714500 # number of LoadLockedReq MSHR miss cycles 1848system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1636714500 # number of LoadLockedReq MSHR miss cycles 1849system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4447799000 # number of StoreCondReq MSHR miss cycles 1850system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4447799000 # number of StoreCondReq MSHR miss cycles 1851system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1876000 # number of StoreCondFailReq MSHR miss cycles 1852system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1876000 # number of StoreCondFailReq MSHR miss cycles 1853system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74077417500 # number of demand (read+write) MSHR miss cycles 1854system.cpu1.dcache.demand_mshr_miss_latency::total 74077417500 # number of demand (read+write) MSHR miss cycles 1855system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87948032500 # number of overall MSHR miss cycles 1856system.cpu1.dcache.overall_mshr_miss_latency::total 87948032500 # number of overall MSHR miss cycles 1857system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 882714500 # number of ReadReq MSHR uncacheable cycles 1858system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 882714500 # number of ReadReq MSHR uncacheable cycles 1859system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 882714500 # number of overall MSHR uncacheable cycles 1860system.cpu1.dcache.overall_mshr_uncacheable_latency::total 882714500 # number of overall MSHR uncacheable cycles 1861system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035745 # mshr miss rate for ReadReq accesses 1862system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035745 # mshr miss rate for ReadReq accesses 1863system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017720 # mshr miss rate for WriteReq accesses 1864system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 1865system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.719889 # mshr miss rate for SoftPFReq accesses 1866system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.719889 # mshr miss rate for SoftPFReq accesses 1867system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738923 # mshr miss rate for WriteLineReq accesses 1868system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738923 # mshr miss rate for WriteLineReq accesses 1869system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063439 # mshr miss rate for LoadLockedReq accesses 1870system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063439 # mshr miss rate for LoadLockedReq accesses 1871system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100087 # mshr miss rate for StoreCondReq accesses 1872system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100087 # mshr miss rate for StoreCondReq accesses 1873system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses 1874system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses 1875system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033621 # mshr miss rate for overall accesses 1876system.cpu1.dcache.overall_mshr_miss_rate::total 0.033621 # mshr miss rate for overall accesses 1877system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169 # average ReadReq mshr miss latency 1878system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169 # average ReadReq mshr miss latency 1879system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614 # average WriteReq mshr miss latency 1880system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614 # average WriteReq mshr miss latency 1881system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514 # average SoftPFReq mshr miss latency 1882system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514 # average SoftPFReq mshr miss latency 1883system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320 # average WriteLineReq mshr miss latency 1884system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320 # average WriteLineReq mshr miss latency 1885system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881 # average LoadLockedReq mshr miss latency 1886system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881 # average LoadLockedReq mshr miss latency 1887system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944 # average StoreCondReq mshr miss latency 1888system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944 # average StoreCondReq mshr miss latency 1889system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1890system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1891system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544 # average overall mshr miss latency 1892system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544 # average overall mshr miss latency 1893system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505 # average overall mshr miss latency 1894system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505 # average overall mshr miss latency 1895system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419 # average ReadReq mshr uncacheable latency 1896system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419 # average ReadReq mshr uncacheable latency 1897system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624 # average overall mshr uncacheable latency 1898system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624 # average overall mshr uncacheable latency 1899system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1900system.cpu1.icache.tags.replacements 9106015 # number of replacements 1901system.cpu1.icache.tags.tagsinuse 507.214941 # Cycle average of tags in use 1902system.cpu1.icache.tags.total_refs 226941610 # Total number of references to valid blocks. 1903system.cpu1.icache.tags.sampled_refs 9106527 # Sample count of references to valid blocks. 1904system.cpu1.icache.tags.avg_refs 24.920764 # Average number of references to valid blocks. 1905system.cpu1.icache.tags.warmup_cycle 8368863514500 # Cycle when the warmup percentage was hit. 1906system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.214941 # Average occupied blocks per requestor 1907system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990654 # Average percentage of cache occupancy 1908system.cpu1.icache.tags.occ_percent::total 0.990654 # Average percentage of cache occupancy 1909system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1910system.cpu1.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id 1911system.cpu1.icache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 1912system.cpu1.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 1913system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1914system.cpu1.icache.tags.tag_accesses 481202803 # Number of tag accesses 1915system.cpu1.icache.tags.data_accesses 481202803 # Number of data accesses 1916system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1917system.cpu1.icache.ReadReq_hits::cpu1.inst 226941610 # number of ReadReq hits 1918system.cpu1.icache.ReadReq_hits::total 226941610 # number of ReadReq hits 1919system.cpu1.icache.demand_hits::cpu1.inst 226941610 # number of demand (read+write) hits 1920system.cpu1.icache.demand_hits::total 226941610 # number of demand (read+write) hits 1921system.cpu1.icache.overall_hits::cpu1.inst 226941610 # number of overall hits 1922system.cpu1.icache.overall_hits::total 226941610 # number of overall hits 1923system.cpu1.icache.ReadReq_misses::cpu1.inst 9106528 # number of ReadReq misses 1924system.cpu1.icache.ReadReq_misses::total 9106528 # number of ReadReq misses 1925system.cpu1.icache.demand_misses::cpu1.inst 9106528 # number of demand (read+write) misses 1926system.cpu1.icache.demand_misses::total 9106528 # number of demand (read+write) misses 1927system.cpu1.icache.overall_misses::cpu1.inst 9106528 # number of overall misses 1928system.cpu1.icache.overall_misses::total 9106528 # number of overall misses 1929system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93334039500 # number of ReadReq miss cycles 1930system.cpu1.icache.ReadReq_miss_latency::total 93334039500 # number of ReadReq miss cycles 1931system.cpu1.icache.demand_miss_latency::cpu1.inst 93334039500 # number of demand (read+write) miss cycles 1932system.cpu1.icache.demand_miss_latency::total 93334039500 # number of demand (read+write) miss cycles 1933system.cpu1.icache.overall_miss_latency::cpu1.inst 93334039500 # number of overall miss cycles 1934system.cpu1.icache.overall_miss_latency::total 93334039500 # number of overall miss cycles 1935system.cpu1.icache.ReadReq_accesses::cpu1.inst 236048138 # number of ReadReq accesses(hits+misses) 1936system.cpu1.icache.ReadReq_accesses::total 236048138 # number of ReadReq accesses(hits+misses) 1937system.cpu1.icache.demand_accesses::cpu1.inst 236048138 # number of demand (read+write) accesses 1938system.cpu1.icache.demand_accesses::total 236048138 # number of demand (read+write) accesses 1939system.cpu1.icache.overall_accesses::cpu1.inst 236048138 # number of overall (read+write) accesses 1940system.cpu1.icache.overall_accesses::total 236048138 # number of overall (read+write) accesses 1941system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038579 # miss rate for ReadReq accesses 1942system.cpu1.icache.ReadReq_miss_rate::total 0.038579 # miss rate for ReadReq accesses 1943system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038579 # miss rate for demand accesses 1944system.cpu1.icache.demand_miss_rate::total 0.038579 # miss rate for demand accesses 1945system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038579 # miss rate for overall accesses 1946system.cpu1.icache.overall_miss_rate::total 0.038579 # miss rate for overall accesses 1947system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510 # average ReadReq miss latency 1948system.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510 # average ReadReq miss latency 1949system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency 1950system.cpu1.icache.demand_avg_miss_latency::total 10249.135510 # average overall miss latency 1951system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency 1952system.cpu1.icache.overall_avg_miss_latency::total 10249.135510 # average overall miss latency 1953system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1954system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1955system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1956system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1957system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1958system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1959system.cpu1.icache.writebacks::writebacks 9106015 # number of writebacks 1960system.cpu1.icache.writebacks::total 9106015 # number of writebacks 1961system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9106528 # number of ReadReq MSHR misses 1962system.cpu1.icache.ReadReq_mshr_misses::total 9106528 # number of ReadReq MSHR misses 1963system.cpu1.icache.demand_mshr_misses::cpu1.inst 9106528 # number of demand (read+write) MSHR misses 1964system.cpu1.icache.demand_mshr_misses::total 9106528 # number of demand (read+write) MSHR misses 1965system.cpu1.icache.overall_mshr_misses::cpu1.inst 9106528 # number of overall MSHR misses 1966system.cpu1.icache.overall_mshr_misses::total 9106528 # number of overall MSHR misses 1967system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 1968system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 1969system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 1970system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 1971system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88780776000 # number of ReadReq MSHR miss cycles 1972system.cpu1.icache.ReadReq_mshr_miss_latency::total 88780776000 # number of ReadReq MSHR miss cycles 1973system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88780776000 # number of demand (read+write) MSHR miss cycles 1974system.cpu1.icache.demand_mshr_miss_latency::total 88780776000 # number of demand (read+write) MSHR miss cycles 1975system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88780776000 # number of overall MSHR miss cycles 1976system.cpu1.icache.overall_mshr_miss_latency::total 88780776000 # number of overall MSHR miss cycles 1977system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9602500 # number of ReadReq MSHR uncacheable cycles 1978system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9602500 # number of ReadReq MSHR uncacheable cycles 1979system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9602500 # number of overall MSHR uncacheable cycles 1980system.cpu1.icache.overall_mshr_uncacheable_latency::total 9602500 # number of overall MSHR uncacheable cycles 1981system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for ReadReq accesses 1982system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038579 # mshr miss rate for ReadReq accesses 1983system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for demand accesses 1984system.cpu1.icache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses 1985system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for overall accesses 1986system.cpu1.icache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses 1987system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average ReadReq mshr miss latency 1988system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9749.135565 # average ReadReq mshr miss latency 1989system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency 1990system.cpu1.icache.demand_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency 1991system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency 1992system.cpu1.icache.overall_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency 1993system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average ReadReq mshr uncacheable latency 1994system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368 # average ReadReq mshr uncacheable latency 1995system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average overall mshr uncacheable latency 1996system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368 # average overall mshr uncacheable latency 1997system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 1998system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104941 # number of hwpf issued 1999system.cpu1.l2cache.prefetcher.pfIdentified 7105044 # number of prefetch candidates identified 2000system.cpu1.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue 2001system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2002system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2003system.cpu1.l2cache.prefetcher.pfSpanPage 891372 # number of prefetches not generated due to page crossing 2004system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2005system.cpu1.l2cache.tags.replacements 2193537 # number of replacements 2006system.cpu1.l2cache.tags.tagsinuse 13101.642441 # Cycle average of tags in use 2007system.cpu1.l2cache.tags.total_refs 12964075 # Total number of references to valid blocks. 2008system.cpu1.l2cache.tags.sampled_refs 2209317 # Sample count of references to valid blocks. 2009system.cpu1.l2cache.tags.avg_refs 5.867911 # Average number of references to valid blocks. 2010system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2011system.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283 # Average occupied blocks per requestor 2012system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 29.247108 # Average occupied blocks per requestor 2013system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.647207 # Average occupied blocks per requestor 2014system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 236.020843 # Average occupied blocks per requestor 2015system.cpu1.l2cache.tags.occ_percent::writebacks 0.782454 # Average percentage of cache occupancy 2016system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001785 # Average percentage of cache occupancy 2017system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001016 # Average percentage of cache occupancy 2018system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014406 # Average percentage of cache occupancy 2019system.cpu1.l2cache.tags.occ_percent::total 0.799661 # Average percentage of cache occupancy 2020system.cpu1.l2cache.tags.occ_task_id_blocks::1022 358 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15375 # Occupied blocks per task id 2023system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 2024system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 2025system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id 2026system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 74 # Occupied blocks per task id 2027system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2028system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 2029system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 2030system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2031system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 2032system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1753 # Occupied blocks per task id 2033system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6630 # Occupied blocks per task id 2034system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5167 # Occupied blocks per task id 2035system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id 2036system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021851 # Percentage of cache occupancy per task id 2037system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id 2038system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.938416 # Percentage of cache occupancy per task id 2039system.cpu1.l2cache.tags.tag_accesses 486850576 # Number of tag accesses 2040system.cpu1.l2cache.tags.data_accesses 486850576 # Number of data accesses 2041system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2042system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 506555 # number of ReadReq hits 2043system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 152150 # number of ReadReq hits 2044system.cpu1.l2cache.ReadReq_hits::total 658705 # number of ReadReq hits 2045system.cpu1.l2cache.WritebackDirty_hits::writebacks 3098065 # number of WritebackDirty hits 2046system.cpu1.l2cache.WritebackDirty_hits::total 3098065 # number of WritebackDirty hits 2047system.cpu1.l2cache.WritebackClean_hits::writebacks 11055157 # number of WritebackClean hits 2048system.cpu1.l2cache.WritebackClean_hits::total 11055157 # number of WritebackClean hits 2049system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits 2050system.cpu1.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 2051system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2052system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2053system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815552 # number of ReadExReq hits 2054system.cpu1.l2cache.ReadExReq_hits::total 815552 # number of ReadExReq hits 2055system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8406399 # number of ReadCleanReq hits 2056system.cpu1.l2cache.ReadCleanReq_hits::total 8406399 # number of ReadCleanReq hits 2057system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2722472 # number of ReadSharedReq hits 2058system.cpu1.l2cache.ReadSharedReq_hits::total 2722472 # number of ReadSharedReq hits 2059system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 157346 # number of InvalidateReq hits 2060system.cpu1.l2cache.InvalidateReq_hits::total 157346 # number of InvalidateReq hits 2061system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 506555 # number of demand (read+write) hits 2062system.cpu1.l2cache.demand_hits::cpu1.itb.walker 152150 # number of demand (read+write) hits 2063system.cpu1.l2cache.demand_hits::cpu1.inst 8406399 # number of demand (read+write) hits 2064system.cpu1.l2cache.demand_hits::cpu1.data 3538024 # number of demand (read+write) hits 2065system.cpu1.l2cache.demand_hits::total 12603128 # number of demand (read+write) hits 2066system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 506555 # number of overall hits 2067system.cpu1.l2cache.overall_hits::cpu1.itb.walker 152150 # number of overall hits 2068system.cpu1.l2cache.overall_hits::cpu1.inst 8406399 # number of overall hits 2069system.cpu1.l2cache.overall_hits::cpu1.data 3538024 # number of overall hits 2070system.cpu1.l2cache.overall_hits::total 12603128 # number of overall hits 2071system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20442 # number of ReadReq misses 2072system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9977 # number of ReadReq misses 2073system.cpu1.l2cache.ReadReq_misses::total 30419 # number of ReadReq misses 2074system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2075system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2076system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 219088 # number of UpgradeReq misses 2077system.cpu1.l2cache.UpgradeReq_misses::total 219088 # number of UpgradeReq misses 2078system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194583 # number of SCUpgradeReq misses 2079system.cpu1.l2cache.SCUpgradeReq_misses::total 194583 # number of SCUpgradeReq misses 2080system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2081system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2082system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241398 # number of ReadExReq misses 2083system.cpu1.l2cache.ReadExReq_misses::total 241398 # number of ReadExReq misses 2084system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700129 # number of ReadCleanReq misses 2085system.cpu1.l2cache.ReadCleanReq_misses::total 700129 # number of ReadCleanReq misses 2086system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 948287 # number of ReadSharedReq misses 2087system.cpu1.l2cache.ReadSharedReq_misses::total 948287 # number of ReadSharedReq misses 2088system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 259232 # number of InvalidateReq misses 2089system.cpu1.l2cache.InvalidateReq_misses::total 259232 # number of InvalidateReq misses 2090system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20442 # number of demand (read+write) misses 2091system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9977 # number of demand (read+write) misses 2092system.cpu1.l2cache.demand_misses::cpu1.inst 700129 # number of demand (read+write) misses 2093system.cpu1.l2cache.demand_misses::cpu1.data 1189685 # number of demand (read+write) misses 2094system.cpu1.l2cache.demand_misses::total 1920233 # number of demand (read+write) misses 2095system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20442 # number of overall misses 2096system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9977 # number of overall misses 2097system.cpu1.l2cache.overall_misses::cpu1.inst 700129 # number of overall misses 2098system.cpu1.l2cache.overall_misses::cpu1.data 1189685 # number of overall misses 2099system.cpu1.l2cache.overall_misses::total 1920233 # number of overall misses 2100system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 617018000 # number of ReadReq miss cycles 2101system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 362407000 # number of ReadReq miss cycles 2102system.cpu1.l2cache.ReadReq_miss_latency::total 979425000 # number of ReadReq miss cycles 2103system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 937065000 # number of UpgradeReq miss cycles 2104system.cpu1.l2cache.UpgradeReq_miss_latency::total 937065000 # number of UpgradeReq miss cycles 2105system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273754000 # number of SCUpgradeReq miss cycles 2106system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273754000 # number of SCUpgradeReq miss cycles 2107system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1804499 # number of SCUpgradeFailReq miss cycles 2108system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1804499 # number of SCUpgradeFailReq miss cycles 2109system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10806413996 # number of ReadExReq miss cycles 2110system.cpu1.l2cache.ReadExReq_miss_latency::total 10806413996 # number of ReadExReq miss cycles 2111system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24362152500 # number of ReadCleanReq miss cycles 2112system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24362152500 # number of ReadCleanReq miss cycles 2113system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33291553995 # number of ReadSharedReq miss cycles 2114system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33291553995 # number of ReadSharedReq miss cycles 2115system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 509000 # number of InvalidateReq miss cycles 2116system.cpu1.l2cache.InvalidateReq_miss_latency::total 509000 # number of InvalidateReq miss cycles 2117system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 617018000 # number of demand (read+write) miss cycles 2118system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 362407000 # number of demand (read+write) miss cycles 2119system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24362152500 # number of demand (read+write) miss cycles 2120system.cpu1.l2cache.demand_miss_latency::cpu1.data 44097967991 # number of demand (read+write) miss cycles 2121system.cpu1.l2cache.demand_miss_latency::total 69439545491 # number of demand (read+write) miss cycles 2122system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 617018000 # number of overall miss cycles 2123system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 362407000 # number of overall miss cycles 2124system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24362152500 # number of overall miss cycles 2125system.cpu1.l2cache.overall_miss_latency::cpu1.data 44097967991 # number of overall miss cycles 2126system.cpu1.l2cache.overall_miss_latency::total 69439545491 # number of overall miss cycles 2127system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 526997 # number of ReadReq accesses(hits+misses) 2128system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 162127 # number of ReadReq accesses(hits+misses) 2129system.cpu1.l2cache.ReadReq_accesses::total 689124 # number of ReadReq accesses(hits+misses) 2130system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3098065 # number of WritebackDirty accesses(hits+misses) 2131system.cpu1.l2cache.WritebackDirty_accesses::total 3098065 # number of WritebackDirty accesses(hits+misses) 2132system.cpu1.l2cache.WritebackClean_accesses::writebacks 11055158 # number of WritebackClean accesses(hits+misses) 2133system.cpu1.l2cache.WritebackClean_accesses::total 11055158 # number of WritebackClean accesses(hits+misses) 2134system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219089 # number of UpgradeReq accesses(hits+misses) 2135system.cpu1.l2cache.UpgradeReq_accesses::total 219089 # number of UpgradeReq accesses(hits+misses) 2136system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194584 # number of SCUpgradeReq accesses(hits+misses) 2137system.cpu1.l2cache.SCUpgradeReq_accesses::total 194584 # number of SCUpgradeReq accesses(hits+misses) 2138system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2139system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2140system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1056950 # number of ReadExReq accesses(hits+misses) 2141system.cpu1.l2cache.ReadExReq_accesses::total 1056950 # number of ReadExReq accesses(hits+misses) 2142system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9106528 # number of ReadCleanReq accesses(hits+misses) 2143system.cpu1.l2cache.ReadCleanReq_accesses::total 9106528 # number of ReadCleanReq accesses(hits+misses) 2144system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3670759 # number of ReadSharedReq accesses(hits+misses) 2145system.cpu1.l2cache.ReadSharedReq_accesses::total 3670759 # number of ReadSharedReq accesses(hits+misses) 2146system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416578 # number of InvalidateReq accesses(hits+misses) 2147system.cpu1.l2cache.InvalidateReq_accesses::total 416578 # number of InvalidateReq accesses(hits+misses) 2148system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 526997 # number of demand (read+write) accesses 2149system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 162127 # number of demand (read+write) accesses 2150system.cpu1.l2cache.demand_accesses::cpu1.inst 9106528 # number of demand (read+write) accesses 2151system.cpu1.l2cache.demand_accesses::cpu1.data 4727709 # number of demand (read+write) accesses 2152system.cpu1.l2cache.demand_accesses::total 14523361 # number of demand (read+write) accesses 2153system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 526997 # number of overall (read+write) accesses 2154system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 162127 # number of overall (read+write) accesses 2155system.cpu1.l2cache.overall_accesses::cpu1.inst 9106528 # number of overall (read+write) accesses 2156system.cpu1.l2cache.overall_accesses::cpu1.data 4727709 # number of overall (read+write) accesses 2157system.cpu1.l2cache.overall_accesses::total 14523361 # number of overall (read+write) accesses 2158system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for ReadReq accesses 2159system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061538 # miss rate for ReadReq accesses 2160system.cpu1.l2cache.ReadReq_miss_rate::total 0.044142 # miss rate for ReadReq accesses 2161system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2162system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2163system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for UpgradeReq accesses 2164system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999995 # miss rate for UpgradeReq accesses 2165system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses 2166system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 2167system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2168system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2169system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228391 # miss rate for ReadExReq accesses 2170system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228391 # miss rate for ReadExReq accesses 2171system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076882 # miss rate for ReadCleanReq accesses 2172system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076882 # miss rate for ReadCleanReq accesses 2173system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258335 # miss rate for ReadSharedReq accesses 2174system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258335 # miss rate for ReadSharedReq accesses 2175system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622289 # miss rate for InvalidateReq accesses 2176system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622289 # miss rate for InvalidateReq accesses 2177system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for demand accesses 2178system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061538 # miss rate for demand accesses 2179system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076882 # miss rate for demand accesses 2180system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251641 # miss rate for demand accesses 2181system.cpu1.l2cache.demand_miss_rate::total 0.132217 # miss rate for demand accesses 2182system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for overall accesses 2183system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061538 # miss rate for overall accesses 2184system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076882 # miss rate for overall accesses 2185system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251641 # miss rate for overall accesses 2186system.cpu1.l2cache.overall_miss_rate::total 0.132217 # miss rate for overall accesses 2187system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average ReadReq miss latency 2188system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36324.245765 # average ReadReq miss latency 2189system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32197.804004 # average ReadReq miss latency 2190system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4277.116958 # average UpgradeReq miss latency 2191system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4277.116958 # average UpgradeReq miss latency 2192system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1406.875215 # average SCUpgradeReq miss latency 2193system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1406.875215 # average SCUpgradeReq miss latency 2194system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 601499.666667 # average SCUpgradeFailReq miss latency 2195system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601499.666667 # average SCUpgradeFailReq miss latency 2196system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44765.963247 # average ReadExReq miss latency 2197system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44765.963247 # average ReadExReq miss latency 2198system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34796.662472 # average ReadCleanReq miss latency 2199system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34796.662472 # average ReadCleanReq miss latency 2200system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35107.044592 # average ReadSharedReq miss latency 2201system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35107.044592 # average ReadSharedReq miss latency 2202system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1.963492 # average InvalidateReq miss latency 2203system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1.963492 # average InvalidateReq miss latency 2204system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency 2205system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency 2206system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency 2207system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency 2208system.cpu1.l2cache.demand_avg_miss_latency::total 36162.041529 # average overall miss latency 2209system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency 2210system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency 2211system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency 2212system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency 2213system.cpu1.l2cache.overall_avg_miss_latency::total 36162.041529 # average overall miss latency 2214system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2215system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2216system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2217system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2218system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2219system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2220system.cpu1.l2cache.unused_prefetches 43998 # number of HardPF blocks evicted w/o reference 2221system.cpu1.l2cache.writebacks::writebacks 1082545 # number of writebacks 2222system.cpu1.l2cache.writebacks::total 1082545 # number of writebacks 2223system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 17 # number of ReadReq MSHR hits 2224system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 90 # number of ReadReq MSHR hits 2225system.cpu1.l2cache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 2226system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6036 # number of ReadExReq MSHR hits 2227system.cpu1.l2cache.ReadExReq_mshr_hits::total 6036 # number of ReadExReq MSHR hits 2228system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2229system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 2230system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 724 # number of ReadSharedReq MSHR hits 2231system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 724 # number of ReadSharedReq MSHR hits 2232system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits 2233system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 2234system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 17 # number of demand (read+write) MSHR hits 2235system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 90 # number of demand (read+write) MSHR hits 2236system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2237system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6760 # number of demand (read+write) MSHR hits 2238system.cpu1.l2cache.demand_mshr_hits::total 6871 # number of demand (read+write) MSHR hits 2239system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 17 # number of overall MSHR hits 2240system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 90 # number of overall MSHR hits 2241system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2242system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6760 # number of overall MSHR hits 2243system.cpu1.l2cache.overall_mshr_hits::total 6871 # number of overall MSHR hits 2244system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20425 # number of ReadReq MSHR misses 2245system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9887 # number of ReadReq MSHR misses 2246system.cpu1.l2cache.ReadReq_mshr_misses::total 30312 # number of ReadReq MSHR misses 2247system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2248system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2249system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of HardPFReq MSHR misses 2250system.cpu1.l2cache.HardPFReq_mshr_misses::total 721434 # number of HardPFReq MSHR misses 2251system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 219088 # number of UpgradeReq MSHR misses 2252system.cpu1.l2cache.UpgradeReq_mshr_misses::total 219088 # number of UpgradeReq MSHR misses 2253system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194583 # number of SCUpgradeReq MSHR misses 2254system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194583 # number of SCUpgradeReq MSHR misses 2255system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2256system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2257system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235362 # number of ReadExReq MSHR misses 2258system.cpu1.l2cache.ReadExReq_mshr_misses::total 235362 # number of ReadExReq MSHR misses 2259system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700125 # number of ReadCleanReq MSHR misses 2260system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700125 # number of ReadCleanReq MSHR misses 2261system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 947563 # number of ReadSharedReq MSHR misses 2262system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 947563 # number of ReadSharedReq MSHR misses 2263system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 259229 # number of InvalidateReq MSHR misses 2264system.cpu1.l2cache.InvalidateReq_mshr_misses::total 259229 # number of InvalidateReq MSHR misses 2265system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20425 # number of demand (read+write) MSHR misses 2266system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9887 # number of demand (read+write) MSHR misses 2267system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700125 # number of demand (read+write) MSHR misses 2268system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1182925 # number of demand (read+write) MSHR misses 2269system.cpu1.l2cache.demand_mshr_misses::total 1913362 # number of demand (read+write) MSHR misses 2270system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20425 # number of overall MSHR misses 2271system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9887 # number of overall MSHR misses 2272system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700125 # number of overall MSHR misses 2273system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1182925 # number of overall MSHR misses 2274system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of overall MSHR misses 2275system.cpu1.l2cache.overall_mshr_misses::total 2634796 # number of overall MSHR misses 2276system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 2277system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable 2278system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7063 # number of ReadReq MSHR uncacheable 2279system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 2280system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable 2281system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 2282system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses 2283system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14250 # number of overall MSHR uncacheable misses 2284system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of ReadReq MSHR miss cycles 2285system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 301606000 # number of ReadReq MSHR miss cycles 2286system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 795670000 # number of ReadReq MSHR miss cycles 2287system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of HardPFReq MSHR miss cycles 2288system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29780460685 # number of HardPFReq MSHR miss cycles 2289system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4150846499 # number of UpgradeReq MSHR miss cycles 2290system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4150846499 # number of UpgradeReq MSHR miss cycles 2291system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2983943996 # number of SCUpgradeReq MSHR miss cycles 2292system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2983943996 # number of SCUpgradeReq MSHR miss cycles 2293system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1522499 # number of SCUpgradeFailReq MSHR miss cycles 2294system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1522499 # number of SCUpgradeFailReq MSHR miss cycles 2295system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8542642996 # number of ReadExReq MSHR miss cycles 2296system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8542642996 # number of ReadExReq MSHR miss cycles 2297system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20161321500 # number of ReadCleanReq MSHR miss cycles 2298system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20161321500 # number of ReadCleanReq MSHR miss cycles 2299system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27488554995 # number of ReadSharedReq MSHR miss cycles 2300system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27488554995 # number of ReadSharedReq MSHR miss cycles 2301system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6032275000 # number of InvalidateReq MSHR miss cycles 2302system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6032275000 # number of InvalidateReq MSHR miss cycles 2303system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of demand (read+write) MSHR miss cycles 2304system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 301606000 # number of demand (read+write) MSHR miss cycles 2305system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20161321500 # number of demand (read+write) MSHR miss cycles 2306system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36031197991 # number of demand (read+write) MSHR miss cycles 2307system.cpu1.l2cache.demand_mshr_miss_latency::total 56988189491 # number of demand (read+write) MSHR miss cycles 2308system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of overall MSHR miss cycles 2309system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 301606000 # number of overall MSHR miss cycles 2310system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20161321500 # number of overall MSHR miss cycles 2311system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36031197991 # number of overall MSHR miss cycles 2312system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of overall MSHR miss cycles 2313system.cpu1.l2cache.overall_mshr_miss_latency::total 86768650176 # number of overall MSHR miss cycles 2314system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8842500 # number of ReadReq MSHR uncacheable cycles 2315system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 826904500 # number of ReadReq MSHR uncacheable cycles 2316system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 835747000 # number of ReadReq MSHR uncacheable cycles 2317system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8842500 # number of overall MSHR uncacheable cycles 2318system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 826904500 # number of overall MSHR uncacheable cycles 2319system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 835747000 # number of overall MSHR uncacheable cycles 2320system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for ReadReq accesses 2321system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for ReadReq accesses 2322system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043986 # mshr miss rate for ReadReq accesses 2323system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2324system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2325system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2326system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2327system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for UpgradeReq accesses 2328system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for UpgradeReq accesses 2329system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 2330system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 2331system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2332system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2333system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222680 # mshr miss rate for ReadExReq accesses 2334system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222680 # mshr miss rate for ReadExReq accesses 2335system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for ReadCleanReq accesses 2336system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076882 # mshr miss rate for ReadCleanReq accesses 2337system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258138 # mshr miss rate for ReadSharedReq accesses 2338system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258138 # mshr miss rate for ReadSharedReq accesses 2339system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.622282 # mshr miss rate for InvalidateReq accesses 2340system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.622282 # mshr miss rate for InvalidateReq accesses 2341system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for demand accesses 2342system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for demand accesses 2343system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for demand accesses 2344system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for demand accesses 2345system.cpu1.l2cache.demand_mshr_miss_rate::total 0.131744 # mshr miss rate for demand accesses 2346system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for overall accesses 2347system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for overall accesses 2348system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for overall accesses 2349system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for overall accesses 2350system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2351system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181418 # mshr miss rate for overall accesses 2352system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average ReadReq mshr miss latency 2353system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average ReadReq mshr miss latency 2354system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195 # average ReadReq mshr miss latency 2355system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average HardPFReq mshr miss latency 2356system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876 # average HardPFReq mshr miss latency 2357system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968 # average UpgradeReq mshr miss latency 2358system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968 # average UpgradeReq mshr miss latency 2359system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361 # average SCUpgradeReq mshr miss latency 2360system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361 # average SCUpgradeReq mshr miss latency 2361system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667 # average SCUpgradeFailReq mshr miss latency 2362system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667 # average SCUpgradeFailReq mshr miss latency 2363system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406 # average ReadExReq mshr miss latency 2364system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406 # average ReadExReq mshr miss latency 2365system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average ReadCleanReq mshr miss latency 2366system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581 # average ReadCleanReq mshr miss latency 2367system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661 # average ReadSharedReq mshr miss latency 2368system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661 # average ReadSharedReq mshr miss latency 2369system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377 # average InvalidateReq mshr miss latency 2370system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377 # average InvalidateReq mshr miss latency 2371system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency 2372system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency 2373system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency 2374system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency 2375system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781 # average overall mshr miss latency 2376system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency 2377system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency 2378system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency 2379system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency 2380system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average overall mshr miss latency 2381system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565 # average overall mshr miss latency 2382system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average ReadReq mshr uncacheable latency 2383system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548 # average ReadReq mshr uncacheable latency 2384system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240 # average ReadReq mshr uncacheable latency 2385system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average overall mshr uncacheable latency 2386system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220 # average overall mshr uncacheable latency 2387system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281 # average overall mshr uncacheable latency 2388system.cpu1.toL2Bus.snoop_filter.tot_requests 29139456 # Total number of requests made to the snoop filter. 2389system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14890637 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2390system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1736 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2391system.cpu1.toL2Bus.snoop_filter.tot_snoops 592017 # Total number of snoops made to the snoop filter. 2392system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 591980 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2393system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 37 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2394system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2395system.cpu1.toL2Bus.trans_dist::ReadReq 780515 # Transaction distribution 2396system.cpu1.toL2Bus.trans_dist::ReadResp 13649954 # Transaction distribution 2397system.cpu1.toL2Bus.trans_dist::WriteReq 7187 # Transaction distribution 2398system.cpu1.toL2Bus.trans_dist::WriteResp 7187 # Transaction distribution 2399system.cpu1.toL2Bus.trans_dist::WritebackDirty 4195318 # Transaction distribution 2400system.cpu1.toL2Bus.trans_dist::WritebackClean 11056894 # Transaction distribution 2401system.cpu1.toL2Bus.trans_dist::CleanEvict 1429217 # Transaction distribution 2402system.cpu1.toL2Bus.trans_dist::HardPFReq 912059 # Transaction distribution 2403system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2404system.cpu1.toL2Bus.trans_dist::UpgradeReq 423433 # Transaction distribution 2405system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346671 # Transaction distribution 2406system.cpu1.toL2Bus.trans_dist::UpgradeResp 478761 # Transaction distribution 2407system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 2408system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 2409system.cpu1.toL2Bus.trans_dist::ReadExReq 1089502 # Transaction distribution 2410system.cpu1.toL2Bus.trans_dist::ReadExResp 1063784 # Transaction distribution 2411system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9106528 # Transaction distribution 2412system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4703864 # Transaction distribution 2413system.cpu1.toL2Bus.trans_dist::InvalidateReq 480825 # Transaction distribution 2414system.cpu1.toL2Bus.trans_dist::InvalidateResp 417736 # Transaction distribution 2415system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27319260 # Packet count per connected master and slave (bytes) 2416system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16358508 # Packet count per connected master and slave (bytes) 2417system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 344119 # Packet count per connected master and slave (bytes) 2418system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1118457 # Packet count per connected master and slave (bytes) 2419system.cpu1.toL2Bus.pkt_count::total 45140344 # Packet count per connected master and slave (bytes) 2420system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1165608768 # Cumulative packet size per connected master and slave (bytes) 2421system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 632082996 # Cumulative packet size per connected master and slave (bytes) 2422system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1297016 # Cumulative packet size per connected master and slave (bytes) 2423system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4215976 # Cumulative packet size per connected master and slave (bytes) 2424system.cpu1.toL2Bus.pkt_size::total 1803204756 # Cumulative packet size per connected master and slave (bytes) 2425system.cpu1.toL2Bus.snoops 5174570 # Total snoops (count) 2426system.cpu1.toL2Bus.snoopTraffic 77236160 # Total snoop traffic (bytes) 2427system.cpu1.toL2Bus.snoop_fanout::samples 20377107 # Request fanout histogram 2428system.cpu1.toL2Bus.snoop_fanout::mean 0.044844 # Request fanout histogram 2429system.cpu1.toL2Bus.snoop_fanout::stdev 0.206971 # Request fanout histogram 2430system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2431system.cpu1.toL2Bus.snoop_fanout::0 19463345 95.52% 95.52% # Request fanout histogram 2432system.cpu1.toL2Bus.snoop_fanout::1 913725 4.48% 100.00% # Request fanout histogram 2433system.cpu1.toL2Bus.snoop_fanout::2 37 0.00% 100.00% # Request fanout histogram 2434system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2435system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2436system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2437system.cpu1.toL2Bus.snoop_fanout::total 20377107 # Request fanout histogram 2438system.cpu1.toL2Bus.reqLayer0.occupancy 28962136490 # Layer occupancy (ticks) 2439system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2440system.cpu1.toL2Bus.snoopLayer0.occupancy 181919759 # Layer occupancy (ticks) 2441system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2442system.cpu1.toL2Bus.respLayer0.occupancy 13662646557 # Layer occupancy (ticks) 2443system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2444system.cpu1.toL2Bus.respLayer1.occupancy 7521057995 # Layer occupancy (ticks) 2445system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2446system.cpu1.toL2Bus.respLayer2.occupancy 182080323 # Layer occupancy (ticks) 2447system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2448system.cpu1.toL2Bus.respLayer3.occupancy 591562794 # Layer occupancy (ticks) 2449system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2450system.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2451system.iobus.trans_dist::ReadReq 40336 # Transaction distribution 2452system.iobus.trans_dist::ReadResp 40336 # Transaction distribution 2453system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 2454system.iobus.trans_dist::WriteResp 136645 # Transaction distribution 2455system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47799 # Packet count per connected master and slave (bytes) 2456system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2457system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2458system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2459system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2460system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2461system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2462system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2463system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2464system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2465system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2466system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 2467system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2468system.iobus.pkt_count_system.bridge.master::total 122681 # Packet count per connected master and slave (bytes) 2469system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) 2470system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) 2471system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2472system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2473system.iobus.pkt_count::total 353963 # Packet count per connected master and slave (bytes) 2474system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) 2475system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2476system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2477system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2478system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2479system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2480system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2481system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2482system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2483system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2484system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2485system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 2486system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2487system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) 2488system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) 2489system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) 2490system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2491system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2492system.iobus.pkt_size::total 7496722 # Cumulative packet size per connected master and slave (bytes) 2493system.iobus.reqLayer0.occupancy 42736003 # Layer occupancy (ticks) 2494system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2495system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 2496system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2497system.iobus.reqLayer2.occupancy 316501 # Layer occupancy (ticks) 2498system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2499system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 2500system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2501system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 2502system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2503system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 2504system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2505system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 2506system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2507system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 2508system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2509system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 2510system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2511system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) 2512system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2513system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 2514system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2515system.iobus.reqLayer23.occupancy 25813003 # Layer occupancy (ticks) 2516system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2517system.iobus.reqLayer24.occupancy 34441500 # Layer occupancy (ticks) 2518system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2519system.iobus.reqLayer25.occupancy 569849738 # Layer occupancy (ticks) 2520system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2521system.iobus.respLayer0.occupancy 92766000 # Layer occupancy (ticks) 2522system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2523system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) 2524system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2525system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2526system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2527system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2528system.iocache.tags.replacements 115581 # number of replacements 2529system.iocache.tags.tagsinuse 11.283387 # Cycle average of tags in use 2530system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2531system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. 2532system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2533system.iocache.tags.warmup_cycle 9167357489000 # Cycle when the warmup percentage was hit. 2534system.iocache.tags.occ_blocks::realview.ethernet 3.841167 # Average occupied blocks per requestor 2535system.iocache.tags.occ_blocks::realview.ide 7.442220 # Average occupied blocks per requestor 2536system.iocache.tags.occ_percent::realview.ethernet 0.240073 # Average percentage of cache occupancy 2537system.iocache.tags.occ_percent::realview.ide 0.465139 # Average percentage of cache occupancy 2538system.iocache.tags.occ_percent::total 0.705212 # Average percentage of cache occupancy 2539system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2540system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2541system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2542system.iocache.tags.tag_accesses 1040766 # Number of tag accesses 2543system.iocache.tags.data_accesses 1040766 # Number of data accesses 2544system.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2545system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2546system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses 2547system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses 2548system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2549system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2550system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2551system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2552system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2553system.iocache.demand_misses::realview.ide 115601 # number of demand (read+write) misses 2554system.iocache.demand_misses::total 115641 # number of demand (read+write) misses 2555system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2556system.iocache.overall_misses::realview.ide 115601 # number of overall misses 2557system.iocache.overall_misses::total 115641 # number of overall misses 2558system.iocache.ReadReq_miss_latency::realview.ethernet 5212500 # number of ReadReq miss cycles 2559system.iocache.ReadReq_miss_latency::realview.ide 1870801980 # number of ReadReq miss cycles 2560system.iocache.ReadReq_miss_latency::total 1876014480 # number of ReadReq miss cycles 2561system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2562system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2563system.iocache.WriteLineReq_miss_latency::realview.ide 13212782258 # number of WriteLineReq miss cycles 2564system.iocache.WriteLineReq_miss_latency::total 13212782258 # number of WriteLineReq miss cycles 2565system.iocache.demand_miss_latency::realview.ethernet 5581500 # number of demand (read+write) miss cycles 2566system.iocache.demand_miss_latency::realview.ide 15083584238 # number of demand (read+write) miss cycles 2567system.iocache.demand_miss_latency::total 15089165738 # number of demand (read+write) miss cycles 2568system.iocache.overall_miss_latency::realview.ethernet 5581500 # number of overall miss cycles 2569system.iocache.overall_miss_latency::realview.ide 15083584238 # number of overall miss cycles 2570system.iocache.overall_miss_latency::total 15089165738 # number of overall miss cycles 2571system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2572system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) 2573system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) 2574system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2575system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2576system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2577system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2578system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2579system.iocache.demand_accesses::realview.ide 115601 # number of demand (read+write) accesses 2580system.iocache.demand_accesses::total 115641 # number of demand (read+write) accesses 2581system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2582system.iocache.overall_accesses::realview.ide 115601 # number of overall (read+write) accesses 2583system.iocache.overall_accesses::total 115641 # number of overall (read+write) accesses 2584system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2585system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2586system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2587system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2588system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2589system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2590system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2591system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2592system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2593system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2594system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2595system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2596system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2597system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378 # average ReadReq miss latency 2598system.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009 # average ReadReq miss latency 2599system.iocache.ReadReq_avg_miss_latency::total 210551.569024 # average ReadReq miss latency 2600system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2601system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2602system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445 # average WriteLineReq miss latency 2603system.iocache.WriteLineReq_avg_miss_latency::total 123798.649445 # average WriteLineReq miss latency 2604system.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency 2605system.iocache.demand_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency 2606system.iocache.demand_avg_miss_latency::total 130482.836866 # average overall miss latency 2607system.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency 2608system.iocache.overall_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency 2609system.iocache.overall_avg_miss_latency::total 130482.836866 # average overall miss latency 2610system.iocache.blocked_cycles::no_mshrs 43615 # number of cycles access was blocked 2611system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2612system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 2613system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2614system.iocache.avg_blocked_cycles::no_mshrs 12.338048 # average number of cycles each access was blocked 2615system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2616system.iocache.writebacks::writebacks 106693 # number of writebacks 2617system.iocache.writebacks::total 106693 # number of writebacks 2618system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2619system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses 2620system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses 2621system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2622system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2623system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2624system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2625system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2626system.iocache.demand_mshr_misses::realview.ide 115601 # number of demand (read+write) MSHR misses 2627system.iocache.demand_mshr_misses::total 115641 # number of demand (read+write) MSHR misses 2628system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2629system.iocache.overall_mshr_misses::realview.ide 115601 # number of overall MSHR misses 2630system.iocache.overall_mshr_misses::total 115641 # number of overall MSHR misses 2631system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3362500 # number of ReadReq MSHR miss cycles 2632system.iocache.ReadReq_mshr_miss_latency::realview.ide 1427151980 # number of ReadReq MSHR miss cycles 2633system.iocache.ReadReq_mshr_miss_latency::total 1430514480 # number of ReadReq MSHR miss cycles 2634system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2635system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2636system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7870696448 # number of WriteLineReq MSHR miss cycles 2637system.iocache.WriteLineReq_mshr_miss_latency::total 7870696448 # number of WriteLineReq MSHR miss cycles 2638system.iocache.demand_mshr_miss_latency::realview.ethernet 3581500 # number of demand (read+write) MSHR miss cycles 2639system.iocache.demand_mshr_miss_latency::realview.ide 9297848428 # number of demand (read+write) MSHR miss cycles 2640system.iocache.demand_mshr_miss_latency::total 9301429928 # number of demand (read+write) MSHR miss cycles 2641system.iocache.overall_mshr_miss_latency::realview.ethernet 3581500 # number of overall MSHR miss cycles 2642system.iocache.overall_mshr_miss_latency::realview.ide 9297848428 # number of overall MSHR miss cycles 2643system.iocache.overall_mshr_miss_latency::total 9301429928 # number of overall MSHR miss cycles 2644system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2645system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2646system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2647system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2648system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2649system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2650system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2651system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2652system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2653system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2654system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2655system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2656system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2657system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378 # average ReadReq mshr miss latency 2658system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160842.103009 # average ReadReq mshr miss latency 2659system.iocache.ReadReq_avg_mshr_miss_latency::total 160551.569024 # average ReadReq mshr miss latency 2660system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2661system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2662system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73745.375609 # average WriteLineReq mshr miss latency 2663system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73745.375609 # average WriteLineReq mshr miss latency 2664system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency 2665system.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency 2666system.iocache.demand_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency 2667system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency 2668system.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency 2669system.iocache.overall_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency 2670system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2671system.l2c.tags.replacements 1414426 # number of replacements 2672system.l2c.tags.tagsinuse 65137.583571 # Cycle average of tags in use 2673system.l2c.tags.total_refs 6994560 # Total number of references to valid blocks. 2674system.l2c.tags.sampled_refs 1476169 # Sample count of references to valid blocks. 2675system.l2c.tags.avg_refs 4.738319 # Average number of references to valid blocks. 2676system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. 2677system.l2c.tags.occ_blocks::writebacks 11569.884492 # Average occupied blocks per requestor 2678system.l2c.tags.occ_blocks::cpu0.dtb.walker 195.527132 # Average occupied blocks per requestor 2679system.l2c.tags.occ_blocks::cpu0.itb.walker 189.575172 # Average occupied blocks per requestor 2680system.l2c.tags.occ_blocks::cpu0.inst 5571.537349 # Average occupied blocks per requestor 2681system.l2c.tags.occ_blocks::cpu0.data 16752.169298 # Average occupied blocks per requestor 2682system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274 # Average occupied blocks per requestor 2683system.l2c.tags.occ_blocks::cpu1.dtb.walker 243.722413 # Average occupied blocks per requestor 2684system.l2c.tags.occ_blocks::cpu1.itb.walker 247.067471 # Average occupied blocks per requestor 2685system.l2c.tags.occ_blocks::cpu1.inst 3668.697792 # Average occupied blocks per requestor 2686system.l2c.tags.occ_blocks::cpu1.data 7415.172357 # Average occupied blocks per requestor 2687system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9157.755820 # Average occupied blocks per requestor 2688system.l2c.tags.occ_percent::writebacks 0.176542 # Average percentage of cache occupancy 2689system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002984 # Average percentage of cache occupancy 2690system.l2c.tags.occ_percent::cpu0.itb.walker 0.002893 # Average percentage of cache occupancy 2691system.l2c.tags.occ_percent::cpu0.inst 0.085015 # Average percentage of cache occupancy 2692system.l2c.tags.occ_percent::cpu0.data 0.255618 # Average percentage of cache occupancy 2693system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.154518 # Average percentage of cache occupancy 2694system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003719 # Average percentage of cache occupancy 2695system.l2c.tags.occ_percent::cpu1.itb.walker 0.003770 # Average percentage of cache occupancy 2696system.l2c.tags.occ_percent::cpu1.inst 0.055980 # Average percentage of cache occupancy 2697system.l2c.tags.occ_percent::cpu1.data 0.113147 # Average percentage of cache occupancy 2698system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.139736 # Average percentage of cache occupancy 2699system.l2c.tags.occ_percent::total 0.993921 # Average percentage of cache occupancy 2700system.l2c.tags.occ_task_id_blocks::1022 10627 # Occupied blocks per task id 2701system.l2c.tags.occ_task_id_blocks::1023 250 # Occupied blocks per task id 2702system.l2c.tags.occ_task_id_blocks::1024 50866 # Occupied blocks per task id 2703system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2704system.l2c.tags.age_task_id_blocks_1022::2 125 # Occupied blocks per task id 2705system.l2c.tags.age_task_id_blocks_1022::3 764 # Occupied blocks per task id 2706system.l2c.tags.age_task_id_blocks_1022::4 9737 # Occupied blocks per task id 2707system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id 2708system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 2709system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 2710system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 2711system.l2c.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id 2712system.l2c.tags.age_task_id_blocks_1024::3 4265 # Occupied blocks per task id 2713system.l2c.tags.age_task_id_blocks_1024::4 44783 # Occupied blocks per task id 2714system.l2c.tags.occ_task_id_percent::1022 0.162155 # Percentage of cache occupancy per task id 2715system.l2c.tags.occ_task_id_percent::1023 0.003815 # Percentage of cache occupancy per task id 2716system.l2c.tags.occ_task_id_percent::1024 0.776154 # Percentage of cache occupancy per task id 2717system.l2c.tags.tag_accesses 76792424 # Number of tag accesses 2718system.l2c.tags.data_accesses 76792424 # Number of data accesses 2719system.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 2720system.l2c.WritebackDirty_hits::writebacks 2702608 # number of WritebackDirty hits 2721system.l2c.WritebackDirty_hits::total 2702608 # number of WritebackDirty hits 2722system.l2c.UpgradeReq_hits::cpu0.data 192434 # number of UpgradeReq hits 2723system.l2c.UpgradeReq_hits::cpu1.data 150964 # number of UpgradeReq hits 2724system.l2c.UpgradeReq_hits::total 343398 # number of UpgradeReq hits 2725system.l2c.SCUpgradeReq_hits::cpu0.data 50257 # number of SCUpgradeReq hits 2726system.l2c.SCUpgradeReq_hits::cpu1.data 52778 # number of SCUpgradeReq hits 2727system.l2c.SCUpgradeReq_hits::total 103035 # number of SCUpgradeReq hits 2728system.l2c.ReadExReq_hits::cpu0.data 55782 # number of ReadExReq hits 2729system.l2c.ReadExReq_hits::cpu1.data 52105 # number of ReadExReq hits 2730system.l2c.ReadExReq_hits::total 107887 # number of ReadExReq hits 2731system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13231 # number of ReadSharedReq hits 2732system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5451 # number of ReadSharedReq hits 2733system.l2c.ReadSharedReq_hits::cpu0.inst 616225 # number of ReadSharedReq hits 2734system.l2c.ReadSharedReq_hits::cpu0.data 581799 # number of ReadSharedReq hits 2735system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 304510 # number of ReadSharedReq hits 2736system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10640 # number of ReadSharedReq hits 2737system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4481 # number of ReadSharedReq hits 2738system.l2c.ReadSharedReq_hits::cpu1.inst 647147 # number of ReadSharedReq hits 2739system.l2c.ReadSharedReq_hits::cpu1.data 570987 # number of ReadSharedReq hits 2740system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 311044 # number of ReadSharedReq hits 2741system.l2c.ReadSharedReq_hits::total 3065515 # number of ReadSharedReq hits 2742system.l2c.InvalidateReq_hits::cpu0.data 124497 # number of InvalidateReq hits 2743system.l2c.InvalidateReq_hits::cpu1.data 122676 # number of InvalidateReq hits 2744system.l2c.InvalidateReq_hits::total 247173 # number of InvalidateReq hits 2745system.l2c.demand_hits::cpu0.dtb.walker 13231 # number of demand (read+write) hits 2746system.l2c.demand_hits::cpu0.itb.walker 5451 # number of demand (read+write) hits 2747system.l2c.demand_hits::cpu0.inst 616225 # number of demand (read+write) hits 2748system.l2c.demand_hits::cpu0.data 637581 # number of demand (read+write) hits 2749system.l2c.demand_hits::cpu0.l2cache.prefetcher 304510 # number of demand (read+write) hits 2750system.l2c.demand_hits::cpu1.dtb.walker 10640 # number of demand (read+write) hits 2751system.l2c.demand_hits::cpu1.itb.walker 4481 # number of demand (read+write) hits 2752system.l2c.demand_hits::cpu1.inst 647147 # number of demand (read+write) hits 2753system.l2c.demand_hits::cpu1.data 623092 # number of demand (read+write) hits 2754system.l2c.demand_hits::cpu1.l2cache.prefetcher 311044 # number of demand (read+write) hits 2755system.l2c.demand_hits::total 3173402 # number of demand (read+write) hits 2756system.l2c.overall_hits::cpu0.dtb.walker 13231 # number of overall hits 2757system.l2c.overall_hits::cpu0.itb.walker 5451 # number of overall hits 2758system.l2c.overall_hits::cpu0.inst 616225 # number of overall hits 2759system.l2c.overall_hits::cpu0.data 637581 # number of overall hits 2760system.l2c.overall_hits::cpu0.l2cache.prefetcher 304510 # number of overall hits 2761system.l2c.overall_hits::cpu1.dtb.walker 10640 # number of overall hits 2762system.l2c.overall_hits::cpu1.itb.walker 4481 # number of overall hits 2763system.l2c.overall_hits::cpu1.inst 647147 # number of overall hits 2764system.l2c.overall_hits::cpu1.data 623092 # number of overall hits 2765system.l2c.overall_hits::cpu1.l2cache.prefetcher 311044 # number of overall hits 2766system.l2c.overall_hits::total 3173402 # number of overall hits 2767system.l2c.UpgradeReq_misses::cpu0.data 19140 # number of UpgradeReq misses 2768system.l2c.UpgradeReq_misses::cpu1.data 25859 # number of UpgradeReq misses 2769system.l2c.UpgradeReq_misses::total 44999 # number of UpgradeReq misses 2770system.l2c.SCUpgradeReq_misses::cpu0.data 523 # number of SCUpgradeReq misses 2771system.l2c.SCUpgradeReq_misses::cpu1.data 682 # number of SCUpgradeReq misses 2772system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses 2773system.l2c.ReadExReq_misses::cpu0.data 81279 # number of ReadExReq misses 2774system.l2c.ReadExReq_misses::cpu1.data 45582 # number of ReadExReq misses 2775system.l2c.ReadExReq_misses::total 126861 # number of ReadExReq misses 2776system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq misses 2777system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1999 # number of ReadSharedReq misses 2778system.l2c.ReadSharedReq_misses::cpu0.inst 72224 # number of ReadSharedReq misses 2779system.l2c.ReadSharedReq_misses::cpu0.data 145719 # number of ReadSharedReq misses 2780system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq misses 2781system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq misses 2782system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1517 # number of ReadSharedReq misses 2783system.l2c.ReadSharedReq_misses::cpu1.inst 52978 # number of ReadSharedReq misses 2784system.l2c.ReadSharedReq_misses::cpu1.data 99810 # number of ReadSharedReq misses 2785system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq misses 2786system.l2c.ReadSharedReq_misses::total 787476 # number of ReadSharedReq misses 2787system.l2c.InvalidateReq_misses::cpu0.data 432248 # number of InvalidateReq misses 2788system.l2c.InvalidateReq_misses::cpu1.data 85316 # number of InvalidateReq misses 2789system.l2c.InvalidateReq_misses::total 517564 # number of InvalidateReq misses 2790system.l2c.demand_misses::cpu0.dtb.walker 2187 # number of demand (read+write) misses 2791system.l2c.demand_misses::cpu0.itb.walker 1999 # number of demand (read+write) misses 2792system.l2c.demand_misses::cpu0.inst 72224 # number of demand (read+write) misses 2793system.l2c.demand_misses::cpu0.data 226998 # number of demand (read+write) misses 2794system.l2c.demand_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) misses 2795system.l2c.demand_misses::cpu1.dtb.walker 1644 # number of demand (read+write) misses 2796system.l2c.demand_misses::cpu1.itb.walker 1517 # number of demand (read+write) misses 2797system.l2c.demand_misses::cpu1.inst 52978 # number of demand (read+write) misses 2798system.l2c.demand_misses::cpu1.data 145392 # number of demand (read+write) misses 2799system.l2c.demand_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) misses 2800system.l2c.demand_misses::total 914337 # number of demand (read+write) misses 2801system.l2c.overall_misses::cpu0.dtb.walker 2187 # number of overall misses 2802system.l2c.overall_misses::cpu0.itb.walker 1999 # number of overall misses 2803system.l2c.overall_misses::cpu0.inst 72224 # number of overall misses 2804system.l2c.overall_misses::cpu0.data 226998 # number of overall misses 2805system.l2c.overall_misses::cpu0.l2cache.prefetcher 234962 # number of overall misses 2806system.l2c.overall_misses::cpu1.dtb.walker 1644 # number of overall misses 2807system.l2c.overall_misses::cpu1.itb.walker 1517 # number of overall misses 2808system.l2c.overall_misses::cpu1.inst 52978 # number of overall misses 2809system.l2c.overall_misses::cpu1.data 145392 # number of overall misses 2810system.l2c.overall_misses::cpu1.l2cache.prefetcher 174436 # number of overall misses 2811system.l2c.overall_misses::total 914337 # number of overall misses 2812system.l2c.UpgradeReq_miss_latency::cpu0.data 159938500 # number of UpgradeReq miss cycles 2813system.l2c.UpgradeReq_miss_latency::cpu1.data 143600000 # number of UpgradeReq miss cycles 2814system.l2c.UpgradeReq_miss_latency::total 303538500 # number of UpgradeReq miss cycles 2815system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6591000 # number of SCUpgradeReq miss cycles 2816system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8923000 # number of SCUpgradeReq miss cycles 2817system.l2c.SCUpgradeReq_miss_latency::total 15514000 # number of SCUpgradeReq miss cycles 2818system.l2c.ReadExReq_miss_latency::cpu0.data 8642428000 # number of ReadExReq miss cycles 2819system.l2c.ReadExReq_miss_latency::cpu1.data 4940577000 # number of ReadExReq miss cycles 2820system.l2c.ReadExReq_miss_latency::total 13583005000 # number of ReadExReq miss cycles 2821system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 231505500 # number of ReadSharedReq miss cycles 2822system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 211185500 # number of ReadSharedReq miss cycles 2823system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7798644500 # number of ReadSharedReq miss cycles 2824system.l2c.ReadSharedReq_miss_latency::cpu0.data 15829133000 # number of ReadSharedReq miss cycles 2825system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of ReadSharedReq miss cycles 2826system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 165185000 # number of ReadSharedReq miss cycles 2827system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 157137500 # number of ReadSharedReq miss cycles 2828system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6014742000 # number of ReadSharedReq miss cycles 2829system.l2c.ReadSharedReq_miss_latency::cpu1.data 11671652500 # number of ReadSharedReq miss cycles 2830system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of ReadSharedReq miss cycles 2831system.l2c.ReadSharedReq_miss_latency::total 99292357724 # number of ReadSharedReq miss cycles 2832system.l2c.demand_miss_latency::cpu0.dtb.walker 231505500 # number of demand (read+write) miss cycles 2833system.l2c.demand_miss_latency::cpu0.itb.walker 211185500 # number of demand (read+write) miss cycles 2834system.l2c.demand_miss_latency::cpu0.inst 7798644500 # number of demand (read+write) miss cycles 2835system.l2c.demand_miss_latency::cpu0.data 24471561000 # number of demand (read+write) miss cycles 2836system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of demand (read+write) miss cycles 2837system.l2c.demand_miss_latency::cpu1.dtb.walker 165185000 # number of demand (read+write) miss cycles 2838system.l2c.demand_miss_latency::cpu1.itb.walker 157137500 # number of demand (read+write) miss cycles 2839system.l2c.demand_miss_latency::cpu1.inst 6014742000 # number of demand (read+write) miss cycles 2840system.l2c.demand_miss_latency::cpu1.data 16612229500 # number of demand (read+write) miss cycles 2841system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of demand (read+write) miss cycles 2842system.l2c.demand_miss_latency::total 112875362724 # number of demand (read+write) miss cycles 2843system.l2c.overall_miss_latency::cpu0.dtb.walker 231505500 # number of overall miss cycles 2844system.l2c.overall_miss_latency::cpu0.itb.walker 211185500 # number of overall miss cycles 2845system.l2c.overall_miss_latency::cpu0.inst 7798644500 # number of overall miss cycles 2846system.l2c.overall_miss_latency::cpu0.data 24471561000 # number of overall miss cycles 2847system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of overall miss cycles 2848system.l2c.overall_miss_latency::cpu1.dtb.walker 165185000 # number of overall miss cycles 2849system.l2c.overall_miss_latency::cpu1.itb.walker 157137500 # number of overall miss cycles 2850system.l2c.overall_miss_latency::cpu1.inst 6014742000 # number of overall miss cycles 2851system.l2c.overall_miss_latency::cpu1.data 16612229500 # number of overall miss cycles 2852system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of overall miss cycles 2853system.l2c.overall_miss_latency::total 112875362724 # number of overall miss cycles 2854system.l2c.WritebackDirty_accesses::writebacks 2702608 # number of WritebackDirty accesses(hits+misses) 2855system.l2c.WritebackDirty_accesses::total 2702608 # number of WritebackDirty accesses(hits+misses) 2856system.l2c.UpgradeReq_accesses::cpu0.data 211574 # number of UpgradeReq accesses(hits+misses) 2857system.l2c.UpgradeReq_accesses::cpu1.data 176823 # number of UpgradeReq accesses(hits+misses) 2858system.l2c.UpgradeReq_accesses::total 388397 # number of UpgradeReq accesses(hits+misses) 2859system.l2c.SCUpgradeReq_accesses::cpu0.data 50780 # number of SCUpgradeReq accesses(hits+misses) 2860system.l2c.SCUpgradeReq_accesses::cpu1.data 53460 # number of SCUpgradeReq accesses(hits+misses) 2861system.l2c.SCUpgradeReq_accesses::total 104240 # number of SCUpgradeReq accesses(hits+misses) 2862system.l2c.ReadExReq_accesses::cpu0.data 137061 # number of ReadExReq accesses(hits+misses) 2863system.l2c.ReadExReq_accesses::cpu1.data 97687 # number of ReadExReq accesses(hits+misses) 2864system.l2c.ReadExReq_accesses::total 234748 # number of ReadExReq accesses(hits+misses) 2865system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15418 # number of ReadSharedReq accesses(hits+misses) 2866system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7450 # number of ReadSharedReq accesses(hits+misses) 2867system.l2c.ReadSharedReq_accesses::cpu0.inst 688449 # number of ReadSharedReq accesses(hits+misses) 2868system.l2c.ReadSharedReq_accesses::cpu0.data 727518 # number of ReadSharedReq accesses(hits+misses) 2869system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 539472 # number of ReadSharedReq accesses(hits+misses) 2870system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12284 # number of ReadSharedReq accesses(hits+misses) 2871system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5998 # number of ReadSharedReq accesses(hits+misses) 2872system.l2c.ReadSharedReq_accesses::cpu1.inst 700125 # number of ReadSharedReq accesses(hits+misses) 2873system.l2c.ReadSharedReq_accesses::cpu1.data 670797 # number of ReadSharedReq accesses(hits+misses) 2874system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 485480 # number of ReadSharedReq accesses(hits+misses) 2875system.l2c.ReadSharedReq_accesses::total 3852991 # number of ReadSharedReq accesses(hits+misses) 2876system.l2c.InvalidateReq_accesses::cpu0.data 556745 # number of InvalidateReq accesses(hits+misses) 2877system.l2c.InvalidateReq_accesses::cpu1.data 207992 # number of InvalidateReq accesses(hits+misses) 2878system.l2c.InvalidateReq_accesses::total 764737 # number of InvalidateReq accesses(hits+misses) 2879system.l2c.demand_accesses::cpu0.dtb.walker 15418 # number of demand (read+write) accesses 2880system.l2c.demand_accesses::cpu0.itb.walker 7450 # number of demand (read+write) accesses 2881system.l2c.demand_accesses::cpu0.inst 688449 # number of demand (read+write) accesses 2882system.l2c.demand_accesses::cpu0.data 864579 # number of demand (read+write) accesses 2883system.l2c.demand_accesses::cpu0.l2cache.prefetcher 539472 # number of demand (read+write) accesses 2884system.l2c.demand_accesses::cpu1.dtb.walker 12284 # number of demand (read+write) accesses 2885system.l2c.demand_accesses::cpu1.itb.walker 5998 # number of demand (read+write) accesses 2886system.l2c.demand_accesses::cpu1.inst 700125 # number of demand (read+write) accesses 2887system.l2c.demand_accesses::cpu1.data 768484 # number of demand (read+write) accesses 2888system.l2c.demand_accesses::cpu1.l2cache.prefetcher 485480 # number of demand (read+write) accesses 2889system.l2c.demand_accesses::total 4087739 # number of demand (read+write) accesses 2890system.l2c.overall_accesses::cpu0.dtb.walker 15418 # number of overall (read+write) accesses 2891system.l2c.overall_accesses::cpu0.itb.walker 7450 # number of overall (read+write) accesses 2892system.l2c.overall_accesses::cpu0.inst 688449 # number of overall (read+write) accesses 2893system.l2c.overall_accesses::cpu0.data 864579 # number of overall (read+write) accesses 2894system.l2c.overall_accesses::cpu0.l2cache.prefetcher 539472 # number of overall (read+write) accesses 2895system.l2c.overall_accesses::cpu1.dtb.walker 12284 # number of overall (read+write) accesses 2896system.l2c.overall_accesses::cpu1.itb.walker 5998 # number of overall (read+write) accesses 2897system.l2c.overall_accesses::cpu1.inst 700125 # number of overall (read+write) accesses 2898system.l2c.overall_accesses::cpu1.data 768484 # number of overall (read+write) accesses 2899system.l2c.overall_accesses::cpu1.l2cache.prefetcher 485480 # number of overall (read+write) accesses 2900system.l2c.overall_accesses::total 4087739 # number of overall (read+write) accesses 2901system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090465 # miss rate for UpgradeReq accesses 2902system.l2c.UpgradeReq_miss_rate::cpu1.data 0.146242 # miss rate for UpgradeReq accesses 2903system.l2c.UpgradeReq_miss_rate::total 0.115858 # miss rate for UpgradeReq accesses 2904system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010299 # miss rate for SCUpgradeReq accesses 2905system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012757 # miss rate for SCUpgradeReq accesses 2906system.l2c.SCUpgradeReq_miss_rate::total 0.011560 # miss rate for SCUpgradeReq accesses 2907system.l2c.ReadExReq_miss_rate::cpu0.data 0.593013 # miss rate for ReadExReq accesses 2908system.l2c.ReadExReq_miss_rate::cpu1.data 0.466613 # miss rate for ReadExReq accesses 2909system.l2c.ReadExReq_miss_rate::total 0.540414 # miss rate for ReadExReq accesses 2910system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for ReadSharedReq accesses 2911system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.268322 # miss rate for ReadSharedReq accesses 2912system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104908 # miss rate for ReadSharedReq accesses 2913system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200296 # miss rate for ReadSharedReq accesses 2914system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for ReadSharedReq accesses 2915system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for ReadSharedReq accesses 2916system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.252918 # miss rate for ReadSharedReq accesses 2917system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses 2918system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.148793 # miss rate for ReadSharedReq accesses 2919system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for ReadSharedReq accesses 2920system.l2c.ReadSharedReq_miss_rate::total 0.204380 # miss rate for ReadSharedReq accesses 2921system.l2c.InvalidateReq_miss_rate::cpu0.data 0.776384 # miss rate for InvalidateReq accesses 2922system.l2c.InvalidateReq_miss_rate::cpu1.data 0.410189 # miss rate for InvalidateReq accesses 2923system.l2c.InvalidateReq_miss_rate::total 0.676787 # miss rate for InvalidateReq accesses 2924system.l2c.demand_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for demand accesses 2925system.l2c.demand_miss_rate::cpu0.itb.walker 0.268322 # miss rate for demand accesses 2926system.l2c.demand_miss_rate::cpu0.inst 0.104908 # miss rate for demand accesses 2927system.l2c.demand_miss_rate::cpu0.data 0.262553 # miss rate for demand accesses 2928system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for demand accesses 2929system.l2c.demand_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for demand accesses 2930system.l2c.demand_miss_rate::cpu1.itb.walker 0.252918 # miss rate for demand accesses 2931system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses 2932system.l2c.demand_miss_rate::cpu1.data 0.189193 # miss rate for demand accesses 2933system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for demand accesses 2934system.l2c.demand_miss_rate::total 0.223678 # miss rate for demand accesses 2935system.l2c.overall_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for overall accesses 2936system.l2c.overall_miss_rate::cpu0.itb.walker 0.268322 # miss rate for overall accesses 2937system.l2c.overall_miss_rate::cpu0.inst 0.104908 # miss rate for overall accesses 2938system.l2c.overall_miss_rate::cpu0.data 0.262553 # miss rate for overall accesses 2939system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for overall accesses 2940system.l2c.overall_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for overall accesses 2941system.l2c.overall_miss_rate::cpu1.itb.walker 0.252918 # miss rate for overall accesses 2942system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses 2943system.l2c.overall_miss_rate::cpu1.data 0.189193 # miss rate for overall accesses 2944system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for overall accesses 2945system.l2c.overall_miss_rate::total 0.223678 # miss rate for overall accesses 2946system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 8356.243469 # average UpgradeReq miss latency 2947system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5553.192312 # average UpgradeReq miss latency 2948system.l2c.UpgradeReq_avg_miss_latency::total 6745.449899 # average UpgradeReq miss latency 2949system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12602.294455 # average SCUpgradeReq miss latency 2950system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13083.577713 # average SCUpgradeReq miss latency 2951system.l2c.SCUpgradeReq_avg_miss_latency::total 12874.688797 # average SCUpgradeReq miss latency 2952system.l2c.ReadExReq_avg_miss_latency::cpu0.data 106330.392844 # average ReadExReq miss latency 2953system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108388.771884 # average ReadExReq miss latency 2954system.l2c.ReadExReq_avg_miss_latency::total 107069.982106 # average ReadExReq miss latency 2955system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average ReadSharedReq miss latency 2956system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105645.572786 # average ReadSharedReq miss latency 2957system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107978.573604 # average ReadSharedReq miss latency 2958system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 108627.790473 # average ReadSharedReq miss latency 2959system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average ReadSharedReq miss latency 2960system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average ReadSharedReq miss latency 2961system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103584.377060 # average ReadSharedReq miss latency 2962system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113532.824946 # average ReadSharedReq miss latency 2963system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116938.708546 # average ReadSharedReq miss latency 2964system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average ReadSharedReq miss latency 2965system.l2c.ReadSharedReq_avg_miss_latency::total 126089.376342 # average ReadSharedReq miss latency 2966system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency 2967system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency 2968system.l2c.demand_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency 2969system.l2c.demand_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency 2970system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency 2971system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency 2972system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency 2973system.l2c.demand_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency 2974system.l2c.demand_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency 2975system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency 2976system.l2c.demand_avg_miss_latency::total 123450.503178 # average overall miss latency 2977system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency 2978system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency 2979system.l2c.overall_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency 2980system.l2c.overall_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency 2981system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency 2982system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency 2983system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency 2984system.l2c.overall_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency 2985system.l2c.overall_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency 2986system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency 2987system.l2c.overall_avg_miss_latency::total 123450.503178 # average overall miss latency 2988system.l2c.blocked_cycles::no_mshrs 159 # number of cycles access was blocked 2989system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2990system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked 2991system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2992system.l2c.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked 2993system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2994system.l2c.writebacks::writebacks 1064634 # number of writebacks 2995system.l2c.writebacks::total 1064634 # number of writebacks 2996system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 107 # number of ReadSharedReq MSHR hits 2997system.l2c.ReadSharedReq_mshr_hits::cpu0.data 22 # number of ReadSharedReq MSHR hits 2998system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 137 # number of ReadSharedReq MSHR hits 2999system.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits 3000system.l2c.ReadSharedReq_mshr_hits::total 289 # number of ReadSharedReq MSHR hits 3001system.l2c.demand_mshr_hits::cpu0.inst 107 # number of demand (read+write) MSHR hits 3002system.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits 3003system.l2c.demand_mshr_hits::cpu1.inst 137 # number of demand (read+write) MSHR hits 3004system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits 3005system.l2c.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits 3006system.l2c.overall_mshr_hits::cpu0.inst 107 # number of overall MSHR hits 3007system.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits 3008system.l2c.overall_mshr_hits::cpu1.inst 137 # number of overall MSHR hits 3009system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits 3010system.l2c.overall_mshr_hits::total 289 # number of overall MSHR hits 3011system.l2c.CleanEvict_mshr_misses::writebacks 58693 # number of CleanEvict MSHR misses 3012system.l2c.CleanEvict_mshr_misses::total 58693 # number of CleanEvict MSHR misses 3013system.l2c.UpgradeReq_mshr_misses::cpu0.data 19140 # number of UpgradeReq MSHR misses 3014system.l2c.UpgradeReq_mshr_misses::cpu1.data 25859 # number of UpgradeReq MSHR misses 3015system.l2c.UpgradeReq_mshr_misses::total 44999 # number of UpgradeReq MSHR misses 3016system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 523 # number of SCUpgradeReq MSHR misses 3017system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 682 # number of SCUpgradeReq MSHR misses 3018system.l2c.SCUpgradeReq_mshr_misses::total 1205 # number of SCUpgradeReq MSHR misses 3019system.l2c.ReadExReq_mshr_misses::cpu0.data 81279 # number of ReadExReq MSHR misses 3020system.l2c.ReadExReq_mshr_misses::cpu1.data 45582 # number of ReadExReq MSHR misses 3021system.l2c.ReadExReq_mshr_misses::total 126861 # number of ReadExReq MSHR misses 3022system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq MSHR misses 3023system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1999 # number of ReadSharedReq MSHR misses 3024system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72117 # number of ReadSharedReq MSHR misses 3025system.l2c.ReadSharedReq_mshr_misses::cpu0.data 145697 # number of ReadSharedReq MSHR misses 3026system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq MSHR misses 3027system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq MSHR misses 3028system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1517 # number of ReadSharedReq MSHR misses 3029system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 52841 # number of ReadSharedReq MSHR misses 3030system.l2c.ReadSharedReq_mshr_misses::cpu1.data 99787 # number of ReadSharedReq MSHR misses 3031system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq MSHR misses 3032system.l2c.ReadSharedReq_mshr_misses::total 787187 # number of ReadSharedReq MSHR misses 3033system.l2c.InvalidateReq_mshr_misses::cpu0.data 432248 # number of InvalidateReq MSHR misses 3034system.l2c.InvalidateReq_mshr_misses::cpu1.data 85316 # number of InvalidateReq MSHR misses 3035system.l2c.InvalidateReq_mshr_misses::total 517564 # number of InvalidateReq MSHR misses 3036system.l2c.demand_mshr_misses::cpu0.dtb.walker 2187 # number of demand (read+write) MSHR misses 3037system.l2c.demand_mshr_misses::cpu0.itb.walker 1999 # number of demand (read+write) MSHR misses 3038system.l2c.demand_mshr_misses::cpu0.inst 72117 # number of demand (read+write) MSHR misses 3039system.l2c.demand_mshr_misses::cpu0.data 226976 # number of demand (read+write) MSHR misses 3040system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) MSHR misses 3041system.l2c.demand_mshr_misses::cpu1.dtb.walker 1644 # number of demand (read+write) MSHR misses 3042system.l2c.demand_mshr_misses::cpu1.itb.walker 1517 # number of demand (read+write) MSHR misses 3043system.l2c.demand_mshr_misses::cpu1.inst 52841 # number of demand (read+write) MSHR misses 3044system.l2c.demand_mshr_misses::cpu1.data 145369 # number of demand (read+write) MSHR misses 3045system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) MSHR misses 3046system.l2c.demand_mshr_misses::total 914048 # number of demand (read+write) MSHR misses 3047system.l2c.overall_mshr_misses::cpu0.dtb.walker 2187 # number of overall MSHR misses 3048system.l2c.overall_mshr_misses::cpu0.itb.walker 1999 # number of overall MSHR misses 3049system.l2c.overall_mshr_misses::cpu0.inst 72117 # number of overall MSHR misses 3050system.l2c.overall_mshr_misses::cpu0.data 226976 # number of overall MSHR misses 3051system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of overall MSHR misses 3052system.l2c.overall_mshr_misses::cpu1.dtb.walker 1644 # number of overall MSHR misses 3053system.l2c.overall_mshr_misses::cpu1.itb.walker 1517 # number of overall MSHR misses 3054system.l2c.overall_mshr_misses::cpu1.inst 52841 # number of overall MSHR misses 3055system.l2c.overall_mshr_misses::cpu1.data 145369 # number of overall MSHR misses 3056system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of overall MSHR misses 3057system.l2c.overall_mshr_misses::total 914048 # number of overall MSHR misses 3058system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable 3059system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable 3060system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 3061system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6966 # number of ReadReq MSHR uncacheable 3062system.l2c.ReadReq_mshr_uncacheable::total 90895 # number of ReadReq MSHR uncacheable 3063system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable 3064system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable 3065system.l2c.WriteReq_mshr_uncacheable::total 38388 # number of WriteReq MSHR uncacheable 3066system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses 3067system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses 3068system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 3069system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14153 # number of overall MSHR uncacheable misses 3070system.l2c.overall_mshr_uncacheable_misses::total 129283 # number of overall MSHR uncacheable misses 3071system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 389704500 # number of UpgradeReq MSHR miss cycles 3072system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 525466000 # number of UpgradeReq MSHR miss cycles 3073system.l2c.UpgradeReq_mshr_miss_latency::total 915170500 # number of UpgradeReq MSHR miss cycles 3074system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12566500 # number of SCUpgradeReq MSHR miss cycles 3075system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16471000 # number of SCUpgradeReq MSHR miss cycles 3076system.l2c.SCUpgradeReq_mshr_miss_latency::total 29037500 # number of SCUpgradeReq MSHR miss cycles 3077system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7829611555 # number of ReadExReq MSHR miss cycles 3078system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4484731054 # number of ReadExReq MSHR miss cycles 3079system.l2c.ReadExReq_mshr_miss_latency::total 12314342609 # number of ReadExReq MSHR miss cycles 3080system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of ReadSharedReq MSHR miss cycles 3081system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 191194502 # number of ReadSharedReq MSHR miss cycles 3082system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7068927036 # number of ReadSharedReq MSHR miss cycles 3083system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14369749705 # number of ReadSharedReq MSHR miss cycles 3084system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of ReadSharedReq MSHR miss cycles 3085system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of ReadSharedReq MSHR miss cycles 3086system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141966502 # number of ReadSharedReq MSHR miss cycles 3087system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5474322057 # number of ReadSharedReq MSHR miss cycles 3088system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10671015209 # number of ReadSharedReq MSHR miss cycles 3089system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of ReadSharedReq MSHR miss cycles 3090system.l2c.ReadSharedReq_mshr_miss_latency::total 91394456852 # number of ReadSharedReq MSHR miss cycles 3091system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8929441001 # number of InvalidateReq MSHR miss cycles 3092system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1642247000 # number of InvalidateReq MSHR miss cycles 3093system.l2c.InvalidateReq_mshr_miss_latency::total 10571688001 # number of InvalidateReq MSHR miss cycles 3094system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of demand (read+write) MSHR miss cycles 3095system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 191194502 # number of demand (read+write) MSHR miss cycles 3096system.l2c.demand_mshr_miss_latency::cpu0.inst 7068927036 # number of demand (read+write) MSHR miss cycles 3097system.l2c.demand_mshr_miss_latency::cpu0.data 22199361260 # number of demand (read+write) MSHR miss cycles 3098system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of demand (read+write) MSHR miss cycles 3099system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of demand (read+write) MSHR miss cycles 3100system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141966502 # number of demand (read+write) MSHR miss cycles 3101system.l2c.demand_mshr_miss_latency::cpu1.inst 5474322057 # number of demand (read+write) MSHR miss cycles 3102system.l2c.demand_mshr_miss_latency::cpu1.data 15155746263 # number of demand (read+write) MSHR miss cycles 3103system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of demand (read+write) MSHR miss cycles 3104system.l2c.demand_mshr_miss_latency::total 103708799461 # number of demand (read+write) MSHR miss cycles 3105system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of overall MSHR miss cycles 3106system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 191194502 # number of overall MSHR miss cycles 3107system.l2c.overall_mshr_miss_latency::cpu0.inst 7068927036 # number of overall MSHR miss cycles 3108system.l2c.overall_mshr_miss_latency::cpu0.data 22199361260 # number of overall MSHR miss cycles 3109system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of overall MSHR miss cycles 3110system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of overall MSHR miss cycles 3111system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141966502 # number of overall MSHR miss cycles 3112system.l2c.overall_mshr_miss_latency::cpu1.inst 5474322057 # number of overall MSHR miss cycles 3113system.l2c.overall_mshr_miss_latency::cpu1.data 15155746263 # number of overall MSHR miss cycles 3114system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of overall MSHR miss cycles 3115system.l2c.overall_mshr_miss_latency::total 103708799461 # number of overall MSHR miss cycles 3116system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles 3117system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5267143505 # number of ReadReq MSHR uncacheable cycles 3118system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6847500 # number of ReadReq MSHR uncacheable cycles 3119system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 701418504 # number of ReadReq MSHR uncacheable cycles 3120system.l2c.ReadReq_mshr_uncacheable_latency::total 9620779009 # number of ReadReq MSHR uncacheable cycles 3121system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles 3122system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5267143505 # number of overall MSHR uncacheable cycles 3123system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6847500 # number of overall MSHR uncacheable cycles 3124system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701418504 # number of overall MSHR uncacheable cycles 3125system.l2c.overall_mshr_uncacheable_latency::total 9620779009 # number of overall MSHR uncacheable cycles 3126system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3127system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3128system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090465 # mshr miss rate for UpgradeReq accesses 3129system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.146242 # mshr miss rate for UpgradeReq accesses 3130system.l2c.UpgradeReq_mshr_miss_rate::total 0.115858 # mshr miss rate for UpgradeReq accesses 3131system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010299 # mshr miss rate for SCUpgradeReq accesses 3132system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012757 # mshr miss rate for SCUpgradeReq accesses 3133system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011560 # mshr miss rate for SCUpgradeReq accesses 3134system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593013 # mshr miss rate for ReadExReq accesses 3135system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466613 # mshr miss rate for ReadExReq accesses 3136system.l2c.ReadExReq_mshr_miss_rate::total 0.540414 # mshr miss rate for ReadExReq accesses 3137system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for ReadSharedReq accesses 3138system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for ReadSharedReq accesses 3139system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for ReadSharedReq accesses 3140system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200266 # mshr miss rate for ReadSharedReq accesses 3141system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for ReadSharedReq accesses 3142system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for ReadSharedReq accesses 3143system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for ReadSharedReq accesses 3144system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for ReadSharedReq accesses 3145system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.148759 # mshr miss rate for ReadSharedReq accesses 3146system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for ReadSharedReq accesses 3147system.l2c.ReadSharedReq_mshr_miss_rate::total 0.204305 # mshr miss rate for ReadSharedReq accesses 3148system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.776384 # mshr miss rate for InvalidateReq accesses 3149system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.410189 # mshr miss rate for InvalidateReq accesses 3150system.l2c.InvalidateReq_mshr_miss_rate::total 0.676787 # mshr miss rate for InvalidateReq accesses 3151system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for demand accesses 3152system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for demand accesses 3153system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for demand accesses 3154system.l2c.demand_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for demand accesses 3155system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for demand accesses 3156system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for demand accesses 3157system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for demand accesses 3158system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for demand accesses 3159system.l2c.demand_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for demand accesses 3160system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for demand accesses 3161system.l2c.demand_mshr_miss_rate::total 0.223607 # mshr miss rate for demand accesses 3162system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for overall accesses 3163system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for overall accesses 3164system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for overall accesses 3165system.l2c.overall_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for overall accesses 3166system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for overall accesses 3167system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for overall accesses 3168system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for overall accesses 3169system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for overall accesses 3170system.l2c.overall_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for overall accesses 3171system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for overall accesses 3172system.l2c.overall_mshr_miss_rate::total 0.223607 # mshr miss rate for overall accesses 3173system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20360.736677 # average UpgradeReq mshr miss latency 3174system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.430024 # average UpgradeReq mshr miss latency 3175system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20337.574168 # average UpgradeReq mshr miss latency 3176system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24027.724665 # average SCUpgradeReq mshr miss latency 3177system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24151.026393 # average SCUpgradeReq mshr miss latency 3178system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24097.510373 # average SCUpgradeReq mshr miss latency 3179system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 96330.067484 # average ReadExReq mshr miss latency 3180system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98388.202668 # average ReadExReq mshr miss latency 3181system.l2c.ReadExReq_avg_mshr_miss_latency::total 97069.569127 # average ReadExReq mshr miss latency 3182system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average ReadSharedReq mshr miss latency 3183system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average ReadSharedReq mshr miss latency 3184system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average ReadSharedReq mshr miss latency 3185system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 98627.629292 # average ReadSharedReq mshr miss latency 3186system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average ReadSharedReq mshr miss latency 3187system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average ReadSharedReq mshr miss latency 3188system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average ReadSharedReq mshr miss latency 3189system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average ReadSharedReq mshr miss latency 3190system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106937.929881 # average ReadSharedReq mshr miss latency 3191system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average ReadSharedReq mshr miss latency 3192system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116102.599321 # average ReadSharedReq mshr miss latency 3193system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20658.143013 # average InvalidateReq mshr miss latency 3194system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19248.991983 # average InvalidateReq mshr miss latency 3195system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20425.856514 # average InvalidateReq mshr miss latency 3196system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency 3197system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency 3198system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency 3199system.l2c.demand_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency 3200system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency 3201system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency 3202system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency 3203system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency 3204system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency 3205system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency 3206system.l2c.demand_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency 3207system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency 3208system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency 3209system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency 3210system.l2c.overall_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency 3211system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency 3212system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency 3213system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency 3214system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency 3215system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency 3216system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency 3217system.l2c.overall_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency 3218system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency 3219system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410 # average ReadReq mshr uncacheable latency 3220system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average ReadReq mshr uncacheable latency 3221system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485 # average ReadReq mshr uncacheable latency 3222system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070 # average ReadReq mshr uncacheable latency 3223system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency 3224system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268 # average overall mshr uncacheable latency 3225system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average overall mshr uncacheable latency 3226system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939 # average overall mshr uncacheable latency 3227system.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597 # average overall mshr uncacheable latency 3228system.membus.snoop_filter.tot_requests 3622014 # Total number of requests made to the snoop filter. 3229system.membus.snoop_filter.hit_single_requests 2135906 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3230system.membus.snoop_filter.hit_multi_requests 2993 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3231system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3232system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3233system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3234system.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3235system.membus.trans_dist::ReadReq 90895 # Transaction distribution 3236system.membus.trans_dist::ReadResp 886992 # Transaction distribution 3237system.membus.trans_dist::WriteReq 38388 # Transaction distribution 3238system.membus.trans_dist::WriteResp 38387 # Transaction distribution 3239system.membus.trans_dist::WritebackDirty 1171327 # Transaction distribution 3240system.membus.trans_dist::CleanEvict 257625 # Transaction distribution 3241system.membus.trans_dist::UpgradeReq 339183 # Transaction distribution 3242system.membus.trans_dist::SCUpgradeReq 279038 # Transaction distribution 3243system.membus.trans_dist::UpgradeResp 24 # Transaction distribution 3244system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3245system.membus.trans_dist::ReadExReq 141595 # Transaction distribution 3246system.membus.trans_dist::ReadExResp 126059 # Transaction distribution 3247system.membus.trans_dist::ReadSharedReq 796097 # Transaction distribution 3248system.membus.trans_dist::InvalidateReq 636810 # Transaction distribution 3249system.membus.trans_dist::InvalidateResp 29788 # Transaction distribution 3250system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122681 # Packet count per connected master and slave (bytes) 3251system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 3252system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25906 # Packet count per connected master and slave (bytes) 3253system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4412900 # Packet count per connected master and slave (bytes) 3254system.membus.pkt_count_system.l2c.mem_side::total 4561541 # Packet count per connected master and slave (bytes) 3255system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238275 # Packet count per connected master and slave (bytes) 3256system.membus.pkt_count_system.iocache.mem_side::total 238275 # Packet count per connected master and slave (bytes) 3257system.membus.pkt_count::total 4799816 # Packet count per connected master and slave (bytes) 3258system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) 3259system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 3260system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51812 # Cumulative packet size per connected master and slave (bytes) 3261system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129909760 # Cumulative packet size per connected master and slave (bytes) 3262system.membus.pkt_size_system.l2c.mem_side::total 130118772 # Cumulative packet size per connected master and slave (bytes) 3263system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279744 # Cumulative packet size per connected master and slave (bytes) 3264system.membus.pkt_size_system.iocache.mem_side::total 7279744 # Cumulative packet size per connected master and slave (bytes) 3265system.membus.pkt_size::total 137398516 # Cumulative packet size per connected master and slave (bytes) 3266system.membus.snoops 631660 # Total snoops (count) 3267system.membus.snoopTraffic 165184 # Total snoop traffic (bytes) 3268system.membus.snoop_fanout::samples 2322011 # Request fanout histogram 3269system.membus.snoop_fanout::mean 0.014128 # Request fanout histogram 3270system.membus.snoop_fanout::stdev 0.118018 # Request fanout histogram 3271system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3272system.membus.snoop_fanout::0 2289206 98.59% 98.59% # Request fanout histogram 3273system.membus.snoop_fanout::1 32805 1.41% 100.00% # Request fanout histogram 3274system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3275system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3276system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3277system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3278system.membus.snoop_fanout::total 2322011 # Request fanout histogram 3279system.membus.reqLayer0.occupancy 103411493 # Layer occupancy (ticks) 3280system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3281system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 3282system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3283system.membus.reqLayer2.occupancy 21687499 # Layer occupancy (ticks) 3284system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3285system.membus.reqLayer5.occupancy 8057234059 # Layer occupancy (ticks) 3286system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3287system.membus.respLayer2.occupancy 5202386097 # Layer occupancy (ticks) 3288system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3289system.membus.respLayer3.occupancy 79808698 # Layer occupancy (ticks) 3290system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3291system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3292system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3293system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3294system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3295system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3296system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3297system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3298system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3299system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3300system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3301system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3302system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3303system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3304system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3305system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3306system.realview.ethernet.txBytes 966 # Bytes Transmitted 3307system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3308system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3309system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3310system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3311system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3312system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3313system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3314system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3315system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3316system.realview.ethernet.totPackets 3 # Total Packets 3317system.realview.ethernet.totBytes 966 # Total Bytes 3318system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3319system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3320system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3321system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3322system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3323system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3324system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3325system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3326system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3327system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3328system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3329system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3330system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3331system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3332system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3333system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3334system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3335system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3336system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3337system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3338system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3339system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3340system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3341system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3342system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3343system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3344system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3345system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3346system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3347system.realview.ethernet.droppedPackets 0 # number of packets dropped 3348system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3349system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3350system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3351system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3352system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3353system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3354system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3355system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3356system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3357system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3358system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3359system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3360system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3361system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3362system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3363system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3364system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3365system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3366system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3367system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3368system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3369system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3370system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3371system.toL2Bus.snoop_filter.tot_requests 12161965 # Total number of requests made to the snoop filter. 3372system.toL2Bus.snoop_filter.hit_single_requests 6407928 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3373system.toL2Bus.snoop_filter.hit_multi_requests 2357892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3374system.toL2Bus.snoop_filter.tot_snoops 209457 # Total number of snoops made to the snoop filter. 3375system.toL2Bus.snoop_filter.hit_single_snoops 187271 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3376system.toL2Bus.snoop_filter.hit_multi_snoops 22186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3377system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states 3378system.toL2Bus.trans_dist::ReadReq 90897 # Transaction distribution 3379system.toL2Bus.trans_dist::ReadResp 4728170 # Transaction distribution 3380system.toL2Bus.trans_dist::WriteReq 38388 # Transaction distribution 3381system.toL2Bus.trans_dist::WriteResp 38387 # Transaction distribution 3382system.toL2Bus.trans_dist::WritebackDirty 3767242 # Transaction distribution 3383system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3384system.toL2Bus.trans_dist::CleanEvict 2958537 # Transaction distribution 3385system.toL2Bus.trans_dist::UpgradeReq 681779 # Transaction distribution 3386system.toL2Bus.trans_dist::SCUpgradeReq 382073 # Transaction distribution 3387system.toL2Bus.trans_dist::UpgradeResp 1063852 # Transaction distribution 3388system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution 3389system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 3390system.toL2Bus.trans_dist::ReadExReq 289918 # Transaction distribution 3391system.toL2Bus.trans_dist::ReadExResp 289918 # Transaction distribution 3392system.toL2Bus.trans_dist::ReadSharedReq 4637675 # Transaction distribution 3393system.toL2Bus.trans_dist::InvalidateReq 890912 # Transaction distribution 3394system.toL2Bus.trans_dist::InvalidateResp 871981 # Transaction distribution 3395system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9721848 # Packet count per connected master and slave (bytes) 3396system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8056306 # Packet count per connected master and slave (bytes) 3397system.toL2Bus.pkt_count::total 17778154 # Packet count per connected master and slave (bytes) 3398system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 242672912 # Cumulative packet size per connected master and slave (bytes) 3399system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 195596708 # Cumulative packet size per connected master and slave (bytes) 3400system.toL2Bus.pkt_size::total 438269620 # Cumulative packet size per connected master and slave (bytes) 3401system.toL2Bus.snoops 2964469 # Total snoops (count) 3402system.toL2Bus.snoopTraffic 121867728 # Total snoop traffic (bytes) 3403system.toL2Bus.snoop_fanout::samples 8426211 # Request fanout histogram 3404system.toL2Bus.snoop_fanout::mean 0.390204 # Request fanout histogram 3405system.toL2Bus.snoop_fanout::stdev 0.493164 # Request fanout histogram 3406system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3407system.toL2Bus.snoop_fanout::0 5160452 61.24% 61.24% # Request fanout histogram 3408system.toL2Bus.snoop_fanout::1 3243573 38.49% 99.74% # Request fanout histogram 3409system.toL2Bus.snoop_fanout::2 22186 0.26% 100.00% # Request fanout histogram 3410system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3411system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3412system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3413system.toL2Bus.snoop_fanout::total 8426211 # Request fanout histogram 3414system.toL2Bus.reqLayer0.occupancy 9265268057 # Layer occupancy (ticks) 3415system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3416system.toL2Bus.snoopLayer0.occupancy 8336972 # Layer occupancy (ticks) 3417system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3418system.toL2Bus.respLayer0.occupancy 4478456950 # Layer occupancy (ticks) 3419system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3420system.toL2Bus.respLayer1.occupancy 4027071928 # Layer occupancy (ticks) 3421system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3422 3423---------- End Simulation Statistics ---------- 3424