stats.txt revision 11606
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 47.276773 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 47276772827000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 47276772827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 146674 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 172507 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 7728246229 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 772984 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 6117.40 # Real time elapsed on the host 1211606Sandreas.sandberg@arm.comsim_insts 897262562 # Number of instructions simulated 1311606Sandreas.sandberg@arm.comsim_ops 1055295890 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 117376 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 90560 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.inst 7953664 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 13400200 # Number of bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 16005120 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 165760 # Number of bytes read from this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 157376 # Number of bytes read from this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 3942400 # Number of bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 13075216 # Number of bytes read from this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 14708224 # Number of bytes read from this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::realview.ide 454784 # Number of bytes read from this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 70070680 # Number of bytes read from this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 7953664 # Number of instructions bytes read from this memory 3011606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3942400 # Number of instructions bytes read from this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 11896064 # Number of instructions bytes read from this memory 3211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 81443392 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 81463976 # Number of bytes written to this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1834 # Number of read requests responded to by this memory 3711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1415 # Number of read requests responded to by this memory 3811606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.inst 124276 # Number of read requests responded to by this memory 3911606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 209391 # Number of read requests responded to by this memory 4011606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 250080 # Number of read requests responded to by this memory 4111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2590 # Number of read requests responded to by this memory 4211606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2459 # Number of read requests responded to by this memory 4311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 61600 # Number of read requests responded to by this memory 4411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 204313 # Number of read requests responded to by this memory 4511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 229816 # Number of read requests responded to by this memory 4611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::realview.ide 7106 # Number of read requests responded to by this memory 4711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 1094880 # Number of read requests responded to by this memory 4811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 1272553 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 1275127 # Number of write requests responded to by this memory 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2483 # Total read bandwidth from this memory (bytes/s) 5311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1916 # Total read bandwidth from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 168236 # Total read bandwidth from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 283442 # Total read bandwidth from this memory (bytes/s) 5611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 338541 # Total read bandwidth from this memory (bytes/s) 5711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3506 # Total read bandwidth from this memory (bytes/s) 5811606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3329 # Total read bandwidth from this memory (bytes/s) 5911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 83390 # Total read bandwidth from this memory (bytes/s) 6011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 276567 # Total read bandwidth from this memory (bytes/s) 6111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 311109 # Total read bandwidth from this memory (bytes/s) 6211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::realview.ide 9620 # Total read bandwidth from this memory (bytes/s) 6311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1482138 # Total read bandwidth from this memory (bytes/s) 6411606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 168236 # Instruction read bandwidth from this memory (bytes/s) 6511606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 83390 # Instruction read bandwidth from this memory (bytes/s) 6611606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 251626 # Instruction read bandwidth from this memory (bytes/s) 6711606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 1722694 # Write bandwidth from this memory (bytes/s) 6811606Sandreas.sandberg@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6910636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 1723129 # Write bandwidth from this memory (bytes/s) 7111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 1722694 # Total bandwidth to/from this memory (bytes/s) 7211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2483 # Total bandwidth to/from this memory (bytes/s) 7311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1916 # Total bandwidth to/from this memory (bytes/s) 7411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 168236 # Total bandwidth to/from this memory (bytes/s) 7511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 283877 # Total bandwidth to/from this memory (bytes/s) 7611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 338541 # Total bandwidth to/from this memory (bytes/s) 7711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3506 # Total bandwidth to/from this memory (bytes/s) 7811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3329 # Total bandwidth to/from this memory (bytes/s) 7911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 83390 # Total bandwidth to/from this memory (bytes/s) 8011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 276568 # Total bandwidth to/from this memory (bytes/s) 8111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 311109 # Total bandwidth to/from this memory (bytes/s) 8211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::realview.ide 9620 # Total bandwidth to/from this memory (bytes/s) 8311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 3205266 # Total bandwidth to/from this memory (bytes/s) 8411606Sandreas.sandberg@arm.comsystem.physmem.readReqs 1094880 # Number of read requests accepted 8511606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 1275127 # Number of write requests accepted 8611606Sandreas.sandberg@arm.comsystem.physmem.readBursts 1094880 # Number of DRAM read bursts, including those serviced by the write queue 8711606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 1275127 # Number of DRAM write bursts, including those merged in the write queue 8811606Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 70042240 # Total number of bytes read from DRAM 8911606Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 30080 # Total number of bytes read from write queue 9011606Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 81461504 # Total number of bytes written to DRAM 9111606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 70070680 # Total read bytes from the system interface side 9211606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 81463976 # Total written bytes from the system interface side 9311606Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 470 # Number of DRAM read bursts serviced by the write queue 9411606Sandreas.sandberg@arm.comsystem.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 60604 # Per bank write bursts 9711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 71691 # Per bank write bursts 9811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 59265 # Per bank write bursts 9911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 66946 # Per bank write bursts 10011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 67906 # Per bank write bursts 10111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 80109 # Per bank write bursts 10211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 61949 # Per bank write bursts 10311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 69447 # Per bank write bursts 10411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 60494 # Per bank write bursts 10511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 115448 # Per bank write bursts 10611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 56514 # Per bank write bursts 10711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 69665 # Per bank write bursts 10811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 63387 # Per bank write bursts 10911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 66346 # Per bank write bursts 11011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 64421 # Per bank write bursts 11111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 60218 # Per bank write bursts 11211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 77101 # Per bank write bursts 11311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 84577 # Per bank write bursts 11411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 74746 # Per bank write bursts 11511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 81276 # Per bank write bursts 11611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 79990 # Per bank write bursts 11711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 87328 # Per bank write bursts 11811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 77464 # Per bank write bursts 11911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 81707 # Per bank write bursts 12011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 78209 # Per bank write bursts 12111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 81569 # Per bank write bursts 12211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 73819 # Per bank write bursts 12311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 80687 # Per bank write bursts 12411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 78674 # Per bank write bursts 12511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 80970 # Per bank write bursts 12611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 77560 # Per bank write bursts 12711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 77159 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911606Sandreas.sandberg@arm.comsystem.physmem.numWrRetry 62 # Number of times write queue was full causing retry 13011606Sandreas.sandberg@arm.comsystem.physmem.totGap 47276770796500 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 1094850 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 1272553 # Write request sizes (log2) 14511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 725931 # What read queue length does an incoming req see 14611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 132585 # What read queue length does an incoming req see 14711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 49587 # What read queue length does an incoming req see 14811606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::3 38066 # What read queue length does an incoming req see 14911606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::4 32959 # What read queue length does an incoming req see 15011606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::5 30077 # What read queue length does an incoming req see 15111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::6 28140 # What read queue length does an incoming req see 15211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::7 24582 # What read queue length does an incoming req see 15311606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::8 22148 # What read queue length does an incoming req see 15411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::9 4123 # What read queue length does an incoming req see 15511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::10 1854 # What read queue length does an incoming req see 15611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::11 1222 # What read queue length does an incoming req see 15711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::12 970 # What read queue length does an incoming req see 15811606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see 15911606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::14 398 # What read queue length does an incoming req see 16011606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::15 328 # What read queue length does an incoming req see 16111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::16 280 # What read queue length does an incoming req see 16211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::17 226 # What read queue length does an incoming req see 16311606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see 16411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see 16511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 16611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 16711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 16811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 26459 # What write queue length does an incoming req see 19311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 34937 # What write queue length does an incoming req see 19411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 52906 # What write queue length does an incoming req see 19511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 61188 # What write queue length does an incoming req see 19611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 67814 # What write queue length does an incoming req see 19711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 70802 # What write queue length does an incoming req see 19811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 73289 # What write queue length does an incoming req see 19911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 75619 # What write queue length does an incoming req see 20011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 78304 # What write queue length does an incoming req see 20111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 78281 # What write queue length does an incoming req see 20211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 81577 # What write queue length does an incoming req see 20311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 85157 # What write queue length does an incoming req see 20411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 81436 # What write queue length does an incoming req see 20511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 80619 # What write queue length does an incoming req see 20611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 87129 # What write queue length does an incoming req see 20711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 77597 # What write queue length does an incoming req see 20811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 71470 # What write queue length does an incoming req see 20911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 67901 # What write queue length does an incoming req see 21011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 3383 # What write queue length does an incoming req see 21111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 2425 # What write queue length does an incoming req see 21211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 1908 # What write queue length does an incoming req see 21311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::36 1516 # What write queue length does an incoming req see 21411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::37 1151 # What write queue length does an incoming req see 21511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::38 1019 # What write queue length does an incoming req see 21611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::39 902 # What write queue length does an incoming req see 21711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::40 665 # What write queue length does an incoming req see 21811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 564 # What write queue length does an incoming req see 21911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see 22011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::43 402 # What write queue length does an incoming req see 22111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see 22211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::45 380 # What write queue length does an incoming req see 22311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::46 456 # What write queue length does an incoming req see 22411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::47 357 # What write queue length does an incoming req see 22511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::48 373 # What write queue length does an incoming req see 22611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see 22711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::50 412 # What write queue length does an incoming req see 22811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::51 339 # What write queue length does an incoming req see 22911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::52 291 # What write queue length does an incoming req see 23011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::53 298 # What write queue length does an incoming req see 23111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::54 296 # What write queue length does an incoming req see 23211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::55 274 # What write queue length does an incoming req see 23311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::56 277 # What write queue length does an incoming req see 23411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::57 275 # What write queue length does an incoming req see 23511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::58 223 # What write queue length does an incoming req see 23611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::59 225 # What write queue length does an incoming req see 23711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::60 157 # What write queue length does an incoming req see 23811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see 23911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see 24011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::63 212 # What write queue length does an incoming req see 24111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 1013795 # Bytes accessed per row activation 24211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 149.441747 # Bytes accessed per row activation 24311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 100.507639 # Bytes accessed per row activation 24411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 197.056675 # Bytes accessed per row activation 24511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 662057 65.30% 65.30% # Bytes accessed per row activation 24611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 208347 20.55% 85.86% # Bytes accessed per row activation 24711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 52181 5.15% 91.00% # Bytes accessed per row activation 24811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 23884 2.36% 93.36% # Bytes accessed per row activation 24911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 17639 1.74% 95.10% # Bytes accessed per row activation 25011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 11113 1.10% 96.20% # Bytes accessed per row activation 25111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 7357 0.73% 96.92% # Bytes accessed per row activation 25211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 6249 0.62% 97.54% # Bytes accessed per row activation 25311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 24968 2.46% 100.00% # Bytes accessed per row activation 25411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 1013795 # Bytes accessed per row activation 25511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 63452 # Reads before turning the bus around for writes 25611606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 17.247415 # Reads before turning the bus around for writes 25711606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 156.483425 # Reads before turning the bus around for writes 25811606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-1023 63450 100.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26111606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 63452 # Reads before turning the bus around for writes 26211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 63452 # Writes before turning the bus around for reads 26311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 20.059825 # Writes before turning the bus around for reads 26411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 18.482738 # Writes before turning the bus around for reads 26511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 12.878895 # Writes before turning the bus around for reads 26611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16-19 55385 87.29% 87.29% # Writes before turning the bus around for reads 26711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::20-23 2264 3.57% 90.85% # Writes before turning the bus around for reads 26811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::24-27 727 1.15% 92.00% # Writes before turning the bus around for reads 26911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::28-31 608 0.96% 92.96% # Writes before turning the bus around for reads 27011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::32-35 1019 1.61% 94.56% # Writes before turning the bus around for reads 27111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::36-39 457 0.72% 95.28% # Writes before turning the bus around for reads 27211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::40-43 338 0.53% 95.82% # Writes before turning the bus around for reads 27311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::44-47 295 0.46% 96.28% # Writes before turning the bus around for reads 27411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::48-51 198 0.31% 96.59% # Writes before turning the bus around for reads 27511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::52-55 179 0.28% 96.88% # Writes before turning the bus around for reads 27611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::56-59 127 0.20% 97.08% # Writes before turning the bus around for reads 27711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::60-63 154 0.24% 97.32% # Writes before turning the bus around for reads 27811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::64-67 464 0.73% 98.05% # Writes before turning the bus around for reads 27911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::68-71 118 0.19% 98.24% # Writes before turning the bus around for reads 28011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::72-75 142 0.22% 98.46% # Writes before turning the bus around for reads 28111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::76-79 119 0.19% 98.65% # Writes before turning the bus around for reads 28211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::80-83 89 0.14% 98.79% # Writes before turning the bus around for reads 28311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::84-87 71 0.11% 98.90% # Writes before turning the bus around for reads 28411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::88-91 72 0.11% 99.01% # Writes before turning the bus around for reads 28511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::92-95 80 0.13% 99.14% # Writes before turning the bus around for reads 28611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::96-99 103 0.16% 99.30% # Writes before turning the bus around for reads 28711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::100-103 73 0.12% 99.42% # Writes before turning the bus around for reads 28811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::104-107 46 0.07% 99.49% # Writes before turning the bus around for reads 28911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::108-111 54 0.09% 99.57% # Writes before turning the bus around for reads 29011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::112-115 48 0.08% 99.65% # Writes before turning the bus around for reads 29111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::116-119 39 0.06% 99.71% # Writes before turning the bus around for reads 29211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::120-123 53 0.08% 99.80% # Writes before turning the bus around for reads 29311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::124-127 25 0.04% 99.83% # Writes before turning the bus around for reads 29411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::128-131 49 0.08% 99.91% # Writes before turning the bus around for reads 29511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::132-135 20 0.03% 99.94% # Writes before turning the bus around for reads 29611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::136-139 13 0.02% 99.96% # Writes before turning the bus around for reads 29711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::140-143 6 0.01% 99.97% # Writes before turning the bus around for reads 29811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads 29911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.98% # Writes before turning the bus around for reads 30011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads 30111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 30211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 30311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads 30411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 30511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 30611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 63452 # Writes before turning the bus around for reads 30711606Sandreas.sandberg@arm.comsystem.physmem.totQLat 38795138463 # Total ticks spent queuing 30811606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 59315325963 # Total ticks spent from burst creation until serviced by the DRAM 30911606Sandreas.sandberg@arm.comsystem.physmem.totBusLat 5472050000 # Total ticks spent in databus transfers 31011606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 35448.45 # Average queueing delay per DRAM burst 31110515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31211606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 54198.45 # Average memory access latency per DRAM burst 31311606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s 31411606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s 31511606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s 31611606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s 31710515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31811606Sandreas.sandberg@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31911353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32011441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32111606Sandreas.sandberg@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 32211606Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing 32311606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 817920 # Number of row buffer hits during reads 32411606Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 535530 # Number of row buffer hits during writes 32511606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 74.74 # Row buffer hit rate for reads 32611606Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 42.07 # Row buffer hit rate for writes 32711606Sandreas.sandberg@arm.comsystem.physmem.avgGap 19947945.64 # Average gap between requests 32811606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 57.17 # Row buffer hit rate, read and write combined 32911606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 3880003680 # Energy for activate commands per rank (pJ) 33011606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 2117065500 # Energy for precharge commands per rank (pJ) 33111606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 4195752600 # Energy for read commands per rank (pJ) 33211606Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 4174344720 # Energy for write commands per rank (pJ) 33311606Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) 33411606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 1190314271070 # Energy for active background per rank (pJ) 33511606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 27321927289500 # Energy for precharge background per rank (pJ) 33611606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 31614497574750 # Total energy per rank (pJ) 33711606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 668.711016 # Core power per rank (mW) 33811606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 45452122728628 # Time in different power states 33911606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 1578675280000 # Time in different power states 34010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34111606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 245973030122 # Time in different power states 34210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34311606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 3784278960 # Energy for activate commands per rank (pJ) 34411606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 2064834750 # Energy for precharge commands per rank (pJ) 34511606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 4340583000 # Energy for read commands per rank (pJ) 34611606Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 4073632560 # Energy for write commands per rank (pJ) 34711606Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) 34811606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 1186461286245 # Energy for active background per rank (pJ) 34911606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 27325307092500 # Energy for precharge background per rank (pJ) 35011606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 31613920555695 # Total energy per rank (pJ) 35111606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 668.698811 # Core power per rank (mW) 35211606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 45457733356018 # Time in different power states 35311606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 1578675280000 # Time in different power states 35410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35511606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 240362584982 # Time in different power states 35610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35711606Sandreas.sandberg@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 35810636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 35910636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 36011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 36211570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 36310515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 36411570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 36511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 36610636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 36710636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36811570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 36910636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 37011570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 37110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 37210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37311606Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 37610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37711606Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) 37811570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 37910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 38010636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 38111606Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) 38210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38311570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 38411606Sandreas.sandberg@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 38511606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 38611606Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 38710585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38810585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38910585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 39011606Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 39111606Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 39211606Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 39311606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.lookups 132137665 # Number of BP lookups 39411606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.condPredicted 93617551 # Number of conditional branches predicted 39511606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.condIncorrect 5999845 # Number of conditional branches incorrect 39611606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.BTBLookups 98810350 # Number of BTB lookups 39711606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.BTBHits 69427031 # Number of BTB hits 39810585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39911606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.BTBHitPct 70.262914 # BTB Hit Percentage 40011606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.usedRAS 15260285 # Number of times the RAS was used to get a target. 40111606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.RASInCorrect 1044115 # Number of incorrect RAS predictions. 40211606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.indirectLookups 3387017 # Number of indirect predictor lookups. 40311606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.indirectHits 2259695 # Number of indirect target hits. 40411606Sandreas.sandberg@arm.comsystem.cpu0.branchPred.indirectMisses 1127322 # Number of indirect misses. 40511606Sandreas.sandberg@arm.comsystem.cpu0.branchPredindirectMispredicted 409659 # Number of mispredicted indirect branches. 40610515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 40711606Sandreas.sandberg@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 40810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 43010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 43811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walks 271762 # Table walker walks requested 43911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLong 271762 # Table walker walks initiated with long descriptors 44011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10351 # Level at which table walker walks with long descriptors terminate 44111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74846 # Level at which table walker walks with long descriptors terminate 44211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 271762 # Table walker wait (enqueue to first request) latency 44311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 271762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 44411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 271762 # Table walker wait (enqueue to first request) latency 44511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 85197 # Table walker service (enqueue to completion) latency 44611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512 # Table walker service (enqueue to completion) latency 44711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295 # Table walker service (enqueue to completion) latency 44811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266 # Table walker service (enqueue to completion) latency 44911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 84296 98.94% 98.94% # Table walker service (enqueue to completion) latency 45011606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 776 0.91% 99.85% # Table walker service (enqueue to completion) latency 45111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 35 0.04% 99.89% # Table walker service (enqueue to completion) latency 45211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.94% # Table walker service (enqueue to completion) latency 45311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 35 0.04% 99.98% # Table walker service (enqueue to completion) latency 45411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 45511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 45611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 45711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 85197 # Table walker service (enqueue to completion) latency 46011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution 46111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution 46211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution 46311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 74846 87.85% 87.85% # Table walker page sizes translated 46411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10351 12.15% 100.00% # Table walker page sizes translated 46511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 85197 # Table walker page sizes translated 46611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271762 # Table walker requests started/completed, data/inst 46710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271762 # Table walker requests started/completed, data/inst 46911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85197 # Table walker requests started/completed, data/inst 47010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85197 # Table walker requests started/completed, data/inst 47211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 356959 # Table walker requests started/completed, data/inst 47310585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47410585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_hits 82756248 # DTB read hits 47611606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_misses 224730 # DTB read misses 47711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_hits 74117187 # DTB write hits 47811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_misses 47032 # DTB write misses 47911441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 48010585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 48211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 48311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_entries 34573 # Number of entries that have been flushed from TLB 48411606Sandreas.sandberg@arm.comsystem.cpu0.dtb.align_faults 2108 # Number of TLB faults due to alignment restrictions 48511606Sandreas.sandberg@arm.comsystem.cpu0.dtb.prefetch_faults 9506 # Number of TLB faults due to prefetch 48610585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48711606Sandreas.sandberg@arm.comsystem.cpu0.dtb.perms_faults 11030 # Number of TLB faults due to permissions restrictions 48811606Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_accesses 82980978 # DTB read accesses 48911606Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_accesses 74164219 # DTB write accesses 49010585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 49111606Sandreas.sandberg@arm.comsystem.cpu0.dtb.hits 156873435 # DTB hits 49211606Sandreas.sandberg@arm.comsystem.cpu0.dtb.misses 271762 # DTB misses 49311606Sandreas.sandberg@arm.comsystem.cpu0.dtb.accesses 157145197 # DTB accesses 49411606Sandreas.sandberg@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 49510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 51910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 52010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 52511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walks 60398 # Table walker walks requested 52611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLong 60398 # Table walker walks initiated with long descriptors 52711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 589 # Level at which table walker walks with long descriptors terminate 52811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 51882 # Level at which table walker walks with long descriptors terminate 52911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 60398 # Table walker wait (enqueue to first request) latency 53011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 60398 100.00% 100.00% # Table walker wait (enqueue to first request) latency 53111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 60398 # Table walker wait (enqueue to first request) latency 53211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52471 # Table walker service (enqueue to completion) latency 53311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25793.819443 # Table walker service (enqueue to completion) latency 53411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428 # Table walker service (enqueue to completion) latency 53511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613 # Table walker service (enqueue to completion) latency 53611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 46836 89.26% 89.26% # Table walker service (enqueue to completion) latency 53711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 4750 9.05% 98.31% # Table walker service (enqueue to completion) latency 53811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 22 0.04% 98.36% # Table walker service (enqueue to completion) latency 53911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 772 1.47% 99.83% # Table walker service (enqueue to completion) latency 54011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.87% # Table walker service (enqueue to completion) latency 54111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 15 0.03% 99.90% # Table walker service (enqueue to completion) latency 54211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 26 0.05% 99.95% # Table walker service (enqueue to completion) latency 54311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.96% # Table walker service (enqueue to completion) latency 54411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 54511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 54611606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 9 0.02% 100.00% # Table walker service (enqueue to completion) latency 54711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 54811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 54911606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52471 # Table walker service (enqueue to completion) latency 55011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution 55111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution 55211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution 55311606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 51882 98.88% 98.88% # Table walker page sizes translated 55411606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 589 1.12% 100.00% # Table walker page sizes translated 55511606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52471 # Table walker page sizes translated 55610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55711606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60398 # Table walker requests started/completed, data/inst 55811606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60398 # Table walker requests started/completed, data/inst 55910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 56011606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52471 # Table walker requests started/completed, data/inst 56111606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52471 # Table walker requests started/completed, data/inst 56211606Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 112869 # Table walker requests started/completed, data/inst 56311606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_hits 234456044 # ITB inst hits 56411606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_misses 60398 # ITB inst misses 56510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 56610585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 56710585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 56810585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 56911441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 57010585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57111606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 57211606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 57311606Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_entries 24118 # Number of entries that have been flushed from TLB 57410585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57510585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57610585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57711606Sandreas.sandberg@arm.comsystem.cpu0.itb.perms_faults 160109 # Number of TLB faults due to permissions restrictions 57810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 57910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 58011606Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_accesses 234516442 # ITB inst accesses 58111606Sandreas.sandberg@arm.comsystem.cpu0.itb.hits 234456044 # DTB hits 58211606Sandreas.sandberg@arm.comsystem.cpu0.itb.misses 60398 # DTB misses 58311606Sandreas.sandberg@arm.comsystem.cpu0.itb.accesses 234516442 # DTB accesses 58411606Sandreas.sandberg@arm.comsystem.cpu0.numPwrStateTransitions 8178 # Number of power state transitions 58511606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::samples 4089 # Distribution of time spent in the clock gated state 58611606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::mean 11447226771.455124 # Distribution of time spent in the clock gated state 58711606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 162386644618.467285 # Distribution of time spent in the clock gated state 58811606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 2836 69.36% 69.36% # Distribution of time spent in the clock gated state 58911606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1230 30.08% 99.44% # Distribution of time spent in the clock gated state 59011606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state 59111606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.51% # Distribution of time spent in the clock gated state 59211606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.56% # Distribution of time spent in the clock gated state 59311606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state 59411606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 59511606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state 59611606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state 59711606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.34% 100.00% # Distribution of time spent in the clock gated state 59811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 59911606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7470355608744 # Distribution of time spent in the clock gated state 60011606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::total 4089 # Distribution of time spent in the clock gated state 60111606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 469062558520 # Cumulative time (in ticks) in various power states 60211606Sandreas.sandberg@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480 # Cumulative time (in ticks) in various power states 60311606Sandreas.sandberg@arm.comsystem.cpu0.numCycles 938130839 # number of cpu cycles simulated 60410585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 60510585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 60611606Sandreas.sandberg@arm.comsystem.cpu0.committedInsts 430200528 # Number of instructions committed 60711606Sandreas.sandberg@arm.comsystem.cpu0.committedOps 505771410 # Number of ops (including micro ops) committed 60811606Sandreas.sandberg@arm.comsystem.cpu0.discardedOps 45690974 # Number of ops (including micro ops) which were discarded before commit 60911606Sandreas.sandberg@arm.comsystem.cpu0.numFetchSuspends 3904 # Number of times Execute suspended instruction fetching 61011606Sandreas.sandberg@arm.comsystem.cpu0.quiesceCycles 93616054941 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 61111606Sandreas.sandberg@arm.comsystem.cpu0.cpi 2.180683 # CPI: cycles per instruction 61211606Sandreas.sandberg@arm.comsystem.cpu0.ipc 0.458572 # IPC: instructions per cycle 61311606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 61411606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::IntAlu 351125189 69.42% 69.42% # Class of committed instruction 61511606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::IntMult 1073769 0.21% 69.64% # Class of committed instruction 61611606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::IntDiv 52983 0.01% 69.65% # Class of committed instruction 61711606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction 61811606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction 61911606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction 62011606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction 62111606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction 62211606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction 62311606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction 62411606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction 62511606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction 62611606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction 62711606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction 62811606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction 62911606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction 63011606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction 63111606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction 63211606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction 63311606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction 63411606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.65% # Class of committed instruction 63511606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction 63611606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.65% # Class of committed instruction 63711606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.65% # Class of committed instruction 63811606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction 63911606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 68782 0.01% 69.66% # Class of committed instruction 64011606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction 64111606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction 64211606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction 64311606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::MemRead 79655364 15.75% 85.41% # Class of committed instruction 64411606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::MemWrite 73795280 14.59% 100.00% # Class of committed instruction 64511441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 64611441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 64711606Sandreas.sandberg@arm.comsystem.cpu0.op_class_0::total 505771410 # Class of committed instruction 64810585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 64911606Sandreas.sandberg@arm.comsystem.cpu0.kern.inst.quiesce 4089 # number of quiesce instructions executed 65011606Sandreas.sandberg@arm.comsystem.cpu0.tickCycles 697846091 # Number of cycles that the object actually ticked 65111606Sandreas.sandberg@arm.comsystem.cpu0.idleCycles 240284748 # Total number of cycles that the object has spent stopped 65211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 65311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.replacements 5497391 # number of replacements 65411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tagsinuse 500.377946 # Cycle average of tags in use 65511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 148839422 # Total number of references to valid blocks. 65611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.sampled_refs 5497903 # Sample count of references to valid blocks. 65711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 27.072035 # Average number of references to valid blocks. 65811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. 65911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.377946 # Average occupied blocks per requestor 66011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.977301 # Average percentage of cache occupancy 66111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.977301 # Average percentage of cache occupancy 66211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 66311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 66411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id 66511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 66611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 66711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tag_accesses 316768421 # Number of tag accesses 66811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.data_accesses 316768421 # Number of data accesses 66911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 67011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 75978032 # number of ReadReq hits 67111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::total 75978032 # number of ReadReq hits 67211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 68482955 # number of WriteReq hits 67311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 68482955 # number of WriteReq hits 67411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 264842 # number of SoftPFReq hits 67511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 264842 # number of SoftPFReq hits 67611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 244065 # number of WriteLineReq hits 67711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 244065 # number of WriteLineReq hits 67811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1687572 # number of LoadLockedReq hits 67911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1687572 # number of LoadLockedReq hits 68011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1654235 # number of StoreCondReq hits 68111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1654235 # number of StoreCondReq hits 68211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 144705052 # number of demand (read+write) hits 68311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 144705052 # number of demand (read+write) hits 68411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 144969894 # number of overall hits 68511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 144969894 # number of overall hits 68611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3066734 # number of ReadReq misses 68711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3066734 # number of ReadReq misses 68811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2419958 # number of WriteReq misses 68911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2419958 # number of WriteReq misses 69011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 670609 # number of SoftPFReq misses 69111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 670609 # number of SoftPFReq misses 69211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 786129 # number of WriteLineReq misses 69311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 786129 # number of WriteLineReq misses 69411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148878 # number of LoadLockedReq misses 69511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 148878 # number of LoadLockedReq misses 69611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 181031 # number of StoreCondReq misses 69711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 181031 # number of StoreCondReq misses 69811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 6272821 # number of demand (read+write) misses 69911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 6272821 # number of demand (read+write) misses 70011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6943430 # number of overall misses 70111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 6943430 # number of overall misses 70211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47243422000 # number of ReadReq miss cycles 70311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 47243422000 # number of ReadReq miss cycles 70411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 49248110500 # number of WriteReq miss cycles 70511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 49248110500 # number of WriteReq miss cycles 70611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26231986000 # number of WriteLineReq miss cycles 70711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 26231986000 # number of WriteLineReq miss cycles 70811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2187373500 # number of LoadLockedReq miss cycles 70911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2187373500 # number of LoadLockedReq miss cycles 71011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4323764500 # number of StoreCondReq miss cycles 71111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4323764500 # number of StoreCondReq miss cycles 71211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2754000 # number of StoreCondFailReq miss cycles 71311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2754000 # number of StoreCondFailReq miss cycles 71411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500 # number of demand (read+write) miss cycles 71511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::total 122723518500 # number of demand (read+write) miss cycles 71611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500 # number of overall miss cycles 71711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::total 122723518500 # number of overall miss cycles 71811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 79044766 # number of ReadReq accesses(hits+misses) 71911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 79044766 # number of ReadReq accesses(hits+misses) 72011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 70902913 # number of WriteReq accesses(hits+misses) 72111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 70902913 # number of WriteReq accesses(hits+misses) 72211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935451 # number of SoftPFReq accesses(hits+misses) 72311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 935451 # number of SoftPFReq accesses(hits+misses) 72411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1030194 # number of WriteLineReq accesses(hits+misses) 72511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1030194 # number of WriteLineReq accesses(hits+misses) 72611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1836450 # number of LoadLockedReq accesses(hits+misses) 72711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1836450 # number of LoadLockedReq accesses(hits+misses) 72811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1835266 # number of StoreCondReq accesses(hits+misses) 72911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1835266 # number of StoreCondReq accesses(hits+misses) 73011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 150977873 # number of demand (read+write) accesses 73111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::total 150977873 # number of demand (read+write) accesses 73211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 151913324 # number of overall (read+write) accesses 73311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::total 151913324 # number of overall (read+write) accesses 73411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038797 # miss rate for ReadReq accesses 73511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.038797 # miss rate for ReadReq accesses 73611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.034131 # miss rate for WriteReq accesses 73711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.034131 # miss rate for WriteReq accesses 73811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716883 # miss rate for SoftPFReq accesses 73911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.716883 # miss rate for SoftPFReq accesses 74011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763088 # miss rate for WriteLineReq accesses 74111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.763088 # miss rate for WriteLineReq accesses 74211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081068 # miss rate for LoadLockedReq accesses 74311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081068 # miss rate for LoadLockedReq accesses 74411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098640 # miss rate for StoreCondReq accesses 74511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.098640 # miss rate for StoreCondReq accesses 74611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses 74711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses 74811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.045707 # miss rate for overall accesses 74911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.045707 # miss rate for overall accesses 75011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453 # average ReadReq miss latency 75111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453 # average ReadReq miss latency 75211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080 # average WriteReq miss latency 75311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080 # average WriteReq miss latency 75411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472 # average WriteLineReq miss latency 75511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472 # average WriteLineReq miss latency 75611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070 # average LoadLockedReq miss latency 75711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070 # average LoadLockedReq miss latency 75811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009 # average StoreCondReq miss latency 75911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009 # average StoreCondReq miss latency 76010636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 76110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 76211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561 # average overall miss latency 76311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19564.326561 # average overall miss latency 76411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594 # average overall miss latency 76511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17674.768594 # average overall miss latency 76610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 76910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 77010585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77110585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 5497393 # number of writebacks 77311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 5497393 # number of writebacks 77411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200047 # number of ReadReq MSHR hits 77511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 200047 # number of ReadReq MSHR hits 77611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012976 # number of WriteReq MSHR hits 77711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1012976 # number of WriteReq MSHR hits 77811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 94 # number of WriteLineReq MSHR hits 77911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 94 # number of WriteLineReq MSHR hits 78011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39271 # number of LoadLockedReq MSHR hits 78111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 39271 # number of LoadLockedReq MSHR hits 78211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 90 # number of StoreCondReq MSHR hits 78311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 90 # number of StoreCondReq MSHR hits 78411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1213117 # number of demand (read+write) MSHR hits 78511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1213117 # number of demand (read+write) MSHR hits 78611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1213117 # number of overall MSHR hits 78711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1213117 # number of overall MSHR hits 78811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2866687 # number of ReadReq MSHR misses 78911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2866687 # number of ReadReq MSHR misses 79011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1406982 # number of WriteReq MSHR misses 79111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1406982 # number of WriteReq MSHR misses 79211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668415 # number of SoftPFReq MSHR misses 79311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 668415 # number of SoftPFReq MSHR misses 79411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 786035 # number of WriteLineReq MSHR misses 79511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 786035 # number of WriteLineReq MSHR misses 79611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109607 # number of LoadLockedReq MSHR misses 79711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 109607 # number of LoadLockedReq MSHR misses 79811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180941 # number of StoreCondReq MSHR misses 79911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 180941 # number of StoreCondReq MSHR misses 80011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5059704 # number of demand (read+write) MSHR misses 80111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5059704 # number of demand (read+write) MSHR misses 80211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5728119 # number of overall MSHR misses 80311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5728119 # number of overall MSHR misses 80411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 80511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 20634 # number of ReadReq MSHR uncacheable 80611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 80711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable 80811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 80911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 42909 # number of overall MSHR uncacheable misses 81011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39457015000 # number of ReadReq MSHR miss cycles 81111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 39457015000 # number of ReadReq MSHR miss cycles 81211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27671793000 # number of WriteReq MSHR miss cycles 81311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 27671793000 # number of WriteReq MSHR miss cycles 81411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15966528000 # number of SoftPFReq MSHR miss cycles 81511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15966528000 # number of SoftPFReq MSHR miss cycles 81611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25439405000 # number of WriteLineReq MSHR miss cycles 81711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25439405000 # number of WriteLineReq MSHR miss cycles 81811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1452927000 # number of LoadLockedReq MSHR miss cycles 81911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1452927000 # number of LoadLockedReq MSHR miss cycles 82011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4140525000 # number of StoreCondReq MSHR miss cycles 82111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4140525000 # number of StoreCondReq MSHR miss cycles 82211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2476500 # number of StoreCondFailReq MSHR miss cycles 82311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2476500 # number of StoreCondFailReq MSHR miss cycles 82411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92568213000 # number of demand (read+write) MSHR miss cycles 82511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 92568213000 # number of demand (read+write) MSHR miss cycles 82611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000 # number of overall MSHR miss cycles 82711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 108534741000 # number of overall MSHR miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4015086500 # number of ReadReq MSHR uncacheable cycles 82911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4015086500 # number of ReadReq MSHR uncacheable cycles 83011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4015086500 # number of overall MSHR uncacheable cycles 83111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 4015086500 # number of overall MSHR uncacheable cycles 83211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036267 # mshr miss rate for ReadReq accesses 83311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036267 # mshr miss rate for ReadReq accesses 83411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019844 # mshr miss rate for WriteReq accesses 83511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019844 # mshr miss rate for WriteReq accesses 83611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714538 # mshr miss rate for SoftPFReq accesses 83711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714538 # mshr miss rate for SoftPFReq accesses 83811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.762997 # mshr miss rate for WriteLineReq accesses 83911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.762997 # mshr miss rate for WriteLineReq accesses 84011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059684 # mshr miss rate for LoadLockedReq accesses 84111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059684 # mshr miss rate for LoadLockedReq accesses 84211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098591 # mshr miss rate for StoreCondReq accesses 84311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098591 # mshr miss rate for StoreCondReq accesses 84411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033513 # mshr miss rate for demand accesses 84511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.033513 # mshr miss rate for demand accesses 84611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037706 # mshr miss rate for overall accesses 84711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.037706 # mshr miss rate for overall accesses 84811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372 # average ReadReq mshr miss latency 84911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372 # average ReadReq mshr miss latency 85011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887 # average WriteReq mshr miss latency 85111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887 # average WriteReq mshr miss latency 85211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954 # average SoftPFReq mshr miss latency 85311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954 # average SoftPFReq mshr miss latency 85411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062 # average WriteLineReq mshr miss latency 85511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062 # average WriteLineReq mshr miss latency 85611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583 # average LoadLockedReq mshr miss latency 85711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583 # average LoadLockedReq mshr miss latency 85811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923 # average StoreCondReq mshr miss latency 85911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923 # average StoreCondReq mshr miss latency 86010636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 86110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 86211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473 # average overall mshr miss latency 86311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473 # average overall mshr miss latency 86411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584 # average overall mshr miss latency 86511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584 # average overall mshr miss latency 86611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373 # average ReadReq mshr uncacheable latency 86711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373 # average ReadReq mshr uncacheable latency 86811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390 # average overall mshr uncacheable latency 86911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390 # average overall mshr uncacheable latency 87011606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 87111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.replacements 9280608 # number of replacements 87211606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tagsinuse 511.932285 # Cycle average of tags in use 87311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 225009210 # Total number of references to valid blocks. 87411606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.sampled_refs 9281120 # Sample count of references to valid blocks. 87511606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 24.243756 # Average number of references to valid blocks. 87611606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.warmup_cycle 22204306000 # Cycle when the warmup percentage was hit. 87711606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932285 # Average occupied blocks per requestor 87811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 87911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 88010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 88211606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 88311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id 88410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88511606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 477861809 # Number of tag accesses 88611606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 477861809 # Number of data accesses 88711606Sandreas.sandberg@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 88811606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 225009210 # number of ReadReq hits 88911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 225009210 # number of ReadReq hits 89011606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 225009210 # number of demand (read+write) hits 89111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 225009210 # number of demand (read+write) hits 89211606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 225009210 # number of overall hits 89311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 225009210 # number of overall hits 89411606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9281130 # number of ReadReq misses 89511606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::total 9281130 # number of ReadReq misses 89611606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9281130 # number of demand (read+write) misses 89711606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::total 9281130 # number of demand (read+write) misses 89811606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9281130 # number of overall misses 89911606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::total 9281130 # number of overall misses 90011606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94226606500 # number of ReadReq miss cycles 90111606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 94226606500 # number of ReadReq miss cycles 90211606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 94226606500 # number of demand (read+write) miss cycles 90311606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::total 94226606500 # number of demand (read+write) miss cycles 90411606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 94226606500 # number of overall miss cycles 90511606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::total 94226606500 # number of overall miss cycles 90611606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 234290340 # number of ReadReq accesses(hits+misses) 90711606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::total 234290340 # number of ReadReq accesses(hits+misses) 90811606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 234290340 # number of demand (read+write) accesses 90911606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::total 234290340 # number of demand (read+write) accesses 91011606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 234290340 # number of overall (read+write) accesses 91111606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::total 234290340 # number of overall (read+write) accesses 91211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039614 # miss rate for ReadReq accesses 91311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.039614 # miss rate for ReadReq accesses 91411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.039614 # miss rate for demand accesses 91511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.039614 # miss rate for demand accesses 91611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.039614 # miss rate for overall accesses 91711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.039614 # miss rate for overall accesses 91811606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908 # average ReadReq miss latency 91911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908 # average ReadReq miss latency 92011606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency 92111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10152.492908 # average overall miss latency 92211606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency 92311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10152.492908 # average overall miss latency 92410585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92510585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 92710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 92810585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92910585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 93011606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::writebacks 9280608 # number of writebacks 93111606Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::total 9280608 # number of writebacks 93211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9281130 # number of ReadReq MSHR misses 93311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9281130 # number of ReadReq MSHR misses 93411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9281130 # number of demand (read+write) MSHR misses 93511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9281130 # number of demand (read+write) MSHR misses 93611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9281130 # number of overall MSHR misses 93711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9281130 # number of overall MSHR misses 93811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 93911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable 94011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 94111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses 94211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89586042000 # number of ReadReq MSHR miss cycles 94311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 89586042000 # number of ReadReq MSHR miss cycles 94411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89586042000 # number of demand (read+write) MSHR miss cycles 94511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 89586042000 # number of demand (read+write) MSHR miss cycles 94611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89586042000 # number of overall MSHR miss cycles 94711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 89586042000 # number of overall MSHR miss cycles 94811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles 94911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles 95011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles 95111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles 95211606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for ReadReq accesses 95311606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039614 # mshr miss rate for ReadReq accesses 95411606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for demand accesses 95511606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.039614 # mshr miss rate for demand accesses 95611606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for overall accesses 95711606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.039614 # mshr miss rate for overall accesses 95811606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average ReadReq mshr miss latency 95911606Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9652.492962 # average ReadReq mshr miss latency 96011606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency 96111606Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency 96211606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency 96311606Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency 96411570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency 96511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency 96611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency 96711570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency 96811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 96911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7507862 # number of hwpf issued 97011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7509065 # number of prefetch candidates identified 97111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1069 # number of redundant prefetches already in prefetch queue 97210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 942183 # number of prefetches not generated due to page crossing 97511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 97611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.replacements 2584098 # number of replacements 97711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15590.889787 # Cycle average of tags in use 97811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.total_refs 13248667 # Total number of references to valid blocks. 97911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2600019 # Sample count of references to valid blocks. 98011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.095604 # Average number of references to valid blocks. 98111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. 98211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15296.249521 # Average occupied blocks per requestor 98311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.752726 # Average occupied blocks per requestor 98411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.010194 # Average occupied blocks per requestor 98511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.877346 # Average occupied blocks per requestor 98611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.933609 # Average percentage of cache occupancy 98711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy 98811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001343 # Average percentage of cache occupancy 98911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014214 # Average percentage of cache occupancy 99011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.951592 # Average percentage of cache occupancy 99111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 376 # Occupied blocks per task id 99211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 99311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15477 # Occupied blocks per task id 99411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id 99511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 99611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 104 # Occupied blocks per task id 99711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 124 # Occupied blocks per task id 99811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 121 # Occupied blocks per task id 99911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 100011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 100111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id 100211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id 100311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 100411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1649 # Occupied blocks per task id 100511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4407 # Occupied blocks per task id 100611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id 100711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3577 # Occupied blocks per task id 100811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022949 # Percentage of cache occupancy per task id 100911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 101011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.944641 # Percentage of cache occupancy per task id 101111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tag_accesses 507607175 # Number of tag accesses 101211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.data_accesses 507607175 # Number of data accesses 101311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 101411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 496900 # number of ReadReq hits 101511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154788 # number of ReadReq hits 101611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 651688 # number of ReadReq hits 101711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3675506 # number of WritebackDirty hits 101811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3675506 # number of WritebackDirty hits 101911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11099665 # number of WritebackClean hits 102011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 11099665 # number of WritebackClean hits 102111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 891359 # number of ReadExReq hits 102211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 891359 # number of ReadExReq hits 102311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8598093 # number of ReadCleanReq hits 102411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 8598093 # number of ReadCleanReq hits 102511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2690347 # number of ReadSharedReq hits 102611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2690347 # number of ReadSharedReq hits 102711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202108 # number of InvalidateReq hits 102811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 202108 # number of InvalidateReq hits 102911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 496900 # number of demand (read+write) hits 103011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 154788 # number of demand (read+write) hits 103111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 8598093 # number of demand (read+write) hits 103211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3581706 # number of demand (read+write) hits 103311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::total 12831487 # number of demand (read+write) hits 103411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 496900 # number of overall hits 103511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 154788 # number of overall hits 103611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 8598093 # number of overall hits 103711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3581706 # number of overall hits 103811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::total 12831487 # number of overall hits 103911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 19803 # number of ReadReq misses 104011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9619 # number of ReadReq misses 104111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 29422 # number of ReadReq misses 104211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 245426 # number of UpgradeReq misses 104311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 245426 # number of UpgradeReq misses 104411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 180938 # number of SCUpgradeReq misses 104511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 180938 # number of SCUpgradeReq misses 104611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 104711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 104811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 278613 # number of ReadExReq misses 104911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 278613 # number of ReadExReq misses 105011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 683036 # number of ReadCleanReq misses 105111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 683036 # number of ReadCleanReq misses 105211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953863 # number of ReadSharedReq misses 105311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 953863 # number of ReadSharedReq misses 105411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 581978 # number of InvalidateReq misses 105511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 581978 # number of InvalidateReq misses 105611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 19803 # number of demand (read+write) misses 105711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 9619 # number of demand (read+write) misses 105811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 683036 # number of demand (read+write) misses 105911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1232476 # number of demand (read+write) misses 106011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::total 1944934 # number of demand (read+write) misses 106111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 19803 # number of overall misses 106211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 9619 # number of overall misses 106311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 683036 # number of overall misses 106411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1232476 # number of overall misses 106511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::total 1944934 # number of overall misses 106611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 614702000 # number of ReadReq miss cycles 106711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 331371000 # number of ReadReq miss cycles 106811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 946073000 # number of ReadReq miss cycles 106911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 874372000 # number of UpgradeReq miss cycles 107011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 874372000 # number of UpgradeReq miss cycles 107111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295339000 # number of SCUpgradeReq miss cycles 107211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295339000 # number of SCUpgradeReq miss cycles 107311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2383999 # number of SCUpgradeFailReq miss cycles 107411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2383999 # number of SCUpgradeFailReq miss cycles 107511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13650875999 # number of ReadExReq miss cycles 107611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 13650875999 # number of ReadExReq miss cycles 107711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23732034500 # number of ReadCleanReq miss cycles 107811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 23732034500 # number of ReadCleanReq miss cycles 107911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33660637494 # number of ReadSharedReq miss cycles 108011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 33660637494 # number of ReadSharedReq miss cycles 108111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333947500 # number of InvalidateReq miss cycles 108211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 333947500 # number of InvalidateReq miss cycles 108311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 614702000 # number of demand (read+write) miss cycles 108411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 331371000 # number of demand (read+write) miss cycles 108511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 23732034500 # number of demand (read+write) miss cycles 108611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 47311513493 # number of demand (read+write) miss cycles 108711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 71989620993 # number of demand (read+write) miss cycles 108811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 614702000 # number of overall miss cycles 108911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 331371000 # number of overall miss cycles 109011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 23732034500 # number of overall miss cycles 109111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 47311513493 # number of overall miss cycles 109211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 71989620993 # number of overall miss cycles 109311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 516703 # number of ReadReq accesses(hits+misses) 109411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164407 # number of ReadReq accesses(hits+misses) 109511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 681110 # number of ReadReq accesses(hits+misses) 109611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3675506 # number of WritebackDirty accesses(hits+misses) 109711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3675506 # number of WritebackDirty accesses(hits+misses) 109811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11099665 # number of WritebackClean accesses(hits+misses) 109911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11099665 # number of WritebackClean accesses(hits+misses) 110011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 245426 # number of UpgradeReq accesses(hits+misses) 110111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 245426 # number of UpgradeReq accesses(hits+misses) 110211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180938 # number of SCUpgradeReq accesses(hits+misses) 110311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 180938 # number of SCUpgradeReq accesses(hits+misses) 110411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 110511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 110611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1169972 # number of ReadExReq accesses(hits+misses) 110711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1169972 # number of ReadExReq accesses(hits+misses) 110811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9281129 # number of ReadCleanReq accesses(hits+misses) 110911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9281129 # number of ReadCleanReq accesses(hits+misses) 111011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3644210 # number of ReadSharedReq accesses(hits+misses) 111111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3644210 # number of ReadSharedReq accesses(hits+misses) 111211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 784086 # number of InvalidateReq accesses(hits+misses) 111311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 784086 # number of InvalidateReq accesses(hits+misses) 111411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 516703 # number of demand (read+write) accesses 111511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164407 # number of demand (read+write) accesses 111611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9281129 # number of demand (read+write) accesses 111711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4814182 # number of demand (read+write) accesses 111811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::total 14776421 # number of demand (read+write) accesses 111911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 516703 # number of overall (read+write) accesses 112011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164407 # number of overall (read+write) accesses 112111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9281129 # number of overall (read+write) accesses 112211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4814182 # number of overall (read+write) accesses 112311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::total 14776421 # number of overall (read+write) accesses 112411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for ReadReq accesses 112511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058507 # miss rate for ReadReq accesses 112611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.043197 # miss rate for ReadReq accesses 112711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 112811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 112911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 113011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 113110636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 113210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 113311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.238136 # miss rate for ReadExReq accesses 113411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.238136 # miss rate for ReadExReq accesses 113511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073594 # miss rate for ReadCleanReq accesses 113611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073594 # miss rate for ReadCleanReq accesses 113711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261748 # miss rate for ReadSharedReq accesses 113811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261748 # miss rate for ReadSharedReq accesses 113911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.742237 # miss rate for InvalidateReq accesses 114011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.742237 # miss rate for InvalidateReq accesses 114111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for demand accesses 114211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058507 # miss rate for demand accesses 114311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073594 # miss rate for demand accesses 114411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.256009 # miss rate for demand accesses 114511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.131624 # miss rate for demand accesses 114611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for overall accesses 114711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058507 # miss rate for overall accesses 114811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073594 # miss rate for overall accesses 114911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.256009 # miss rate for overall accesses 115011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.131624 # miss rate for overall accesses 115111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average ReadReq miss latency 115211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34449.630939 # average ReadReq miss latency 115311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 32155.291958 # average ReadReq miss latency 115411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3562.670622 # average UpgradeReq miss latency 115511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3562.670622 # average UpgradeReq miss latency 115611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1632.266301 # average SCUpgradeReq miss latency 115711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1632.266301 # average SCUpgradeReq miss latency 115811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 794666.333333 # average SCUpgradeFailReq miss latency 115911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 794666.333333 # average SCUpgradeFailReq miss latency 116011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48995.832926 # average ReadExReq miss latency 116111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48995.832926 # average ReadExReq miss latency 116211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34744.924865 # average ReadCleanReq miss latency 116311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34744.924865 # average ReadCleanReq miss latency 116411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35288.754773 # average ReadSharedReq miss latency 116511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35288.754773 # average ReadSharedReq miss latency 116611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 573.814646 # average InvalidateReq miss latency 116711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 573.814646 # average InvalidateReq miss latency 116811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency 116911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency 117011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency 117111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency 117211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 37013.914607 # average overall miss latency 117311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency 117411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency 117511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency 117611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency 117711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 37013.914607 # average overall miss latency 117811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 118110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 118211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 118411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.unused_prefetches 44195 # number of HardPF blocks evicted w/o reference 118511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1595582 # number of writebacks 118611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::total 1595582 # number of writebacks 118711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 11 # number of ReadReq MSHR hits 118811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 92 # number of ReadReq MSHR hits 118911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 119011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9447 # number of ReadExReq MSHR hits 119111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9447 # number of ReadExReq MSHR hits 119211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits 119311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 119411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 778 # number of ReadSharedReq MSHR hits 119511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 778 # number of ReadSharedReq MSHR hits 119611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 119711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 119811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 11 # number of demand (read+write) MSHR hits 119911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 92 # number of demand (read+write) MSHR hits 120011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits 120111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 10225 # number of demand (read+write) MSHR hits 120211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 10340 # number of demand (read+write) MSHR hits 120311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 11 # number of overall MSHR hits 120411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 92 # number of overall MSHR hits 120511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits 120611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 10225 # number of overall MSHR hits 120711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 10340 # number of overall MSHR hits 120811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 19792 # number of ReadReq MSHR misses 120911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9527 # number of ReadReq MSHR misses 121011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 29319 # number of ReadReq MSHR misses 121111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of HardPFReq MSHR misses 121211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 781759 # number of HardPFReq MSHR misses 121311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 245426 # number of UpgradeReq MSHR misses 121411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 245426 # number of UpgradeReq MSHR misses 121511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 180938 # number of SCUpgradeReq MSHR misses 121611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 180938 # number of SCUpgradeReq MSHR misses 121711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 121811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 121911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269166 # number of ReadExReq MSHR misses 122011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 269166 # number of ReadExReq MSHR misses 122111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 683024 # number of ReadCleanReq MSHR misses 122211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 683024 # number of ReadCleanReq MSHR misses 122311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 953085 # number of ReadSharedReq MSHR misses 122411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 953085 # number of ReadSharedReq MSHR misses 122511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 581976 # number of InvalidateReq MSHR misses 122611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 581976 # number of InvalidateReq MSHR misses 122711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 19792 # number of demand (read+write) MSHR misses 122811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9527 # number of demand (read+write) MSHR misses 122911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 683024 # number of demand (read+write) MSHR misses 123011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1222251 # number of demand (read+write) MSHR misses 123111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1934594 # number of demand (read+write) MSHR misses 123211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 19792 # number of overall MSHR misses 123311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9527 # number of overall MSHR misses 123411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 683024 # number of overall MSHR misses 123511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1222251 # number of overall MSHR misses 123611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of overall MSHR misses 123711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2716353 # number of overall MSHR misses 123811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 123911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 124011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72934 # number of ReadReq MSHR uncacheable 124111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 124211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable 124311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 124411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 124511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 95209 # number of overall MSHR uncacheable misses 124611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of ReadReq MSHR miss cycles 124711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 272683000 # number of ReadReq MSHR miss cycles 124811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 768369000 # number of ReadReq MSHR miss cycles 124911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of HardPFReq MSHR miss cycles 125011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38385674547 # number of HardPFReq MSHR miss cycles 125111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4516919997 # number of UpgradeReq MSHR miss cycles 125211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4516919997 # number of UpgradeReq MSHR miss cycles 125311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2779143996 # number of SCUpgradeReq MSHR miss cycles 125411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2779143996 # number of SCUpgradeReq MSHR miss cycles 125511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2017999 # number of SCUpgradeFailReq MSHR miss cycles 125611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2017999 # number of SCUpgradeFailReq MSHR miss cycles 125711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10852711499 # number of ReadExReq MSHR miss cycles 125811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10852711499 # number of ReadExReq MSHR miss cycles 125911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19633488000 # number of ReadCleanReq MSHR miss cycles 126011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19633488000 # number of ReadCleanReq MSHR miss cycles 126111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27859151994 # number of ReadSharedReq MSHR miss cycles 126211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27859151994 # number of ReadSharedReq MSHR miss cycles 126311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19308557500 # number of InvalidateReq MSHR miss cycles 126411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19308557500 # number of InvalidateReq MSHR miss cycles 126511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of demand (read+write) MSHR miss cycles 126611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 272683000 # number of demand (read+write) MSHR miss cycles 126711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19633488000 # number of demand (read+write) MSHR miss cycles 126811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38711863493 # number of demand (read+write) MSHR miss cycles 126911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 59113720493 # number of demand (read+write) MSHR miss cycles 127011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of overall MSHR miss cycles 127111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 272683000 # number of overall MSHR miss cycles 127211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19633488000 # number of overall MSHR miss cycles 127311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38711863493 # number of overall MSHR miss cycles 127411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of overall MSHR miss cycles 127511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 97499395040 # number of overall MSHR miss cycles 127611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles 127711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3849707000 # number of ReadReq MSHR uncacheable cycles 127811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8268091500 # number of ReadReq MSHR uncacheable cycles 127911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles 128011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3849707000 # number of overall MSHR uncacheable cycles 128111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8268091500 # number of overall MSHR uncacheable cycles 128211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for ReadReq accesses 128311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for ReadReq accesses 128411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 128510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 128610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 128711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 128811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 128911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 129011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 129110636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 129210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 129311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.230062 # mshr miss rate for ReadExReq accesses 129411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.230062 # mshr miss rate for ReadExReq accesses 129511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for ReadCleanReq accesses 129611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073593 # mshr miss rate for ReadCleanReq accesses 129711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261534 # mshr miss rate for ReadSharedReq accesses 129811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261534 # mshr miss rate for ReadSharedReq accesses 129911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.742235 # mshr miss rate for InvalidateReq accesses 130011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.742235 # mshr miss rate for InvalidateReq accesses 130111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for demand accesses 130211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for demand accesses 130311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for demand accesses 130411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for demand accesses 130511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.130924 # mshr miss rate for demand accesses 130611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for overall accesses 130711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for overall accesses 130811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for overall accesses 130911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for overall accesses 131010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 131111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.183830 # mshr miss rate for overall accesses 131211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average ReadReq mshr miss latency 131311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average ReadReq mshr miss latency 131411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520 # average ReadReq mshr miss latency 131511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average HardPFReq mshr miss latency 131611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698 # average HardPFReq mshr miss latency 131711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019 # average UpgradeReq mshr miss latency 131811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019 # average UpgradeReq mshr miss latency 131911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034 # average SCUpgradeReq mshr miss latency 132011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034 # average SCUpgradeReq mshr miss latency 132111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333 # average SCUpgradeFailReq mshr miss latency 132211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333 # average SCUpgradeFailReq mshr miss latency 132311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067 # average ReadExReq mshr miss latency 132411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067 # average ReadExReq mshr miss latency 132511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average ReadCleanReq mshr miss latency 132611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005 # average ReadCleanReq mshr miss latency 132711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946 # average ReadSharedReq mshr miss latency 132811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946 # average ReadSharedReq mshr miss latency 132911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784 # average InvalidateReq mshr miss latency 133011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784 # average InvalidateReq mshr miss latency 133111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency 133211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency 133311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency 133411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency 133511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615 # average overall mshr miss latency 133611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency 133711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency 133811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency 133911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency 134011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average overall mshr miss latency 134111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134 # average overall mshr miss latency 134211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency 134311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785 # average ReadReq mshr uncacheable latency 134411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896 # average ReadReq mshr uncacheable latency 134511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency 134611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962 # average overall mshr uncacheable latency 134711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825 # average overall mshr uncacheable latency 134811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 30377137 # Total number of requests made to the snoop filter. 134911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 15497883 # Number of requests hitting in the snoop filter with a single holder of the requested data. 135011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2826 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 135111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 666100 # Total number of snoops made to the snoop filter. 135211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 666086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 135311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 135411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 135511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 826394 # Transaction distribution 135611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13852976 # Transaction distribution 135711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 135811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 22275 # Transaction distribution 135911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 22275 # Transaction distribution 136011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5277668 # Transaction distribution 136111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11102490 # Transaction distribution 136211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1369040 # Transaction distribution 136311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 998456 # Transaction distribution 136411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 452524 # Transaction distribution 136511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330100 # Transaction distribution 136611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 496609 # Transaction distribution 136711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 136811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 136911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1203701 # Transaction distribution 137011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1179860 # Transaction distribution 137111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9281130 # Transaction distribution 137211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4723846 # Transaction distribution 137311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 838465 # Transaction distribution 137411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 784086 # Transaction distribution 137511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 27947466 # Packet count per connected master and slave (bytes) 137611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17813968 # Packet count per connected master and slave (bytes) 137711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 344869 # Packet count per connected master and slave (bytes) 137811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1089699 # Packet count per connected master and slave (bytes) 137911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count::total 47196002 # Packet count per connected master and slave (bytes) 138011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1191298304 # Cumulative packet size per connected master and slave (bytes) 138111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 667170422 # Cumulative packet size per connected master and slave (bytes) 138211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1315256 # Cumulative packet size per connected master and slave (bytes) 138311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4133624 # Cumulative packet size per connected master and slave (bytes) 138411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1863917606 # Cumulative packet size per connected master and slave (bytes) 138511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoops 5747559 # Total snoops (count) 138611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopTraffic 110232304 # Total snoop traffic (bytes) 138711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 21648150 # Request fanout histogram 138811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.044453 # Request fanout histogram 138911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.206103 # Request fanout histogram 139010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 139111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 20685836 95.55% 95.55% # Request fanout histogram 139211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 962300 4.45% 100.00% # Request fanout histogram 139311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram 139410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 139511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 139610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 139711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 21648150 # Request fanout histogram 139811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 30255355989 # Layer occupancy (ticks) 139911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 140011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 202143120 # Layer occupancy (ticks) 140110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 140211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14002739292 # Layer occupancy (ticks) 140310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 140411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7861824025 # Layer occupancy (ticks) 140510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 140611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 180564794 # Layer occupancy (ticks) 140710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 140811606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 573087816 # Layer occupancy (ticks) 140910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 141011606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.lookups 142890193 # Number of BP lookups 141111606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.condPredicted 101173603 # Number of conditional branches predicted 141211606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.condIncorrect 6378415 # Number of conditional branches incorrect 141311606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.BTBLookups 107083119 # Number of BTB lookups 141411606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.BTBHits 74895456 # Number of BTB hits 141510585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 141611606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.BTBHitPct 69.941422 # BTB Hit Percentage 141711606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.usedRAS 16732142 # Number of times the RAS was used to get a target. 141811606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.RASInCorrect 1061167 # Number of incorrect RAS predictions. 141911606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.indirectLookups 3812146 # Number of indirect predictor lookups. 142011606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.indirectHits 2601182 # Number of indirect target hits. 142111606Sandreas.sandberg@arm.comsystem.cpu1.branchPred.indirectMisses 1210964 # Number of indirect misses. 142211606Sandreas.sandberg@arm.comsystem.cpu1.branchPredindirectMispredicted 435637 # Number of mispredicted indirect branches. 142311606Sandreas.sandberg@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 142410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 142610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 142710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 142810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 142910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 143110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 143210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 143310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 143410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 143510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 143610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 143710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 143810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 143910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 144310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 144410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 144510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 144610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 144710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 144810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 144910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 145010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 145110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 145210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 145311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 145411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walks 301450 # Table walker walks requested 145511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLong 301450 # Table walker walks initiated with long descriptors 145611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14052 # Level at which table walker walks with long descriptors terminate 145711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94528 # Level at which table walker walks with long descriptors terminate 145811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 301450 # Table walker wait (enqueue to first request) latency 145911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 301450 100.00% 100.00% # Table walker wait (enqueue to first request) latency 146011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 301450 # Table walker wait (enqueue to first request) latency 146111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 108580 # Table walker service (enqueue to completion) latency 146211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294 # Table walker service (enqueue to completion) latency 146311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975 # Table walker service (enqueue to completion) latency 146411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293 # Table walker service (enqueue to completion) latency 146511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 107036 98.58% 98.58% # Table walker service (enqueue to completion) latency 146611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1312 1.21% 99.79% # Table walker service (enqueue to completion) latency 146711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 57 0.05% 99.84% # Table walker service (enqueue to completion) latency 146811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.06% 99.90% # Table walker service (enqueue to completion) latency 146911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 74 0.07% 99.97% # Table walker service (enqueue to completion) latency 147011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency 147111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 147211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 147311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 147411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 108580 # Table walker service (enqueue to completion) latency 147511606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::samples -588118056 # Table walker pending requests distribution 147611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::0 -588118056 100.00% 100.00% # Table walker pending requests distribution 147711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::total -588118056 # Table walker pending requests distribution 147811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 94528 87.06% 87.06% # Table walker page sizes translated 147911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14052 12.94% 100.00% # Table walker page sizes translated 148011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 108580 # Table walker page sizes translated 148111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 301450 # Table walker requests started/completed, data/inst 148210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 301450 # Table walker requests started/completed, data/inst 148411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108580 # Table walker requests started/completed, data/inst 148510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 148611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108580 # Table walker requests started/completed, data/inst 148711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 410030 # Table walker requests started/completed, data/inst 148810585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 148910585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 149011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_hits 92214946 # DTB read hits 149111606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_misses 251350 # DTB read misses 149211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_hits 79863458 # DTB write hits 149311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_misses 50100 # DTB write misses 149411441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 149510585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 149711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 149811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_entries 41485 # Number of entries that have been flushed from TLB 149911606Sandreas.sandberg@arm.comsystem.cpu1.dtb.align_faults 1017 # Number of TLB faults due to alignment restrictions 150011606Sandreas.sandberg@arm.comsystem.cpu1.dtb.prefetch_faults 8355 # Number of TLB faults due to prefetch 150110585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 150211606Sandreas.sandberg@arm.comsystem.cpu1.dtb.perms_faults 11459 # Number of TLB faults due to permissions restrictions 150311606Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_accesses 92466296 # DTB read accesses 150411606Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_accesses 79913558 # DTB write accesses 150510585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 150611606Sandreas.sandberg@arm.comsystem.cpu1.dtb.hits 172078404 # DTB hits 150711606Sandreas.sandberg@arm.comsystem.cpu1.dtb.misses 301450 # DTB misses 150811606Sandreas.sandberg@arm.comsystem.cpu1.dtb.accesses 172379854 # DTB accesses 150911606Sandreas.sandberg@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 151010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 151110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 151310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 151410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 151510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 151710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 151810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 151910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 152010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 152110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 152210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 152310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 152410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 152510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 152610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 152710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 152810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 152910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 153010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 153110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 153210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 153410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 153510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 153610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 153710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 153810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 154011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walks 68405 # Table walker walks requested 154111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLong 68405 # Table walker walks initiated with long descriptors 154211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 536 # Level at which table walker walks with long descriptors terminate 154311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 57692 # Level at which table walker walks with long descriptors terminate 154411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 68405 # Table walker wait (enqueue to first request) latency 154511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 68405 100.00% 100.00% # Table walker wait (enqueue to first request) latency 154611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 68405 # Table walker wait (enqueue to first request) latency 154711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 58228 # Table walker service (enqueue to completion) latency 154811606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26184.473106 # Table walker service (enqueue to completion) latency 154911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832 # Table walker service (enqueue to completion) latency 155011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639 # Table walker service (enqueue to completion) latency 155111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 52664 90.44% 90.44% # Table walker service (enqueue to completion) latency 155211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 3935 6.76% 97.20% # Table walker service (enqueue to completion) latency 155311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 14 0.02% 97.23% # Table walker service (enqueue to completion) latency 155411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 1454 2.50% 99.72% # Table walker service (enqueue to completion) latency 155511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency 155611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.82% # Table walker service (enqueue to completion) latency 155711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 63 0.11% 99.93% # Table walker service (enqueue to completion) latency 155811606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 12 0.02% 99.95% # Table walker service (enqueue to completion) latency 155911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 10 0.02% 99.96% # Table walker service (enqueue to completion) latency 156011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 156111606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 156211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 156311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 156411606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 58228 # Table walker service (enqueue to completion) latency 156511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::samples -588816556 # Table walker pending requests distribution 156611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::0 -588816556 100.00% 100.00% # Table walker pending requests distribution 156711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksPending::total -588816556 # Table walker pending requests distribution 156811606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 57692 99.08% 99.08% # Table walker page sizes translated 156911606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 536 0.92% 100.00% # Table walker page sizes translated 157011606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 58228 # Table walker page sizes translated 157110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 157211606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68405 # Table walker requests started/completed, data/inst 157311606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 68405 # Table walker requests started/completed, data/inst 157410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 157511606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58228 # Table walker requests started/completed, data/inst 157611606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 58228 # Table walker requests started/completed, data/inst 157711606Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 126633 # Table walker requests started/completed, data/inst 157811606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_hits 253981708 # ITB inst hits 157911606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_misses 68405 # ITB inst misses 158010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 158110585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 158210585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 158310585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 158411441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 158510585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 158611606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 158711606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 158811606Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_entries 29878 # Number of entries that have been flushed from TLB 158910585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 159010585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 159110585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 159211606Sandreas.sandberg@arm.comsystem.cpu1.itb.perms_faults 186858 # Number of TLB faults due to permissions restrictions 159310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 159410585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 159511606Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_accesses 254050113 # ITB inst accesses 159611606Sandreas.sandberg@arm.comsystem.cpu1.itb.hits 253981708 # DTB hits 159711606Sandreas.sandberg@arm.comsystem.cpu1.itb.misses 68405 # DTB misses 159811606Sandreas.sandberg@arm.comsystem.cpu1.itb.accesses 254050113 # DTB accesses 159911606Sandreas.sandberg@arm.comsystem.cpu1.numPwrStateTransitions 29008 # Number of power state transitions 160011606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::samples 14504 # Distribution of time spent in the clock gated state 160111606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::mean 3226000342.121070 # Distribution of time spent in the clock gated state 160211606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 122202778079.734619 # Distribution of time spent in the clock gated state 160311606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4515 31.13% 31.13% # Distribution of time spent in the clock gated state 160411606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 9966 68.71% 99.84% # Distribution of time spent in the clock gated state 160511606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.89% # Distribution of time spent in the clock gated state 160611606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.91% # Distribution of time spent in the clock gated state 160711606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 160811606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 160911606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state 161011606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state 161111570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 161211606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813587669000 # Distribution of time spent in the clock gated state 161311606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::total 14504 # Distribution of time spent in the clock gated state 161411606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 486863864876 # Cumulative time (in ticks) in various power states 161511606Sandreas.sandberg@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124 # Cumulative time (in ticks) in various power states 161611606Sandreas.sandberg@arm.comsystem.cpu1.numCycles 973770006 # number of cpu cycles simulated 161710585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 161810585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 161911606Sandreas.sandberg@arm.comsystem.cpu1.committedInsts 467062034 # Number of instructions committed 162011606Sandreas.sandberg@arm.comsystem.cpu1.committedOps 549524480 # Number of ops (including micro ops) committed 162111606Sandreas.sandberg@arm.comsystem.cpu1.discardedOps 49354477 # Number of ops (including micro ops) which were discarded before commit 162211606Sandreas.sandberg@arm.comsystem.cpu1.numFetchSuspends 5829 # Number of times Execute suspended instruction fetching 162311606Sandreas.sandberg@arm.comsystem.cpu1.quiesceCycles 93580668477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 162411606Sandreas.sandberg@arm.comsystem.cpu1.cpi 2.084884 # CPI: cycles per instruction 162511606Sandreas.sandberg@arm.comsystem.cpu1.ipc 0.479643 # IPC: instructions per cycle 162611606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 162711606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::IntAlu 379758717 69.11% 69.11% # Class of committed instruction 162811606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::IntMult 1174710 0.21% 69.32% # Class of committed instruction 162911606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::IntDiv 62873 0.01% 69.33% # Class of committed instruction 163011606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction 163111606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction 163211606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction 163311606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction 163411606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction 163511606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction 163611606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction 163711606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction 163811606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction 163911606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction 164011606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction 164111606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction 164211606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction 164311606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction 164411606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction 164511606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction 164611606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction 164711606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction 164811606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction 164911606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction 165011606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction 165111606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction 165211606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 42788 0.01% 69.34% # Class of committed instruction 165311606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction 165411606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction 165511606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction 165611606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::MemRead 88942339 16.19% 85.53% # Class of committed instruction 165711606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::MemWrite 79543053 14.47% 100.00% # Class of committed instruction 165811441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 165911441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 166011606Sandreas.sandberg@arm.comsystem.cpu1.op_class_0::total 549524480 # Class of committed instruction 166110585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 166211606Sandreas.sandberg@arm.comsystem.cpu1.kern.inst.quiesce 14504 # number of quiesce instructions executed 166311606Sandreas.sandberg@arm.comsystem.cpu1.tickCycles 754340504 # Number of cycles that the object actually ticked 166411606Sandreas.sandberg@arm.comsystem.cpu1.idleCycles 219429502 # Total number of cycles that the object has spent stopped 166511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 166611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.replacements 5584308 # number of replacements 166711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tagsinuse 440.375822 # Cycle average of tags in use 166811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.total_refs 163963779 # Total number of references to valid blocks. 166911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.sampled_refs 5584818 # Sample count of references to valid blocks. 167011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.avg_refs 29.358840 # Average number of references to valid blocks. 167111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8377741807000 # Cycle when the warmup percentage was hit. 167211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 440.375822 # Average occupied blocks per requestor 167311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.860109 # Average percentage of cache occupancy 167411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.860109 # Average percentage of cache occupancy 167511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 167611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 167711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 167811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 234 # Occupied blocks per task id 167911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 168011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tag_accesses 347150058 # Number of tag accesses 168111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.data_accesses 347150058 # Number of data accesses 168211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 168311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 84821089 # number of ReadReq hits 168411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::total 84821089 # number of ReadReq hits 168511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 74565342 # number of WriteReq hits 168611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 74565342 # number of WriteReq hits 168711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 240493 # number of SoftPFReq hits 168811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 240493 # number of SoftPFReq hits 168911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 73857 # number of WriteLineReq hits 169011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 73857 # number of WriteLineReq hits 169111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1888770 # number of LoadLockedReq hits 169211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1888770 # number of LoadLockedReq hits 169311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1879546 # number of StoreCondReq hits 169411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1879546 # number of StoreCondReq hits 169511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 159460288 # number of demand (read+write) hits 169611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 159460288 # number of demand (read+write) hits 169711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 159700781 # number of overall hits 169811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 159700781 # number of overall hits 169911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3413550 # number of ReadReq misses 170011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3413550 # number of ReadReq misses 170111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2348662 # number of WriteReq misses 170211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2348662 # number of WriteReq misses 170311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 664960 # number of SoftPFReq misses 170411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 664960 # number of SoftPFReq misses 170511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 462804 # number of WriteLineReq misses 170611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 462804 # number of WriteLineReq misses 170711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186013 # number of LoadLockedReq misses 170811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 186013 # number of LoadLockedReq misses 170911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 193851 # number of StoreCondReq misses 171011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 193851 # number of StoreCondReq misses 171111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 6225016 # number of demand (read+write) misses 171211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 6225016 # number of demand (read+write) misses 171311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6889976 # number of overall misses 171411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 6889976 # number of overall misses 171511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52244752500 # number of ReadReq miss cycles 171611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 52244752500 # number of ReadReq miss cycles 171711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 43500498500 # number of WriteReq miss cycles 171811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 43500498500 # number of WriteReq miss cycles 171911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11517052000 # number of WriteLineReq miss cycles 172011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 11517052000 # number of WriteLineReq miss cycles 172111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2853085500 # number of LoadLockedReq miss cycles 172211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2853085500 # number of LoadLockedReq miss cycles 172311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4630433000 # number of StoreCondReq miss cycles 172411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4630433000 # number of StoreCondReq miss cycles 172511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2585500 # number of StoreCondFailReq miss cycles 172611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2585500 # number of StoreCondFailReq miss cycles 172711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000 # number of demand (read+write) miss cycles 172811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::total 107262303000 # number of demand (read+write) miss cycles 172911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000 # number of overall miss cycles 173011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::total 107262303000 # number of overall miss cycles 173111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 88234639 # number of ReadReq accesses(hits+misses) 173211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 88234639 # number of ReadReq accesses(hits+misses) 173311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 76914004 # number of WriteReq accesses(hits+misses) 173411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 76914004 # number of WriteReq accesses(hits+misses) 173511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 905453 # number of SoftPFReq accesses(hits+misses) 173611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 905453 # number of SoftPFReq accesses(hits+misses) 173711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 536661 # number of WriteLineReq accesses(hits+misses) 173811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 536661 # number of WriteLineReq accesses(hits+misses) 173911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074783 # number of LoadLockedReq accesses(hits+misses) 174011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2074783 # number of LoadLockedReq accesses(hits+misses) 174111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2073397 # number of StoreCondReq accesses(hits+misses) 174211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2073397 # number of StoreCondReq accesses(hits+misses) 174311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 165685304 # number of demand (read+write) accesses 174411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::total 165685304 # number of demand (read+write) accesses 174511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 166590757 # number of overall (read+write) accesses 174611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::total 166590757 # number of overall (read+write) accesses 174711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038687 # miss rate for ReadReq accesses 174811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038687 # miss rate for ReadReq accesses 174911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030536 # miss rate for WriteReq accesses 175011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.030536 # miss rate for WriteReq accesses 175111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.734395 # miss rate for SoftPFReq accesses 175211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.734395 # miss rate for SoftPFReq accesses 175311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.862377 # miss rate for WriteLineReq accesses 175411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.862377 # miss rate for WriteLineReq accesses 175511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089654 # miss rate for LoadLockedReq accesses 175611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089654 # miss rate for LoadLockedReq accesses 175711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.093494 # miss rate for StoreCondReq accesses 175811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.093494 # miss rate for StoreCondReq accesses 175911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.037571 # miss rate for demand accesses 176011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.037571 # miss rate for demand accesses 176111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.041359 # miss rate for overall accesses 176211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.041359 # miss rate for overall accesses 176311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318 # average ReadReq miss latency 176411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318 # average ReadReq miss latency 176511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799 # average WriteReq miss latency 176611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799 # average WriteReq miss latency 176711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963 # average WriteLineReq miss latency 176811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963 # average WriteLineReq miss latency 176911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337 # average LoadLockedReq miss latency 177011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337 # average LoadLockedReq miss latency 177111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201 # average StoreCondReq miss latency 177211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201 # average StoreCondReq miss latency 177310636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 177410585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 177511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760 # average overall miss latency 177611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17230.847760 # average overall miss latency 177711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595 # average overall miss latency 177811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15567.877595 # average overall miss latency 177910585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178110585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178210585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 178310585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178410585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 178511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 5584335 # number of writebacks 178611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 5584335 # number of writebacks 178711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169267 # number of ReadReq MSHR hits 178811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 169267 # number of ReadReq MSHR hits 178911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 957224 # number of WriteReq MSHR hits 179011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 957224 # number of WriteReq MSHR hits 179111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 179211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 179311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44866 # number of LoadLockedReq MSHR hits 179411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44866 # number of LoadLockedReq MSHR hits 179511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 87 # number of StoreCondReq MSHR hits 179611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 87 # number of StoreCondReq MSHR hits 179711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1126549 # number of demand (read+write) MSHR hits 179811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1126549 # number of demand (read+write) MSHR hits 179911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1126549 # number of overall MSHR hits 180011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1126549 # number of overall MSHR hits 180111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3244283 # number of ReadReq MSHR misses 180211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3244283 # number of ReadReq MSHR misses 180311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1391438 # number of WriteReq MSHR misses 180411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1391438 # number of WriteReq MSHR misses 180511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664681 # number of SoftPFReq MSHR misses 180611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 664681 # number of SoftPFReq MSHR misses 180711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462746 # number of WriteLineReq MSHR misses 180811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 462746 # number of WriteLineReq MSHR misses 180911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141147 # number of LoadLockedReq MSHR misses 181011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 141147 # number of LoadLockedReq MSHR misses 181111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193764 # number of StoreCondReq MSHR misses 181211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 193764 # number of StoreCondReq MSHR misses 181311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 5098467 # number of demand (read+write) MSHR misses 181411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5098467 # number of demand (read+write) MSHR misses 181511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5763148 # number of overall MSHR misses 181611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5763148 # number of overall MSHR misses 181711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable 181811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 17608 # number of ReadReq MSHR uncacheable 181911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 182011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable 182111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses 182211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 33461 # number of overall MSHR uncacheable misses 182311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45298654500 # number of ReadReq MSHR miss cycles 182411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 45298654500 # number of ReadReq MSHR miss cycles 182511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 25106196000 # number of WriteReq MSHR miss cycles 182611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 25106196000 # number of WriteReq MSHR miss cycles 182711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14639124500 # number of SoftPFReq MSHR miss cycles 182811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14639124500 # number of SoftPFReq MSHR miss cycles 182911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11050641000 # number of WriteLineReq MSHR miss cycles 183011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11050641000 # number of WriteLineReq MSHR miss cycles 183111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1898988000 # number of LoadLockedReq MSHR miss cycles 183211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1898988000 # number of LoadLockedReq MSHR miss cycles 183311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4434665000 # number of StoreCondReq MSHR miss cycles 183411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4434665000 # number of StoreCondReq MSHR miss cycles 183511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2119500 # number of StoreCondFailReq MSHR miss cycles 183611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2119500 # number of StoreCondFailReq MSHR miss cycles 183711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81455491500 # number of demand (read+write) MSHR miss cycles 183811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 81455491500 # number of demand (read+write) MSHR miss cycles 183911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 96094616000 # number of overall MSHR miss cycles 184011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 96094616000 # number of overall MSHR miss cycles 184111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2936127500 # number of ReadReq MSHR uncacheable cycles 184211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2936127500 # number of ReadReq MSHR uncacheable cycles 184311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2936127500 # number of overall MSHR uncacheable cycles 184411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 2936127500 # number of overall MSHR uncacheable cycles 184511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036769 # mshr miss rate for ReadReq accesses 184611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036769 # mshr miss rate for ReadReq accesses 184711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses 184811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses 184911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.734087 # mshr miss rate for SoftPFReq accesses 185011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.734087 # mshr miss rate for SoftPFReq accesses 185111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.862269 # mshr miss rate for WriteLineReq accesses 185211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.862269 # mshr miss rate for WriteLineReq accesses 185311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068030 # mshr miss rate for LoadLockedReq accesses 185411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068030 # mshr miss rate for LoadLockedReq accesses 185511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.093452 # mshr miss rate for StoreCondReq accesses 185611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.093452 # mshr miss rate for StoreCondReq accesses 185711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for demand accesses 185811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030772 # mshr miss rate for demand accesses 185911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034595 # mshr miss rate for overall accesses 186011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034595 # mshr miss rate for overall accesses 186111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841 # average ReadReq mshr miss latency 186211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841 # average ReadReq mshr miss latency 186311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086 # average WriteReq mshr miss latency 186411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086 # average WriteReq mshr miss latency 186511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086 # average SoftPFReq mshr miss latency 186611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086 # average SoftPFReq mshr miss latency 186711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953 # average WriteLineReq mshr miss latency 186811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953 # average WriteLineReq mshr miss latency 186911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517 # average LoadLockedReq mshr miss latency 187011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517 # average LoadLockedReq mshr miss latency 187111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782 # average StoreCondReq mshr miss latency 187211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782 # average StoreCondReq mshr miss latency 187310636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 187410585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 187511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338 # average overall mshr miss latency 187611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338 # average overall mshr miss latency 187711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262 # average overall mshr miss latency 187811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262 # average overall mshr miss latency 187911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850 # average ReadReq mshr uncacheable latency 188011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850 # average ReadReq mshr uncacheable latency 188111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113 # average overall mshr uncacheable latency 188211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113 # average overall mshr uncacheable latency 188311606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 188411606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.replacements 9521452 # number of replacements 188511606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tagsinuse 507.043038 # Cycle average of tags in use 188611606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.total_refs 244267020 # Total number of references to valid blocks. 188711606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.sampled_refs 9521964 # Sample count of references to valid blocks. 188811606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.avg_refs 25.653008 # Average number of references to valid blocks. 188911606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.warmup_cycle 8368158607000 # Cycle when the warmup percentage was hit. 189011606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.043038 # Average occupied blocks per requestor 189111606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990318 # Average percentage of cache occupancy 189211606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990318 # Average percentage of cache occupancy 189310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 189411606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id 189511606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 189611606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 189710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 189811606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tag_accesses 517099934 # Number of tag accesses 189911606Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.data_accesses 517099934 # Number of data accesses 190011606Sandreas.sandberg@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 190111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 244267020 # number of ReadReq hits 190211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::total 244267020 # number of ReadReq hits 190311606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 244267020 # number of demand (read+write) hits 190411606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::total 244267020 # number of demand (read+write) hits 190511606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 244267020 # number of overall hits 190611606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::total 244267020 # number of overall hits 190711606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9521965 # number of ReadReq misses 190811606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::total 9521965 # number of ReadReq misses 190911606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9521965 # number of demand (read+write) misses 191011606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::total 9521965 # number of demand (read+write) misses 191111606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9521965 # number of overall misses 191211606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::total 9521965 # number of overall misses 191311606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96688620500 # number of ReadReq miss cycles 191411606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 96688620500 # number of ReadReq miss cycles 191511606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 96688620500 # number of demand (read+write) miss cycles 191611606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::total 96688620500 # number of demand (read+write) miss cycles 191711606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 96688620500 # number of overall miss cycles 191811606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::total 96688620500 # number of overall miss cycles 191911606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 253788985 # number of ReadReq accesses(hits+misses) 192011606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::total 253788985 # number of ReadReq accesses(hits+misses) 192111606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 253788985 # number of demand (read+write) accesses 192211606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::total 253788985 # number of demand (read+write) accesses 192311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 253788985 # number of overall (read+write) accesses 192411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::total 253788985 # number of overall (read+write) accesses 192511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037519 # miss rate for ReadReq accesses 192611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.037519 # miss rate for ReadReq accesses 192711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.037519 # miss rate for demand accesses 192811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.037519 # miss rate for demand accesses 192911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.037519 # miss rate for overall accesses 193011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.037519 # miss rate for overall accesses 193111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781 # average ReadReq miss latency 193211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781 # average ReadReq miss latency 193311606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency 193411606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10154.271781 # average overall miss latency 193511606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency 193611606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10154.271781 # average overall miss latency 193710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 193910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 194110585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 194210585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194311606Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::writebacks 9521452 # number of writebacks 194411606Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::total 9521452 # number of writebacks 194511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9521965 # number of ReadReq MSHR misses 194611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9521965 # number of ReadReq MSHR misses 194711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9521965 # number of demand (read+write) MSHR misses 194811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9521965 # number of demand (read+write) MSHR misses 194911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9521965 # number of overall MSHR misses 195011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9521965 # number of overall MSHR misses 195111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 195211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 195311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 195411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 195511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91927638500 # number of ReadReq MSHR miss cycles 195611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 91927638500 # number of ReadReq MSHR miss cycles 195711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91927638500 # number of demand (read+write) MSHR miss cycles 195811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 91927638500 # number of demand (read+write) MSHR miss cycles 195911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91927638500 # number of overall MSHR miss cycles 196011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 91927638500 # number of overall MSHR miss cycles 196111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9070500 # number of ReadReq MSHR uncacheable cycles 196211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9070500 # number of ReadReq MSHR uncacheable cycles 196311606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9070500 # number of overall MSHR uncacheable cycles 196411606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 9070500 # number of overall MSHR uncacheable cycles 196511606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for ReadReq accesses 196611606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037519 # mshr miss rate for ReadReq accesses 196711606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for demand accesses 196811606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.037519 # mshr miss rate for demand accesses 196911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for overall accesses 197011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.037519 # mshr miss rate for overall accesses 197111606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average ReadReq mshr miss latency 197211606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9654.271834 # average ReadReq mshr miss latency 197311606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency 197411606Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency 197511606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency 197611606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency 197711606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average ReadReq mshr uncacheable latency 197811606Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368 # average ReadReq mshr uncacheable latency 197911606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average overall mshr uncacheable latency 198011606Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368 # average overall mshr uncacheable latency 198111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 198211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7586302 # number of hwpf issued 198311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7586460 # number of prefetch candidates identified 198411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 136 # number of redundant prefetches already in prefetch queue 198510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 198610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 198711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 987804 # number of prefetches not generated due to page crossing 198811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 198911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.replacements 2406613 # number of replacements 199011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13125.467163 # Cycle average of tags in use 199111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.total_refs 13856134 # Total number of references to valid blocks. 199211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2421819 # Sample count of references to valid blocks. 199311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.721375 # Average number of references to valid blocks. 199411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806 # Average occupied blocks per requestor 199611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.086630 # Average occupied blocks per requestor 199711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.305413 # Average occupied blocks per requestor 199811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 234.798314 # Average occupied blocks per requestor 199911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.784258 # Average percentage of cache occupancy 200011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001653 # Average percentage of cache occupancy 200111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000873 # Average percentage of cache occupancy 200211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014331 # Average percentage of cache occupancy 200311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.801115 # Average percentage of cache occupancy 200411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id 200511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 200611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14856 # Occupied blocks per task id 200711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 200811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 106 # Occupied blocks per task id 200911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 108 # Occupied blocks per task id 201011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 47 # Occupied blocks per task id 201111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 201211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id 201311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 201411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 201511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id 201611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 743 # Occupied blocks per task id 201711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6180 # Occupied blocks per task id 201811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6756 # Occupied blocks per task id 201911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 775 # Occupied blocks per task id 202011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id 202111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 202211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.906738 # Percentage of cache occupancy per task id 202311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tag_accesses 519862521 # Number of tag accesses 202411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.data_accesses 519862521 # Number of data accesses 202511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 202611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 578094 # number of ReadReq hits 202711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 171981 # number of ReadReq hits 202811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 750075 # number of ReadReq hits 202911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3464322 # number of WritebackDirty hits 203011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3464322 # number of WritebackDirty hits 203111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 11639503 # number of WritebackClean hits 203211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 11639503 # number of WritebackClean hits 203311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 901874 # number of ReadExReq hits 203411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 901874 # number of ReadExReq hits 203511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8781698 # number of ReadCleanReq hits 203611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8781698 # number of ReadCleanReq hits 203711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3023137 # number of ReadSharedReq hits 203811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3023137 # number of ReadSharedReq hits 203911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191670 # number of InvalidateReq hits 204011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 191670 # number of InvalidateReq hits 204111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 578094 # number of demand (read+write) hits 204211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 171981 # number of demand (read+write) hits 204311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8781698 # number of demand (read+write) hits 204411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3925011 # number of demand (read+write) hits 204511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::total 13456784 # number of demand (read+write) hits 204611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 578094 # number of overall hits 204711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 171981 # number of overall hits 204811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8781698 # number of overall hits 204911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3925011 # number of overall hits 205011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::total 13456784 # number of overall hits 205111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22586 # number of ReadReq misses 205211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11050 # number of ReadReq misses 205311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 33636 # number of ReadReq misses 205411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 232349 # number of UpgradeReq misses 205511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 232349 # number of UpgradeReq misses 205611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193761 # number of SCUpgradeReq misses 205711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 193761 # number of SCUpgradeReq misses 205811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 205911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 206011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 259533 # number of ReadExReq misses 206111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 259533 # number of ReadExReq misses 206211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 740267 # number of ReadCleanReq misses 206311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 740267 # number of ReadCleanReq misses 206411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1026659 # number of ReadSharedReq misses 206511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1026659 # number of ReadSharedReq misses 206611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 269262 # number of InvalidateReq misses 206711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 269262 # number of InvalidateReq misses 206811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22586 # number of demand (read+write) misses 206911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 11050 # number of demand (read+write) misses 207011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 740267 # number of demand (read+write) misses 207111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1286192 # number of demand (read+write) misses 207211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::total 2060095 # number of demand (read+write) misses 207311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22586 # number of overall misses 207411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 11050 # number of overall misses 207511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 740267 # number of overall misses 207611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1286192 # number of overall misses 207711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::total 2060095 # number of overall misses 207811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 726971000 # number of ReadReq miss cycles 207911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 437240000 # number of ReadReq miss cycles 208011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1164211000 # number of ReadReq miss cycles 208111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 947721000 # number of UpgradeReq miss cycles 208211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 947721000 # number of UpgradeReq miss cycles 208311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273329000 # number of SCUpgradeReq miss cycles 208411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273329000 # number of SCUpgradeReq miss cycles 208511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2036499 # number of SCUpgradeFailReq miss cycles 208611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2036499 # number of SCUpgradeFailReq miss cycles 208711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11444500498 # number of ReadExReq miss cycles 208811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11444500498 # number of ReadExReq miss cycles 208911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24621036000 # number of ReadCleanReq miss cycles 209011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 24621036000 # number of ReadCleanReq miss cycles 209111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 35849827996 # number of ReadSharedReq miss cycles 209211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 35849827996 # number of ReadSharedReq miss cycles 209311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 304696500 # number of InvalidateReq miss cycles 209411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 304696500 # number of InvalidateReq miss cycles 209511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 726971000 # number of demand (read+write) miss cycles 209611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 437240000 # number of demand (read+write) miss cycles 209711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 24621036000 # number of demand (read+write) miss cycles 209811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 47294328494 # number of demand (read+write) miss cycles 209911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 73079575494 # number of demand (read+write) miss cycles 210011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 726971000 # number of overall miss cycles 210111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 437240000 # number of overall miss cycles 210211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 24621036000 # number of overall miss cycles 210311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 47294328494 # number of overall miss cycles 210411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 73079575494 # number of overall miss cycles 210511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 600680 # number of ReadReq accesses(hits+misses) 210611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 183031 # number of ReadReq accesses(hits+misses) 210711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 783711 # number of ReadReq accesses(hits+misses) 210811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3464322 # number of WritebackDirty accesses(hits+misses) 210911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3464322 # number of WritebackDirty accesses(hits+misses) 211011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 11639503 # number of WritebackClean accesses(hits+misses) 211111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 11639503 # number of WritebackClean accesses(hits+misses) 211211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232349 # number of UpgradeReq accesses(hits+misses) 211311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 232349 # number of UpgradeReq accesses(hits+misses) 211411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193761 # number of SCUpgradeReq accesses(hits+misses) 211511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 193761 # number of SCUpgradeReq accesses(hits+misses) 211611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 211711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 211811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1161407 # number of ReadExReq accesses(hits+misses) 211911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1161407 # number of ReadExReq accesses(hits+misses) 212011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9521965 # number of ReadCleanReq accesses(hits+misses) 212111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9521965 # number of ReadCleanReq accesses(hits+misses) 212211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4049796 # number of ReadSharedReq accesses(hits+misses) 212311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4049796 # number of ReadSharedReq accesses(hits+misses) 212411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 460932 # number of InvalidateReq accesses(hits+misses) 212511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 460932 # number of InvalidateReq accesses(hits+misses) 212611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 600680 # number of demand (read+write) accesses 212711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 183031 # number of demand (read+write) accesses 212811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9521965 # number of demand (read+write) accesses 212911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5211203 # number of demand (read+write) accesses 213011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::total 15516879 # number of demand (read+write) accesses 213111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 600680 # number of overall (read+write) accesses 213211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 183031 # number of overall (read+write) accesses 213311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9521965 # number of overall (read+write) accesses 213411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5211203 # number of overall (read+write) accesses 213511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::total 15516879 # number of overall (read+write) accesses 213611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for ReadReq accesses 213711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.060372 # miss rate for ReadReq accesses 213811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.042919 # miss rate for ReadReq accesses 213911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 214011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 214111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 214211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 214310636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 214410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 214511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.223464 # miss rate for ReadExReq accesses 214611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.223464 # miss rate for ReadExReq accesses 214711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077743 # miss rate for ReadCleanReq accesses 214811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077743 # miss rate for ReadCleanReq accesses 214911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253509 # miss rate for ReadSharedReq accesses 215011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253509 # miss rate for ReadSharedReq accesses 215111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584169 # miss rate for InvalidateReq accesses 215211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584169 # miss rate for InvalidateReq accesses 215311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for demand accesses 215411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.060372 # miss rate for demand accesses 215511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077743 # miss rate for demand accesses 215611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246813 # miss rate for demand accesses 215711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.132765 # miss rate for demand accesses 215811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for overall accesses 215911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.060372 # miss rate for overall accesses 216011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077743 # miss rate for overall accesses 216111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246813 # miss rate for overall accesses 216211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.132765 # miss rate for overall accesses 216311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average ReadReq miss latency 216411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39569.230769 # average ReadReq miss latency 216511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 34612.052563 # average ReadReq miss latency 216611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4078.868426 # average UpgradeReq miss latency 216711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4078.868426 # average UpgradeReq miss latency 216811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1410.650234 # average SCUpgradeReq miss latency 216911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1410.650234 # average SCUpgradeReq miss latency 217011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678833 # average SCUpgradeFailReq miss latency 217111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678833 # average SCUpgradeFailReq miss latency 217211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44096.513730 # average ReadExReq miss latency 217311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44096.513730 # average ReadExReq miss latency 217411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33259.669822 # average ReadCleanReq miss latency 217511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33259.669822 # average ReadCleanReq miss latency 217611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34918.924391 # average ReadSharedReq miss latency 217711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34918.924391 # average ReadSharedReq miss latency 217811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1131.598592 # average InvalidateReq miss latency 217911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1131.598592 # average InvalidateReq miss latency 218011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency 218111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency 218211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency 218311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency 218411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 35473.886153 # average overall miss latency 218511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency 218611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency 218711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency 218811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency 218911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 35473.886153 # average overall miss latency 219011441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 219211441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 219310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 219411441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 219510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 219611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.unused_prefetches 49424 # number of HardPF blocks evicted w/o reference 219711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1233392 # number of writebacks 219811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::total 1233392 # number of writebacks 219911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 16 # number of ReadReq MSHR hits 220011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 110 # number of ReadReq MSHR hits 220111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits 220211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7522 # number of ReadExReq MSHR hits 220311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 7522 # number of ReadExReq MSHR hits 220411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits 220511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 220611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 653 # number of ReadSharedReq MSHR hits 220711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 653 # number of ReadSharedReq MSHR hits 220811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 16 # number of demand (read+write) MSHR hits 220911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 110 # number of demand (read+write) MSHR hits 221011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 221111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 8175 # number of demand (read+write) MSHR hits 221211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 8303 # number of demand (read+write) MSHR hits 221311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 16 # number of overall MSHR hits 221411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 110 # number of overall MSHR hits 221511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 221611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 8175 # number of overall MSHR hits 221711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 8303 # number of overall MSHR hits 221811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 22570 # number of ReadReq MSHR misses 221911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10940 # number of ReadReq MSHR misses 222011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 33510 # number of ReadReq MSHR misses 222111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 779944 # number of HardPFReq MSHR misses 222211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 779944 # number of HardPFReq MSHR misses 222311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 232349 # number of UpgradeReq MSHR misses 222411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 232349 # number of UpgradeReq MSHR misses 222511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193761 # number of SCUpgradeReq MSHR misses 222611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193761 # number of SCUpgradeReq MSHR misses 222711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 222811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 222911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 252011 # number of ReadExReq MSHR misses 223011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 252011 # number of ReadExReq MSHR misses 223111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 740265 # number of ReadCleanReq MSHR misses 223211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 740265 # number of ReadCleanReq MSHR misses 223311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1026006 # number of ReadSharedReq MSHR misses 223411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1026006 # number of ReadSharedReq MSHR misses 223511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 269262 # number of InvalidateReq MSHR misses 223611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 269262 # number of InvalidateReq MSHR misses 223711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 22570 # number of demand (read+write) MSHR misses 223811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10940 # number of demand (read+write) MSHR misses 223911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 740265 # number of demand (read+write) MSHR misses 224011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1278017 # number of demand (read+write) MSHR misses 224111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 2051792 # number of demand (read+write) MSHR misses 224211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 22570 # number of overall MSHR misses 224311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10940 # number of overall MSHR misses 224411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 740265 # number of overall MSHR misses 224511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1278017 # number of overall MSHR misses 224611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 779944 # number of overall MSHR misses 224711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2831736 # number of overall MSHR misses 224811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 224911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable 225011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17703 # number of ReadReq MSHR uncacheable 225111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 225211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable 225311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 225411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses 225511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33556 # number of overall MSHR uncacheable misses 225611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of ReadReq MSHR miss cycles 225711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369748000 # number of ReadReq MSHR miss cycles 225811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 960914500 # number of ReadReq MSHR miss cycles 225911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of HardPFReq MSHR miss cycles 226011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 34084097769 # number of HardPFReq MSHR miss cycles 226111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4320296500 # number of UpgradeReq MSHR miss cycles 226211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4320296500 # number of UpgradeReq MSHR miss cycles 226311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2976407492 # number of SCUpgradeReq MSHR miss cycles 226411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2976407492 # number of SCUpgradeReq MSHR miss cycles 226511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1712499 # number of SCUpgradeFailReq MSHR miss cycles 226611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1712499 # number of SCUpgradeFailReq MSHR miss cycles 226711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8961948498 # number of ReadExReq MSHR miss cycles 226811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8961948498 # number of ReadExReq MSHR miss cycles 226911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20179405000 # number of ReadCleanReq MSHR miss cycles 227011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20179405000 # number of ReadCleanReq MSHR miss cycles 227111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29636625496 # number of ReadSharedReq MSHR miss cycles 227211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29636625496 # number of ReadSharedReq MSHR miss cycles 227311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7368901000 # number of InvalidateReq MSHR miss cycles 227411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7368901000 # number of InvalidateReq MSHR miss cycles 227511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of demand (read+write) MSHR miss cycles 227611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369748000 # number of demand (read+write) MSHR miss cycles 227711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20179405000 # number of demand (read+write) MSHR miss cycles 227811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38598573994 # number of demand (read+write) MSHR miss cycles 227911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 59738893494 # number of demand (read+write) MSHR miss cycles 228011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of overall MSHR miss cycles 228111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369748000 # number of overall MSHR miss cycles 228211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20179405000 # number of overall MSHR miss cycles 228311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38598573994 # number of overall MSHR miss cycles 228411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of overall MSHR miss cycles 228511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 93822991263 # number of overall MSHR miss cycles 228611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8310500 # number of ReadReq MSHR uncacheable cycles 228711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2795199500 # number of ReadReq MSHR uncacheable cycles 228811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2803510000 # number of ReadReq MSHR uncacheable cycles 228911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8310500 # number of overall MSHR uncacheable cycles 229011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2795199500 # number of overall MSHR uncacheable cycles 229111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2803510000 # number of overall MSHR uncacheable cycles 229211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for ReadReq accesses 229311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for ReadReq accesses 229411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042758 # mshr miss rate for ReadReq accesses 229510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 229610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 229711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 229811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 229911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 230011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 230110636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 230210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 230311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.216988 # mshr miss rate for ReadExReq accesses 230411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.216988 # mshr miss rate for ReadExReq accesses 230511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for ReadCleanReq accesses 230611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077743 # mshr miss rate for ReadCleanReq accesses 230711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253348 # mshr miss rate for ReadSharedReq accesses 230811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253348 # mshr miss rate for ReadSharedReq accesses 230911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584169 # mshr miss rate for InvalidateReq accesses 231011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584169 # mshr miss rate for InvalidateReq accesses 231111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for demand accesses 231211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for demand accesses 231311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for demand accesses 231411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for demand accesses 231511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.132230 # mshr miss rate for demand accesses 231611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for overall accesses 231711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for overall accesses 231811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for overall accesses 231911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for overall accesses 232010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 232111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.182494 # mshr miss rate for overall accesses 232211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average ReadReq mshr miss latency 232311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average ReadReq mshr miss latency 232411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088 # average ReadReq mshr miss latency 232511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average HardPFReq mshr miss latency 232611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728 # average HardPFReq mshr miss latency 232711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531 # average UpgradeReq mshr miss latency 232811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531 # average UpgradeReq mshr miss latency 232911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063 # average SCUpgradeReq mshr miss latency 233011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063 # average SCUpgradeReq mshr miss latency 233111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 570833 # average SCUpgradeFailReq mshr miss latency 233211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 570833 # average SCUpgradeFailReq mshr miss latency 233311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393 # average ReadExReq mshr miss latency 233411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393 # average ReadExReq mshr miss latency 233511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average ReadCleanReq mshr miss latency 233611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295 # average ReadCleanReq mshr miss latency 233711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978 # average ReadSharedReq mshr miss latency 233811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978 # average ReadSharedReq mshr miss latency 233911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139 # average InvalidateReq mshr miss latency 234011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139 # average InvalidateReq mshr miss latency 234111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency 234211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency 234311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency 234411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency 234511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472 # average overall mshr miss latency 234611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency 234711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency 234811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency 234911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency 235011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average overall mshr miss latency 235111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950 # average overall mshr miss latency 235211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average ReadReq mshr uncacheable latency 235311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138 # average ReadReq mshr uncacheable latency 235411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200 # average ReadReq mshr uncacheable latency 235511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average overall mshr uncacheable latency 235611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959 # average overall mshr uncacheable latency 235711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673 # average overall mshr uncacheable latency 235811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 31064178 # Total number of requests made to the snoop filter. 235911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 15870221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 236011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 236111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 609547 # Total number of snoops made to the snoop filter. 236211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 609525 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 236311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 22 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 236411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 236511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 891069 # Transaction distribution 236611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 14544906 # Transaction distribution 236711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 15853 # Transaction distribution 236811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 15853 # Transaction distribution 236911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4703319 # Transaction distribution 237011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 11641461 # Transaction distribution 237111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1517999 # Transaction distribution 237211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 982833 # Transaction distribution 237311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 435735 # Transaction distribution 237411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338791 # Transaction distribution 237511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 485404 # Transaction distribution 237611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution 237711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 237811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1187635 # Transaction distribution 237911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1166992 # Transaction distribution 238011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9521965 # Transaction distribution 238111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 5021918 # Transaction distribution 238211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 508584 # Transaction distribution 238311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 460932 # Transaction distribution 238411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28565571 # Packet count per connected master and slave (bytes) 238511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17994817 # Packet count per connected master and slave (bytes) 238611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387517 # Packet count per connected master and slave (bytes) 238711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1269560 # Packet count per connected master and slave (bytes) 238811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count::total 48217465 # Packet count per connected master and slave (bytes) 238911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1218784704 # Cumulative packet size per connected master and slave (bytes) 239011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 696648341 # Cumulative packet size per connected master and slave (bytes) 239111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1464248 # Cumulative packet size per connected master and slave (bytes) 239211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4805440 # Cumulative packet size per connected master and slave (bytes) 239311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1921702733 # Cumulative packet size per connected master and slave (bytes) 239411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 5371031 # Total snoops (count) 239511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopTraffic 85625912 # Total snoop traffic (bytes) 239611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 21661443 # Request fanout histogram 239711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.043843 # Request fanout histogram 239811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.204751 # Request fanout histogram 239910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 240011606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 20711756 95.62% 95.62% # Request fanout histogram 240111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 949665 4.38% 100.00% # Request fanout histogram 240211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 22 0.00% 100.00% # Request fanout histogram 240310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 240411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 240510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 240611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 21661443 # Request fanout histogram 240711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 30930175985 # Layer occupancy (ticks) 240811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 240911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 161428122 # Layer occupancy (ticks) 241010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 241111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 14285968218 # Layer occupancy (ticks) 241210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 241311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8290126100 # Layer occupancy (ticks) 241410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 241511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 204584802 # Layer occupancy (ticks) 241610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 241711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 668995768 # Layer occupancy (ticks) 241810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 241911606Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 242011606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 40347 # Transaction distribution 242111606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 40347 # Transaction distribution 242211606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteReq 136610 # Transaction distribution 242311606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteResp 136610 # Transaction distribution 242411606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47638 # Packet count per connected master and slave (bytes) 242510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 242611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 242710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 242810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 242910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 243010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 243110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 243210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 243310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 243410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 243511606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 243610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 243711606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122572 # Packet count per connected master and slave (bytes) 243811606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) 243911606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) 244010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 244110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 244211606Sandreas.sandberg@arm.comsystem.iobus.pkt_count::total 353914 # Packet count per connected master and slave (bytes) 244311606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47658 # Cumulative packet size per connected master and slave (bytes) 244410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 244511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 244610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 244710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 244810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 244910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 245310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 245411606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 245510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 245611606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155679 # Cumulative packet size per connected master and slave (bytes) 245711606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) 245811606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) 245910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 246010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 246111606Sandreas.sandberg@arm.comsystem.iobus.pkt_size::total 7496829 # Cumulative packet size per connected master and slave (bytes) 246211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer0.occupancy 41998503 # Layer occupancy (ticks) 246310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 246411570SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 246510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 246611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) 246710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 246811606Sandreas.sandberg@arm.comsystem.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 246910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 247011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 247111245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 247211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 247310585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 247411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 247510585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 247611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 247710585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 247811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 247910585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 248011606Sandreas.sandberg@arm.comsystem.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 248110585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 248211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 248310585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 248411606Sandreas.sandberg@arm.comsystem.iobus.reqLayer23.occupancy 25719009 # Layer occupancy (ticks) 248510585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 248611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer24.occupancy 34474500 # Layer occupancy (ticks) 248710585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 248811606Sandreas.sandberg@arm.comsystem.iobus.reqLayer25.occupancy 569697884 # Layer occupancy (ticks) 248910585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 249011606Sandreas.sandberg@arm.comsystem.iobus.respLayer0.occupancy 92693000 # Layer occupancy (ticks) 249110585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 249211606Sandreas.sandberg@arm.comsystem.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) 249310585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 249410892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 249510585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 249611606Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 249711606Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 115612 # number of replacements 249811606Sandreas.sandberg@arm.comsystem.iocache.tags.tagsinuse 11.289058 # Cycle average of tags in use 249911336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 250011606Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. 250111336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 250211606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 9127814531000 # Cycle when the warmup percentage was hit. 250311606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.847615 # Average occupied blocks per requestor 250411606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.441443 # Average occupied blocks per requestor 250511606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240476 # Average percentage of cache occupancy 250611606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.465090 # Average percentage of cache occupancy 250711606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::total 0.705566 # Average percentage of cache occupancy 250810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 250910827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 251010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 251111606Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 1041036 # Number of tag accesses 251211606Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 1041036 # Number of data accesses 251311606Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 251410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 251511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses 251611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 8940 # number of ReadReq misses 251710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 251810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 251911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 252011606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 252110585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 252211606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses 252311606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 115671 # number of demand (read+write) misses 252410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 252511606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::realview.ide 115631 # number of overall misses 252611606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 115671 # number of overall misses 252711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles 252811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1683130463 # number of ReadReq miss cycles 252911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::total 1688328963 # number of ReadReq miss cycles 253010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 253110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 253211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12860878921 # number of WriteLineReq miss cycles 253311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12860878921 # number of WriteLineReq miss cycles 253411606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles 253511606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::realview.ide 14544009384 # number of demand (read+write) miss cycles 253611606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::total 14549576884 # number of demand (read+write) miss cycles 253711606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles 253811606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::realview.ide 14544009384 # number of overall miss cycles 253911606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::total 14549576884 # number of overall miss cycles 254010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 254111606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) 254211606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) 254310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 254410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 254511606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 254611606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 254710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 254811606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses 254911606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses 255010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 255111606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses 255211606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses 255310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 255410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 255510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 255610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 255710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 255811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 255911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 256010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 256110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 256210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 256310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 256410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 256510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 256611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency 256711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947 # average ReadReq miss latency 256811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 188851.114430 # average ReadReq miss latency 256910726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 257010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 257111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550 # average WriteLineReq miss latency 257211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 120501.451550 # average WriteLineReq miss latency 257311606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 257411606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency 257511606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::total 125784.136767 # average overall miss latency 257611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 257711606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency 257811606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::total 125784.136767 # average overall miss latency 257911606Sandreas.sandberg@arm.comsystem.iocache.blocked_cycles::no_mshrs 33720 # number of cycles access was blocked 258010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 258111606Sandreas.sandberg@arm.comsystem.iocache.blocked::no_mshrs 3566 # number of cycles access was blocked 258210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 258311606Sandreas.sandberg@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.455973 # average number of cycles each access was blocked 258410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 258511606Sandreas.sandberg@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 258611606Sandreas.sandberg@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 258710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 258811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses 258911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses 259010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 259110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 259211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 259311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 259410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 259511606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses 259611606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses 259710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 259811606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses 259911606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses 260011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles 260111606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1237980463 # number of ReadReq MSHR miss cycles 260211606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1241328963 # number of ReadReq MSHR miss cycles 260310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 260410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 260511606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7515783412 # number of WriteLineReq MSHR miss cycles 260611606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7515783412 # number of WriteLineReq MSHR miss cycles 260711606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles 260811606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8753763875 # number of demand (read+write) MSHR miss cycles 260911606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::total 8757331375 # number of demand (read+write) MSHR miss cycles 261011606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles 261111606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8753763875 # number of overall MSHR miss cycles 261211606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::total 8757331375 # number of overall MSHR miss cycles 261310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 261410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 261510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 261610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 261710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 261811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 261911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 262010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 262110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 262210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 262310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 262410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 262510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 262611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency 262711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947 # average ReadReq mshr miss latency 262811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430 # average ReadReq mshr miss latency 262910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 263010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 263111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000 # average WriteLineReq mshr miss latency 263211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000 # average WriteLineReq mshr miss latency 263311606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 263411606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency 263511606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency 263611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 263711606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency 263811606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency 263911606Sandreas.sandberg@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 264011606Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 1555997 # number of replacements 264111606Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 65230.630092 # Cycle average of tags in use 264211606Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 7273929 # Total number of references to valid blocks. 264311606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 1617589 # Sample count of references to valid blocks. 264411606Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 4.496772 # Average number of references to valid blocks. 264511606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 7807986500 # Cycle when the warmup percentage was hit. 264611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::writebacks 8906.310468 # Average occupied blocks per requestor 264711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 15.466536 # Average occupied blocks per requestor 264811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 9.611192 # Average occupied blocks per requestor 264911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3875.011018 # Average occupied blocks per requestor 265011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 9658.633081 # Average occupied blocks per requestor 265111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3787.473530 # Average occupied blocks per requestor 265211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 432.466953 # Average occupied blocks per requestor 265311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 495.764320 # Average occupied blocks per requestor 265411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3981.420883 # Average occupied blocks per requestor 265511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 15318.580710 # Average occupied blocks per requestor 265611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401 # Average occupied blocks per requestor 265711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.135900 # Average percentage of cache occupancy 265811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000236 # Average percentage of cache occupancy 265911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000147 # Average percentage of cache occupancy 266011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.059128 # Average percentage of cache occupancy 266111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.147379 # Average percentage of cache occupancy 266211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057792 # Average percentage of cache occupancy 266311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.006599 # Average percentage of cache occupancy 266411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.007565 # Average percentage of cache occupancy 266511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.060752 # Average percentage of cache occupancy 266611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.233743 # Average percentage of cache occupancy 266711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.286101 # Average percentage of cache occupancy 266811606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.995340 # Average percentage of cache occupancy 266911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10605 # Occupied blocks per task id 267011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 254 # Occupied blocks per task id 267111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50733 # Occupied blocks per task id 267211606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 267311606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 57 # Occupied blocks per task id 267411606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 363 # Occupied blocks per task id 267511606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10181 # Occupied blocks per task id 267611606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 267711606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 267811606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 267911606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 268011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 268111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id 268211606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4720 # Occupied blocks per task id 268311606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 44382 # Occupied blocks per task id 268411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.161819 # Percentage of cache occupancy per task id 268511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003876 # Percentage of cache occupancy per task id 268611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.774124 # Percentage of cache occupancy per task id 268711606Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 80901066 # Number of tag accesses 268811606Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 80901066 # Number of data accesses 268911606Sandreas.sandberg@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 269011606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2828973 # number of WritebackDirty hits 269111606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 2828973 # number of WritebackDirty hits 269211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 204859 # number of UpgradeReq hits 269311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 171268 # number of UpgradeReq hits 269411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 376127 # number of UpgradeReq hits 269511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 49678 # number of SCUpgradeReq hits 269611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 57164 # number of SCUpgradeReq hits 269711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 106842 # number of SCUpgradeReq hits 269811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 57243 # number of ReadExReq hits 269911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 53868 # number of ReadExReq hits 270011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 111111 # number of ReadExReq hits 270111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12667 # number of ReadSharedReq hits 270211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5625 # number of ReadSharedReq hits 270311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 610867 # number of ReadSharedReq hits 270411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 589040 # number of ReadSharedReq hits 270511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292600 # number of ReadSharedReq hits 270611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12537 # number of ReadSharedReq hits 270711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4791 # number of ReadSharedReq hits 270811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 678625 # number of ReadSharedReq hits 270911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 607071 # number of ReadSharedReq hits 271011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 308630 # number of ReadSharedReq hits 271111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 3122453 # number of ReadSharedReq hits 271211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 131047 # number of InvalidateReq hits 271311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 131317 # number of InvalidateReq hits 271411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_hits::total 262364 # number of InvalidateReq hits 271511606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 12667 # number of demand (read+write) hits 271611606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5625 # number of demand (read+write) hits 271711606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.inst 610867 # number of demand (read+write) hits 271811606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 646283 # number of demand (read+write) hits 271911606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 292600 # number of demand (read+write) hits 272011606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 12537 # number of demand (read+write) hits 272111606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4791 # number of demand (read+write) hits 272211606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.inst 678625 # number of demand (read+write) hits 272311606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 660939 # number of demand (read+write) hits 272411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 308630 # number of demand (read+write) hits 272511606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 3233564 # number of demand (read+write) hits 272611606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 12667 # number of overall hits 272711606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5625 # number of overall hits 272811606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.inst 610867 # number of overall hits 272911606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 646283 # number of overall hits 273011606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 292600 # number of overall hits 273111606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 12537 # number of overall hits 273211606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4791 # number of overall hits 273311606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.inst 678625 # number of overall hits 273411606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 660939 # number of overall hits 273511606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 308630 # number of overall hits 273611606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 3233564 # number of overall hits 273711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21060 # number of UpgradeReq misses 273811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 26656 # number of UpgradeReq misses 273911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 47716 # number of UpgradeReq misses 274011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 518 # number of SCUpgradeReq misses 274111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 636 # number of SCUpgradeReq misses 274211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1154 # number of SCUpgradeReq misses 274311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 76722 # number of ReadExReq misses 274411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 60050 # number of ReadExReq misses 274511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 136772 # number of ReadExReq misses 274611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq misses 274711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1415 # number of ReadSharedReq misses 274811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 72156 # number of ReadSharedReq misses 274911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 133347 # number of ReadSharedReq misses 275011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq misses 275111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq misses 275211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2459 # number of ReadSharedReq misses 275311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 61640 # number of ReadSharedReq misses 275411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 144790 # number of ReadSharedReq misses 275511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq misses 275611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 900362 # number of ReadSharedReq misses 275711606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 438466 # number of InvalidateReq misses 275811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 125863 # number of InvalidateReq misses 275911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_misses::total 564329 # number of InvalidateReq misses 276011606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1834 # number of demand (read+write) misses 276111606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1415 # number of demand (read+write) misses 276211606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.inst 72156 # number of demand (read+write) misses 276311606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 210069 # number of demand (read+write) misses 276411606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) misses 276511606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2590 # number of demand (read+write) misses 276611606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2459 # number of demand (read+write) misses 276711606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.inst 61640 # number of demand (read+write) misses 276811606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 204840 # number of demand (read+write) misses 276911606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) misses 277011606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 1037134 # number of demand (read+write) misses 277111606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1834 # number of overall misses 277211606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1415 # number of overall misses 277311606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.inst 72156 # number of overall misses 277411606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 210069 # number of overall misses 277511606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 250233 # number of overall misses 277611606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2590 # number of overall misses 277711606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2459 # number of overall misses 277811606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.inst 61640 # number of overall misses 277911606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 204840 # number of overall misses 278011606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 229898 # number of overall misses 278111606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 1037134 # number of overall misses 278211606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 165743500 # number of UpgradeReq miss cycles 278311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 162277500 # number of UpgradeReq miss cycles 278411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::total 328021000 # number of UpgradeReq miss cycles 278511606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 8669000 # number of SCUpgradeReq miss cycles 278611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 8803000 # number of SCUpgradeReq miss cycles 278711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 17472000 # number of SCUpgradeReq miss cycles 278811606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7005748000 # number of ReadExReq miss cycles 278911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5240435998 # number of ReadExReq miss cycles 279011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::total 12246183998 # number of ReadExReq miss cycles 279111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 169372000 # number of ReadSharedReq miss cycles 279211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 128340500 # number of ReadSharedReq miss cycles 279311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6167992000 # number of ReadSharedReq miss cycles 279411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 12302035500 # number of ReadSharedReq miss cycles 279511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of ReadSharedReq miss cycles 279611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 231186000 # number of ReadSharedReq miss cycles 279711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 216219500 # number of ReadSharedReq miss cycles 279811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5316209000 # number of ReadSharedReq miss cycles 279911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 13039902500 # number of ReadSharedReq miss cycles 280011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of ReadSharedReq miss cycles 280111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 99287989218 # number of ReadSharedReq miss cycles 280211606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 31523000 # number of InvalidateReq miss cycles 280311606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 29313000 # number of InvalidateReq miss cycles 280411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_latency::total 60836000 # number of InvalidateReq miss cycles 280511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 169372000 # number of demand (read+write) miss cycles 280611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 128340500 # number of demand (read+write) miss cycles 280711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6167992000 # number of demand (read+write) miss cycles 280811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.data 19307783500 # number of demand (read+write) miss cycles 280911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of demand (read+write) miss cycles 281011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 231186000 # number of demand (read+write) miss cycles 281111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 216219500 # number of demand (read+write) miss cycles 281211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5316209000 # number of demand (read+write) miss cycles 281311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.data 18280338498 # number of demand (read+write) miss cycles 281411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of demand (read+write) miss cycles 281511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::total 111534173216 # number of demand (read+write) miss cycles 281611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 169372000 # number of overall miss cycles 281711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 128340500 # number of overall miss cycles 281811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6167992000 # number of overall miss cycles 281911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.data 19307783500 # number of overall miss cycles 282011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of overall miss cycles 282111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 231186000 # number of overall miss cycles 282211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 216219500 # number of overall miss cycles 282311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5316209000 # number of overall miss cycles 282411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.data 18280338498 # number of overall miss cycles 282511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of overall miss cycles 282611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::total 111534173216 # number of overall miss cycles 282711606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2828973 # number of WritebackDirty accesses(hits+misses) 282811606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 2828973 # number of WritebackDirty accesses(hits+misses) 282911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 225919 # number of UpgradeReq accesses(hits+misses) 283011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 197924 # number of UpgradeReq accesses(hits+misses) 283111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 423843 # number of UpgradeReq accesses(hits+misses) 283211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 50196 # number of SCUpgradeReq accesses(hits+misses) 283311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 57800 # number of SCUpgradeReq accesses(hits+misses) 283411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 107996 # number of SCUpgradeReq accesses(hits+misses) 283511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 133965 # number of ReadExReq accesses(hits+misses) 283611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 113918 # number of ReadExReq accesses(hits+misses) 283711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 247883 # number of ReadExReq accesses(hits+misses) 283811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14501 # number of ReadSharedReq accesses(hits+misses) 283911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7040 # number of ReadSharedReq accesses(hits+misses) 284011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 683023 # number of ReadSharedReq accesses(hits+misses) 284111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 722387 # number of ReadSharedReq accesses(hits+misses) 284211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 542833 # number of ReadSharedReq accesses(hits+misses) 284311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15127 # number of ReadSharedReq accesses(hits+misses) 284411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7250 # number of ReadSharedReq accesses(hits+misses) 284511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 740265 # number of ReadSharedReq accesses(hits+misses) 284611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 751861 # number of ReadSharedReq accesses(hits+misses) 284711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 538528 # number of ReadSharedReq accesses(hits+misses) 284811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 4022815 # number of ReadSharedReq accesses(hits+misses) 284911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 569513 # number of InvalidateReq accesses(hits+misses) 285011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 257180 # number of InvalidateReq accesses(hits+misses) 285111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_accesses::total 826693 # number of InvalidateReq accesses(hits+misses) 285211606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 14501 # number of demand (read+write) accesses 285311606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7040 # number of demand (read+write) accesses 285411606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.inst 683023 # number of demand (read+write) accesses 285511606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 856352 # number of demand (read+write) accesses 285611606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 542833 # number of demand (read+write) accesses 285711606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 15127 # number of demand (read+write) accesses 285811606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7250 # number of demand (read+write) accesses 285911606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.inst 740265 # number of demand (read+write) accesses 286011606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 865779 # number of demand (read+write) accesses 286111606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 538528 # number of demand (read+write) accesses 286211606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 4270698 # number of demand (read+write) accesses 286311606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 14501 # number of overall (read+write) accesses 286411606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7040 # number of overall (read+write) accesses 286511606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.inst 683023 # number of overall (read+write) accesses 286611606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 856352 # number of overall (read+write) accesses 286711606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 542833 # number of overall (read+write) accesses 286811606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 15127 # number of overall (read+write) accesses 286911606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7250 # number of overall (read+write) accesses 287011606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.inst 740265 # number of overall (read+write) accesses 287111606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 865779 # number of overall (read+write) accesses 287211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 538528 # number of overall (read+write) accesses 287311606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 4270698 # number of overall (read+write) accesses 287411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.093219 # miss rate for UpgradeReq accesses 287511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.134678 # miss rate for UpgradeReq accesses 287611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.112579 # miss rate for UpgradeReq accesses 287711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010320 # miss rate for SCUpgradeReq accesses 287811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011003 # miss rate for SCUpgradeReq accesses 287911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.010686 # miss rate for SCUpgradeReq accesses 288011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.572702 # miss rate for ReadExReq accesses 288111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.527134 # miss rate for ReadExReq accesses 288211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.551760 # miss rate for ReadExReq accesses 288311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for ReadSharedReq accesses 288411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.200994 # miss rate for ReadSharedReq accesses 288511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.105642 # miss rate for ReadSharedReq accesses 288611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.184592 # miss rate for ReadSharedReq accesses 288711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for ReadSharedReq accesses 288811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for ReadSharedReq accesses 288911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339172 # miss rate for ReadSharedReq accesses 289011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.083267 # miss rate for ReadSharedReq accesses 289111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.192575 # miss rate for ReadSharedReq accesses 289211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for ReadSharedReq accesses 289311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.223814 # miss rate for ReadSharedReq accesses 289411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.769896 # miss rate for InvalidateReq accesses 289511606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.489397 # miss rate for InvalidateReq accesses 289611606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.682634 # miss rate for InvalidateReq accesses 289711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for demand accesses 289811606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.200994 # miss rate for demand accesses 289911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.105642 # miss rate for demand accesses 290011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.245307 # miss rate for demand accesses 290111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for demand accesses 290211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for demand accesses 290311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.339172 # miss rate for demand accesses 290411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.083267 # miss rate for demand accesses 290511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.236596 # miss rate for demand accesses 290611606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for demand accesses 290711606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.242849 # miss rate for demand accesses 290811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for overall accesses 290911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.200994 # miss rate for overall accesses 291011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.105642 # miss rate for overall accesses 291111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.245307 # miss rate for overall accesses 291211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for overall accesses 291311606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for overall accesses 291411606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.339172 # miss rate for overall accesses 291511606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.083267 # miss rate for overall accesses 291611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.236596 # miss rate for overall accesses 291711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for overall accesses 291811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.242849 # miss rate for overall accesses 291911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7870.061728 # average UpgradeReq miss latency 292011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6087.841387 # average UpgradeReq miss latency 292111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6874.444631 # average UpgradeReq miss latency 292211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16735.521236 # average SCUpgradeReq miss latency 292311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13841.194969 # average SCUpgradeReq miss latency 292411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 15140.381282 # average SCUpgradeReq miss latency 292511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 91313.417273 # average ReadExReq miss latency 292611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 87267.876736 # average ReadExReq miss latency 292711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 89537.215205 # average ReadExReq miss latency 292811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average ReadSharedReq miss latency 292911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90700 # average ReadSharedReq miss latency 293011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85481.345973 # average ReadSharedReq miss latency 293111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92255.810029 # average ReadSharedReq miss latency 293211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average ReadSharedReq miss latency 293311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average ReadSharedReq miss latency 293411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 87929.849532 # average ReadSharedReq miss latency 293511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86246.090201 # average ReadSharedReq miss latency 293611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90060.794944 # average ReadSharedReq miss latency 293711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average ReadSharedReq miss latency 293811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 110275.632710 # average ReadSharedReq miss latency 293911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 71.893830 # average InvalidateReq miss latency 294011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 232.896085 # average InvalidateReq miss latency 294111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 107.802364 # average InvalidateReq miss latency 294211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average overall miss latency 294311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 90700 # average overall miss latency 294411606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 85481.345973 # average overall miss latency 294511606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 91911.626656 # average overall miss latency 294611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average overall miss latency 294711606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average overall miss latency 294811606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 87929.849532 # average overall miss latency 294911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 86246.090201 # average overall miss latency 295011606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 89242.035237 # average overall miss latency 295111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average overall miss latency 295211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::total 107540.754826 # average overall miss latency 295311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average overall miss latency 295411606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 90700 # average overall miss latency 295511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 85481.345973 # average overall miss latency 295611606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 91911.626656 # average overall miss latency 295711606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average overall miss latency 295811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average overall miss latency 295911606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 87929.849532 # average overall miss latency 296011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 86246.090201 # average overall miss latency 296111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 89242.035237 # average overall miss latency 296211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average overall miss latency 296311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::total 107540.754826 # average overall miss latency 296411606Sandreas.sandberg@arm.comsystem.l2c.blocked_cycles::no_mshrs 751 # number of cycles access was blocked 296510515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 296611606Sandreas.sandberg@arm.comsystem.l2c.blocked::no_mshrs 17 # number of cycles access was blocked 296710515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 296811606Sandreas.sandberg@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 44.176471 # average number of cycles each access was blocked 296910515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 297011606Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 1165859 # number of writebacks 297111606Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 1165859 # number of writebacks 297211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 169 # number of ReadSharedReq MSHR hits 297311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 21 # number of ReadSharedReq MSHR hits 297411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 110 # number of ReadSharedReq MSHR hits 297511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 297611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 317 # number of ReadSharedReq MSHR hits 297711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 169 # number of demand (read+write) MSHR hits 297811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 21 # number of demand (read+write) MSHR hits 297911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 110 # number of demand (read+write) MSHR hits 298011502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 298111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::total 317 # number of demand (read+write) MSHR hits 298211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 169 # number of overall MSHR hits 298311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 21 # number of overall MSHR hits 298411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 110 # number of overall MSHR hits 298511502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 298611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::total 317 # number of overall MSHR hits 298711606Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 72347 # number of CleanEvict MSHR misses 298811606Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::total 72347 # number of CleanEvict MSHR misses 298911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 21060 # number of UpgradeReq MSHR misses 299011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 26656 # number of UpgradeReq MSHR misses 299111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 47716 # number of UpgradeReq MSHR misses 299211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 518 # number of SCUpgradeReq MSHR misses 299311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 636 # number of SCUpgradeReq MSHR misses 299411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1154 # number of SCUpgradeReq MSHR misses 299511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 76722 # number of ReadExReq MSHR misses 299611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 60050 # number of ReadExReq MSHR misses 299711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::total 136772 # number of ReadExReq MSHR misses 299811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq MSHR misses 299911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1415 # number of ReadSharedReq MSHR misses 300011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 71987 # number of ReadSharedReq MSHR misses 300111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 133326 # number of ReadSharedReq MSHR misses 300211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq MSHR misses 300311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq MSHR misses 300411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2459 # number of ReadSharedReq MSHR misses 300511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 61530 # number of ReadSharedReq MSHR misses 300611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 144773 # number of ReadSharedReq MSHR misses 300711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq MSHR misses 300811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 900045 # number of ReadSharedReq MSHR misses 300911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 438466 # number of InvalidateReq MSHR misses 301011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 125863 # number of InvalidateReq MSHR misses 301111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 564329 # number of InvalidateReq MSHR misses 301211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1834 # number of demand (read+write) MSHR misses 301311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1415 # number of demand (read+write) MSHR misses 301411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 71987 # number of demand (read+write) MSHR misses 301511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 210048 # number of demand (read+write) MSHR misses 301611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) MSHR misses 301711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2590 # number of demand (read+write) MSHR misses 301811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2459 # number of demand (read+write) MSHR misses 301911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 61530 # number of demand (read+write) MSHR misses 302011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 204823 # number of demand (read+write) MSHR misses 302111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) MSHR misses 302211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::total 1036817 # number of demand (read+write) MSHR misses 302311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1834 # number of overall MSHR misses 302411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1415 # number of overall MSHR misses 302511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 71987 # number of overall MSHR misses 302611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 210048 # number of overall MSHR misses 302711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of overall MSHR misses 302811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2590 # number of overall MSHR misses 302911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2459 # number of overall MSHR misses 303011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 61530 # number of overall MSHR misses 303111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 204823 # number of overall MSHR misses 303211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of overall MSHR misses 303311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::total 1036817 # number of overall MSHR misses 303411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 303511606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 303611570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 303711606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 17606 # number of ReadReq MSHR uncacheable 303811606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 90635 # number of ReadReq MSHR uncacheable 303911606Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 304011606Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 304111606Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38128 # number of WriteReq MSHR uncacheable 304211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 304311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 304411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 304511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 33459 # number of overall MSHR uncacheable misses 304611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 128763 # number of overall MSHR uncacheable misses 304711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 428042501 # number of UpgradeReq MSHR miss cycles 304811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 541214000 # number of UpgradeReq MSHR miss cycles 304911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 969256501 # number of UpgradeReq MSHR miss cycles 305011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12312000 # number of SCUpgradeReq MSHR miss cycles 305111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15177000 # number of SCUpgradeReq MSHR miss cycles 305211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 27489000 # number of SCUpgradeReq MSHR miss cycles 305311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6238487583 # number of ReadExReq MSHR miss cycles 305411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4639903563 # number of ReadExReq MSHR miss cycles 305511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 10878391146 # number of ReadExReq MSHR miss cycles 305611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of ReadSharedReq MSHR miss cycles 305711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 114190001 # number of ReadSharedReq MSHR miss cycles 305811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5436084068 # number of ReadSharedReq MSHR miss cycles 305911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10966992245 # number of ReadSharedReq MSHR miss cycles 306011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # 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number of InvalidateReq MSHR miss cycles 306811606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2543921000 # number of InvalidateReq MSHR miss cycles 306911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 11701338500 # number of InvalidateReq MSHR miss cycles 307011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of demand (read+write) MSHR miss cycles 307111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 114190001 # number of demand (read+write) MSHR miss cycles 307211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5436084068 # number of demand (read+write) MSHR miss cycles 307311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 17205479828 # number of demand (read+write) MSHR miss cycles 307411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of demand (read+write) MSHR miss cycles 307511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of demand (read+write) MSHR miss cycles 307611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191629001 # number of demand (read+write) MSHR miss cycles 307711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 4693018541 # number of demand (read+write) MSHR miss cycles 307811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 16230689731 # number of demand (read+write) MSHR miss cycles 307911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of demand (read+write) MSHR miss cycles 308011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::total 101142417768 # number of demand (read+write) MSHR miss cycles 308111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of overall MSHR miss cycles 308211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 114190001 # number of overall MSHR miss cycles 308311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5436084068 # number of overall MSHR miss cycles 308411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 17205479828 # number of overall MSHR miss cycles 308511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of overall MSHR miss cycles 308611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of overall MSHR miss cycles 308711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191629001 # number of overall MSHR miss cycles 308811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 4693018541 # number of overall MSHR miss cycles 308911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 16230689731 # number of overall MSHR miss cycles 309011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of overall MSHR miss cycles 309111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::total 101142417768 # number of overall MSHR miss cycles 309211570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of ReadReq MSHR uncacheable cycles 309311606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3477966008 # number of ReadReq MSHR uncacheable cycles 309411606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6312000 # number of ReadReq MSHR uncacheable cycles 309511606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2478199000 # number of ReadReq MSHR uncacheable cycles 309611606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 9282561008 # number of ReadReq MSHR uncacheable cycles 309711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles 309811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3477966008 # number of overall MSHR uncacheable cycles 309911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6312000 # number of overall MSHR uncacheable cycles 310011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 2478199000 # number of overall MSHR uncacheable cycles 310111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 9282561008 # number of overall MSHR uncacheable cycles 310210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 310310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 310411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.093219 # mshr miss rate for UpgradeReq accesses 310511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.134678 # mshr miss rate for UpgradeReq accesses 310611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.112579 # mshr miss rate for UpgradeReq accesses 310711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010320 # mshr miss rate for SCUpgradeReq accesses 310811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011003 # mshr miss rate for SCUpgradeReq accesses 310911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.010686 # mshr miss rate for SCUpgradeReq accesses 311011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572702 # mshr miss rate for ReadExReq accesses 311111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.527134 # mshr miss rate for ReadExReq accesses 311211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.551760 # mshr miss rate for ReadExReq accesses 311311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for ReadSharedReq accesses 311411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for ReadSharedReq accesses 311511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for ReadSharedReq accesses 311611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184563 # mshr miss rate for ReadSharedReq accesses 311711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for ReadSharedReq accesses 311811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for ReadSharedReq accesses 311911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for ReadSharedReq accesses 312011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for ReadSharedReq accesses 312111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192553 # mshr miss rate for ReadSharedReq accesses 312211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for ReadSharedReq accesses 312311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.223735 # mshr miss rate for ReadSharedReq accesses 312411606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.769896 # mshr miss rate for InvalidateReq accesses 312511606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489397 # mshr miss rate for InvalidateReq accesses 312611606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.682634 # mshr miss rate for InvalidateReq accesses 312711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for demand accesses 312811606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for demand accesses 312911606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for demand accesses 313011606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for demand accesses 313111606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for demand accesses 313211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for demand accesses 313311606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for demand accesses 313411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for demand accesses 313511606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for demand accesses 313611606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for demand accesses 313711606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.242775 # mshr miss rate for demand accesses 313811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for overall accesses 313911606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for overall accesses 314011606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for overall accesses 314111606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for overall accesses 314211606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for overall accesses 314311606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for overall accesses 314411606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for overall accesses 314511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for overall accesses 314611606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for overall accesses 314711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for overall accesses 314811606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.242775 # mshr miss rate for overall accesses 314911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081 # average UpgradeReq mshr miss latency 315011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459 # average UpgradeReq mshr miss latency 315111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194 # average UpgradeReq mshr miss latency 315211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768 # average SCUpgradeReq mshr miss latency 315311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547 # average SCUpgradeReq mshr miss latency 315411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917 # average SCUpgradeReq mshr miss latency 315511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475 # average ReadExReq mshr miss latency 315611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603 # average ReadExReq mshr miss latency 315711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552 # average ReadExReq mshr miss latency 315811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average ReadSharedReq mshr miss latency 315911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average ReadSharedReq mshr miss latency 316011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average ReadSharedReq mshr miss latency 316111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971 # average ReadSharedReq mshr miss latency 316211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average ReadSharedReq mshr miss latency 316311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average ReadSharedReq mshr miss latency 316411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average ReadSharedReq mshr miss latency 316511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average ReadSharedReq mshr miss latency 316611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451 # average ReadSharedReq mshr miss latency 316711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average ReadSharedReq mshr miss latency 316811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496 # average ReadSharedReq mshr miss latency 316911606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643 # average InvalidateReq mshr miss latency 317011606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556 # average InvalidateReq mshr miss latency 317111606Sandreas.sandberg@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685 # average InvalidateReq mshr miss latency 317211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency 317311606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency 317411606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency 317511606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency 317611606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency 317711606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency 317811606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency 317911606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency 318011606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency 318111606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency 318211606Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency 318311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency 318411606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency 318511606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency 318611606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency 318711606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency 318811606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency 318911606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency 319011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency 319111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency 319211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency 319311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency 319411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency 319511606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615 # average ReadReq mshr uncacheable latency 319611606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average ReadReq mshr uncacheable latency 319711606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417 # average ReadReq mshr uncacheable latency 319811606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217 # average ReadReq mshr uncacheable latency 319911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency 320011606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285 # average overall mshr uncacheable latency 320111606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average overall mshr uncacheable latency 320211606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396 # average overall mshr uncacheable latency 320311606Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208 # average overall mshr uncacheable latency 320411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 3909047 # Total number of requests made to the snoop filter. 320511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 2292243 # Number of requests hitting in the snoop filter with a single holder of the requested data. 320611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 2625 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 320711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 320811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 320911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 321011606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 321111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 90635 # Transaction distribution 321211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 999620 # Transaction distribution 321311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 38128 # Transaction distribution 321411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 38128 # Transaction distribution 321511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 1272553 # Transaction distribution 321611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 289712 # Transaction distribution 321711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 348270 # Transaction distribution 321811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 267748 # Transaction distribution 321911570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 322011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 322111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 152656 # Transaction distribution 322211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 136047 # Transaction distribution 322311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 908985 # Transaction distribution 322411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateReq 669058 # Transaction distribution 322511606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122572 # Packet count per connected master and slave (bytes) 322611570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 322711606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24944 # Packet count per connected master and slave (bytes) 322811606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4823028 # Packet count per connected master and slave (bytes) 322911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4970598 # Packet count per connected master and slave (bytes) 323011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238389 # Packet count per connected master and slave (bytes) 323111606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238389 # Packet count per connected master and slave (bytes) 323211606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 5208987 # Packet count per connected master and slave (bytes) 323311606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155679 # Cumulative packet size per connected master and slave (bytes) 323411570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 323511606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49888 # Cumulative packet size per connected master and slave (bytes) 323611606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144251456 # Cumulative packet size per connected master and slave (bytes) 323711606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 144458411 # Cumulative packet size per connected master and slave (bytes) 323811606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283200 # Cumulative packet size per connected master and slave (bytes) 323911606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7283200 # Cumulative packet size per connected master and slave (bytes) 324011606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 151741611 # Cumulative packet size per connected master and slave (bytes) 324111606Sandreas.sandberg@arm.comsystem.membus.snoops 583612 # Total snoops (count) 324211606Sandreas.sandberg@arm.comsystem.membus.snoopTraffic 163584 # Total snoop traffic (bytes) 324311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 2475487 # Request fanout histogram 324411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.012229 # Request fanout histogram 324511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.109905 # Request fanout histogram 324610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 324711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 2445215 98.78% 98.78% # Request fanout histogram 324811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 30272 1.22% 100.00% # Request fanout histogram 324910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 325010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 325111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 325210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 325311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 2475487 # Request fanout histogram 325411606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 102607988 # Layer occupancy (ticks) 325510585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 325611570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 325710585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 325811606Sandreas.sandberg@arm.comsystem.membus.reqLayer2.occupancy 20962995 # Layer occupancy (ticks) 325910585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 326011606Sandreas.sandberg@arm.comsystem.membus.reqLayer5.occupancy 8793410200 # Layer occupancy (ticks) 326110585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 326211606Sandreas.sandberg@arm.comsystem.membus.respLayer2.occupancy 5849158337 # Layer occupancy (ticks) 326310585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 326411606Sandreas.sandberg@arm.comsystem.membus.respLayer3.occupancy 45598905 # Layer occupancy (ticks) 326510585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 326611606Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 326711606Sandreas.sandberg@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 326811606Sandreas.sandberg@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 326911606Sandreas.sandberg@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 327011606Sandreas.sandberg@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 327111606Sandreas.sandberg@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 327211606Sandreas.sandberg@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 327311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 327411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 327511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 327611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 327711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 327811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 327911606Sandreas.sandberg@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 328011606Sandreas.sandberg@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 328110515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 328210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 328310515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 328410515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 328510515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 328610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 328710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 328810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 328910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 329011201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 329110515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 329210515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 329310515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 329411201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 329510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 329610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 329710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 329810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 329910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 330010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 330110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 330210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 330310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 330410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 330510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 330610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 330710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 330810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 330910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 331010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 331110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 331210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 331310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 331410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 331510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 331610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 331710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 331810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 331910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 332010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 332110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 332210515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 332311606Sandreas.sandberg@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332411606Sandreas.sandberg@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332511606Sandreas.sandberg@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332611606Sandreas.sandberg@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332711606Sandreas.sandberg@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332811606Sandreas.sandberg@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 332911606Sandreas.sandberg@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 333111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 333211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 333311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 333411606Sandreas.sandberg@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333511606Sandreas.sandberg@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333611606Sandreas.sandberg@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333711606Sandreas.sandberg@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333811606Sandreas.sandberg@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 333911606Sandreas.sandberg@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334011606Sandreas.sandberg@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334111606Sandreas.sandberg@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334211606Sandreas.sandberg@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334311606Sandreas.sandberg@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334411606Sandreas.sandberg@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334511606Sandreas.sandberg@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 334611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12529275 # Total number of requests made to the snoop filter. 334711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6783970 # Number of requests hitting in the snoop filter with a single holder of the requested data. 334811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2045593 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 334911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 207524 # Total number of snoops made to the snoop filter. 335011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 190768 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 335111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 16756 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 335211606Sandreas.sandberg@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 335311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 90637 # Transaction distribution 335411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadResp 4878287 # Transaction distribution 335511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteReq 38128 # Transaction distribution 335611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteResp 38128 # Transaction distribution 335711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3994832 # Transaction distribution 335811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 3079472 # Transaction distribution 335911606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 721673 # Transaction distribution 336011606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 374590 # Transaction distribution 336111606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1096263 # Transaction distribution 336211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution 336311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 336411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExReq 301835 # Transaction distribution 336511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExResp 301835 # Transaction distribution 336611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4787847 # Transaction distribution 336711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 854297 # Transaction distribution 336811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 826693 # Transaction distribution 336911606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9608901 # Packet count per connected master and slave (bytes) 337011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8808719 # Packet count per connected master and slave (bytes) 337111606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 18417620 # Packet count per connected master and slave (bytes) 337211606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240252134 # Cumulative packet size per connected master and slave (bytes) 337311606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 217815813 # Cumulative packet size per connected master and slave (bytes) 337411606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 458067947 # Cumulative packet size per connected master and slave (bytes) 337511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoops 2968837 # Total snoops (count) 337611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopTraffic 127024720 # Total snoop traffic (bytes) 337711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::samples 8725155 # Request fanout histogram 337811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::mean 0.358566 # Request fanout histogram 337911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.483567 # Request fanout histogram 338010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 338111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::0 5613365 64.34% 64.34% # Request fanout histogram 338211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::1 3095034 35.47% 99.81% # Request fanout histogram 338311606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::2 16756 0.19% 100.00% # Request fanout histogram 338410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 338511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 338610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 338711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::total 8725155 # Request fanout histogram 338811606Sandreas.sandberg@arm.comsystem.toL2Bus.reqLayer0.occupancy 9593262018 # Layer occupancy (ticks) 338910515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 339011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2632911 # Layer occupancy (ticks) 339110515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 339211606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer0.occupancy 4411209152 # Layer occupancy (ticks) 339310515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 339411606Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer1.occupancy 4336941336 # Layer occupancy (ticks) 339510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 339610515SAli.Saidi@ARM.com 339710515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3398