stats.txt revision 11606
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.276773 # Number of seconds simulated 4sim_ticks 47276772827000 # Number of ticks simulated 5final_tick 47276772827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 146674 # Simulator instruction rate (inst/s) 8host_op_rate 172507 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7728246229 # Simulator tick rate (ticks/s) 10host_mem_usage 772984 # Number of bytes of host memory used 11host_seconds 6117.40 # Real time elapsed on the host 12sim_insts 897262562 # Number of instructions simulated 13sim_ops 1055295890 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 117376 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 90560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7953664 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13400200 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 16005120 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 165760 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 157376 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3942400 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 13075216 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 14708224 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 454784 # Number of bytes read from this memory 28system.physmem.bytes_read::total 70070680 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 7953664 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3942400 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 11896064 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 81443392 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 81463976 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1834 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1415 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 124276 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 209391 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 250080 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2590 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2459 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 61600 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 204313 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 229816 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 7106 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1094880 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1272553 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1275127 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2483 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 1916 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 168236 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 283442 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 338541 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 3506 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 3329 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 83390 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 276567 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 311109 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9620 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1482138 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 168236 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 83390 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 251626 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1722694 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1723129 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1722694 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2483 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 1916 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 168236 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 283877 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 338541 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 3506 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 3329 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 83390 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 276568 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 311109 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9620 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 3205266 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 1094880 # Number of read requests accepted 85system.physmem.writeReqs 1275127 # Number of write requests accepted 86system.physmem.readBursts 1094880 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1275127 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 70042240 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 30080 # Total number of bytes read from write queue 90system.physmem.bytesWritten 81461504 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 70070680 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 81463976 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 470 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 60604 # Per bank write bursts 97system.physmem.perBankRdBursts::1 71691 # Per bank write bursts 98system.physmem.perBankRdBursts::2 59265 # Per bank write bursts 99system.physmem.perBankRdBursts::3 66946 # Per bank write bursts 100system.physmem.perBankRdBursts::4 67906 # Per bank write bursts 101system.physmem.perBankRdBursts::5 80109 # Per bank write bursts 102system.physmem.perBankRdBursts::6 61949 # Per bank write bursts 103system.physmem.perBankRdBursts::7 69447 # Per bank write bursts 104system.physmem.perBankRdBursts::8 60494 # Per bank write bursts 105system.physmem.perBankRdBursts::9 115448 # Per bank write bursts 106system.physmem.perBankRdBursts::10 56514 # Per bank write bursts 107system.physmem.perBankRdBursts::11 69665 # Per bank write bursts 108system.physmem.perBankRdBursts::12 63387 # Per bank write bursts 109system.physmem.perBankRdBursts::13 66346 # Per bank write bursts 110system.physmem.perBankRdBursts::14 64421 # Per bank write bursts 111system.physmem.perBankRdBursts::15 60218 # Per bank write bursts 112system.physmem.perBankWrBursts::0 77101 # Per bank write bursts 113system.physmem.perBankWrBursts::1 84577 # Per bank write bursts 114system.physmem.perBankWrBursts::2 74746 # Per bank write bursts 115system.physmem.perBankWrBursts::3 81276 # Per bank write bursts 116system.physmem.perBankWrBursts::4 79990 # Per bank write bursts 117system.physmem.perBankWrBursts::5 87328 # Per bank write bursts 118system.physmem.perBankWrBursts::6 77464 # Per bank write bursts 119system.physmem.perBankWrBursts::7 81707 # Per bank write bursts 120system.physmem.perBankWrBursts::8 78209 # Per bank write bursts 121system.physmem.perBankWrBursts::9 81569 # Per bank write bursts 122system.physmem.perBankWrBursts::10 73819 # Per bank write bursts 123system.physmem.perBankWrBursts::11 80687 # Per bank write bursts 124system.physmem.perBankWrBursts::12 78674 # Per bank write bursts 125system.physmem.perBankWrBursts::13 80970 # Per bank write bursts 126system.physmem.perBankWrBursts::14 77560 # Per bank write bursts 127system.physmem.perBankWrBursts::15 77159 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 62 # Number of times write queue was full causing retry 130system.physmem.totGap 47276770796500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 1094850 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1272553 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 725931 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 132585 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 49587 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 38066 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 32959 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 30077 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 28140 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 24582 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 22148 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 4123 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1854 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 1222 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 970 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 398 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 328 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 280 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 226 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 26459 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 34937 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 52906 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 61188 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 67814 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 70802 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 73289 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 75619 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 78304 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 78281 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 81577 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 85157 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 81436 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 80619 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 87129 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 77597 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 71470 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 67901 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3383 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2425 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1908 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1516 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1151 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 1019 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 902 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 665 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 564 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 402 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 380 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 456 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 357 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 373 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 412 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 339 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 291 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 298 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 296 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 274 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 277 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 275 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 223 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 225 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 157 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 212 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 1013795 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 149.441747 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 100.507639 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 197.056675 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 662057 65.30% 65.30% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 208347 20.55% 85.86% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 52181 5.15% 91.00% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 23884 2.36% 93.36% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 17639 1.74% 95.10% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 11113 1.10% 96.20% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 7357 0.73% 96.92% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 6249 0.62% 97.54% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 24968 2.46% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 1013795 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 63452 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.247415 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 156.483425 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 63450 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 63452 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 63452 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.059825 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.482738 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 12.878895 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 55385 87.29% 87.29% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 2264 3.57% 90.85% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 727 1.15% 92.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 608 0.96% 92.96% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 1019 1.61% 94.56% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 457 0.72% 95.28% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 338 0.53% 95.82% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 295 0.46% 96.28% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 198 0.31% 96.59% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 179 0.28% 96.88% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 127 0.20% 97.08% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 154 0.24% 97.32% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 464 0.73% 98.05% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 118 0.19% 98.24% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 142 0.22% 98.46% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 119 0.19% 98.65% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 89 0.14% 98.79% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 71 0.11% 98.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 72 0.11% 99.01% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 80 0.13% 99.14% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 103 0.16% 99.30% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 73 0.12% 99.42% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 46 0.07% 99.49% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 54 0.09% 99.57% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 48 0.08% 99.65% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 39 0.06% 99.71% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 53 0.08% 99.80% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 25 0.04% 99.83% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 49 0.08% 99.91% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::132-135 20 0.03% 99.94% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::136-139 13 0.02% 99.96% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::140-143 6 0.01% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::152-155 2 0.00% 99.98% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::total 63452 # Writes before turning the bus around for reads 307system.physmem.totQLat 38795138463 # Total ticks spent queuing 308system.physmem.totMemAccLat 59315325963 # Total ticks spent from burst creation until serviced by the DRAM 309system.physmem.totBusLat 5472050000 # Total ticks spent in databus transfers 310system.physmem.avgQLat 35448.45 # Average queueing delay per DRAM burst 311system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 312system.physmem.avgMemAccLat 54198.45 # Average memory access latency per DRAM burst 313system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s 314system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s 315system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s 316system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s 317system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 318system.physmem.busUtil 0.03 # Data bus utilization in percentage 319system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 320system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 321system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 322system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing 323system.physmem.readRowHits 817920 # Number of row buffer hits during reads 324system.physmem.writeRowHits 535530 # Number of row buffer hits during writes 325system.physmem.readRowHitRate 74.74 # Row buffer hit rate for reads 326system.physmem.writeRowHitRate 42.07 # Row buffer hit rate for writes 327system.physmem.avgGap 19947945.64 # Average gap between requests 328system.physmem.pageHitRate 57.17 # Row buffer hit rate, read and write combined 329system.physmem_0.actEnergy 3880003680 # Energy for activate commands per rank (pJ) 330system.physmem_0.preEnergy 2117065500 # Energy for precharge commands per rank (pJ) 331system.physmem_0.readEnergy 4195752600 # Energy for read commands per rank (pJ) 332system.physmem_0.writeEnergy 4174344720 # Energy for write commands per rank (pJ) 333system.physmem_0.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) 334system.physmem_0.actBackEnergy 1190314271070 # Energy for active background per rank (pJ) 335system.physmem_0.preBackEnergy 27321927289500 # Energy for precharge background per rank (pJ) 336system.physmem_0.totalEnergy 31614497574750 # Total energy per rank (pJ) 337system.physmem_0.averagePower 668.711016 # Core power per rank (mW) 338system.physmem_0.memoryStateTime::IDLE 45452122728628 # Time in different power states 339system.physmem_0.memoryStateTime::REF 1578675280000 # Time in different power states 340system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 341system.physmem_0.memoryStateTime::ACT 245973030122 # Time in different power states 342system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 343system.physmem_1.actEnergy 3784278960 # Energy for activate commands per rank (pJ) 344system.physmem_1.preEnergy 2064834750 # Energy for precharge commands per rank (pJ) 345system.physmem_1.readEnergy 4340583000 # Energy for read commands per rank (pJ) 346system.physmem_1.writeEnergy 4073632560 # Energy for write commands per rank (pJ) 347system.physmem_1.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) 348system.physmem_1.actBackEnergy 1186461286245 # Energy for active background per rank (pJ) 349system.physmem_1.preBackEnergy 27325307092500 # Energy for precharge background per rank (pJ) 350system.physmem_1.totalEnergy 31613920555695 # Total energy per rank (pJ) 351system.physmem_1.averagePower 668.698811 # Core power per rank (mW) 352system.physmem_1.memoryStateTime::IDLE 45457733356018 # Time in different power states 353system.physmem_1.memoryStateTime::REF 1578675280000 # Time in different power states 354system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 355system.physmem_1.memoryStateTime::ACT 240362584982 # Time in different power states 356system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 357system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 358system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 360system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 365system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 366system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 369system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 370system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 371system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 383system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 384system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 385system.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 386system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 387system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 388system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 389system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 390system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 391system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 392system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 393system.cpu0.branchPred.lookups 132137665 # Number of BP lookups 394system.cpu0.branchPred.condPredicted 93617551 # Number of conditional branches predicted 395system.cpu0.branchPred.condIncorrect 5999845 # Number of conditional branches incorrect 396system.cpu0.branchPred.BTBLookups 98810350 # Number of BTB lookups 397system.cpu0.branchPred.BTBHits 69427031 # Number of BTB hits 398system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 399system.cpu0.branchPred.BTBHitPct 70.262914 # BTB Hit Percentage 400system.cpu0.branchPred.usedRAS 15260285 # Number of times the RAS was used to get a target. 401system.cpu0.branchPred.RASInCorrect 1044115 # Number of incorrect RAS predictions. 402system.cpu0.branchPred.indirectLookups 3387017 # Number of indirect predictor lookups. 403system.cpu0.branchPred.indirectHits 2259695 # Number of indirect target hits. 404system.cpu0.branchPred.indirectMisses 1127322 # Number of indirect misses. 405system.cpu0.branchPredindirectMispredicted 409659 # Number of mispredicted indirect branches. 406system.cpu_clk_domain.clock 500 # Clock period in ticks 407system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 416system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 417system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 418system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 419system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 420system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 421system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 422system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 423system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 424system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 425system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 426system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 427system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 428system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 429system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 430system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 431system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 432system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 433system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 434system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 435system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 436system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 437system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 438system.cpu0.dtb.walker.walks 271762 # Table walker walks requested 439system.cpu0.dtb.walker.walksLong 271762 # Table walker walks initiated with long descriptors 440system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10351 # Level at which table walker walks with long descriptors terminate 441system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74846 # Level at which table walker walks with long descriptors terminate 442system.cpu0.dtb.walker.walkWaitTime::samples 271762 # Table walker wait (enqueue to first request) latency 443system.cpu0.dtb.walker.walkWaitTime::0 271762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 444system.cpu0.dtb.walker.walkWaitTime::total 271762 # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkCompletionTime::samples 85197 # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512 # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295 # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::0-65535 84296 98.94% 98.94% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::65536-131071 776 0.91% 99.85% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::131072-196607 35 0.04% 99.89% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.94% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::262144-327679 35 0.04% 99.98% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::total 85197 # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution 463system.cpu0.dtb.walker.walkPageSizes::4K 74846 87.85% 87.85% # Table walker page sizes translated 464system.cpu0.dtb.walker.walkPageSizes::2M 10351 12.15% 100.00% # Table walker page sizes translated 465system.cpu0.dtb.walker.walkPageSizes::total 85197 # Table walker page sizes translated 466system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271762 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271762 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85197 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85197 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin::total 356959 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.inst_hits 0 # ITB inst hits 474system.cpu0.dtb.inst_misses 0 # ITB inst misses 475system.cpu0.dtb.read_hits 82756248 # DTB read hits 476system.cpu0.dtb.read_misses 224730 # DTB read misses 477system.cpu0.dtb.write_hits 74117187 # DTB write hits 478system.cpu0.dtb.write_misses 47032 # DTB write misses 479system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 480system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 481system.cpu0.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 482system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 483system.cpu0.dtb.flush_entries 34573 # Number of entries that have been flushed from TLB 484system.cpu0.dtb.align_faults 2108 # Number of TLB faults due to alignment restrictions 485system.cpu0.dtb.prefetch_faults 9506 # Number of TLB faults due to prefetch 486system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu0.dtb.perms_faults 11030 # Number of TLB faults due to permissions restrictions 488system.cpu0.dtb.read_accesses 82980978 # DTB read accesses 489system.cpu0.dtb.write_accesses 74164219 # DTB write accesses 490system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 491system.cpu0.dtb.hits 156873435 # DTB hits 492system.cpu0.dtb.misses 271762 # DTB misses 493system.cpu0.dtb.accesses 157145197 # DTB accesses 494system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 495system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 504system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 505system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 506system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 507system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 508system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 511system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 512system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 513system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 514system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 515system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 516system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 517system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 518system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 519system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 520system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 521system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 522system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 523system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 524system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 525system.cpu0.itb.walker.walks 60398 # Table walker walks requested 526system.cpu0.itb.walker.walksLong 60398 # Table walker walks initiated with long descriptors 527system.cpu0.itb.walker.walksLongTerminationLevel::Level2 589 # Level at which table walker walks with long descriptors terminate 528system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51882 # Level at which table walker walks with long descriptors terminate 529system.cpu0.itb.walker.walkWaitTime::samples 60398 # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::0 60398 100.00% 100.00% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::total 60398 # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkCompletionTime::samples 52471 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428 # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::0-32767 46836 89.26% 89.26% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::32768-65535 4750 9.05% 98.31% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::65536-98303 22 0.04% 98.36% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::98304-131071 772 1.47% 99.83% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.87% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::163840-196607 15 0.03% 99.90% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::196608-229375 26 0.05% 99.95% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.96% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::327680-360447 9 0.02% 100.00% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::total 52471 # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution 551system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution 553system.cpu0.itb.walker.walkPageSizes::4K 51882 98.88% 98.88% # Table walker page sizes translated 554system.cpu0.itb.walker.walkPageSizes::2M 589 1.12% 100.00% # Table walker page sizes translated 555system.cpu0.itb.walker.walkPageSizes::total 52471 # Table walker page sizes translated 556system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 557system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60398 # Table walker requests started/completed, data/inst 558system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60398 # Table walker requests started/completed, data/inst 559system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 560system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52471 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52471 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin::total 112869 # Table walker requests started/completed, data/inst 563system.cpu0.itb.inst_hits 234456044 # ITB inst hits 564system.cpu0.itb.inst_misses 60398 # ITB inst misses 565system.cpu0.itb.read_hits 0 # DTB read hits 566system.cpu0.itb.read_misses 0 # DTB read misses 567system.cpu0.itb.write_hits 0 # DTB write hits 568system.cpu0.itb.write_misses 0 # DTB write misses 569system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 570system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 571system.cpu0.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 572system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 573system.cpu0.itb.flush_entries 24118 # Number of entries that have been flushed from TLB 574system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 575system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 576system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 577system.cpu0.itb.perms_faults 160109 # Number of TLB faults due to permissions restrictions 578system.cpu0.itb.read_accesses 0 # DTB read accesses 579system.cpu0.itb.write_accesses 0 # DTB write accesses 580system.cpu0.itb.inst_accesses 234516442 # ITB inst accesses 581system.cpu0.itb.hits 234456044 # DTB hits 582system.cpu0.itb.misses 60398 # DTB misses 583system.cpu0.itb.accesses 234516442 # DTB accesses 584system.cpu0.numPwrStateTransitions 8178 # Number of power state transitions 585system.cpu0.pwrStateClkGateDist::samples 4089 # Distribution of time spent in the clock gated state 586system.cpu0.pwrStateClkGateDist::mean 11447226771.455124 # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::stdev 162386644618.467285 # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateClkGateDist::underflows 2836 69.36% 69.36% # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::1000-5e+10 1230 30.08% 99.44% # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.51% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.56% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::overflows 14 0.34% 100.00% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::max_value 7470355608744 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::total 4089 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateResidencyTicks::ON 469062558520 # Cumulative time (in ticks) in various power states 602system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480 # Cumulative time (in ticks) in various power states 603system.cpu0.numCycles 938130839 # number of cpu cycles simulated 604system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 605system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 606system.cpu0.committedInsts 430200528 # Number of instructions committed 607system.cpu0.committedOps 505771410 # Number of ops (including micro ops) committed 608system.cpu0.discardedOps 45690974 # Number of ops (including micro ops) which were discarded before commit 609system.cpu0.numFetchSuspends 3904 # Number of times Execute suspended instruction fetching 610system.cpu0.quiesceCycles 93616054941 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 611system.cpu0.cpi 2.180683 # CPI: cycles per instruction 612system.cpu0.ipc 0.458572 # IPC: instructions per cycle 613system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 614system.cpu0.op_class_0::IntAlu 351125189 69.42% 69.42% # Class of committed instruction 615system.cpu0.op_class_0::IntMult 1073769 0.21% 69.64% # Class of committed instruction 616system.cpu0.op_class_0::IntDiv 52983 0.01% 69.65% # Class of committed instruction 617system.cpu0.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction 618system.cpu0.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction 619system.cpu0.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction 620system.cpu0.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction 621system.cpu0.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction 622system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction 623system.cpu0.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction 624system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction 625system.cpu0.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction 626system.cpu0.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction 627system.cpu0.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction 628system.cpu0.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction 629system.cpu0.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction 630system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction 631system.cpu0.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction 632system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction 633system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction 634system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.65% # Class of committed instruction 635system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction 636system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.65% # Class of committed instruction 637system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.65% # Class of committed instruction 638system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction 639system.cpu0.op_class_0::SimdFloatMisc 68782 0.01% 69.66% # Class of committed instruction 640system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction 641system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction 642system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction 643system.cpu0.op_class_0::MemRead 79655364 15.75% 85.41% # Class of committed instruction 644system.cpu0.op_class_0::MemWrite 73795280 14.59% 100.00% # Class of committed instruction 645system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 646system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 647system.cpu0.op_class_0::total 505771410 # Class of committed instruction 648system.cpu0.kern.inst.arm 0 # number of arm instructions executed 649system.cpu0.kern.inst.quiesce 4089 # number of quiesce instructions executed 650system.cpu0.tickCycles 697846091 # Number of cycles that the object actually ticked 651system.cpu0.idleCycles 240284748 # Total number of cycles that the object has spent stopped 652system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 653system.cpu0.dcache.tags.replacements 5497391 # number of replacements 654system.cpu0.dcache.tags.tagsinuse 500.377946 # Cycle average of tags in use 655system.cpu0.dcache.tags.total_refs 148839422 # Total number of references to valid blocks. 656system.cpu0.dcache.tags.sampled_refs 5497903 # Sample count of references to valid blocks. 657system.cpu0.dcache.tags.avg_refs 27.072035 # Average number of references to valid blocks. 658system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. 659system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.377946 # Average occupied blocks per requestor 660system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977301 # Average percentage of cache occupancy 661system.cpu0.dcache.tags.occ_percent::total 0.977301 # Average percentage of cache occupancy 662system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 663system.cpu0.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 664system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id 665system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 666system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 667system.cpu0.dcache.tags.tag_accesses 316768421 # Number of tag accesses 668system.cpu0.dcache.tags.data_accesses 316768421 # Number of data accesses 669system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 670system.cpu0.dcache.ReadReq_hits::cpu0.data 75978032 # number of ReadReq hits 671system.cpu0.dcache.ReadReq_hits::total 75978032 # number of ReadReq hits 672system.cpu0.dcache.WriteReq_hits::cpu0.data 68482955 # number of WriteReq hits 673system.cpu0.dcache.WriteReq_hits::total 68482955 # number of WriteReq hits 674system.cpu0.dcache.SoftPFReq_hits::cpu0.data 264842 # number of SoftPFReq hits 675system.cpu0.dcache.SoftPFReq_hits::total 264842 # number of SoftPFReq hits 676system.cpu0.dcache.WriteLineReq_hits::cpu0.data 244065 # number of WriteLineReq hits 677system.cpu0.dcache.WriteLineReq_hits::total 244065 # number of WriteLineReq hits 678system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1687572 # number of LoadLockedReq hits 679system.cpu0.dcache.LoadLockedReq_hits::total 1687572 # number of LoadLockedReq hits 680system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1654235 # number of StoreCondReq hits 681system.cpu0.dcache.StoreCondReq_hits::total 1654235 # number of StoreCondReq hits 682system.cpu0.dcache.demand_hits::cpu0.data 144705052 # number of demand (read+write) hits 683system.cpu0.dcache.demand_hits::total 144705052 # number of demand (read+write) hits 684system.cpu0.dcache.overall_hits::cpu0.data 144969894 # number of overall hits 685system.cpu0.dcache.overall_hits::total 144969894 # number of overall hits 686system.cpu0.dcache.ReadReq_misses::cpu0.data 3066734 # number of ReadReq misses 687system.cpu0.dcache.ReadReq_misses::total 3066734 # number of ReadReq misses 688system.cpu0.dcache.WriteReq_misses::cpu0.data 2419958 # number of WriteReq misses 689system.cpu0.dcache.WriteReq_misses::total 2419958 # number of WriteReq misses 690system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670609 # number of SoftPFReq misses 691system.cpu0.dcache.SoftPFReq_misses::total 670609 # number of SoftPFReq misses 692system.cpu0.dcache.WriteLineReq_misses::cpu0.data 786129 # number of WriteLineReq misses 693system.cpu0.dcache.WriteLineReq_misses::total 786129 # number of WriteLineReq misses 694system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148878 # number of LoadLockedReq misses 695system.cpu0.dcache.LoadLockedReq_misses::total 148878 # number of LoadLockedReq misses 696system.cpu0.dcache.StoreCondReq_misses::cpu0.data 181031 # number of StoreCondReq misses 697system.cpu0.dcache.StoreCondReq_misses::total 181031 # number of StoreCondReq misses 698system.cpu0.dcache.demand_misses::cpu0.data 6272821 # number of demand (read+write) misses 699system.cpu0.dcache.demand_misses::total 6272821 # number of demand (read+write) misses 700system.cpu0.dcache.overall_misses::cpu0.data 6943430 # number of overall misses 701system.cpu0.dcache.overall_misses::total 6943430 # number of overall misses 702system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47243422000 # number of ReadReq miss cycles 703system.cpu0.dcache.ReadReq_miss_latency::total 47243422000 # number of ReadReq miss cycles 704system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 49248110500 # number of WriteReq miss cycles 705system.cpu0.dcache.WriteReq_miss_latency::total 49248110500 # number of WriteReq miss cycles 706system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26231986000 # number of WriteLineReq miss cycles 707system.cpu0.dcache.WriteLineReq_miss_latency::total 26231986000 # number of WriteLineReq miss cycles 708system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2187373500 # number of LoadLockedReq miss cycles 709system.cpu0.dcache.LoadLockedReq_miss_latency::total 2187373500 # number of LoadLockedReq miss cycles 710system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4323764500 # number of StoreCondReq miss cycles 711system.cpu0.dcache.StoreCondReq_miss_latency::total 4323764500 # number of StoreCondReq miss cycles 712system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2754000 # number of StoreCondFailReq miss cycles 713system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2754000 # number of StoreCondFailReq miss cycles 714system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500 # number of demand (read+write) miss cycles 715system.cpu0.dcache.demand_miss_latency::total 122723518500 # number of demand (read+write) miss cycles 716system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500 # number of overall miss cycles 717system.cpu0.dcache.overall_miss_latency::total 122723518500 # number of overall miss cycles 718system.cpu0.dcache.ReadReq_accesses::cpu0.data 79044766 # number of ReadReq accesses(hits+misses) 719system.cpu0.dcache.ReadReq_accesses::total 79044766 # number of ReadReq accesses(hits+misses) 720system.cpu0.dcache.WriteReq_accesses::cpu0.data 70902913 # number of WriteReq accesses(hits+misses) 721system.cpu0.dcache.WriteReq_accesses::total 70902913 # number of WriteReq accesses(hits+misses) 722system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935451 # number of SoftPFReq accesses(hits+misses) 723system.cpu0.dcache.SoftPFReq_accesses::total 935451 # number of SoftPFReq accesses(hits+misses) 724system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1030194 # number of WriteLineReq accesses(hits+misses) 725system.cpu0.dcache.WriteLineReq_accesses::total 1030194 # number of WriteLineReq accesses(hits+misses) 726system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1836450 # number of LoadLockedReq accesses(hits+misses) 727system.cpu0.dcache.LoadLockedReq_accesses::total 1836450 # number of LoadLockedReq accesses(hits+misses) 728system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1835266 # number of StoreCondReq accesses(hits+misses) 729system.cpu0.dcache.StoreCondReq_accesses::total 1835266 # number of StoreCondReq accesses(hits+misses) 730system.cpu0.dcache.demand_accesses::cpu0.data 150977873 # number of demand (read+write) accesses 731system.cpu0.dcache.demand_accesses::total 150977873 # number of demand (read+write) accesses 732system.cpu0.dcache.overall_accesses::cpu0.data 151913324 # number of overall (read+write) accesses 733system.cpu0.dcache.overall_accesses::total 151913324 # number of overall (read+write) accesses 734system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038797 # miss rate for ReadReq accesses 735system.cpu0.dcache.ReadReq_miss_rate::total 0.038797 # miss rate for ReadReq accesses 736system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.034131 # miss rate for WriteReq accesses 737system.cpu0.dcache.WriteReq_miss_rate::total 0.034131 # miss rate for WriteReq accesses 738system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716883 # miss rate for SoftPFReq accesses 739system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716883 # miss rate for SoftPFReq accesses 740system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763088 # miss rate for WriteLineReq accesses 741system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763088 # miss rate for WriteLineReq accesses 742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081068 # miss rate for LoadLockedReq accesses 743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081068 # miss rate for LoadLockedReq accesses 744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098640 # miss rate for StoreCondReq accesses 745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098640 # miss rate for StoreCondReq accesses 746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses 747system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses 748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045707 # miss rate for overall accesses 749system.cpu0.dcache.overall_miss_rate::total 0.045707 # miss rate for overall accesses 750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453 # average ReadReq miss latency 751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453 # average ReadReq miss latency 752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080 # average WriteReq miss latency 753system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080 # average WriteReq miss latency 754system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472 # average WriteLineReq miss latency 755system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472 # average WriteLineReq miss latency 756system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070 # average LoadLockedReq miss latency 757system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070 # average LoadLockedReq miss latency 758system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009 # average StoreCondReq miss latency 759system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009 # average StoreCondReq miss latency 760system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 761system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 762system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561 # average overall miss latency 763system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561 # average overall miss latency 764system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594 # average overall miss latency 765system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594 # average overall miss latency 766system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 768system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 769system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 770system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 772system.cpu0.dcache.writebacks::writebacks 5497393 # number of writebacks 773system.cpu0.dcache.writebacks::total 5497393 # number of writebacks 774system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200047 # number of ReadReq MSHR hits 775system.cpu0.dcache.ReadReq_mshr_hits::total 200047 # number of ReadReq MSHR hits 776system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012976 # number of WriteReq MSHR hits 777system.cpu0.dcache.WriteReq_mshr_hits::total 1012976 # number of WriteReq MSHR hits 778system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 94 # number of WriteLineReq MSHR hits 779system.cpu0.dcache.WriteLineReq_mshr_hits::total 94 # number of WriteLineReq MSHR hits 780system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39271 # number of LoadLockedReq MSHR hits 781system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39271 # number of LoadLockedReq MSHR hits 782system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 90 # number of StoreCondReq MSHR hits 783system.cpu0.dcache.StoreCondReq_mshr_hits::total 90 # number of StoreCondReq MSHR hits 784system.cpu0.dcache.demand_mshr_hits::cpu0.data 1213117 # number of demand (read+write) MSHR hits 785system.cpu0.dcache.demand_mshr_hits::total 1213117 # number of demand (read+write) MSHR hits 786system.cpu0.dcache.overall_mshr_hits::cpu0.data 1213117 # number of overall MSHR hits 787system.cpu0.dcache.overall_mshr_hits::total 1213117 # number of overall MSHR hits 788system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2866687 # number of ReadReq MSHR misses 789system.cpu0.dcache.ReadReq_mshr_misses::total 2866687 # number of ReadReq MSHR misses 790system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1406982 # number of WriteReq MSHR misses 791system.cpu0.dcache.WriteReq_mshr_misses::total 1406982 # number of WriteReq MSHR misses 792system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668415 # number of SoftPFReq MSHR misses 793system.cpu0.dcache.SoftPFReq_mshr_misses::total 668415 # number of SoftPFReq MSHR misses 794system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 786035 # number of WriteLineReq MSHR misses 795system.cpu0.dcache.WriteLineReq_mshr_misses::total 786035 # number of WriteLineReq MSHR misses 796system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109607 # number of LoadLockedReq MSHR misses 797system.cpu0.dcache.LoadLockedReq_mshr_misses::total 109607 # number of LoadLockedReq MSHR misses 798system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180941 # number of StoreCondReq MSHR misses 799system.cpu0.dcache.StoreCondReq_mshr_misses::total 180941 # number of StoreCondReq MSHR misses 800system.cpu0.dcache.demand_mshr_misses::cpu0.data 5059704 # number of demand (read+write) MSHR misses 801system.cpu0.dcache.demand_mshr_misses::total 5059704 # number of demand (read+write) MSHR misses 802system.cpu0.dcache.overall_mshr_misses::cpu0.data 5728119 # number of overall MSHR misses 803system.cpu0.dcache.overall_mshr_misses::total 5728119 # number of overall MSHR misses 804system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 805system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20634 # number of ReadReq MSHR uncacheable 806system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 807system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable 808system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 809system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42909 # number of overall MSHR uncacheable misses 810system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39457015000 # number of ReadReq MSHR miss cycles 811system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39457015000 # number of ReadReq MSHR miss cycles 812system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27671793000 # number of WriteReq MSHR miss cycles 813system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27671793000 # number of WriteReq MSHR miss cycles 814system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15966528000 # number of SoftPFReq MSHR miss cycles 815system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15966528000 # number of SoftPFReq MSHR miss cycles 816system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25439405000 # number of WriteLineReq MSHR miss cycles 817system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25439405000 # number of WriteLineReq MSHR miss cycles 818system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1452927000 # number of LoadLockedReq MSHR miss cycles 819system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1452927000 # number of LoadLockedReq MSHR miss cycles 820system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4140525000 # number of StoreCondReq MSHR miss cycles 821system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4140525000 # number of StoreCondReq MSHR miss cycles 822system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2476500 # number of StoreCondFailReq MSHR miss cycles 823system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2476500 # number of StoreCondFailReq MSHR miss cycles 824system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92568213000 # number of demand (read+write) MSHR miss cycles 825system.cpu0.dcache.demand_mshr_miss_latency::total 92568213000 # number of demand (read+write) MSHR miss cycles 826system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000 # number of overall MSHR miss cycles 827system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000 # number of overall MSHR miss cycles 828system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4015086500 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4015086500 # number of ReadReq MSHR uncacheable cycles 830system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4015086500 # number of overall MSHR uncacheable cycles 831system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4015086500 # number of overall MSHR uncacheable cycles 832system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036267 # mshr miss rate for ReadReq accesses 833system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036267 # mshr miss rate for ReadReq accesses 834system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019844 # mshr miss rate for WriteReq accesses 835system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019844 # mshr miss rate for WriteReq accesses 836system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714538 # mshr miss rate for SoftPFReq accesses 837system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714538 # mshr miss rate for SoftPFReq accesses 838system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.762997 # mshr miss rate for WriteLineReq accesses 839system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.762997 # mshr miss rate for WriteLineReq accesses 840system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059684 # mshr miss rate for LoadLockedReq accesses 841system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059684 # mshr miss rate for LoadLockedReq accesses 842system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098591 # mshr miss rate for StoreCondReq accesses 843system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098591 # mshr miss rate for StoreCondReq accesses 844system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033513 # mshr miss rate for demand accesses 845system.cpu0.dcache.demand_mshr_miss_rate::total 0.033513 # mshr miss rate for demand accesses 846system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037706 # mshr miss rate for overall accesses 847system.cpu0.dcache.overall_mshr_miss_rate::total 0.037706 # mshr miss rate for overall accesses 848system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372 # average ReadReq mshr miss latency 849system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372 # average ReadReq mshr miss latency 850system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887 # average WriteReq mshr miss latency 851system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887 # average WriteReq mshr miss latency 852system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954 # average SoftPFReq mshr miss latency 853system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954 # average SoftPFReq mshr miss latency 854system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062 # average WriteLineReq mshr miss latency 855system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062 # average WriteLineReq mshr miss latency 856system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583 # average LoadLockedReq mshr miss latency 857system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583 # average LoadLockedReq mshr miss latency 858system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923 # average StoreCondReq mshr miss latency 859system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923 # average StoreCondReq mshr miss latency 860system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 861system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 862system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473 # average overall mshr miss latency 863system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473 # average overall mshr miss latency 864system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584 # average overall mshr miss latency 865system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584 # average overall mshr miss latency 866system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373 # average ReadReq mshr uncacheable latency 867system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373 # average ReadReq mshr uncacheable latency 868system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390 # average overall mshr uncacheable latency 869system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390 # average overall mshr uncacheable latency 870system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 871system.cpu0.icache.tags.replacements 9280608 # number of replacements 872system.cpu0.icache.tags.tagsinuse 511.932285 # Cycle average of tags in use 873system.cpu0.icache.tags.total_refs 225009210 # Total number of references to valid blocks. 874system.cpu0.icache.tags.sampled_refs 9281120 # Sample count of references to valid blocks. 875system.cpu0.icache.tags.avg_refs 24.243756 # Average number of references to valid blocks. 876system.cpu0.icache.tags.warmup_cycle 22204306000 # Cycle when the warmup percentage was hit. 877system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932285 # Average occupied blocks per requestor 878system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 879system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 880system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 881system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 882system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 883system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id 884system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 885system.cpu0.icache.tags.tag_accesses 477861809 # Number of tag accesses 886system.cpu0.icache.tags.data_accesses 477861809 # Number of data accesses 887system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 888system.cpu0.icache.ReadReq_hits::cpu0.inst 225009210 # number of ReadReq hits 889system.cpu0.icache.ReadReq_hits::total 225009210 # number of ReadReq hits 890system.cpu0.icache.demand_hits::cpu0.inst 225009210 # number of demand (read+write) hits 891system.cpu0.icache.demand_hits::total 225009210 # number of demand (read+write) hits 892system.cpu0.icache.overall_hits::cpu0.inst 225009210 # number of overall hits 893system.cpu0.icache.overall_hits::total 225009210 # number of overall hits 894system.cpu0.icache.ReadReq_misses::cpu0.inst 9281130 # number of ReadReq misses 895system.cpu0.icache.ReadReq_misses::total 9281130 # number of ReadReq misses 896system.cpu0.icache.demand_misses::cpu0.inst 9281130 # number of demand (read+write) misses 897system.cpu0.icache.demand_misses::total 9281130 # number of demand (read+write) misses 898system.cpu0.icache.overall_misses::cpu0.inst 9281130 # number of overall misses 899system.cpu0.icache.overall_misses::total 9281130 # number of overall misses 900system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94226606500 # number of ReadReq miss cycles 901system.cpu0.icache.ReadReq_miss_latency::total 94226606500 # number of ReadReq miss cycles 902system.cpu0.icache.demand_miss_latency::cpu0.inst 94226606500 # number of demand (read+write) miss cycles 903system.cpu0.icache.demand_miss_latency::total 94226606500 # number of demand (read+write) miss cycles 904system.cpu0.icache.overall_miss_latency::cpu0.inst 94226606500 # number of overall miss cycles 905system.cpu0.icache.overall_miss_latency::total 94226606500 # number of overall miss cycles 906system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290340 # number of ReadReq accesses(hits+misses) 907system.cpu0.icache.ReadReq_accesses::total 234290340 # number of ReadReq accesses(hits+misses) 908system.cpu0.icache.demand_accesses::cpu0.inst 234290340 # number of demand (read+write) accesses 909system.cpu0.icache.demand_accesses::total 234290340 # number of demand (read+write) accesses 910system.cpu0.icache.overall_accesses::cpu0.inst 234290340 # number of overall (read+write) accesses 911system.cpu0.icache.overall_accesses::total 234290340 # number of overall (read+write) accesses 912system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039614 # miss rate for ReadReq accesses 913system.cpu0.icache.ReadReq_miss_rate::total 0.039614 # miss rate for ReadReq accesses 914system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039614 # miss rate for demand accesses 915system.cpu0.icache.demand_miss_rate::total 0.039614 # miss rate for demand accesses 916system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039614 # miss rate for overall accesses 917system.cpu0.icache.overall_miss_rate::total 0.039614 # miss rate for overall accesses 918system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908 # average ReadReq miss latency 919system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908 # average ReadReq miss latency 920system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency 921system.cpu0.icache.demand_avg_miss_latency::total 10152.492908 # average overall miss latency 922system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency 923system.cpu0.icache.overall_avg_miss_latency::total 10152.492908 # average overall miss latency 924system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 925system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 926system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 927system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 928system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 929system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 930system.cpu0.icache.writebacks::writebacks 9280608 # number of writebacks 931system.cpu0.icache.writebacks::total 9280608 # number of writebacks 932system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9281130 # number of ReadReq MSHR misses 933system.cpu0.icache.ReadReq_mshr_misses::total 9281130 # number of ReadReq MSHR misses 934system.cpu0.icache.demand_mshr_misses::cpu0.inst 9281130 # number of demand (read+write) MSHR misses 935system.cpu0.icache.demand_mshr_misses::total 9281130 # number of demand (read+write) MSHR misses 936system.cpu0.icache.overall_mshr_misses::cpu0.inst 9281130 # number of overall MSHR misses 937system.cpu0.icache.overall_mshr_misses::total 9281130 # number of overall MSHR misses 938system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 939system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable 940system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 941system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses 942system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89586042000 # number of ReadReq MSHR miss cycles 943system.cpu0.icache.ReadReq_mshr_miss_latency::total 89586042000 # number of ReadReq MSHR miss cycles 944system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89586042000 # number of demand (read+write) MSHR miss cycles 945system.cpu0.icache.demand_mshr_miss_latency::total 89586042000 # number of demand (read+write) MSHR miss cycles 946system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89586042000 # number of overall MSHR miss cycles 947system.cpu0.icache.overall_mshr_miss_latency::total 89586042000 # number of overall MSHR miss cycles 948system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles 949system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles 950system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles 951system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles 952system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for ReadReq accesses 953system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039614 # mshr miss rate for ReadReq accesses 954system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for demand accesses 955system.cpu0.icache.demand_mshr_miss_rate::total 0.039614 # mshr miss rate for demand accesses 956system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for overall accesses 957system.cpu0.icache.overall_mshr_miss_rate::total 0.039614 # mshr miss rate for overall accesses 958system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average ReadReq mshr miss latency 959system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9652.492962 # average ReadReq mshr miss latency 960system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency 961system.cpu0.icache.demand_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency 962system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency 963system.cpu0.icache.overall_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency 964system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency 965system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency 966system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency 967system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency 968system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 969system.cpu0.l2cache.prefetcher.num_hwpf_issued 7507862 # number of hwpf issued 970system.cpu0.l2cache.prefetcher.pfIdentified 7509065 # number of prefetch candidates identified 971system.cpu0.l2cache.prefetcher.pfBufferHit 1069 # number of redundant prefetches already in prefetch queue 972system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 973system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 974system.cpu0.l2cache.prefetcher.pfSpanPage 942183 # number of prefetches not generated due to page crossing 975system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 976system.cpu0.l2cache.tags.replacements 2584098 # number of replacements 977system.cpu0.l2cache.tags.tagsinuse 15590.889787 # Cycle average of tags in use 978system.cpu0.l2cache.tags.total_refs 13248667 # Total number of references to valid blocks. 979system.cpu0.l2cache.tags.sampled_refs 2600019 # Sample count of references to valid blocks. 980system.cpu0.l2cache.tags.avg_refs 5.095604 # Average number of references to valid blocks. 981system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. 982system.cpu0.l2cache.tags.occ_blocks::writebacks 15296.249521 # Average occupied blocks per requestor 983system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.752726 # Average occupied blocks per requestor 984system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.010194 # Average occupied blocks per requestor 985system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.877346 # Average occupied blocks per requestor 986system.cpu0.l2cache.tags.occ_percent::writebacks 0.933609 # Average percentage of cache occupancy 987system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy 988system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001343 # Average percentage of cache occupancy 989system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014214 # Average percentage of cache occupancy 990system.cpu0.l2cache.tags.occ_percent::total 0.951592 # Average percentage of cache occupancy 991system.cpu0.l2cache.tags.occ_task_id_blocks::1022 376 # Occupied blocks per task id 992system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 993system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15477 # Occupied blocks per task id 994system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id 995system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 996system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 104 # Occupied blocks per task id 997system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 124 # Occupied blocks per task id 998system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 121 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id 1002system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id 1003system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 1004system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1649 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4407 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3577 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022949 # Percentage of cache occupancy per task id 1009system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 1010system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.944641 # Percentage of cache occupancy per task id 1011system.cpu0.l2cache.tags.tag_accesses 507607175 # Number of tag accesses 1012system.cpu0.l2cache.tags.data_accesses 507607175 # Number of data accesses 1013system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1014system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 496900 # number of ReadReq hits 1015system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154788 # number of ReadReq hits 1016system.cpu0.l2cache.ReadReq_hits::total 651688 # number of ReadReq hits 1017system.cpu0.l2cache.WritebackDirty_hits::writebacks 3675506 # number of WritebackDirty hits 1018system.cpu0.l2cache.WritebackDirty_hits::total 3675506 # number of WritebackDirty hits 1019system.cpu0.l2cache.WritebackClean_hits::writebacks 11099665 # number of WritebackClean hits 1020system.cpu0.l2cache.WritebackClean_hits::total 11099665 # number of WritebackClean hits 1021system.cpu0.l2cache.ReadExReq_hits::cpu0.data 891359 # number of ReadExReq hits 1022system.cpu0.l2cache.ReadExReq_hits::total 891359 # number of ReadExReq hits 1023system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8598093 # number of ReadCleanReq hits 1024system.cpu0.l2cache.ReadCleanReq_hits::total 8598093 # number of ReadCleanReq hits 1025system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2690347 # number of ReadSharedReq hits 1026system.cpu0.l2cache.ReadSharedReq_hits::total 2690347 # number of ReadSharedReq hits 1027system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202108 # number of InvalidateReq hits 1028system.cpu0.l2cache.InvalidateReq_hits::total 202108 # number of InvalidateReq hits 1029system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 496900 # number of demand (read+write) hits 1030system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154788 # number of demand (read+write) hits 1031system.cpu0.l2cache.demand_hits::cpu0.inst 8598093 # number of demand (read+write) hits 1032system.cpu0.l2cache.demand_hits::cpu0.data 3581706 # number of demand (read+write) hits 1033system.cpu0.l2cache.demand_hits::total 12831487 # number of demand (read+write) hits 1034system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 496900 # number of overall hits 1035system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154788 # number of overall hits 1036system.cpu0.l2cache.overall_hits::cpu0.inst 8598093 # number of overall hits 1037system.cpu0.l2cache.overall_hits::cpu0.data 3581706 # number of overall hits 1038system.cpu0.l2cache.overall_hits::total 12831487 # number of overall hits 1039system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 19803 # number of ReadReq misses 1040system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9619 # number of ReadReq misses 1041system.cpu0.l2cache.ReadReq_misses::total 29422 # number of ReadReq misses 1042system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 245426 # number of UpgradeReq misses 1043system.cpu0.l2cache.UpgradeReq_misses::total 245426 # number of UpgradeReq misses 1044system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 180938 # number of SCUpgradeReq misses 1045system.cpu0.l2cache.SCUpgradeReq_misses::total 180938 # number of SCUpgradeReq misses 1046system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 1047system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1048system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278613 # number of ReadExReq misses 1049system.cpu0.l2cache.ReadExReq_misses::total 278613 # number of ReadExReq misses 1050system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 683036 # number of ReadCleanReq misses 1051system.cpu0.l2cache.ReadCleanReq_misses::total 683036 # number of ReadCleanReq misses 1052system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953863 # number of ReadSharedReq misses 1053system.cpu0.l2cache.ReadSharedReq_misses::total 953863 # number of ReadSharedReq misses 1054system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 581978 # number of InvalidateReq misses 1055system.cpu0.l2cache.InvalidateReq_misses::total 581978 # number of InvalidateReq misses 1056system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 19803 # number of demand (read+write) misses 1057system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9619 # number of demand (read+write) misses 1058system.cpu0.l2cache.demand_misses::cpu0.inst 683036 # number of demand (read+write) misses 1059system.cpu0.l2cache.demand_misses::cpu0.data 1232476 # number of demand (read+write) misses 1060system.cpu0.l2cache.demand_misses::total 1944934 # number of demand (read+write) misses 1061system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 19803 # number of overall misses 1062system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9619 # number of overall misses 1063system.cpu0.l2cache.overall_misses::cpu0.inst 683036 # number of overall misses 1064system.cpu0.l2cache.overall_misses::cpu0.data 1232476 # number of overall misses 1065system.cpu0.l2cache.overall_misses::total 1944934 # number of overall misses 1066system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 614702000 # number of ReadReq miss cycles 1067system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 331371000 # number of ReadReq miss cycles 1068system.cpu0.l2cache.ReadReq_miss_latency::total 946073000 # number of ReadReq miss cycles 1069system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 874372000 # number of UpgradeReq miss cycles 1070system.cpu0.l2cache.UpgradeReq_miss_latency::total 874372000 # number of UpgradeReq miss cycles 1071system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295339000 # number of SCUpgradeReq miss cycles 1072system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295339000 # number of SCUpgradeReq miss cycles 1073system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2383999 # number of SCUpgradeFailReq miss cycles 1074system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2383999 # number of SCUpgradeFailReq miss cycles 1075system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13650875999 # number of ReadExReq miss cycles 1076system.cpu0.l2cache.ReadExReq_miss_latency::total 13650875999 # number of ReadExReq miss cycles 1077system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23732034500 # number of ReadCleanReq miss cycles 1078system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23732034500 # number of ReadCleanReq miss cycles 1079system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33660637494 # number of ReadSharedReq miss cycles 1080system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33660637494 # number of ReadSharedReq miss cycles 1081system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333947500 # number of InvalidateReq miss cycles 1082system.cpu0.l2cache.InvalidateReq_miss_latency::total 333947500 # number of InvalidateReq miss cycles 1083system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 614702000 # number of demand (read+write) miss cycles 1084system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 331371000 # number of demand (read+write) miss cycles 1085system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23732034500 # number of demand (read+write) miss cycles 1086system.cpu0.l2cache.demand_miss_latency::cpu0.data 47311513493 # number of demand (read+write) miss cycles 1087system.cpu0.l2cache.demand_miss_latency::total 71989620993 # number of demand (read+write) miss cycles 1088system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 614702000 # number of overall miss cycles 1089system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 331371000 # number of overall miss cycles 1090system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23732034500 # number of overall miss cycles 1091system.cpu0.l2cache.overall_miss_latency::cpu0.data 47311513493 # number of overall miss cycles 1092system.cpu0.l2cache.overall_miss_latency::total 71989620993 # number of overall miss cycles 1093system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 516703 # number of ReadReq accesses(hits+misses) 1094system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164407 # number of ReadReq accesses(hits+misses) 1095system.cpu0.l2cache.ReadReq_accesses::total 681110 # number of ReadReq accesses(hits+misses) 1096system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3675506 # number of WritebackDirty accesses(hits+misses) 1097system.cpu0.l2cache.WritebackDirty_accesses::total 3675506 # number of WritebackDirty accesses(hits+misses) 1098system.cpu0.l2cache.WritebackClean_accesses::writebacks 11099665 # number of WritebackClean accesses(hits+misses) 1099system.cpu0.l2cache.WritebackClean_accesses::total 11099665 # number of WritebackClean accesses(hits+misses) 1100system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 245426 # number of UpgradeReq accesses(hits+misses) 1101system.cpu0.l2cache.UpgradeReq_accesses::total 245426 # number of UpgradeReq accesses(hits+misses) 1102system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180938 # number of SCUpgradeReq accesses(hits+misses) 1103system.cpu0.l2cache.SCUpgradeReq_accesses::total 180938 # number of SCUpgradeReq accesses(hits+misses) 1104system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1105system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1106system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1169972 # number of ReadExReq accesses(hits+misses) 1107system.cpu0.l2cache.ReadExReq_accesses::total 1169972 # number of ReadExReq accesses(hits+misses) 1108system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9281129 # number of ReadCleanReq accesses(hits+misses) 1109system.cpu0.l2cache.ReadCleanReq_accesses::total 9281129 # number of ReadCleanReq accesses(hits+misses) 1110system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3644210 # number of ReadSharedReq accesses(hits+misses) 1111system.cpu0.l2cache.ReadSharedReq_accesses::total 3644210 # number of ReadSharedReq accesses(hits+misses) 1112system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 784086 # number of InvalidateReq accesses(hits+misses) 1113system.cpu0.l2cache.InvalidateReq_accesses::total 784086 # number of InvalidateReq accesses(hits+misses) 1114system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 516703 # number of demand (read+write) accesses 1115system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164407 # number of demand (read+write) accesses 1116system.cpu0.l2cache.demand_accesses::cpu0.inst 9281129 # number of demand (read+write) accesses 1117system.cpu0.l2cache.demand_accesses::cpu0.data 4814182 # number of demand (read+write) accesses 1118system.cpu0.l2cache.demand_accesses::total 14776421 # number of demand (read+write) accesses 1119system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 516703 # number of overall (read+write) accesses 1120system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164407 # number of overall (read+write) accesses 1121system.cpu0.l2cache.overall_accesses::cpu0.inst 9281129 # number of overall (read+write) accesses 1122system.cpu0.l2cache.overall_accesses::cpu0.data 4814182 # number of overall (read+write) accesses 1123system.cpu0.l2cache.overall_accesses::total 14776421 # number of overall (read+write) accesses 1124system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for ReadReq accesses 1125system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058507 # miss rate for ReadReq accesses 1126system.cpu0.l2cache.ReadReq_miss_rate::total 0.043197 # miss rate for ReadReq accesses 1127system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1128system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1129system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1130system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1131system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1132system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1133system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.238136 # miss rate for ReadExReq accesses 1134system.cpu0.l2cache.ReadExReq_miss_rate::total 0.238136 # miss rate for ReadExReq accesses 1135system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073594 # miss rate for ReadCleanReq accesses 1136system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073594 # miss rate for ReadCleanReq accesses 1137system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261748 # miss rate for ReadSharedReq accesses 1138system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261748 # miss rate for ReadSharedReq accesses 1139system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.742237 # miss rate for InvalidateReq accesses 1140system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.742237 # miss rate for InvalidateReq accesses 1141system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for demand accesses 1142system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058507 # miss rate for demand accesses 1143system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073594 # miss rate for demand accesses 1144system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.256009 # miss rate for demand accesses 1145system.cpu0.l2cache.demand_miss_rate::total 0.131624 # miss rate for demand accesses 1146system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for overall accesses 1147system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058507 # miss rate for overall accesses 1148system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073594 # miss rate for overall accesses 1149system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.256009 # miss rate for overall accesses 1150system.cpu0.l2cache.overall_miss_rate::total 0.131624 # miss rate for overall accesses 1151system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average ReadReq miss latency 1152system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34449.630939 # average ReadReq miss latency 1153system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32155.291958 # average ReadReq miss latency 1154system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3562.670622 # average UpgradeReq miss latency 1155system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3562.670622 # average UpgradeReq miss latency 1156system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1632.266301 # average SCUpgradeReq miss latency 1157system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1632.266301 # average SCUpgradeReq miss latency 1158system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 794666.333333 # average SCUpgradeFailReq miss latency 1159system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 794666.333333 # average SCUpgradeFailReq miss latency 1160system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48995.832926 # average ReadExReq miss latency 1161system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48995.832926 # average ReadExReq miss latency 1162system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34744.924865 # average ReadCleanReq miss latency 1163system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34744.924865 # average ReadCleanReq miss latency 1164system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35288.754773 # average ReadSharedReq miss latency 1165system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35288.754773 # average ReadSharedReq miss latency 1166system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 573.814646 # average InvalidateReq miss latency 1167system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 573.814646 # average InvalidateReq miss latency 1168system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency 1169system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency 1170system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency 1171system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency 1172system.cpu0.l2cache.demand_avg_miss_latency::total 37013.914607 # average overall miss latency 1173system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency 1174system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency 1175system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency 1176system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency 1177system.cpu0.l2cache.overall_avg_miss_latency::total 37013.914607 # average overall miss latency 1178system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1179system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1180system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1181system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1182system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1183system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1184system.cpu0.l2cache.unused_prefetches 44195 # number of HardPF blocks evicted w/o reference 1185system.cpu0.l2cache.writebacks::writebacks 1595582 # number of writebacks 1186system.cpu0.l2cache.writebacks::total 1595582 # number of writebacks 1187system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 11 # number of ReadReq MSHR hits 1188system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 92 # number of ReadReq MSHR hits 1189system.cpu0.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 1190system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9447 # number of ReadExReq MSHR hits 1191system.cpu0.l2cache.ReadExReq_mshr_hits::total 9447 # number of ReadExReq MSHR hits 1192system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits 1193system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1194system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 778 # number of ReadSharedReq MSHR hits 1195system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 778 # number of ReadSharedReq MSHR hits 1196system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 1197system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 1198system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 11 # number of demand (read+write) MSHR hits 1199system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 92 # number of demand (read+write) MSHR hits 1200system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits 1201system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10225 # number of demand (read+write) MSHR hits 1202system.cpu0.l2cache.demand_mshr_hits::total 10340 # number of demand (read+write) MSHR hits 1203system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 11 # number of overall MSHR hits 1204system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 92 # number of overall MSHR hits 1205system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits 1206system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10225 # number of overall MSHR hits 1207system.cpu0.l2cache.overall_mshr_hits::total 10340 # number of overall MSHR hits 1208system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 19792 # number of ReadReq MSHR misses 1209system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9527 # number of ReadReq MSHR misses 1210system.cpu0.l2cache.ReadReq_mshr_misses::total 29319 # number of ReadReq MSHR misses 1211system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of HardPFReq MSHR misses 1212system.cpu0.l2cache.HardPFReq_mshr_misses::total 781759 # number of HardPFReq MSHR misses 1213system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 245426 # number of UpgradeReq MSHR misses 1214system.cpu0.l2cache.UpgradeReq_mshr_misses::total 245426 # number of UpgradeReq MSHR misses 1215system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 180938 # number of SCUpgradeReq MSHR misses 1216system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 180938 # number of SCUpgradeReq MSHR misses 1217system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1218system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1219system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269166 # number of ReadExReq MSHR misses 1220system.cpu0.l2cache.ReadExReq_mshr_misses::total 269166 # number of ReadExReq MSHR misses 1221system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 683024 # number of ReadCleanReq MSHR misses 1222system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 683024 # number of ReadCleanReq MSHR misses 1223system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 953085 # number of ReadSharedReq MSHR misses 1224system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 953085 # number of ReadSharedReq MSHR misses 1225system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 581976 # number of InvalidateReq MSHR misses 1226system.cpu0.l2cache.InvalidateReq_mshr_misses::total 581976 # number of InvalidateReq MSHR misses 1227system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 19792 # number of demand (read+write) MSHR misses 1228system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9527 # number of demand (read+write) MSHR misses 1229system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 683024 # number of demand (read+write) MSHR misses 1230system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1222251 # number of demand (read+write) MSHR misses 1231system.cpu0.l2cache.demand_mshr_misses::total 1934594 # number of demand (read+write) MSHR misses 1232system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 19792 # number of overall MSHR misses 1233system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9527 # number of overall MSHR misses 1234system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 683024 # number of overall MSHR misses 1235system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1222251 # number of overall MSHR misses 1236system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of overall MSHR misses 1237system.cpu0.l2cache.overall_mshr_misses::total 2716353 # number of overall MSHR misses 1238system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 1239system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 1240system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72934 # number of ReadReq MSHR uncacheable 1241system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 1242system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable 1243system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 1244system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 1245system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 95209 # number of overall MSHR uncacheable misses 1246system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of ReadReq MSHR miss cycles 1247system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 272683000 # number of ReadReq MSHR miss cycles 1248system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 768369000 # number of ReadReq MSHR miss cycles 1249system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of HardPFReq MSHR miss cycles 1250system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38385674547 # number of HardPFReq MSHR miss cycles 1251system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4516919997 # number of UpgradeReq MSHR miss cycles 1252system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4516919997 # number of UpgradeReq MSHR miss cycles 1253system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2779143996 # number of SCUpgradeReq MSHR miss cycles 1254system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2779143996 # number of SCUpgradeReq MSHR miss cycles 1255system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2017999 # number of SCUpgradeFailReq MSHR miss cycles 1256system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2017999 # number of SCUpgradeFailReq MSHR miss cycles 1257system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10852711499 # number of ReadExReq MSHR miss cycles 1258system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10852711499 # number of ReadExReq MSHR miss cycles 1259system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19633488000 # number of ReadCleanReq MSHR miss cycles 1260system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19633488000 # number of ReadCleanReq MSHR miss cycles 1261system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27859151994 # number of ReadSharedReq MSHR miss cycles 1262system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27859151994 # number of ReadSharedReq MSHR miss cycles 1263system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19308557500 # number of InvalidateReq MSHR miss cycles 1264system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19308557500 # number of InvalidateReq MSHR miss cycles 1265system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of demand (read+write) MSHR miss cycles 1266system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 272683000 # number of demand (read+write) MSHR miss cycles 1267system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19633488000 # number of demand (read+write) MSHR miss cycles 1268system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38711863493 # number of demand (read+write) MSHR miss cycles 1269system.cpu0.l2cache.demand_mshr_miss_latency::total 59113720493 # number of demand (read+write) MSHR miss cycles 1270system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of overall MSHR miss cycles 1271system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 272683000 # number of overall MSHR miss cycles 1272system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19633488000 # number of overall MSHR miss cycles 1273system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38711863493 # number of overall MSHR miss cycles 1274system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of overall MSHR miss cycles 1275system.cpu0.l2cache.overall_mshr_miss_latency::total 97499395040 # number of overall MSHR miss cycles 1276system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles 1277system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3849707000 # number of ReadReq MSHR uncacheable cycles 1278system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8268091500 # number of ReadReq MSHR uncacheable cycles 1279system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles 1280system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3849707000 # number of overall MSHR uncacheable cycles 1281system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8268091500 # number of overall MSHR uncacheable cycles 1282system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for ReadReq accesses 1283system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for ReadReq accesses 1284system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 1285system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1286system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1287system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1288system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1289system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1290system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1291system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1292system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1293system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.230062 # mshr miss rate for ReadExReq accesses 1294system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.230062 # mshr miss rate for ReadExReq accesses 1295system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for ReadCleanReq accesses 1296system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073593 # mshr miss rate for ReadCleanReq accesses 1297system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261534 # mshr miss rate for ReadSharedReq accesses 1298system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261534 # mshr miss rate for ReadSharedReq accesses 1299system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.742235 # mshr miss rate for InvalidateReq accesses 1300system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.742235 # mshr miss rate for InvalidateReq accesses 1301system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for demand accesses 1302system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for demand accesses 1303system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for demand accesses 1304system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for demand accesses 1305system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130924 # mshr miss rate for demand accesses 1306system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for overall accesses 1307system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for overall accesses 1308system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for overall accesses 1309system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for overall accesses 1310system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1311system.cpu0.l2cache.overall_mshr_miss_rate::total 0.183830 # mshr miss rate for overall accesses 1312system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average ReadReq mshr miss latency 1313system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average ReadReq mshr miss latency 1314system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520 # average ReadReq mshr miss latency 1315system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average HardPFReq mshr miss latency 1316system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698 # average HardPFReq mshr miss latency 1317system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019 # average UpgradeReq mshr miss latency 1318system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019 # average UpgradeReq mshr miss latency 1319system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034 # average SCUpgradeReq mshr miss latency 1320system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034 # average SCUpgradeReq mshr miss latency 1321system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333 # average SCUpgradeFailReq mshr miss latency 1322system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333 # average SCUpgradeFailReq mshr miss latency 1323system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067 # average ReadExReq mshr miss latency 1324system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067 # average ReadExReq mshr miss latency 1325system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average ReadCleanReq mshr miss latency 1326system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005 # average ReadCleanReq mshr miss latency 1327system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946 # average ReadSharedReq mshr miss latency 1328system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946 # average ReadSharedReq mshr miss latency 1329system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784 # average InvalidateReq mshr miss latency 1330system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784 # average InvalidateReq mshr miss latency 1331system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency 1332system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency 1333system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency 1334system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency 1335system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615 # average overall mshr miss latency 1336system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency 1337system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency 1338system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency 1339system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency 1340system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average overall mshr miss latency 1341system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134 # average overall mshr miss latency 1342system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency 1343system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785 # average ReadReq mshr uncacheable latency 1344system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896 # average ReadReq mshr uncacheable latency 1345system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency 1346system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962 # average overall mshr uncacheable latency 1347system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825 # average overall mshr uncacheable latency 1348system.cpu0.toL2Bus.snoop_filter.tot_requests 30377137 # Total number of requests made to the snoop filter. 1349system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15497883 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1350system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2826 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1351system.cpu0.toL2Bus.snoop_filter.tot_snoops 666100 # Total number of snoops made to the snoop filter. 1352system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 666086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1353system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1354system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1355system.cpu0.toL2Bus.trans_dist::ReadReq 826394 # Transaction distribution 1356system.cpu0.toL2Bus.trans_dist::ReadResp 13852976 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::WriteReq 22275 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::WriteResp 22275 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::WritebackDirty 5277668 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::WritebackClean 11102490 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::CleanEvict 1369040 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::HardPFReq 998456 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::UpgradeReq 452524 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330100 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::UpgradeResp 496609 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::ReadExReq 1203701 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::ReadExResp 1179860 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9281130 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4723846 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::InvalidateReq 838465 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::InvalidateResp 784086 # Transaction distribution 1375system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 27947466 # Packet count per connected master and slave (bytes) 1376system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17813968 # Packet count per connected master and slave (bytes) 1377system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 344869 # Packet count per connected master and slave (bytes) 1378system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1089699 # Packet count per connected master and slave (bytes) 1379system.cpu0.toL2Bus.pkt_count::total 47196002 # Packet count per connected master and slave (bytes) 1380system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1191298304 # Cumulative packet size per connected master and slave (bytes) 1381system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 667170422 # Cumulative packet size per connected master and slave (bytes) 1382system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1315256 # Cumulative packet size per connected master and slave (bytes) 1383system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4133624 # Cumulative packet size per connected master and slave (bytes) 1384system.cpu0.toL2Bus.pkt_size::total 1863917606 # Cumulative packet size per connected master and slave (bytes) 1385system.cpu0.toL2Bus.snoops 5747559 # Total snoops (count) 1386system.cpu0.toL2Bus.snoopTraffic 110232304 # Total snoop traffic (bytes) 1387system.cpu0.toL2Bus.snoop_fanout::samples 21648150 # Request fanout histogram 1388system.cpu0.toL2Bus.snoop_fanout::mean 0.044453 # Request fanout histogram 1389system.cpu0.toL2Bus.snoop_fanout::stdev 0.206103 # Request fanout histogram 1390system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1391system.cpu0.toL2Bus.snoop_fanout::0 20685836 95.55% 95.55% # Request fanout histogram 1392system.cpu0.toL2Bus.snoop_fanout::1 962300 4.45% 100.00% # Request fanout histogram 1393system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram 1394system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1396system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1397system.cpu0.toL2Bus.snoop_fanout::total 21648150 # Request fanout histogram 1398system.cpu0.toL2Bus.reqLayer0.occupancy 30255355989 # Layer occupancy (ticks) 1399system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1400system.cpu0.toL2Bus.snoopLayer0.occupancy 202143120 # Layer occupancy (ticks) 1401system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1402system.cpu0.toL2Bus.respLayer0.occupancy 14002739292 # Layer occupancy (ticks) 1403system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1404system.cpu0.toL2Bus.respLayer1.occupancy 7861824025 # Layer occupancy (ticks) 1405system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1406system.cpu0.toL2Bus.respLayer2.occupancy 180564794 # Layer occupancy (ticks) 1407system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1408system.cpu0.toL2Bus.respLayer3.occupancy 573087816 # Layer occupancy (ticks) 1409system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1410system.cpu1.branchPred.lookups 142890193 # Number of BP lookups 1411system.cpu1.branchPred.condPredicted 101173603 # Number of conditional branches predicted 1412system.cpu1.branchPred.condIncorrect 6378415 # Number of conditional branches incorrect 1413system.cpu1.branchPred.BTBLookups 107083119 # Number of BTB lookups 1414system.cpu1.branchPred.BTBHits 74895456 # Number of BTB hits 1415system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1416system.cpu1.branchPred.BTBHitPct 69.941422 # BTB Hit Percentage 1417system.cpu1.branchPred.usedRAS 16732142 # Number of times the RAS was used to get a target. 1418system.cpu1.branchPred.RASInCorrect 1061167 # Number of incorrect RAS predictions. 1419system.cpu1.branchPred.indirectLookups 3812146 # Number of indirect predictor lookups. 1420system.cpu1.branchPred.indirectHits 2601182 # Number of indirect target hits. 1421system.cpu1.branchPred.indirectMisses 1210964 # Number of indirect misses. 1422system.cpu1.branchPredindirectMispredicted 435637 # Number of mispredicted indirect branches. 1423system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1424system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1425system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1429system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1430system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1431system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1432system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1433system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1434system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1435system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1436system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1437system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1438system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1439system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1440system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1441system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1442system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1443system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1444system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1445system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1446system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1447system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1448system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1449system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1450system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1451system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1452system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1453system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1454system.cpu1.dtb.walker.walks 301450 # Table walker walks requested 1455system.cpu1.dtb.walker.walksLong 301450 # Table walker walks initiated with long descriptors 1456system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14052 # Level at which table walker walks with long descriptors terminate 1457system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94528 # Level at which table walker walks with long descriptors terminate 1458system.cpu1.dtb.walker.walkWaitTime::samples 301450 # Table walker wait (enqueue to first request) latency 1459system.cpu1.dtb.walker.walkWaitTime::0 301450 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1460system.cpu1.dtb.walker.walkWaitTime::total 301450 # Table walker wait (enqueue to first request) latency 1461system.cpu1.dtb.walker.walkCompletionTime::samples 108580 # Table walker service (enqueue to completion) latency 1462system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294 # Table walker service (enqueue to completion) latency 1463system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975 # Table walker service (enqueue to completion) latency 1464system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293 # Table walker service (enqueue to completion) latency 1465system.cpu1.dtb.walker.walkCompletionTime::0-65535 107036 98.58% 98.58% # Table walker service (enqueue to completion) latency 1466system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1312 1.21% 99.79% # Table walker service (enqueue to completion) latency 1467system.cpu1.dtb.walker.walkCompletionTime::131072-196607 57 0.05% 99.84% # Table walker service (enqueue to completion) latency 1468system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.06% 99.90% # Table walker service (enqueue to completion) latency 1469system.cpu1.dtb.walker.walkCompletionTime::262144-327679 74 0.07% 99.97% # Table walker service (enqueue to completion) latency 1470system.cpu1.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency 1471system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 1472system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1473system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.dtb.walker.walkCompletionTime::total 108580 # Table walker service (enqueue to completion) latency 1475system.cpu1.dtb.walker.walksPending::samples -588118056 # Table walker pending requests distribution 1476system.cpu1.dtb.walker.walksPending::0 -588118056 100.00% 100.00% # Table walker pending requests distribution 1477system.cpu1.dtb.walker.walksPending::total -588118056 # Table walker pending requests distribution 1478system.cpu1.dtb.walker.walkPageSizes::4K 94528 87.06% 87.06% # Table walker page sizes translated 1479system.cpu1.dtb.walker.walkPageSizes::2M 14052 12.94% 100.00% # Table walker page sizes translated 1480system.cpu1.dtb.walker.walkPageSizes::total 108580 # Table walker page sizes translated 1481system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 301450 # Table walker requests started/completed, data/inst 1482system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1483system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 301450 # Table walker requests started/completed, data/inst 1484system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108580 # Table walker requests started/completed, data/inst 1485system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1486system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108580 # Table walker requests started/completed, data/inst 1487system.cpu1.dtb.walker.walkRequestOrigin::total 410030 # Table walker requests started/completed, data/inst 1488system.cpu1.dtb.inst_hits 0 # ITB inst hits 1489system.cpu1.dtb.inst_misses 0 # ITB inst misses 1490system.cpu1.dtb.read_hits 92214946 # DTB read hits 1491system.cpu1.dtb.read_misses 251350 # DTB read misses 1492system.cpu1.dtb.write_hits 79863458 # DTB write hits 1493system.cpu1.dtb.write_misses 50100 # DTB write misses 1494system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1495system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1496system.cpu1.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 1498system.cpu1.dtb.flush_entries 41485 # Number of entries that have been flushed from TLB 1499system.cpu1.dtb.align_faults 1017 # Number of TLB faults due to alignment restrictions 1500system.cpu1.dtb.prefetch_faults 8355 # Number of TLB faults due to prefetch 1501system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.dtb.perms_faults 11459 # Number of TLB faults due to permissions restrictions 1503system.cpu1.dtb.read_accesses 92466296 # DTB read accesses 1504system.cpu1.dtb.write_accesses 79913558 # DTB write accesses 1505system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1506system.cpu1.dtb.hits 172078404 # DTB hits 1507system.cpu1.dtb.misses 301450 # DTB misses 1508system.cpu1.dtb.accesses 172379854 # DTB accesses 1509system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1510system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1511system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1512system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1513system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1514system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1515system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1516system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1517system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1518system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1519system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1520system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1521system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1522system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1523system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1524system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1525system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1526system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1527system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1528system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1529system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1530system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1531system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1532system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1533system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1534system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1535system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1536system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1537system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1538system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1539system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1540system.cpu1.itb.walker.walks 68405 # Table walker walks requested 1541system.cpu1.itb.walker.walksLong 68405 # Table walker walks initiated with long descriptors 1542system.cpu1.itb.walker.walksLongTerminationLevel::Level2 536 # Level at which table walker walks with long descriptors terminate 1543system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57692 # Level at which table walker walks with long descriptors terminate 1544system.cpu1.itb.walker.walkWaitTime::samples 68405 # Table walker wait (enqueue to first request) latency 1545system.cpu1.itb.walker.walkWaitTime::0 68405 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1546system.cpu1.itb.walker.walkWaitTime::total 68405 # Table walker wait (enqueue to first request) latency 1547system.cpu1.itb.walker.walkCompletionTime::samples 58228 # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106 # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832 # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639 # Table walker service (enqueue to completion) latency 1551system.cpu1.itb.walker.walkCompletionTime::0-32767 52664 90.44% 90.44% # Table walker service (enqueue to completion) latency 1552system.cpu1.itb.walker.walkCompletionTime::32768-65535 3935 6.76% 97.20% # Table walker service (enqueue to completion) latency 1553system.cpu1.itb.walker.walkCompletionTime::65536-98303 14 0.02% 97.23% # Table walker service (enqueue to completion) latency 1554system.cpu1.itb.walker.walkCompletionTime::98304-131071 1454 2.50% 99.72% # Table walker service (enqueue to completion) latency 1555system.cpu1.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency 1556system.cpu1.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.82% # Table walker service (enqueue to completion) latency 1557system.cpu1.itb.walker.walkCompletionTime::196608-229375 63 0.11% 99.93% # Table walker service (enqueue to completion) latency 1558system.cpu1.itb.walker.walkCompletionTime::229376-262143 12 0.02% 99.95% # Table walker service (enqueue to completion) latency 1559system.cpu1.itb.walker.walkCompletionTime::262144-294911 10 0.02% 99.96% # Table walker service (enqueue to completion) latency 1560system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 1561system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 1562system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1563system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1564system.cpu1.itb.walker.walkCompletionTime::total 58228 # Table walker service (enqueue to completion) latency 1565system.cpu1.itb.walker.walksPending::samples -588816556 # Table walker pending requests distribution 1566system.cpu1.itb.walker.walksPending::0 -588816556 100.00% 100.00% # Table walker pending requests distribution 1567system.cpu1.itb.walker.walksPending::total -588816556 # Table walker pending requests distribution 1568system.cpu1.itb.walker.walkPageSizes::4K 57692 99.08% 99.08% # Table walker page sizes translated 1569system.cpu1.itb.walker.walkPageSizes::2M 536 0.92% 100.00% # Table walker page sizes translated 1570system.cpu1.itb.walker.walkPageSizes::total 58228 # Table walker page sizes translated 1571system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1572system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68405 # Table walker requests started/completed, data/inst 1573system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68405 # Table walker requests started/completed, data/inst 1574system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1575system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58228 # Table walker requests started/completed, data/inst 1576system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58228 # Table walker requests started/completed, data/inst 1577system.cpu1.itb.walker.walkRequestOrigin::total 126633 # Table walker requests started/completed, data/inst 1578system.cpu1.itb.inst_hits 253981708 # ITB inst hits 1579system.cpu1.itb.inst_misses 68405 # ITB inst misses 1580system.cpu1.itb.read_hits 0 # DTB read hits 1581system.cpu1.itb.read_misses 0 # DTB read misses 1582system.cpu1.itb.write_hits 0 # DTB write hits 1583system.cpu1.itb.write_misses 0 # DTB write misses 1584system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1585system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1586system.cpu1.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID 1587system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID 1588system.cpu1.itb.flush_entries 29878 # Number of entries that have been flushed from TLB 1589system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1590system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1591system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1592system.cpu1.itb.perms_faults 186858 # Number of TLB faults due to permissions restrictions 1593system.cpu1.itb.read_accesses 0 # DTB read accesses 1594system.cpu1.itb.write_accesses 0 # DTB write accesses 1595system.cpu1.itb.inst_accesses 254050113 # ITB inst accesses 1596system.cpu1.itb.hits 253981708 # DTB hits 1597system.cpu1.itb.misses 68405 # DTB misses 1598system.cpu1.itb.accesses 254050113 # DTB accesses 1599system.cpu1.numPwrStateTransitions 29008 # Number of power state transitions 1600system.cpu1.pwrStateClkGateDist::samples 14504 # Distribution of time spent in the clock gated state 1601system.cpu1.pwrStateClkGateDist::mean 3226000342.121070 # Distribution of time spent in the clock gated state 1602system.cpu1.pwrStateClkGateDist::stdev 122202778079.734619 # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::underflows 4515 31.13% 31.13% # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::1000-5e+10 9966 68.71% 99.84% # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.89% # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.91% # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 1608system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state 1609system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state 1610system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state 1611system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1612system.cpu1.pwrStateClkGateDist::max_value 11813587669000 # Distribution of time spent in the clock gated state 1613system.cpu1.pwrStateClkGateDist::total 14504 # Distribution of time spent in the clock gated state 1614system.cpu1.pwrStateResidencyTicks::ON 486863864876 # Cumulative time (in ticks) in various power states 1615system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124 # Cumulative time (in ticks) in various power states 1616system.cpu1.numCycles 973770006 # number of cpu cycles simulated 1617system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1618system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1619system.cpu1.committedInsts 467062034 # Number of instructions committed 1620system.cpu1.committedOps 549524480 # Number of ops (including micro ops) committed 1621system.cpu1.discardedOps 49354477 # Number of ops (including micro ops) which were discarded before commit 1622system.cpu1.numFetchSuspends 5829 # Number of times Execute suspended instruction fetching 1623system.cpu1.quiesceCycles 93580668477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1624system.cpu1.cpi 2.084884 # CPI: cycles per instruction 1625system.cpu1.ipc 0.479643 # IPC: instructions per cycle 1626system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1627system.cpu1.op_class_0::IntAlu 379758717 69.11% 69.11% # Class of committed instruction 1628system.cpu1.op_class_0::IntMult 1174710 0.21% 69.32% # Class of committed instruction 1629system.cpu1.op_class_0::IntDiv 62873 0.01% 69.33% # Class of committed instruction 1630system.cpu1.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction 1631system.cpu1.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction 1632system.cpu1.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction 1633system.cpu1.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction 1634system.cpu1.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction 1635system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction 1636system.cpu1.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction 1637system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction 1638system.cpu1.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction 1639system.cpu1.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction 1640system.cpu1.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction 1641system.cpu1.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction 1642system.cpu1.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction 1643system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction 1644system.cpu1.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction 1645system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction 1646system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction 1647system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction 1648system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction 1649system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction 1650system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction 1651system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction 1652system.cpu1.op_class_0::SimdFloatMisc 42788 0.01% 69.34% # Class of committed instruction 1653system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction 1654system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction 1655system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction 1656system.cpu1.op_class_0::MemRead 88942339 16.19% 85.53% # Class of committed instruction 1657system.cpu1.op_class_0::MemWrite 79543053 14.47% 100.00% # Class of committed instruction 1658system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1659system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1660system.cpu1.op_class_0::total 549524480 # Class of committed instruction 1661system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1662system.cpu1.kern.inst.quiesce 14504 # number of quiesce instructions executed 1663system.cpu1.tickCycles 754340504 # Number of cycles that the object actually ticked 1664system.cpu1.idleCycles 219429502 # Total number of cycles that the object has spent stopped 1665system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1666system.cpu1.dcache.tags.replacements 5584308 # number of replacements 1667system.cpu1.dcache.tags.tagsinuse 440.375822 # Cycle average of tags in use 1668system.cpu1.dcache.tags.total_refs 163963779 # Total number of references to valid blocks. 1669system.cpu1.dcache.tags.sampled_refs 5584818 # Sample count of references to valid blocks. 1670system.cpu1.dcache.tags.avg_refs 29.358840 # Average number of references to valid blocks. 1671system.cpu1.dcache.tags.warmup_cycle 8377741807000 # Cycle when the warmup percentage was hit. 1672system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.375822 # Average occupied blocks per requestor 1673system.cpu1.dcache.tags.occ_percent::cpu1.data 0.860109 # Average percentage of cache occupancy 1674system.cpu1.dcache.tags.occ_percent::total 0.860109 # Average percentage of cache occupancy 1675system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 1676system.cpu1.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 1677system.cpu1.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1678system.cpu1.dcache.tags.age_task_id_blocks_1024::2 234 # Occupied blocks per task id 1679system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 1680system.cpu1.dcache.tags.tag_accesses 347150058 # Number of tag accesses 1681system.cpu1.dcache.tags.data_accesses 347150058 # Number of data accesses 1682system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1683system.cpu1.dcache.ReadReq_hits::cpu1.data 84821089 # number of ReadReq hits 1684system.cpu1.dcache.ReadReq_hits::total 84821089 # number of ReadReq hits 1685system.cpu1.dcache.WriteReq_hits::cpu1.data 74565342 # number of WriteReq hits 1686system.cpu1.dcache.WriteReq_hits::total 74565342 # number of WriteReq hits 1687system.cpu1.dcache.SoftPFReq_hits::cpu1.data 240493 # number of SoftPFReq hits 1688system.cpu1.dcache.SoftPFReq_hits::total 240493 # number of SoftPFReq hits 1689system.cpu1.dcache.WriteLineReq_hits::cpu1.data 73857 # number of WriteLineReq hits 1690system.cpu1.dcache.WriteLineReq_hits::total 73857 # number of WriteLineReq hits 1691system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1888770 # number of LoadLockedReq hits 1692system.cpu1.dcache.LoadLockedReq_hits::total 1888770 # number of LoadLockedReq hits 1693system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1879546 # number of StoreCondReq hits 1694system.cpu1.dcache.StoreCondReq_hits::total 1879546 # number of StoreCondReq hits 1695system.cpu1.dcache.demand_hits::cpu1.data 159460288 # number of demand (read+write) hits 1696system.cpu1.dcache.demand_hits::total 159460288 # number of demand (read+write) hits 1697system.cpu1.dcache.overall_hits::cpu1.data 159700781 # number of overall hits 1698system.cpu1.dcache.overall_hits::total 159700781 # number of overall hits 1699system.cpu1.dcache.ReadReq_misses::cpu1.data 3413550 # number of ReadReq misses 1700system.cpu1.dcache.ReadReq_misses::total 3413550 # number of ReadReq misses 1701system.cpu1.dcache.WriteReq_misses::cpu1.data 2348662 # number of WriteReq misses 1702system.cpu1.dcache.WriteReq_misses::total 2348662 # number of WriteReq misses 1703system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664960 # number of SoftPFReq misses 1704system.cpu1.dcache.SoftPFReq_misses::total 664960 # number of SoftPFReq misses 1705system.cpu1.dcache.WriteLineReq_misses::cpu1.data 462804 # number of WriteLineReq misses 1706system.cpu1.dcache.WriteLineReq_misses::total 462804 # number of WriteLineReq misses 1707system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186013 # number of LoadLockedReq misses 1708system.cpu1.dcache.LoadLockedReq_misses::total 186013 # number of LoadLockedReq misses 1709system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193851 # number of StoreCondReq misses 1710system.cpu1.dcache.StoreCondReq_misses::total 193851 # number of StoreCondReq misses 1711system.cpu1.dcache.demand_misses::cpu1.data 6225016 # number of demand (read+write) misses 1712system.cpu1.dcache.demand_misses::total 6225016 # number of demand (read+write) misses 1713system.cpu1.dcache.overall_misses::cpu1.data 6889976 # number of overall misses 1714system.cpu1.dcache.overall_misses::total 6889976 # number of overall misses 1715system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52244752500 # number of ReadReq miss cycles 1716system.cpu1.dcache.ReadReq_miss_latency::total 52244752500 # number of ReadReq miss cycles 1717system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 43500498500 # number of WriteReq miss cycles 1718system.cpu1.dcache.WriteReq_miss_latency::total 43500498500 # number of WriteReq miss cycles 1719system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11517052000 # number of WriteLineReq miss cycles 1720system.cpu1.dcache.WriteLineReq_miss_latency::total 11517052000 # number of WriteLineReq miss cycles 1721system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2853085500 # number of LoadLockedReq miss cycles 1722system.cpu1.dcache.LoadLockedReq_miss_latency::total 2853085500 # number of LoadLockedReq miss cycles 1723system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4630433000 # number of StoreCondReq miss cycles 1724system.cpu1.dcache.StoreCondReq_miss_latency::total 4630433000 # number of StoreCondReq miss cycles 1725system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2585500 # number of StoreCondFailReq miss cycles 1726system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2585500 # number of StoreCondFailReq miss cycles 1727system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000 # number of demand (read+write) miss cycles 1728system.cpu1.dcache.demand_miss_latency::total 107262303000 # number of demand (read+write) miss cycles 1729system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000 # number of overall miss cycles 1730system.cpu1.dcache.overall_miss_latency::total 107262303000 # number of overall miss cycles 1731system.cpu1.dcache.ReadReq_accesses::cpu1.data 88234639 # number of ReadReq accesses(hits+misses) 1732system.cpu1.dcache.ReadReq_accesses::total 88234639 # number of ReadReq accesses(hits+misses) 1733system.cpu1.dcache.WriteReq_accesses::cpu1.data 76914004 # number of WriteReq accesses(hits+misses) 1734system.cpu1.dcache.WriteReq_accesses::total 76914004 # number of WriteReq accesses(hits+misses) 1735system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 905453 # number of SoftPFReq accesses(hits+misses) 1736system.cpu1.dcache.SoftPFReq_accesses::total 905453 # number of SoftPFReq accesses(hits+misses) 1737system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 536661 # number of WriteLineReq accesses(hits+misses) 1738system.cpu1.dcache.WriteLineReq_accesses::total 536661 # number of WriteLineReq accesses(hits+misses) 1739system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074783 # number of LoadLockedReq accesses(hits+misses) 1740system.cpu1.dcache.LoadLockedReq_accesses::total 2074783 # number of LoadLockedReq accesses(hits+misses) 1741system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2073397 # number of StoreCondReq accesses(hits+misses) 1742system.cpu1.dcache.StoreCondReq_accesses::total 2073397 # number of StoreCondReq accesses(hits+misses) 1743system.cpu1.dcache.demand_accesses::cpu1.data 165685304 # number of demand (read+write) accesses 1744system.cpu1.dcache.demand_accesses::total 165685304 # number of demand (read+write) accesses 1745system.cpu1.dcache.overall_accesses::cpu1.data 166590757 # number of overall (read+write) accesses 1746system.cpu1.dcache.overall_accesses::total 166590757 # number of overall (read+write) accesses 1747system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038687 # miss rate for ReadReq accesses 1748system.cpu1.dcache.ReadReq_miss_rate::total 0.038687 # miss rate for ReadReq accesses 1749system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030536 # miss rate for WriteReq accesses 1750system.cpu1.dcache.WriteReq_miss_rate::total 0.030536 # miss rate for WriteReq accesses 1751system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.734395 # miss rate for SoftPFReq accesses 1752system.cpu1.dcache.SoftPFReq_miss_rate::total 0.734395 # miss rate for SoftPFReq accesses 1753system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.862377 # miss rate for WriteLineReq accesses 1754system.cpu1.dcache.WriteLineReq_miss_rate::total 0.862377 # miss rate for WriteLineReq accesses 1755system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089654 # miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089654 # miss rate for LoadLockedReq accesses 1757system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.093494 # miss rate for StoreCondReq accesses 1758system.cpu1.dcache.StoreCondReq_miss_rate::total 0.093494 # miss rate for StoreCondReq accesses 1759system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037571 # miss rate for demand accesses 1760system.cpu1.dcache.demand_miss_rate::total 0.037571 # miss rate for demand accesses 1761system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041359 # miss rate for overall accesses 1762system.cpu1.dcache.overall_miss_rate::total 0.041359 # miss rate for overall accesses 1763system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318 # average ReadReq miss latency 1764system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318 # average ReadReq miss latency 1765system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799 # average WriteReq miss latency 1766system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799 # average WriteReq miss latency 1767system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963 # average WriteLineReq miss latency 1768system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963 # average WriteLineReq miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337 # average LoadLockedReq miss latency 1770system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337 # average LoadLockedReq miss latency 1771system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201 # average StoreCondReq miss latency 1772system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201 # average StoreCondReq miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1774system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1775system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760 # average overall miss latency 1776system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760 # average overall miss latency 1777system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595 # average overall miss latency 1778system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595 # average overall miss latency 1779system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1780system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1781system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1782system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1783system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1784system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1785system.cpu1.dcache.writebacks::writebacks 5584335 # number of writebacks 1786system.cpu1.dcache.writebacks::total 5584335 # number of writebacks 1787system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169267 # number of ReadReq MSHR hits 1788system.cpu1.dcache.ReadReq_mshr_hits::total 169267 # number of ReadReq MSHR hits 1789system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 957224 # number of WriteReq MSHR hits 1790system.cpu1.dcache.WriteReq_mshr_hits::total 957224 # number of WriteReq MSHR hits 1791system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1792system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1793system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44866 # number of LoadLockedReq MSHR hits 1794system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44866 # number of LoadLockedReq MSHR hits 1795system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 87 # number of StoreCondReq MSHR hits 1796system.cpu1.dcache.StoreCondReq_mshr_hits::total 87 # number of StoreCondReq MSHR hits 1797system.cpu1.dcache.demand_mshr_hits::cpu1.data 1126549 # number of demand (read+write) MSHR hits 1798system.cpu1.dcache.demand_mshr_hits::total 1126549 # number of demand (read+write) MSHR hits 1799system.cpu1.dcache.overall_mshr_hits::cpu1.data 1126549 # number of overall MSHR hits 1800system.cpu1.dcache.overall_mshr_hits::total 1126549 # number of overall MSHR hits 1801system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3244283 # number of ReadReq MSHR misses 1802system.cpu1.dcache.ReadReq_mshr_misses::total 3244283 # number of ReadReq MSHR misses 1803system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1391438 # number of WriteReq MSHR misses 1804system.cpu1.dcache.WriteReq_mshr_misses::total 1391438 # number of WriteReq MSHR misses 1805system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664681 # number of SoftPFReq MSHR misses 1806system.cpu1.dcache.SoftPFReq_mshr_misses::total 664681 # number of SoftPFReq MSHR misses 1807system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462746 # number of WriteLineReq MSHR misses 1808system.cpu1.dcache.WriteLineReq_mshr_misses::total 462746 # number of WriteLineReq MSHR misses 1809system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141147 # number of LoadLockedReq MSHR misses 1810system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141147 # number of LoadLockedReq MSHR misses 1811system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193764 # number of StoreCondReq MSHR misses 1812system.cpu1.dcache.StoreCondReq_mshr_misses::total 193764 # number of StoreCondReq MSHR misses 1813system.cpu1.dcache.demand_mshr_misses::cpu1.data 5098467 # number of demand (read+write) MSHR misses 1814system.cpu1.dcache.demand_mshr_misses::total 5098467 # number of demand (read+write) MSHR misses 1815system.cpu1.dcache.overall_mshr_misses::cpu1.data 5763148 # number of overall MSHR misses 1816system.cpu1.dcache.overall_mshr_misses::total 5763148 # number of overall MSHR misses 1817system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable 1818system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17608 # number of ReadReq MSHR uncacheable 1819system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 1820system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable 1821system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses 1822system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33461 # number of overall MSHR uncacheable misses 1823system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45298654500 # number of ReadReq MSHR miss cycles 1824system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45298654500 # number of ReadReq MSHR miss cycles 1825system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 25106196000 # number of WriteReq MSHR miss cycles 1826system.cpu1.dcache.WriteReq_mshr_miss_latency::total 25106196000 # number of WriteReq MSHR miss cycles 1827system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14639124500 # number of SoftPFReq MSHR miss cycles 1828system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14639124500 # number of SoftPFReq MSHR miss cycles 1829system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11050641000 # number of WriteLineReq MSHR miss cycles 1830system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11050641000 # number of WriteLineReq MSHR miss cycles 1831system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1898988000 # number of LoadLockedReq MSHR miss cycles 1832system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1898988000 # number of LoadLockedReq MSHR miss cycles 1833system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4434665000 # number of StoreCondReq MSHR miss cycles 1834system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4434665000 # number of StoreCondReq MSHR miss cycles 1835system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2119500 # number of StoreCondFailReq MSHR miss cycles 1836system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2119500 # number of StoreCondFailReq MSHR miss cycles 1837system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81455491500 # number of demand (read+write) MSHR miss cycles 1838system.cpu1.dcache.demand_mshr_miss_latency::total 81455491500 # number of demand (read+write) MSHR miss cycles 1839system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 96094616000 # number of overall MSHR miss cycles 1840system.cpu1.dcache.overall_mshr_miss_latency::total 96094616000 # number of overall MSHR miss cycles 1841system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2936127500 # number of ReadReq MSHR uncacheable cycles 1842system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2936127500 # number of ReadReq MSHR uncacheable cycles 1843system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2936127500 # number of overall MSHR uncacheable cycles 1844system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2936127500 # number of overall MSHR uncacheable cycles 1845system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036769 # mshr miss rate for ReadReq accesses 1846system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036769 # mshr miss rate for ReadReq accesses 1847system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses 1848system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses 1849system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.734087 # mshr miss rate for SoftPFReq accesses 1850system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.734087 # mshr miss rate for SoftPFReq accesses 1851system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.862269 # mshr miss rate for WriteLineReq accesses 1852system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.862269 # mshr miss rate for WriteLineReq accesses 1853system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068030 # mshr miss rate for LoadLockedReq accesses 1854system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068030 # mshr miss rate for LoadLockedReq accesses 1855system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.093452 # mshr miss rate for StoreCondReq accesses 1856system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.093452 # mshr miss rate for StoreCondReq accesses 1857system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for demand accesses 1858system.cpu1.dcache.demand_mshr_miss_rate::total 0.030772 # mshr miss rate for demand accesses 1859system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034595 # mshr miss rate for overall accesses 1860system.cpu1.dcache.overall_mshr_miss_rate::total 0.034595 # mshr miss rate for overall accesses 1861system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841 # average ReadReq mshr miss latency 1862system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841 # average ReadReq mshr miss latency 1863system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086 # average WriteReq mshr miss latency 1864system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086 # average WriteReq mshr miss latency 1865system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086 # average SoftPFReq mshr miss latency 1866system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086 # average SoftPFReq mshr miss latency 1867system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953 # average WriteLineReq mshr miss latency 1868system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953 # average WriteLineReq mshr miss latency 1869system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517 # average LoadLockedReq mshr miss latency 1870system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517 # average LoadLockedReq mshr miss latency 1871system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782 # average StoreCondReq mshr miss latency 1872system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782 # average StoreCondReq mshr miss latency 1873system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1874system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1875system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338 # average overall mshr miss latency 1876system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338 # average overall mshr miss latency 1877system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262 # average overall mshr miss latency 1878system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262 # average overall mshr miss latency 1879system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850 # average ReadReq mshr uncacheable latency 1880system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850 # average ReadReq mshr uncacheable latency 1881system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113 # average overall mshr uncacheable latency 1882system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113 # average overall mshr uncacheable latency 1883system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1884system.cpu1.icache.tags.replacements 9521452 # number of replacements 1885system.cpu1.icache.tags.tagsinuse 507.043038 # Cycle average of tags in use 1886system.cpu1.icache.tags.total_refs 244267020 # Total number of references to valid blocks. 1887system.cpu1.icache.tags.sampled_refs 9521964 # Sample count of references to valid blocks. 1888system.cpu1.icache.tags.avg_refs 25.653008 # Average number of references to valid blocks. 1889system.cpu1.icache.tags.warmup_cycle 8368158607000 # Cycle when the warmup percentage was hit. 1890system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.043038 # Average occupied blocks per requestor 1891system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990318 # Average percentage of cache occupancy 1892system.cpu1.icache.tags.occ_percent::total 0.990318 # Average percentage of cache occupancy 1893system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1894system.cpu1.icache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id 1895system.cpu1.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 1896system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 1897system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1898system.cpu1.icache.tags.tag_accesses 517099934 # Number of tag accesses 1899system.cpu1.icache.tags.data_accesses 517099934 # Number of data accesses 1900system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1901system.cpu1.icache.ReadReq_hits::cpu1.inst 244267020 # number of ReadReq hits 1902system.cpu1.icache.ReadReq_hits::total 244267020 # number of ReadReq hits 1903system.cpu1.icache.demand_hits::cpu1.inst 244267020 # number of demand (read+write) hits 1904system.cpu1.icache.demand_hits::total 244267020 # number of demand (read+write) hits 1905system.cpu1.icache.overall_hits::cpu1.inst 244267020 # number of overall hits 1906system.cpu1.icache.overall_hits::total 244267020 # number of overall hits 1907system.cpu1.icache.ReadReq_misses::cpu1.inst 9521965 # number of ReadReq misses 1908system.cpu1.icache.ReadReq_misses::total 9521965 # number of ReadReq misses 1909system.cpu1.icache.demand_misses::cpu1.inst 9521965 # number of demand (read+write) misses 1910system.cpu1.icache.demand_misses::total 9521965 # number of demand (read+write) misses 1911system.cpu1.icache.overall_misses::cpu1.inst 9521965 # number of overall misses 1912system.cpu1.icache.overall_misses::total 9521965 # number of overall misses 1913system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96688620500 # number of ReadReq miss cycles 1914system.cpu1.icache.ReadReq_miss_latency::total 96688620500 # number of ReadReq miss cycles 1915system.cpu1.icache.demand_miss_latency::cpu1.inst 96688620500 # number of demand (read+write) miss cycles 1916system.cpu1.icache.demand_miss_latency::total 96688620500 # number of demand (read+write) miss cycles 1917system.cpu1.icache.overall_miss_latency::cpu1.inst 96688620500 # number of overall miss cycles 1918system.cpu1.icache.overall_miss_latency::total 96688620500 # number of overall miss cycles 1919system.cpu1.icache.ReadReq_accesses::cpu1.inst 253788985 # number of ReadReq accesses(hits+misses) 1920system.cpu1.icache.ReadReq_accesses::total 253788985 # number of ReadReq accesses(hits+misses) 1921system.cpu1.icache.demand_accesses::cpu1.inst 253788985 # number of demand (read+write) accesses 1922system.cpu1.icache.demand_accesses::total 253788985 # number of demand (read+write) accesses 1923system.cpu1.icache.overall_accesses::cpu1.inst 253788985 # number of overall (read+write) accesses 1924system.cpu1.icache.overall_accesses::total 253788985 # number of overall (read+write) accesses 1925system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037519 # miss rate for ReadReq accesses 1926system.cpu1.icache.ReadReq_miss_rate::total 0.037519 # miss rate for ReadReq accesses 1927system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037519 # miss rate for demand accesses 1928system.cpu1.icache.demand_miss_rate::total 0.037519 # miss rate for demand accesses 1929system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037519 # miss rate for overall accesses 1930system.cpu1.icache.overall_miss_rate::total 0.037519 # miss rate for overall accesses 1931system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781 # average ReadReq miss latency 1932system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781 # average ReadReq miss latency 1933system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency 1934system.cpu1.icache.demand_avg_miss_latency::total 10154.271781 # average overall miss latency 1935system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency 1936system.cpu1.icache.overall_avg_miss_latency::total 10154.271781 # average overall miss latency 1937system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1938system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1939system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1940system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1941system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1942system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1943system.cpu1.icache.writebacks::writebacks 9521452 # number of writebacks 1944system.cpu1.icache.writebacks::total 9521452 # number of writebacks 1945system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9521965 # number of ReadReq MSHR misses 1946system.cpu1.icache.ReadReq_mshr_misses::total 9521965 # number of ReadReq MSHR misses 1947system.cpu1.icache.demand_mshr_misses::cpu1.inst 9521965 # number of demand (read+write) MSHR misses 1948system.cpu1.icache.demand_mshr_misses::total 9521965 # number of demand (read+write) MSHR misses 1949system.cpu1.icache.overall_mshr_misses::cpu1.inst 9521965 # number of overall MSHR misses 1950system.cpu1.icache.overall_mshr_misses::total 9521965 # number of overall MSHR misses 1951system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 1952system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 1953system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 1954system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 1955system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91927638500 # number of ReadReq MSHR miss cycles 1956system.cpu1.icache.ReadReq_mshr_miss_latency::total 91927638500 # number of ReadReq MSHR miss cycles 1957system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91927638500 # number of demand (read+write) MSHR miss cycles 1958system.cpu1.icache.demand_mshr_miss_latency::total 91927638500 # number of demand (read+write) MSHR miss cycles 1959system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91927638500 # number of overall MSHR miss cycles 1960system.cpu1.icache.overall_mshr_miss_latency::total 91927638500 # number of overall MSHR miss cycles 1961system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9070500 # number of ReadReq MSHR uncacheable cycles 1962system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9070500 # number of ReadReq MSHR uncacheable cycles 1963system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9070500 # number of overall MSHR uncacheable cycles 1964system.cpu1.icache.overall_mshr_uncacheable_latency::total 9070500 # number of overall MSHR uncacheable cycles 1965system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for ReadReq accesses 1966system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037519 # mshr miss rate for ReadReq accesses 1967system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for demand accesses 1968system.cpu1.icache.demand_mshr_miss_rate::total 0.037519 # mshr miss rate for demand accesses 1969system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for overall accesses 1970system.cpu1.icache.overall_mshr_miss_rate::total 0.037519 # mshr miss rate for overall accesses 1971system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average ReadReq mshr miss latency 1972system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9654.271834 # average ReadReq mshr miss latency 1973system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency 1974system.cpu1.icache.demand_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency 1975system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency 1976system.cpu1.icache.overall_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency 1977system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average ReadReq mshr uncacheable latency 1978system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368 # average ReadReq mshr uncacheable latency 1979system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average overall mshr uncacheable latency 1980system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368 # average overall mshr uncacheable latency 1981system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1982system.cpu1.l2cache.prefetcher.num_hwpf_issued 7586302 # number of hwpf issued 1983system.cpu1.l2cache.prefetcher.pfIdentified 7586460 # number of prefetch candidates identified 1984system.cpu1.l2cache.prefetcher.pfBufferHit 136 # number of redundant prefetches already in prefetch queue 1985system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1986system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1987system.cpu1.l2cache.prefetcher.pfSpanPage 987804 # number of prefetches not generated due to page crossing 1988system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 1989system.cpu1.l2cache.tags.replacements 2406613 # number of replacements 1990system.cpu1.l2cache.tags.tagsinuse 13125.467163 # Cycle average of tags in use 1991system.cpu1.l2cache.tags.total_refs 13856134 # Total number of references to valid blocks. 1992system.cpu1.l2cache.tags.sampled_refs 2421819 # Sample count of references to valid blocks. 1993system.cpu1.l2cache.tags.avg_refs 5.721375 # Average number of references to valid blocks. 1994system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1995system.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806 # Average occupied blocks per requestor 1996system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.086630 # Average occupied blocks per requestor 1997system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.305413 # Average occupied blocks per requestor 1998system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 234.798314 # Average occupied blocks per requestor 1999system.cpu1.l2cache.tags.occ_percent::writebacks 0.784258 # Average percentage of cache occupancy 2000system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001653 # Average percentage of cache occupancy 2001system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000873 # Average percentage of cache occupancy 2002system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014331 # Average percentage of cache occupancy 2003system.cpu1.l2cache.tags.occ_percent::total 0.801115 # Average percentage of cache occupancy 2004system.cpu1.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id 2005system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 2006system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14856 # Occupied blocks per task id 2007system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 2008system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 106 # Occupied blocks per task id 2009system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 108 # Occupied blocks per task id 2010system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 47 # Occupied blocks per task id 2011system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2015system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id 2016system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 743 # Occupied blocks per task id 2017system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6180 # Occupied blocks per task id 2018system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6756 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 775 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id 2021system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 2022system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.906738 # Percentage of cache occupancy per task id 2023system.cpu1.l2cache.tags.tag_accesses 519862521 # Number of tag accesses 2024system.cpu1.l2cache.tags.data_accesses 519862521 # Number of data accesses 2025system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2026system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 578094 # number of ReadReq hits 2027system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 171981 # number of ReadReq hits 2028system.cpu1.l2cache.ReadReq_hits::total 750075 # number of ReadReq hits 2029system.cpu1.l2cache.WritebackDirty_hits::writebacks 3464322 # number of WritebackDirty hits 2030system.cpu1.l2cache.WritebackDirty_hits::total 3464322 # number of WritebackDirty hits 2031system.cpu1.l2cache.WritebackClean_hits::writebacks 11639503 # number of WritebackClean hits 2032system.cpu1.l2cache.WritebackClean_hits::total 11639503 # number of WritebackClean hits 2033system.cpu1.l2cache.ReadExReq_hits::cpu1.data 901874 # number of ReadExReq hits 2034system.cpu1.l2cache.ReadExReq_hits::total 901874 # number of ReadExReq hits 2035system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8781698 # number of ReadCleanReq hits 2036system.cpu1.l2cache.ReadCleanReq_hits::total 8781698 # number of ReadCleanReq hits 2037system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3023137 # number of ReadSharedReq hits 2038system.cpu1.l2cache.ReadSharedReq_hits::total 3023137 # number of ReadSharedReq hits 2039system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191670 # number of InvalidateReq hits 2040system.cpu1.l2cache.InvalidateReq_hits::total 191670 # number of InvalidateReq hits 2041system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 578094 # number of demand (read+write) hits 2042system.cpu1.l2cache.demand_hits::cpu1.itb.walker 171981 # number of demand (read+write) hits 2043system.cpu1.l2cache.demand_hits::cpu1.inst 8781698 # number of demand (read+write) hits 2044system.cpu1.l2cache.demand_hits::cpu1.data 3925011 # number of demand (read+write) hits 2045system.cpu1.l2cache.demand_hits::total 13456784 # number of demand (read+write) hits 2046system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 578094 # number of overall hits 2047system.cpu1.l2cache.overall_hits::cpu1.itb.walker 171981 # number of overall hits 2048system.cpu1.l2cache.overall_hits::cpu1.inst 8781698 # number of overall hits 2049system.cpu1.l2cache.overall_hits::cpu1.data 3925011 # number of overall hits 2050system.cpu1.l2cache.overall_hits::total 13456784 # number of overall hits 2051system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22586 # number of ReadReq misses 2052system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11050 # number of ReadReq misses 2053system.cpu1.l2cache.ReadReq_misses::total 33636 # number of ReadReq misses 2054system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 232349 # number of UpgradeReq misses 2055system.cpu1.l2cache.UpgradeReq_misses::total 232349 # number of UpgradeReq misses 2056system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193761 # number of SCUpgradeReq misses 2057system.cpu1.l2cache.SCUpgradeReq_misses::total 193761 # number of SCUpgradeReq misses 2058system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2059system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2060system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259533 # number of ReadExReq misses 2061system.cpu1.l2cache.ReadExReq_misses::total 259533 # number of ReadExReq misses 2062system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 740267 # number of ReadCleanReq misses 2063system.cpu1.l2cache.ReadCleanReq_misses::total 740267 # number of ReadCleanReq misses 2064system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1026659 # number of ReadSharedReq misses 2065system.cpu1.l2cache.ReadSharedReq_misses::total 1026659 # number of ReadSharedReq misses 2066system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 269262 # number of InvalidateReq misses 2067system.cpu1.l2cache.InvalidateReq_misses::total 269262 # number of InvalidateReq misses 2068system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22586 # number of demand (read+write) misses 2069system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11050 # number of demand (read+write) misses 2070system.cpu1.l2cache.demand_misses::cpu1.inst 740267 # number of demand (read+write) misses 2071system.cpu1.l2cache.demand_misses::cpu1.data 1286192 # number of demand (read+write) misses 2072system.cpu1.l2cache.demand_misses::total 2060095 # number of demand (read+write) misses 2073system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22586 # number of overall misses 2074system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11050 # number of overall misses 2075system.cpu1.l2cache.overall_misses::cpu1.inst 740267 # number of overall misses 2076system.cpu1.l2cache.overall_misses::cpu1.data 1286192 # number of overall misses 2077system.cpu1.l2cache.overall_misses::total 2060095 # number of overall misses 2078system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 726971000 # number of ReadReq miss cycles 2079system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 437240000 # number of ReadReq miss cycles 2080system.cpu1.l2cache.ReadReq_miss_latency::total 1164211000 # number of ReadReq miss cycles 2081system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 947721000 # number of UpgradeReq miss cycles 2082system.cpu1.l2cache.UpgradeReq_miss_latency::total 947721000 # number of UpgradeReq miss cycles 2083system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273329000 # number of SCUpgradeReq miss cycles 2084system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273329000 # number of SCUpgradeReq miss cycles 2085system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2036499 # number of SCUpgradeFailReq miss cycles 2086system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2036499 # number of SCUpgradeFailReq miss cycles 2087system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11444500498 # number of ReadExReq miss cycles 2088system.cpu1.l2cache.ReadExReq_miss_latency::total 11444500498 # number of ReadExReq miss cycles 2089system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24621036000 # number of ReadCleanReq miss cycles 2090system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24621036000 # number of ReadCleanReq miss cycles 2091system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 35849827996 # number of ReadSharedReq miss cycles 2092system.cpu1.l2cache.ReadSharedReq_miss_latency::total 35849827996 # number of ReadSharedReq miss cycles 2093system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 304696500 # number of InvalidateReq miss cycles 2094system.cpu1.l2cache.InvalidateReq_miss_latency::total 304696500 # number of InvalidateReq miss cycles 2095system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 726971000 # number of demand (read+write) miss cycles 2096system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 437240000 # number of demand (read+write) miss cycles 2097system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24621036000 # number of demand (read+write) miss cycles 2098system.cpu1.l2cache.demand_miss_latency::cpu1.data 47294328494 # number of demand (read+write) miss cycles 2099system.cpu1.l2cache.demand_miss_latency::total 73079575494 # number of demand (read+write) miss cycles 2100system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 726971000 # number of overall miss cycles 2101system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 437240000 # number of overall miss cycles 2102system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24621036000 # number of overall miss cycles 2103system.cpu1.l2cache.overall_miss_latency::cpu1.data 47294328494 # number of overall miss cycles 2104system.cpu1.l2cache.overall_miss_latency::total 73079575494 # number of overall miss cycles 2105system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 600680 # number of ReadReq accesses(hits+misses) 2106system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 183031 # number of ReadReq accesses(hits+misses) 2107system.cpu1.l2cache.ReadReq_accesses::total 783711 # number of ReadReq accesses(hits+misses) 2108system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3464322 # number of WritebackDirty accesses(hits+misses) 2109system.cpu1.l2cache.WritebackDirty_accesses::total 3464322 # number of WritebackDirty accesses(hits+misses) 2110system.cpu1.l2cache.WritebackClean_accesses::writebacks 11639503 # number of WritebackClean accesses(hits+misses) 2111system.cpu1.l2cache.WritebackClean_accesses::total 11639503 # number of WritebackClean accesses(hits+misses) 2112system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232349 # number of UpgradeReq accesses(hits+misses) 2113system.cpu1.l2cache.UpgradeReq_accesses::total 232349 # number of UpgradeReq accesses(hits+misses) 2114system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193761 # number of SCUpgradeReq accesses(hits+misses) 2115system.cpu1.l2cache.SCUpgradeReq_accesses::total 193761 # number of SCUpgradeReq accesses(hits+misses) 2116system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2117system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2118system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1161407 # number of ReadExReq accesses(hits+misses) 2119system.cpu1.l2cache.ReadExReq_accesses::total 1161407 # number of ReadExReq accesses(hits+misses) 2120system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9521965 # number of ReadCleanReq accesses(hits+misses) 2121system.cpu1.l2cache.ReadCleanReq_accesses::total 9521965 # number of ReadCleanReq accesses(hits+misses) 2122system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4049796 # number of ReadSharedReq accesses(hits+misses) 2123system.cpu1.l2cache.ReadSharedReq_accesses::total 4049796 # number of ReadSharedReq accesses(hits+misses) 2124system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 460932 # number of InvalidateReq accesses(hits+misses) 2125system.cpu1.l2cache.InvalidateReq_accesses::total 460932 # number of InvalidateReq accesses(hits+misses) 2126system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 600680 # number of demand (read+write) accesses 2127system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 183031 # number of demand (read+write) accesses 2128system.cpu1.l2cache.demand_accesses::cpu1.inst 9521965 # number of demand (read+write) accesses 2129system.cpu1.l2cache.demand_accesses::cpu1.data 5211203 # number of demand (read+write) accesses 2130system.cpu1.l2cache.demand_accesses::total 15516879 # number of demand (read+write) accesses 2131system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 600680 # number of overall (read+write) accesses 2132system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 183031 # number of overall (read+write) accesses 2133system.cpu1.l2cache.overall_accesses::cpu1.inst 9521965 # number of overall (read+write) accesses 2134system.cpu1.l2cache.overall_accesses::cpu1.data 5211203 # number of overall (read+write) accesses 2135system.cpu1.l2cache.overall_accesses::total 15516879 # number of overall (read+write) accesses 2136system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for ReadReq accesses 2137system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.060372 # miss rate for ReadReq accesses 2138system.cpu1.l2cache.ReadReq_miss_rate::total 0.042919 # miss rate for ReadReq accesses 2139system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2140system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2141system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2142system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2143system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2144system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2145system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.223464 # miss rate for ReadExReq accesses 2146system.cpu1.l2cache.ReadExReq_miss_rate::total 0.223464 # miss rate for ReadExReq accesses 2147system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077743 # miss rate for ReadCleanReq accesses 2148system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077743 # miss rate for ReadCleanReq accesses 2149system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253509 # miss rate for ReadSharedReq accesses 2150system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253509 # miss rate for ReadSharedReq accesses 2151system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584169 # miss rate for InvalidateReq accesses 2152system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584169 # miss rate for InvalidateReq accesses 2153system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for demand accesses 2154system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.060372 # miss rate for demand accesses 2155system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077743 # miss rate for demand accesses 2156system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246813 # miss rate for demand accesses 2157system.cpu1.l2cache.demand_miss_rate::total 0.132765 # miss rate for demand accesses 2158system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for overall accesses 2159system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.060372 # miss rate for overall accesses 2160system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077743 # miss rate for overall accesses 2161system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246813 # miss rate for overall accesses 2162system.cpu1.l2cache.overall_miss_rate::total 0.132765 # miss rate for overall accesses 2163system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average ReadReq miss latency 2164system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39569.230769 # average ReadReq miss latency 2165system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34612.052563 # average ReadReq miss latency 2166system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4078.868426 # average UpgradeReq miss latency 2167system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4078.868426 # average UpgradeReq miss latency 2168system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1410.650234 # average SCUpgradeReq miss latency 2169system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1410.650234 # average SCUpgradeReq miss latency 2170system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678833 # average SCUpgradeFailReq miss latency 2171system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678833 # average SCUpgradeFailReq miss latency 2172system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44096.513730 # average ReadExReq miss latency 2173system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44096.513730 # average ReadExReq miss latency 2174system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33259.669822 # average ReadCleanReq miss latency 2175system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33259.669822 # average ReadCleanReq miss latency 2176system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34918.924391 # average ReadSharedReq miss latency 2177system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34918.924391 # average ReadSharedReq miss latency 2178system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1131.598592 # average InvalidateReq miss latency 2179system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1131.598592 # average InvalidateReq miss latency 2180system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency 2181system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency 2182system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency 2183system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency 2184system.cpu1.l2cache.demand_avg_miss_latency::total 35473.886153 # average overall miss latency 2185system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency 2186system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency 2187system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency 2188system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency 2189system.cpu1.l2cache.overall_avg_miss_latency::total 35473.886153 # average overall miss latency 2190system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2191system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2192system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2193system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2194system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2195system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2196system.cpu1.l2cache.unused_prefetches 49424 # number of HardPF blocks evicted w/o reference 2197system.cpu1.l2cache.writebacks::writebacks 1233392 # number of writebacks 2198system.cpu1.l2cache.writebacks::total 1233392 # number of writebacks 2199system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 16 # number of ReadReq MSHR hits 2200system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 110 # number of ReadReq MSHR hits 2201system.cpu1.l2cache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits 2202system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7522 # number of ReadExReq MSHR hits 2203system.cpu1.l2cache.ReadExReq_mshr_hits::total 7522 # number of ReadExReq MSHR hits 2204system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits 2205system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 2206system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 653 # number of ReadSharedReq MSHR hits 2207system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 653 # number of ReadSharedReq MSHR hits 2208system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 16 # number of demand (read+write) MSHR hits 2209system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 110 # number of demand (read+write) MSHR hits 2210system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2211system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8175 # number of demand (read+write) MSHR hits 2212system.cpu1.l2cache.demand_mshr_hits::total 8303 # number of demand (read+write) MSHR hits 2213system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 16 # number of overall MSHR hits 2214system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 110 # number of overall MSHR hits 2215system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2216system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8175 # number of overall MSHR hits 2217system.cpu1.l2cache.overall_mshr_hits::total 8303 # number of overall MSHR hits 2218system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 22570 # number of ReadReq MSHR misses 2219system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10940 # number of ReadReq MSHR misses 2220system.cpu1.l2cache.ReadReq_mshr_misses::total 33510 # number of ReadReq MSHR misses 2221system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 779944 # number of HardPFReq MSHR misses 2222system.cpu1.l2cache.HardPFReq_mshr_misses::total 779944 # number of HardPFReq MSHR misses 2223system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 232349 # number of UpgradeReq MSHR misses 2224system.cpu1.l2cache.UpgradeReq_mshr_misses::total 232349 # number of UpgradeReq MSHR misses 2225system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193761 # number of SCUpgradeReq MSHR misses 2226system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193761 # number of SCUpgradeReq MSHR misses 2227system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2228system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2229system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 252011 # number of ReadExReq MSHR misses 2230system.cpu1.l2cache.ReadExReq_mshr_misses::total 252011 # number of ReadExReq MSHR misses 2231system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 740265 # number of ReadCleanReq MSHR misses 2232system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 740265 # number of ReadCleanReq MSHR misses 2233system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1026006 # number of ReadSharedReq MSHR misses 2234system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1026006 # number of ReadSharedReq MSHR misses 2235system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 269262 # number of InvalidateReq MSHR misses 2236system.cpu1.l2cache.InvalidateReq_mshr_misses::total 269262 # number of InvalidateReq MSHR misses 2237system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 22570 # number of demand (read+write) MSHR misses 2238system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10940 # number of demand (read+write) MSHR misses 2239system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 740265 # number of demand (read+write) MSHR misses 2240system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1278017 # number of demand (read+write) MSHR misses 2241system.cpu1.l2cache.demand_mshr_misses::total 2051792 # number of demand (read+write) MSHR misses 2242system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 22570 # number of overall MSHR misses 2243system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10940 # number of overall MSHR misses 2244system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 740265 # number of overall MSHR misses 2245system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1278017 # number of overall MSHR misses 2246system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 779944 # number of overall MSHR misses 2247system.cpu1.l2cache.overall_mshr_misses::total 2831736 # number of overall MSHR misses 2248system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 2249system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable 2250system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17703 # number of ReadReq MSHR uncacheable 2251system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 2252system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable 2253system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 2254system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses 2255system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33556 # number of overall MSHR uncacheable misses 2256system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of ReadReq MSHR miss cycles 2257system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369748000 # number of ReadReq MSHR miss cycles 2258system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 960914500 # number of ReadReq MSHR miss cycles 2259system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of HardPFReq MSHR miss cycles 2260system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 34084097769 # number of HardPFReq MSHR miss cycles 2261system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4320296500 # number of UpgradeReq MSHR miss cycles 2262system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4320296500 # number of UpgradeReq MSHR miss cycles 2263system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2976407492 # number of SCUpgradeReq MSHR miss cycles 2264system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2976407492 # number of SCUpgradeReq MSHR miss cycles 2265system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1712499 # number of SCUpgradeFailReq MSHR miss cycles 2266system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1712499 # number of SCUpgradeFailReq MSHR miss cycles 2267system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8961948498 # number of ReadExReq MSHR miss cycles 2268system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8961948498 # number of ReadExReq MSHR miss cycles 2269system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20179405000 # number of ReadCleanReq MSHR miss cycles 2270system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20179405000 # number of ReadCleanReq MSHR miss cycles 2271system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29636625496 # number of ReadSharedReq MSHR miss cycles 2272system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29636625496 # number of ReadSharedReq MSHR miss cycles 2273system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7368901000 # number of InvalidateReq MSHR miss cycles 2274system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7368901000 # number of InvalidateReq MSHR miss cycles 2275system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of demand (read+write) MSHR miss cycles 2276system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369748000 # number of demand (read+write) MSHR miss cycles 2277system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20179405000 # number of demand (read+write) MSHR miss cycles 2278system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38598573994 # number of demand (read+write) MSHR miss cycles 2279system.cpu1.l2cache.demand_mshr_miss_latency::total 59738893494 # number of demand (read+write) MSHR miss cycles 2280system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of overall MSHR miss cycles 2281system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369748000 # number of overall MSHR miss cycles 2282system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20179405000 # number of overall MSHR miss cycles 2283system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38598573994 # number of overall MSHR miss cycles 2284system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of overall MSHR miss cycles 2285system.cpu1.l2cache.overall_mshr_miss_latency::total 93822991263 # number of overall MSHR miss cycles 2286system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8310500 # number of ReadReq MSHR uncacheable cycles 2287system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2795199500 # number of ReadReq MSHR uncacheable cycles 2288system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2803510000 # number of ReadReq MSHR uncacheable cycles 2289system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8310500 # number of overall MSHR uncacheable cycles 2290system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2795199500 # number of overall MSHR uncacheable cycles 2291system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2803510000 # number of overall MSHR uncacheable cycles 2292system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for ReadReq accesses 2293system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for ReadReq accesses 2294system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042758 # mshr miss rate for ReadReq accesses 2295system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2296system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2297system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2298system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2299system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2300system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2301system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2302system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2303system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.216988 # mshr miss rate for ReadExReq accesses 2304system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.216988 # mshr miss rate for ReadExReq accesses 2305system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for ReadCleanReq accesses 2306system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077743 # mshr miss rate for ReadCleanReq accesses 2307system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253348 # mshr miss rate for ReadSharedReq accesses 2308system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253348 # mshr miss rate for ReadSharedReq accesses 2309system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584169 # mshr miss rate for InvalidateReq accesses 2310system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584169 # mshr miss rate for InvalidateReq accesses 2311system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for demand accesses 2312system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for demand accesses 2313system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for demand accesses 2314system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for demand accesses 2315system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132230 # mshr miss rate for demand accesses 2316system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for overall accesses 2317system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for overall accesses 2318system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for overall accesses 2319system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for overall accesses 2320system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2321system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182494 # mshr miss rate for overall accesses 2322system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average ReadReq mshr miss latency 2323system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average ReadReq mshr miss latency 2324system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088 # average ReadReq mshr miss latency 2325system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average HardPFReq mshr miss latency 2326system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728 # average HardPFReq mshr miss latency 2327system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531 # average UpgradeReq mshr miss latency 2328system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531 # average UpgradeReq mshr miss latency 2329system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063 # average SCUpgradeReq mshr miss latency 2330system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063 # average SCUpgradeReq mshr miss latency 2331system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 570833 # average SCUpgradeFailReq mshr miss latency 2332system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 570833 # average SCUpgradeFailReq mshr miss latency 2333system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393 # average ReadExReq mshr miss latency 2334system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393 # average ReadExReq mshr miss latency 2335system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average ReadCleanReq mshr miss latency 2336system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295 # average ReadCleanReq mshr miss latency 2337system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978 # average ReadSharedReq mshr miss latency 2338system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978 # average ReadSharedReq mshr miss latency 2339system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139 # average InvalidateReq mshr miss latency 2340system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139 # average InvalidateReq mshr miss latency 2341system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency 2342system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency 2343system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency 2344system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency 2345system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472 # average overall mshr miss latency 2346system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency 2347system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency 2348system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency 2349system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency 2350system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average overall mshr miss latency 2351system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950 # average overall mshr miss latency 2352system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average ReadReq mshr uncacheable latency 2353system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138 # average ReadReq mshr uncacheable latency 2354system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200 # average ReadReq mshr uncacheable latency 2355system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average overall mshr uncacheable latency 2356system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959 # average overall mshr uncacheable latency 2357system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673 # average overall mshr uncacheable latency 2358system.cpu1.toL2Bus.snoop_filter.tot_requests 31064178 # Total number of requests made to the snoop filter. 2359system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15870221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2360system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2361system.cpu1.toL2Bus.snoop_filter.tot_snoops 609547 # Total number of snoops made to the snoop filter. 2362system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 609525 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2363system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 22 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2364system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2365system.cpu1.toL2Bus.trans_dist::ReadReq 891069 # Transaction distribution 2366system.cpu1.toL2Bus.trans_dist::ReadResp 14544906 # Transaction distribution 2367system.cpu1.toL2Bus.trans_dist::WriteReq 15853 # Transaction distribution 2368system.cpu1.toL2Bus.trans_dist::WriteResp 15853 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::WritebackDirty 4703319 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::WritebackClean 11641461 # Transaction distribution 2371system.cpu1.toL2Bus.trans_dist::CleanEvict 1517999 # Transaction distribution 2372system.cpu1.toL2Bus.trans_dist::HardPFReq 982833 # Transaction distribution 2373system.cpu1.toL2Bus.trans_dist::UpgradeReq 435735 # Transaction distribution 2374system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338791 # Transaction distribution 2375system.cpu1.toL2Bus.trans_dist::UpgradeResp 485404 # Transaction distribution 2376system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution 2377system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 2378system.cpu1.toL2Bus.trans_dist::ReadExReq 1187635 # Transaction distribution 2379system.cpu1.toL2Bus.trans_dist::ReadExResp 1166992 # Transaction distribution 2380system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9521965 # Transaction distribution 2381system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5021918 # Transaction distribution 2382system.cpu1.toL2Bus.trans_dist::InvalidateReq 508584 # Transaction distribution 2383system.cpu1.toL2Bus.trans_dist::InvalidateResp 460932 # Transaction distribution 2384system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28565571 # Packet count per connected master and slave (bytes) 2385system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17994817 # Packet count per connected master and slave (bytes) 2386system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387517 # Packet count per connected master and slave (bytes) 2387system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1269560 # Packet count per connected master and slave (bytes) 2388system.cpu1.toL2Bus.pkt_count::total 48217465 # Packet count per connected master and slave (bytes) 2389system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1218784704 # Cumulative packet size per connected master and slave (bytes) 2390system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 696648341 # Cumulative packet size per connected master and slave (bytes) 2391system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1464248 # Cumulative packet size per connected master and slave (bytes) 2392system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4805440 # Cumulative packet size per connected master and slave (bytes) 2393system.cpu1.toL2Bus.pkt_size::total 1921702733 # Cumulative packet size per connected master and slave (bytes) 2394system.cpu1.toL2Bus.snoops 5371031 # Total snoops (count) 2395system.cpu1.toL2Bus.snoopTraffic 85625912 # Total snoop traffic (bytes) 2396system.cpu1.toL2Bus.snoop_fanout::samples 21661443 # Request fanout histogram 2397system.cpu1.toL2Bus.snoop_fanout::mean 0.043843 # Request fanout histogram 2398system.cpu1.toL2Bus.snoop_fanout::stdev 0.204751 # Request fanout histogram 2399system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2400system.cpu1.toL2Bus.snoop_fanout::0 20711756 95.62% 95.62% # Request fanout histogram 2401system.cpu1.toL2Bus.snoop_fanout::1 949665 4.38% 100.00% # Request fanout histogram 2402system.cpu1.toL2Bus.snoop_fanout::2 22 0.00% 100.00% # Request fanout histogram 2403system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2404system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2405system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2406system.cpu1.toL2Bus.snoop_fanout::total 21661443 # Request fanout histogram 2407system.cpu1.toL2Bus.reqLayer0.occupancy 30930175985 # Layer occupancy (ticks) 2408system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2409system.cpu1.toL2Bus.snoopLayer0.occupancy 161428122 # Layer occupancy (ticks) 2410system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2411system.cpu1.toL2Bus.respLayer0.occupancy 14285968218 # Layer occupancy (ticks) 2412system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2413system.cpu1.toL2Bus.respLayer1.occupancy 8290126100 # Layer occupancy (ticks) 2414system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2415system.cpu1.toL2Bus.respLayer2.occupancy 204584802 # Layer occupancy (ticks) 2416system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2417system.cpu1.toL2Bus.respLayer3.occupancy 668995768 # Layer occupancy (ticks) 2418system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2419system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2420system.iobus.trans_dist::ReadReq 40347 # Transaction distribution 2421system.iobus.trans_dist::ReadResp 40347 # Transaction distribution 2422system.iobus.trans_dist::WriteReq 136610 # Transaction distribution 2423system.iobus.trans_dist::WriteResp 136610 # Transaction distribution 2424system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47638 # Packet count per connected master and slave (bytes) 2425system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2426system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2427system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2430system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2431system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2432system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2433system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2434system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2435system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2436system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2437system.iobus.pkt_count_system.bridge.master::total 122572 # Packet count per connected master and slave (bytes) 2438system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) 2439system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) 2440system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2441system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2442system.iobus.pkt_count::total 353914 # Packet count per connected master and slave (bytes) 2443system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47658 # Cumulative packet size per connected master and slave (bytes) 2444system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2445system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2446system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2449system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2450system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2451system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2452system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2453system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2454system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2455system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2456system.iobus.pkt_size_system.bridge.master::total 155679 # Cumulative packet size per connected master and slave (bytes) 2457system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) 2458system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) 2459system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2460system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2461system.iobus.pkt_size::total 7496829 # Cumulative packet size per connected master and slave (bytes) 2462system.iobus.reqLayer0.occupancy 41998503 # Layer occupancy (ticks) 2463system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2464system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 2465system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2466system.iobus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) 2467system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2468system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 2469system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2470system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 2471system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2472system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 2473system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2474system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 2475system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2476system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 2477system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2478system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 2479system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2480system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 2481system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2482system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 2483system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2484system.iobus.reqLayer23.occupancy 25719009 # Layer occupancy (ticks) 2485system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2486system.iobus.reqLayer24.occupancy 34474500 # Layer occupancy (ticks) 2487system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2488system.iobus.reqLayer25.occupancy 569697884 # Layer occupancy (ticks) 2489system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2490system.iobus.respLayer0.occupancy 92693000 # Layer occupancy (ticks) 2491system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2492system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) 2493system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2494system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2495system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2496system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2497system.iocache.tags.replacements 115612 # number of replacements 2498system.iocache.tags.tagsinuse 11.289058 # Cycle average of tags in use 2499system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2500system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. 2501system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2502system.iocache.tags.warmup_cycle 9127814531000 # Cycle when the warmup percentage was hit. 2503system.iocache.tags.occ_blocks::realview.ethernet 3.847615 # Average occupied blocks per requestor 2504system.iocache.tags.occ_blocks::realview.ide 7.441443 # Average occupied blocks per requestor 2505system.iocache.tags.occ_percent::realview.ethernet 0.240476 # Average percentage of cache occupancy 2506system.iocache.tags.occ_percent::realview.ide 0.465090 # Average percentage of cache occupancy 2507system.iocache.tags.occ_percent::total 0.705566 # Average percentage of cache occupancy 2508system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2509system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2510system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2511system.iocache.tags.tag_accesses 1041036 # Number of tag accesses 2512system.iocache.tags.data_accesses 1041036 # Number of data accesses 2513system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2514system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2515system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses 2516system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses 2517system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2518system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2519system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2520system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2521system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2522system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses 2523system.iocache.demand_misses::total 115671 # number of demand (read+write) misses 2524system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2525system.iocache.overall_misses::realview.ide 115631 # number of overall misses 2526system.iocache.overall_misses::total 115671 # number of overall misses 2527system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles 2528system.iocache.ReadReq_miss_latency::realview.ide 1683130463 # number of ReadReq miss cycles 2529system.iocache.ReadReq_miss_latency::total 1688328963 # number of ReadReq miss cycles 2530system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2531system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2532system.iocache.WriteLineReq_miss_latency::realview.ide 12860878921 # number of WriteLineReq miss cycles 2533system.iocache.WriteLineReq_miss_latency::total 12860878921 # number of WriteLineReq miss cycles 2534system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles 2535system.iocache.demand_miss_latency::realview.ide 14544009384 # number of demand (read+write) miss cycles 2536system.iocache.demand_miss_latency::total 14549576884 # number of demand (read+write) miss cycles 2537system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles 2538system.iocache.overall_miss_latency::realview.ide 14544009384 # number of overall miss cycles 2539system.iocache.overall_miss_latency::total 14549576884 # number of overall miss cycles 2540system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2541system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) 2542system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) 2543system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2544system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2545system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2546system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2547system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2548system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses 2549system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses 2550system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2551system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses 2552system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses 2553system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2554system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2555system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2556system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2557system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2558system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2559system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2560system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2561system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2562system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2563system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2564system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2565system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2566system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency 2567system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947 # average ReadReq miss latency 2568system.iocache.ReadReq_avg_miss_latency::total 188851.114430 # average ReadReq miss latency 2569system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2570system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2571system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550 # average WriteLineReq miss latency 2572system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550 # average WriteLineReq miss latency 2573system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 2574system.iocache.demand_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency 2575system.iocache.demand_avg_miss_latency::total 125784.136767 # average overall miss latency 2576system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 2577system.iocache.overall_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency 2578system.iocache.overall_avg_miss_latency::total 125784.136767 # average overall miss latency 2579system.iocache.blocked_cycles::no_mshrs 33720 # number of cycles access was blocked 2580system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2581system.iocache.blocked::no_mshrs 3566 # number of cycles access was blocked 2582system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2583system.iocache.avg_blocked_cycles::no_mshrs 9.455973 # average number of cycles each access was blocked 2584system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2585system.iocache.writebacks::writebacks 106694 # number of writebacks 2586system.iocache.writebacks::total 106694 # number of writebacks 2587system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2588system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses 2589system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses 2590system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2591system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2592system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2593system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2594system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2595system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses 2596system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses 2597system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2598system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses 2599system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses 2600system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles 2601system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237980463 # number of ReadReq MSHR miss cycles 2602system.iocache.ReadReq_mshr_miss_latency::total 1241328963 # number of ReadReq MSHR miss cycles 2603system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2604system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2605system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7515783412 # number of WriteLineReq MSHR miss cycles 2606system.iocache.WriteLineReq_mshr_miss_latency::total 7515783412 # number of WriteLineReq MSHR miss cycles 2607system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles 2608system.iocache.demand_mshr_miss_latency::realview.ide 8753763875 # number of demand (read+write) MSHR miss cycles 2609system.iocache.demand_mshr_miss_latency::total 8757331375 # number of demand (read+write) MSHR miss cycles 2610system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles 2611system.iocache.overall_mshr_miss_latency::realview.ide 8753763875 # number of overall MSHR miss cycles 2612system.iocache.overall_mshr_miss_latency::total 8757331375 # number of overall MSHR miss cycles 2613system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2614system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2615system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2616system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2617system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2618system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2619system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2620system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2621system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2622system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2623system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2624system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2625system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2626system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency 2627system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947 # average ReadReq mshr miss latency 2628system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430 # average ReadReq mshr miss latency 2629system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2630system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2631system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000 # average WriteLineReq mshr miss latency 2632system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000 # average WriteLineReq mshr miss latency 2633system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 2634system.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency 2635system.iocache.demand_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency 2636system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 2637system.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency 2638system.iocache.overall_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency 2639system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2640system.l2c.tags.replacements 1555997 # number of replacements 2641system.l2c.tags.tagsinuse 65230.630092 # Cycle average of tags in use 2642system.l2c.tags.total_refs 7273929 # Total number of references to valid blocks. 2643system.l2c.tags.sampled_refs 1617589 # Sample count of references to valid blocks. 2644system.l2c.tags.avg_refs 4.496772 # Average number of references to valid blocks. 2645system.l2c.tags.warmup_cycle 7807986500 # Cycle when the warmup percentage was hit. 2646system.l2c.tags.occ_blocks::writebacks 8906.310468 # Average occupied blocks per requestor 2647system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.466536 # Average occupied blocks per requestor 2648system.l2c.tags.occ_blocks::cpu0.itb.walker 9.611192 # Average occupied blocks per requestor 2649system.l2c.tags.occ_blocks::cpu0.inst 3875.011018 # Average occupied blocks per requestor 2650system.l2c.tags.occ_blocks::cpu0.data 9658.633081 # Average occupied blocks per requestor 2651system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3787.473530 # Average occupied blocks per requestor 2652system.l2c.tags.occ_blocks::cpu1.dtb.walker 432.466953 # Average occupied blocks per requestor 2653system.l2c.tags.occ_blocks::cpu1.itb.walker 495.764320 # Average occupied blocks per requestor 2654system.l2c.tags.occ_blocks::cpu1.inst 3981.420883 # Average occupied blocks per requestor 2655system.l2c.tags.occ_blocks::cpu1.data 15318.580710 # Average occupied blocks per requestor 2656system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401 # Average occupied blocks per requestor 2657system.l2c.tags.occ_percent::writebacks 0.135900 # Average percentage of cache occupancy 2658system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000236 # Average percentage of cache occupancy 2659system.l2c.tags.occ_percent::cpu0.itb.walker 0.000147 # Average percentage of cache occupancy 2660system.l2c.tags.occ_percent::cpu0.inst 0.059128 # Average percentage of cache occupancy 2661system.l2c.tags.occ_percent::cpu0.data 0.147379 # Average percentage of cache occupancy 2662system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057792 # Average percentage of cache occupancy 2663system.l2c.tags.occ_percent::cpu1.dtb.walker 0.006599 # Average percentage of cache occupancy 2664system.l2c.tags.occ_percent::cpu1.itb.walker 0.007565 # Average percentage of cache occupancy 2665system.l2c.tags.occ_percent::cpu1.inst 0.060752 # Average percentage of cache occupancy 2666system.l2c.tags.occ_percent::cpu1.data 0.233743 # Average percentage of cache occupancy 2667system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.286101 # Average percentage of cache occupancy 2668system.l2c.tags.occ_percent::total 0.995340 # Average percentage of cache occupancy 2669system.l2c.tags.occ_task_id_blocks::1022 10605 # Occupied blocks per task id 2670system.l2c.tags.occ_task_id_blocks::1023 254 # Occupied blocks per task id 2671system.l2c.tags.occ_task_id_blocks::1024 50733 # Occupied blocks per task id 2672system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 2673system.l2c.tags.age_task_id_blocks_1022::2 57 # Occupied blocks per task id 2674system.l2c.tags.age_task_id_blocks_1022::3 363 # Occupied blocks per task id 2675system.l2c.tags.age_task_id_blocks_1022::4 10181 # Occupied blocks per task id 2676system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 2677system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2678system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 2679system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 2680system.l2c.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 2681system.l2c.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id 2682system.l2c.tags.age_task_id_blocks_1024::3 4720 # Occupied blocks per task id 2683system.l2c.tags.age_task_id_blocks_1024::4 44382 # Occupied blocks per task id 2684system.l2c.tags.occ_task_id_percent::1022 0.161819 # Percentage of cache occupancy per task id 2685system.l2c.tags.occ_task_id_percent::1023 0.003876 # Percentage of cache occupancy per task id 2686system.l2c.tags.occ_task_id_percent::1024 0.774124 # Percentage of cache occupancy per task id 2687system.l2c.tags.tag_accesses 80901066 # Number of tag accesses 2688system.l2c.tags.data_accesses 80901066 # Number of data accesses 2689system.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 2690system.l2c.WritebackDirty_hits::writebacks 2828973 # number of WritebackDirty hits 2691system.l2c.WritebackDirty_hits::total 2828973 # number of WritebackDirty hits 2692system.l2c.UpgradeReq_hits::cpu0.data 204859 # number of UpgradeReq hits 2693system.l2c.UpgradeReq_hits::cpu1.data 171268 # number of UpgradeReq hits 2694system.l2c.UpgradeReq_hits::total 376127 # number of UpgradeReq hits 2695system.l2c.SCUpgradeReq_hits::cpu0.data 49678 # number of SCUpgradeReq hits 2696system.l2c.SCUpgradeReq_hits::cpu1.data 57164 # number of SCUpgradeReq hits 2697system.l2c.SCUpgradeReq_hits::total 106842 # number of SCUpgradeReq hits 2698system.l2c.ReadExReq_hits::cpu0.data 57243 # number of ReadExReq hits 2699system.l2c.ReadExReq_hits::cpu1.data 53868 # number of ReadExReq hits 2700system.l2c.ReadExReq_hits::total 111111 # number of ReadExReq hits 2701system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12667 # number of ReadSharedReq hits 2702system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5625 # number of ReadSharedReq hits 2703system.l2c.ReadSharedReq_hits::cpu0.inst 610867 # number of ReadSharedReq hits 2704system.l2c.ReadSharedReq_hits::cpu0.data 589040 # number of ReadSharedReq hits 2705system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292600 # number of ReadSharedReq hits 2706system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12537 # number of ReadSharedReq hits 2707system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4791 # number of ReadSharedReq hits 2708system.l2c.ReadSharedReq_hits::cpu1.inst 678625 # number of ReadSharedReq hits 2709system.l2c.ReadSharedReq_hits::cpu1.data 607071 # number of ReadSharedReq hits 2710system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 308630 # number of ReadSharedReq hits 2711system.l2c.ReadSharedReq_hits::total 3122453 # number of ReadSharedReq hits 2712system.l2c.InvalidateReq_hits::cpu0.data 131047 # number of InvalidateReq hits 2713system.l2c.InvalidateReq_hits::cpu1.data 131317 # number of InvalidateReq hits 2714system.l2c.InvalidateReq_hits::total 262364 # number of InvalidateReq hits 2715system.l2c.demand_hits::cpu0.dtb.walker 12667 # number of demand (read+write) hits 2716system.l2c.demand_hits::cpu0.itb.walker 5625 # number of demand (read+write) hits 2717system.l2c.demand_hits::cpu0.inst 610867 # number of demand (read+write) hits 2718system.l2c.demand_hits::cpu0.data 646283 # number of demand (read+write) hits 2719system.l2c.demand_hits::cpu0.l2cache.prefetcher 292600 # number of demand (read+write) hits 2720system.l2c.demand_hits::cpu1.dtb.walker 12537 # number of demand (read+write) hits 2721system.l2c.demand_hits::cpu1.itb.walker 4791 # number of demand (read+write) hits 2722system.l2c.demand_hits::cpu1.inst 678625 # number of demand (read+write) hits 2723system.l2c.demand_hits::cpu1.data 660939 # number of demand (read+write) hits 2724system.l2c.demand_hits::cpu1.l2cache.prefetcher 308630 # number of demand (read+write) hits 2725system.l2c.demand_hits::total 3233564 # number of demand (read+write) hits 2726system.l2c.overall_hits::cpu0.dtb.walker 12667 # number of overall hits 2727system.l2c.overall_hits::cpu0.itb.walker 5625 # number of overall hits 2728system.l2c.overall_hits::cpu0.inst 610867 # number of overall hits 2729system.l2c.overall_hits::cpu0.data 646283 # number of overall hits 2730system.l2c.overall_hits::cpu0.l2cache.prefetcher 292600 # number of overall hits 2731system.l2c.overall_hits::cpu1.dtb.walker 12537 # number of overall hits 2732system.l2c.overall_hits::cpu1.itb.walker 4791 # number of overall hits 2733system.l2c.overall_hits::cpu1.inst 678625 # number of overall hits 2734system.l2c.overall_hits::cpu1.data 660939 # number of overall hits 2735system.l2c.overall_hits::cpu1.l2cache.prefetcher 308630 # number of overall hits 2736system.l2c.overall_hits::total 3233564 # number of overall hits 2737system.l2c.UpgradeReq_misses::cpu0.data 21060 # number of UpgradeReq misses 2738system.l2c.UpgradeReq_misses::cpu1.data 26656 # number of UpgradeReq misses 2739system.l2c.UpgradeReq_misses::total 47716 # number of UpgradeReq misses 2740system.l2c.SCUpgradeReq_misses::cpu0.data 518 # number of SCUpgradeReq misses 2741system.l2c.SCUpgradeReq_misses::cpu1.data 636 # number of SCUpgradeReq misses 2742system.l2c.SCUpgradeReq_misses::total 1154 # number of SCUpgradeReq misses 2743system.l2c.ReadExReq_misses::cpu0.data 76722 # number of ReadExReq misses 2744system.l2c.ReadExReq_misses::cpu1.data 60050 # number of ReadExReq misses 2745system.l2c.ReadExReq_misses::total 136772 # number of ReadExReq misses 2746system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq misses 2747system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1415 # number of ReadSharedReq misses 2748system.l2c.ReadSharedReq_misses::cpu0.inst 72156 # number of ReadSharedReq misses 2749system.l2c.ReadSharedReq_misses::cpu0.data 133347 # number of ReadSharedReq misses 2750system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq misses 2751system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq misses 2752system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2459 # number of ReadSharedReq misses 2753system.l2c.ReadSharedReq_misses::cpu1.inst 61640 # number of ReadSharedReq misses 2754system.l2c.ReadSharedReq_misses::cpu1.data 144790 # number of ReadSharedReq misses 2755system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq misses 2756system.l2c.ReadSharedReq_misses::total 900362 # number of ReadSharedReq misses 2757system.l2c.InvalidateReq_misses::cpu0.data 438466 # number of InvalidateReq misses 2758system.l2c.InvalidateReq_misses::cpu1.data 125863 # number of InvalidateReq misses 2759system.l2c.InvalidateReq_misses::total 564329 # number of InvalidateReq misses 2760system.l2c.demand_misses::cpu0.dtb.walker 1834 # number of demand (read+write) misses 2761system.l2c.demand_misses::cpu0.itb.walker 1415 # number of demand (read+write) misses 2762system.l2c.demand_misses::cpu0.inst 72156 # number of demand (read+write) misses 2763system.l2c.demand_misses::cpu0.data 210069 # number of demand (read+write) misses 2764system.l2c.demand_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) misses 2765system.l2c.demand_misses::cpu1.dtb.walker 2590 # number of demand (read+write) misses 2766system.l2c.demand_misses::cpu1.itb.walker 2459 # number of demand (read+write) misses 2767system.l2c.demand_misses::cpu1.inst 61640 # number of demand (read+write) misses 2768system.l2c.demand_misses::cpu1.data 204840 # number of demand (read+write) misses 2769system.l2c.demand_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) misses 2770system.l2c.demand_misses::total 1037134 # number of demand (read+write) misses 2771system.l2c.overall_misses::cpu0.dtb.walker 1834 # number of overall misses 2772system.l2c.overall_misses::cpu0.itb.walker 1415 # number of overall misses 2773system.l2c.overall_misses::cpu0.inst 72156 # number of overall misses 2774system.l2c.overall_misses::cpu0.data 210069 # number of overall misses 2775system.l2c.overall_misses::cpu0.l2cache.prefetcher 250233 # number of overall misses 2776system.l2c.overall_misses::cpu1.dtb.walker 2590 # number of overall misses 2777system.l2c.overall_misses::cpu1.itb.walker 2459 # number of overall misses 2778system.l2c.overall_misses::cpu1.inst 61640 # number of overall misses 2779system.l2c.overall_misses::cpu1.data 204840 # number of overall misses 2780system.l2c.overall_misses::cpu1.l2cache.prefetcher 229898 # number of overall misses 2781system.l2c.overall_misses::total 1037134 # number of overall misses 2782system.l2c.UpgradeReq_miss_latency::cpu0.data 165743500 # number of UpgradeReq miss cycles 2783system.l2c.UpgradeReq_miss_latency::cpu1.data 162277500 # number of UpgradeReq miss cycles 2784system.l2c.UpgradeReq_miss_latency::total 328021000 # number of UpgradeReq miss cycles 2785system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8669000 # number of SCUpgradeReq miss cycles 2786system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8803000 # number of SCUpgradeReq miss cycles 2787system.l2c.SCUpgradeReq_miss_latency::total 17472000 # number of SCUpgradeReq miss cycles 2788system.l2c.ReadExReq_miss_latency::cpu0.data 7005748000 # number of ReadExReq miss cycles 2789system.l2c.ReadExReq_miss_latency::cpu1.data 5240435998 # number of ReadExReq miss cycles 2790system.l2c.ReadExReq_miss_latency::total 12246183998 # number of ReadExReq miss cycles 2791system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 169372000 # number of ReadSharedReq miss cycles 2792system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 128340500 # number of ReadSharedReq miss cycles 2793system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6167992000 # number of ReadSharedReq miss cycles 2794system.l2c.ReadSharedReq_miss_latency::cpu0.data 12302035500 # number of ReadSharedReq miss cycles 2795system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of ReadSharedReq miss cycles 2796system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 231186000 # number of ReadSharedReq miss cycles 2797system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 216219500 # number of ReadSharedReq miss cycles 2798system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5316209000 # number of ReadSharedReq miss cycles 2799system.l2c.ReadSharedReq_miss_latency::cpu1.data 13039902500 # number of ReadSharedReq miss cycles 2800system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of ReadSharedReq miss cycles 2801system.l2c.ReadSharedReq_miss_latency::total 99287989218 # number of ReadSharedReq miss cycles 2802system.l2c.InvalidateReq_miss_latency::cpu0.data 31523000 # number of InvalidateReq miss cycles 2803system.l2c.InvalidateReq_miss_latency::cpu1.data 29313000 # number of InvalidateReq miss cycles 2804system.l2c.InvalidateReq_miss_latency::total 60836000 # number of InvalidateReq miss cycles 2805system.l2c.demand_miss_latency::cpu0.dtb.walker 169372000 # number of demand (read+write) miss cycles 2806system.l2c.demand_miss_latency::cpu0.itb.walker 128340500 # number of demand (read+write) miss cycles 2807system.l2c.demand_miss_latency::cpu0.inst 6167992000 # number of demand (read+write) miss cycles 2808system.l2c.demand_miss_latency::cpu0.data 19307783500 # number of demand (read+write) miss cycles 2809system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of demand (read+write) miss cycles 2810system.l2c.demand_miss_latency::cpu1.dtb.walker 231186000 # number of demand (read+write) miss cycles 2811system.l2c.demand_miss_latency::cpu1.itb.walker 216219500 # number of demand (read+write) miss cycles 2812system.l2c.demand_miss_latency::cpu1.inst 5316209000 # number of demand (read+write) miss cycles 2813system.l2c.demand_miss_latency::cpu1.data 18280338498 # number of demand (read+write) miss cycles 2814system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of demand (read+write) miss cycles 2815system.l2c.demand_miss_latency::total 111534173216 # number of demand (read+write) miss cycles 2816system.l2c.overall_miss_latency::cpu0.dtb.walker 169372000 # number of overall miss cycles 2817system.l2c.overall_miss_latency::cpu0.itb.walker 128340500 # number of overall miss cycles 2818system.l2c.overall_miss_latency::cpu0.inst 6167992000 # number of overall miss cycles 2819system.l2c.overall_miss_latency::cpu0.data 19307783500 # number of overall miss cycles 2820system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of overall miss cycles 2821system.l2c.overall_miss_latency::cpu1.dtb.walker 231186000 # number of overall miss cycles 2822system.l2c.overall_miss_latency::cpu1.itb.walker 216219500 # number of overall miss cycles 2823system.l2c.overall_miss_latency::cpu1.inst 5316209000 # number of overall miss cycles 2824system.l2c.overall_miss_latency::cpu1.data 18280338498 # number of overall miss cycles 2825system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of overall miss cycles 2826system.l2c.overall_miss_latency::total 111534173216 # number of overall miss cycles 2827system.l2c.WritebackDirty_accesses::writebacks 2828973 # number of WritebackDirty accesses(hits+misses) 2828system.l2c.WritebackDirty_accesses::total 2828973 # number of WritebackDirty accesses(hits+misses) 2829system.l2c.UpgradeReq_accesses::cpu0.data 225919 # number of UpgradeReq accesses(hits+misses) 2830system.l2c.UpgradeReq_accesses::cpu1.data 197924 # number of UpgradeReq accesses(hits+misses) 2831system.l2c.UpgradeReq_accesses::total 423843 # number of UpgradeReq accesses(hits+misses) 2832system.l2c.SCUpgradeReq_accesses::cpu0.data 50196 # number of SCUpgradeReq accesses(hits+misses) 2833system.l2c.SCUpgradeReq_accesses::cpu1.data 57800 # number of SCUpgradeReq accesses(hits+misses) 2834system.l2c.SCUpgradeReq_accesses::total 107996 # number of SCUpgradeReq accesses(hits+misses) 2835system.l2c.ReadExReq_accesses::cpu0.data 133965 # number of ReadExReq accesses(hits+misses) 2836system.l2c.ReadExReq_accesses::cpu1.data 113918 # number of ReadExReq accesses(hits+misses) 2837system.l2c.ReadExReq_accesses::total 247883 # number of ReadExReq accesses(hits+misses) 2838system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14501 # number of ReadSharedReq accesses(hits+misses) 2839system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7040 # number of ReadSharedReq accesses(hits+misses) 2840system.l2c.ReadSharedReq_accesses::cpu0.inst 683023 # number of ReadSharedReq accesses(hits+misses) 2841system.l2c.ReadSharedReq_accesses::cpu0.data 722387 # number of ReadSharedReq accesses(hits+misses) 2842system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 542833 # number of ReadSharedReq accesses(hits+misses) 2843system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15127 # number of ReadSharedReq accesses(hits+misses) 2844system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7250 # number of ReadSharedReq accesses(hits+misses) 2845system.l2c.ReadSharedReq_accesses::cpu1.inst 740265 # number of ReadSharedReq accesses(hits+misses) 2846system.l2c.ReadSharedReq_accesses::cpu1.data 751861 # number of ReadSharedReq accesses(hits+misses) 2847system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 538528 # number of ReadSharedReq accesses(hits+misses) 2848system.l2c.ReadSharedReq_accesses::total 4022815 # number of ReadSharedReq accesses(hits+misses) 2849system.l2c.InvalidateReq_accesses::cpu0.data 569513 # number of InvalidateReq accesses(hits+misses) 2850system.l2c.InvalidateReq_accesses::cpu1.data 257180 # number of InvalidateReq accesses(hits+misses) 2851system.l2c.InvalidateReq_accesses::total 826693 # number of InvalidateReq accesses(hits+misses) 2852system.l2c.demand_accesses::cpu0.dtb.walker 14501 # number of demand (read+write) accesses 2853system.l2c.demand_accesses::cpu0.itb.walker 7040 # number of demand (read+write) accesses 2854system.l2c.demand_accesses::cpu0.inst 683023 # number of demand (read+write) accesses 2855system.l2c.demand_accesses::cpu0.data 856352 # number of demand (read+write) accesses 2856system.l2c.demand_accesses::cpu0.l2cache.prefetcher 542833 # number of demand (read+write) accesses 2857system.l2c.demand_accesses::cpu1.dtb.walker 15127 # number of demand (read+write) accesses 2858system.l2c.demand_accesses::cpu1.itb.walker 7250 # number of demand (read+write) accesses 2859system.l2c.demand_accesses::cpu1.inst 740265 # number of demand (read+write) accesses 2860system.l2c.demand_accesses::cpu1.data 865779 # number of demand (read+write) accesses 2861system.l2c.demand_accesses::cpu1.l2cache.prefetcher 538528 # number of demand (read+write) accesses 2862system.l2c.demand_accesses::total 4270698 # number of demand (read+write) accesses 2863system.l2c.overall_accesses::cpu0.dtb.walker 14501 # number of overall (read+write) accesses 2864system.l2c.overall_accesses::cpu0.itb.walker 7040 # number of overall (read+write) accesses 2865system.l2c.overall_accesses::cpu0.inst 683023 # number of overall (read+write) accesses 2866system.l2c.overall_accesses::cpu0.data 856352 # number of overall (read+write) accesses 2867system.l2c.overall_accesses::cpu0.l2cache.prefetcher 542833 # number of overall (read+write) accesses 2868system.l2c.overall_accesses::cpu1.dtb.walker 15127 # number of overall (read+write) accesses 2869system.l2c.overall_accesses::cpu1.itb.walker 7250 # number of overall (read+write) accesses 2870system.l2c.overall_accesses::cpu1.inst 740265 # number of overall (read+write) accesses 2871system.l2c.overall_accesses::cpu1.data 865779 # number of overall (read+write) accesses 2872system.l2c.overall_accesses::cpu1.l2cache.prefetcher 538528 # number of overall (read+write) accesses 2873system.l2c.overall_accesses::total 4270698 # number of overall (read+write) accesses 2874system.l2c.UpgradeReq_miss_rate::cpu0.data 0.093219 # miss rate for UpgradeReq accesses 2875system.l2c.UpgradeReq_miss_rate::cpu1.data 0.134678 # miss rate for UpgradeReq accesses 2876system.l2c.UpgradeReq_miss_rate::total 0.112579 # miss rate for UpgradeReq accesses 2877system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010320 # miss rate for SCUpgradeReq accesses 2878system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011003 # miss rate for SCUpgradeReq accesses 2879system.l2c.SCUpgradeReq_miss_rate::total 0.010686 # miss rate for SCUpgradeReq accesses 2880system.l2c.ReadExReq_miss_rate::cpu0.data 0.572702 # miss rate for ReadExReq accesses 2881system.l2c.ReadExReq_miss_rate::cpu1.data 0.527134 # miss rate for ReadExReq accesses 2882system.l2c.ReadExReq_miss_rate::total 0.551760 # miss rate for ReadExReq accesses 2883system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for ReadSharedReq accesses 2884system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.200994 # miss rate for ReadSharedReq accesses 2885system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.105642 # miss rate for ReadSharedReq accesses 2886system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.184592 # miss rate for ReadSharedReq accesses 2887system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for ReadSharedReq accesses 2888system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for ReadSharedReq accesses 2889system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339172 # miss rate for ReadSharedReq accesses 2890system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.083267 # miss rate for ReadSharedReq accesses 2891system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.192575 # miss rate for ReadSharedReq accesses 2892system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for ReadSharedReq accesses 2893system.l2c.ReadSharedReq_miss_rate::total 0.223814 # miss rate for ReadSharedReq accesses 2894system.l2c.InvalidateReq_miss_rate::cpu0.data 0.769896 # miss rate for InvalidateReq accesses 2895system.l2c.InvalidateReq_miss_rate::cpu1.data 0.489397 # miss rate for InvalidateReq accesses 2896system.l2c.InvalidateReq_miss_rate::total 0.682634 # miss rate for InvalidateReq accesses 2897system.l2c.demand_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for demand accesses 2898system.l2c.demand_miss_rate::cpu0.itb.walker 0.200994 # miss rate for demand accesses 2899system.l2c.demand_miss_rate::cpu0.inst 0.105642 # miss rate for demand accesses 2900system.l2c.demand_miss_rate::cpu0.data 0.245307 # miss rate for demand accesses 2901system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for demand accesses 2902system.l2c.demand_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for demand accesses 2903system.l2c.demand_miss_rate::cpu1.itb.walker 0.339172 # miss rate for demand accesses 2904system.l2c.demand_miss_rate::cpu1.inst 0.083267 # miss rate for demand accesses 2905system.l2c.demand_miss_rate::cpu1.data 0.236596 # miss rate for demand accesses 2906system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for demand accesses 2907system.l2c.demand_miss_rate::total 0.242849 # miss rate for demand accesses 2908system.l2c.overall_miss_rate::cpu0.dtb.walker 0.126474 # miss rate for overall accesses 2909system.l2c.overall_miss_rate::cpu0.itb.walker 0.200994 # miss rate for overall accesses 2910system.l2c.overall_miss_rate::cpu0.inst 0.105642 # miss rate for overall accesses 2911system.l2c.overall_miss_rate::cpu0.data 0.245307 # miss rate for overall accesses 2912system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.460976 # miss rate for overall accesses 2913system.l2c.overall_miss_rate::cpu1.dtb.walker 0.171217 # miss rate for overall accesses 2914system.l2c.overall_miss_rate::cpu1.itb.walker 0.339172 # miss rate for overall accesses 2915system.l2c.overall_miss_rate::cpu1.inst 0.083267 # miss rate for overall accesses 2916system.l2c.overall_miss_rate::cpu1.data 0.236596 # miss rate for overall accesses 2917system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.426901 # miss rate for overall accesses 2918system.l2c.overall_miss_rate::total 0.242849 # miss rate for overall accesses 2919system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7870.061728 # average UpgradeReq miss latency 2920system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6087.841387 # average UpgradeReq miss latency 2921system.l2c.UpgradeReq_avg_miss_latency::total 6874.444631 # average UpgradeReq miss latency 2922system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16735.521236 # average SCUpgradeReq miss latency 2923system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13841.194969 # average SCUpgradeReq miss latency 2924system.l2c.SCUpgradeReq_avg_miss_latency::total 15140.381282 # average SCUpgradeReq miss latency 2925system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91313.417273 # average ReadExReq miss latency 2926system.l2c.ReadExReq_avg_miss_latency::cpu1.data 87267.876736 # average ReadExReq miss latency 2927system.l2c.ReadExReq_avg_miss_latency::total 89537.215205 # average ReadExReq miss latency 2928system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average ReadSharedReq miss latency 2929system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90700 # average ReadSharedReq miss latency 2930system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85481.345973 # average ReadSharedReq miss latency 2931system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92255.810029 # average ReadSharedReq miss latency 2932system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average ReadSharedReq miss latency 2933system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average ReadSharedReq miss latency 2934system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 87929.849532 # average ReadSharedReq miss latency 2935system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86246.090201 # average ReadSharedReq miss latency 2936system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90060.794944 # average ReadSharedReq miss latency 2937system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average ReadSharedReq miss latency 2938system.l2c.ReadSharedReq_avg_miss_latency::total 110275.632710 # average ReadSharedReq miss latency 2939system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 71.893830 # average InvalidateReq miss latency 2940system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 232.896085 # average InvalidateReq miss latency 2941system.l2c.InvalidateReq_avg_miss_latency::total 107.802364 # average InvalidateReq miss latency 2942system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average overall miss latency 2943system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90700 # average overall miss latency 2944system.l2c.demand_avg_miss_latency::cpu0.inst 85481.345973 # average overall miss latency 2945system.l2c.demand_avg_miss_latency::cpu0.data 91911.626656 # average overall miss latency 2946system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average overall miss latency 2947system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average overall miss latency 2948system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87929.849532 # average overall miss latency 2949system.l2c.demand_avg_miss_latency::cpu1.inst 86246.090201 # average overall miss latency 2950system.l2c.demand_avg_miss_latency::cpu1.data 89242.035237 # average overall miss latency 2951system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average overall miss latency 2952system.l2c.demand_avg_miss_latency::total 107540.754826 # average overall miss latency 2953system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92351.145038 # average overall miss latency 2954system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90700 # average overall miss latency 2955system.l2c.overall_avg_miss_latency::cpu0.inst 85481.345973 # average overall miss latency 2956system.l2c.overall_avg_miss_latency::cpu0.data 91911.626656 # average overall miss latency 2957system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600 # average overall miss latency 2958system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89261.003861 # average overall miss latency 2959system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87929.849532 # average overall miss latency 2960system.l2c.overall_avg_miss_latency::cpu1.inst 86246.090201 # average overall miss latency 2961system.l2c.overall_avg_miss_latency::cpu1.data 89242.035237 # average overall miss latency 2962system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527 # average overall miss latency 2963system.l2c.overall_avg_miss_latency::total 107540.754826 # average overall miss latency 2964system.l2c.blocked_cycles::no_mshrs 751 # number of cycles access was blocked 2965system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2966system.l2c.blocked::no_mshrs 17 # number of cycles access was blocked 2967system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2968system.l2c.avg_blocked_cycles::no_mshrs 44.176471 # average number of cycles each access was blocked 2969system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2970system.l2c.writebacks::writebacks 1165859 # number of writebacks 2971system.l2c.writebacks::total 1165859 # number of writebacks 2972system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 169 # number of ReadSharedReq MSHR hits 2973system.l2c.ReadSharedReq_mshr_hits::cpu0.data 21 # number of ReadSharedReq MSHR hits 2974system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 110 # number of ReadSharedReq MSHR hits 2975system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2976system.l2c.ReadSharedReq_mshr_hits::total 317 # number of ReadSharedReq MSHR hits 2977system.l2c.demand_mshr_hits::cpu0.inst 169 # number of demand (read+write) MSHR hits 2978system.l2c.demand_mshr_hits::cpu0.data 21 # number of demand (read+write) MSHR hits 2979system.l2c.demand_mshr_hits::cpu1.inst 110 # number of demand (read+write) MSHR hits 2980system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 2981system.l2c.demand_mshr_hits::total 317 # number of demand (read+write) MSHR hits 2982system.l2c.overall_mshr_hits::cpu0.inst 169 # number of overall MSHR hits 2983system.l2c.overall_mshr_hits::cpu0.data 21 # number of overall MSHR hits 2984system.l2c.overall_mshr_hits::cpu1.inst 110 # number of overall MSHR hits 2985system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 2986system.l2c.overall_mshr_hits::total 317 # number of overall MSHR hits 2987system.l2c.CleanEvict_mshr_misses::writebacks 72347 # number of CleanEvict MSHR misses 2988system.l2c.CleanEvict_mshr_misses::total 72347 # number of CleanEvict MSHR misses 2989system.l2c.UpgradeReq_mshr_misses::cpu0.data 21060 # number of UpgradeReq MSHR misses 2990system.l2c.UpgradeReq_mshr_misses::cpu1.data 26656 # number of UpgradeReq MSHR misses 2991system.l2c.UpgradeReq_mshr_misses::total 47716 # number of UpgradeReq MSHR misses 2992system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 518 # number of SCUpgradeReq MSHR misses 2993system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 636 # number of SCUpgradeReq MSHR misses 2994system.l2c.SCUpgradeReq_mshr_misses::total 1154 # number of SCUpgradeReq MSHR misses 2995system.l2c.ReadExReq_mshr_misses::cpu0.data 76722 # number of ReadExReq MSHR misses 2996system.l2c.ReadExReq_mshr_misses::cpu1.data 60050 # number of ReadExReq MSHR misses 2997system.l2c.ReadExReq_mshr_misses::total 136772 # number of ReadExReq MSHR misses 2998system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq MSHR misses 2999system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1415 # number of ReadSharedReq MSHR misses 3000system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 71987 # number of ReadSharedReq MSHR misses 3001system.l2c.ReadSharedReq_mshr_misses::cpu0.data 133326 # number of ReadSharedReq MSHR misses 3002system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq MSHR misses 3003system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq MSHR misses 3004system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2459 # number of ReadSharedReq MSHR misses 3005system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 61530 # number of ReadSharedReq MSHR misses 3006system.l2c.ReadSharedReq_mshr_misses::cpu1.data 144773 # number of ReadSharedReq MSHR misses 3007system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq MSHR misses 3008system.l2c.ReadSharedReq_mshr_misses::total 900045 # number of ReadSharedReq MSHR misses 3009system.l2c.InvalidateReq_mshr_misses::cpu0.data 438466 # number of InvalidateReq MSHR misses 3010system.l2c.InvalidateReq_mshr_misses::cpu1.data 125863 # number of InvalidateReq MSHR misses 3011system.l2c.InvalidateReq_mshr_misses::total 564329 # number of InvalidateReq MSHR misses 3012system.l2c.demand_mshr_misses::cpu0.dtb.walker 1834 # number of demand (read+write) MSHR misses 3013system.l2c.demand_mshr_misses::cpu0.itb.walker 1415 # number of demand (read+write) MSHR misses 3014system.l2c.demand_mshr_misses::cpu0.inst 71987 # number of demand (read+write) MSHR misses 3015system.l2c.demand_mshr_misses::cpu0.data 210048 # number of demand (read+write) MSHR misses 3016system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) MSHR misses 3017system.l2c.demand_mshr_misses::cpu1.dtb.walker 2590 # number of demand (read+write) MSHR misses 3018system.l2c.demand_mshr_misses::cpu1.itb.walker 2459 # number of demand (read+write) MSHR misses 3019system.l2c.demand_mshr_misses::cpu1.inst 61530 # number of demand (read+write) MSHR misses 3020system.l2c.demand_mshr_misses::cpu1.data 204823 # number of demand (read+write) MSHR misses 3021system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) MSHR misses 3022system.l2c.demand_mshr_misses::total 1036817 # number of demand (read+write) MSHR misses 3023system.l2c.overall_mshr_misses::cpu0.dtb.walker 1834 # number of overall MSHR misses 3024system.l2c.overall_mshr_misses::cpu0.itb.walker 1415 # number of overall MSHR misses 3025system.l2c.overall_mshr_misses::cpu0.inst 71987 # number of overall MSHR misses 3026system.l2c.overall_mshr_misses::cpu0.data 210048 # number of overall MSHR misses 3027system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 250233 # number of overall MSHR misses 3028system.l2c.overall_mshr_misses::cpu1.dtb.walker 2590 # number of overall MSHR misses 3029system.l2c.overall_mshr_misses::cpu1.itb.walker 2459 # number of overall MSHR misses 3030system.l2c.overall_mshr_misses::cpu1.inst 61530 # number of overall MSHR misses 3031system.l2c.overall_mshr_misses::cpu1.data 204823 # number of overall MSHR misses 3032system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 229898 # number of overall MSHR misses 3033system.l2c.overall_mshr_misses::total 1036817 # number of overall MSHR misses 3034system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 3035system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable 3036system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 3037system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17606 # number of ReadReq MSHR uncacheable 3038system.l2c.ReadReq_mshr_uncacheable::total 90635 # number of ReadReq MSHR uncacheable 3039system.l2c.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable 3040system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable 3041system.l2c.WriteReq_mshr_uncacheable::total 38128 # number of WriteReq MSHR uncacheable 3042system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 3043system.l2c.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses 3044system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 3045system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33459 # number of overall MSHR uncacheable misses 3046system.l2c.overall_mshr_uncacheable_misses::total 128763 # number of overall MSHR uncacheable misses 3047system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 428042501 # number of UpgradeReq MSHR miss cycles 3048system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 541214000 # number of UpgradeReq MSHR miss cycles 3049system.l2c.UpgradeReq_mshr_miss_latency::total 969256501 # number of UpgradeReq MSHR miss cycles 3050system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12312000 # number of SCUpgradeReq MSHR miss cycles 3051system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15177000 # number of SCUpgradeReq MSHR miss cycles 3052system.l2c.SCUpgradeReq_mshr_miss_latency::total 27489000 # number of SCUpgradeReq MSHR miss cycles 3053system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6238487583 # number of ReadExReq MSHR miss cycles 3054system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4639903563 # number of ReadExReq MSHR miss cycles 3055system.l2c.ReadExReq_mshr_miss_latency::total 10878391146 # number of ReadExReq MSHR miss cycles 3056system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of ReadSharedReq MSHR miss cycles 3057system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 114190001 # number of ReadSharedReq MSHR miss cycles 3058system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5436084068 # number of ReadSharedReq MSHR miss cycles 3059system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10966992245 # number of ReadSharedReq MSHR miss cycles 3060system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of ReadSharedReq MSHR miss cycles 3061system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of ReadSharedReq MSHR miss cycles 3062system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 191629001 # number of ReadSharedReq MSHR miss cycles 3063system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4693018541 # number of ReadSharedReq MSHR miss cycles 3064system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11590786168 # number of ReadSharedReq MSHR miss cycles 3065system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of ReadSharedReq MSHR miss cycles 3066system.l2c.ReadSharedReq_mshr_miss_latency::total 90264026622 # number of ReadSharedReq MSHR miss cycles 3067system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9157417500 # number of InvalidateReq MSHR miss cycles 3068system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2543921000 # number of InvalidateReq MSHR miss cycles 3069system.l2c.InvalidateReq_mshr_miss_latency::total 11701338500 # number of InvalidateReq MSHR miss cycles 3070system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of demand (read+write) MSHR miss cycles 3071system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 114190001 # number of demand (read+write) MSHR miss cycles 3072system.l2c.demand_mshr_miss_latency::cpu0.inst 5436084068 # number of demand (read+write) MSHR miss cycles 3073system.l2c.demand_mshr_miss_latency::cpu0.data 17205479828 # number of demand (read+write) MSHR miss cycles 3074system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of demand (read+write) MSHR miss cycles 3075system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of demand (read+write) MSHR miss cycles 3076system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191629001 # number of demand (read+write) MSHR miss cycles 3077system.l2c.demand_mshr_miss_latency::cpu1.inst 4693018541 # number of demand (read+write) MSHR miss cycles 3078system.l2c.demand_mshr_miss_latency::cpu1.data 16230689731 # number of demand (read+write) MSHR miss cycles 3079system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of demand (read+write) MSHR miss cycles 3080system.l2c.demand_mshr_miss_latency::total 101142417768 # number of demand (read+write) MSHR miss cycles 3081system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of overall MSHR miss cycles 3082system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 114190001 # number of overall MSHR miss cycles 3083system.l2c.overall_mshr_miss_latency::cpu0.inst 5436084068 # number of overall MSHR miss cycles 3084system.l2c.overall_mshr_miss_latency::cpu0.data 17205479828 # number of overall MSHR miss cycles 3085system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of overall MSHR miss cycles 3086system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of overall MSHR miss cycles 3087system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191629001 # number of overall MSHR miss cycles 3088system.l2c.overall_mshr_miss_latency::cpu1.inst 4693018541 # number of overall MSHR miss cycles 3089system.l2c.overall_mshr_miss_latency::cpu1.data 16230689731 # number of overall MSHR miss cycles 3090system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of overall MSHR miss cycles 3091system.l2c.overall_mshr_miss_latency::total 101142417768 # number of overall MSHR miss cycles 3092system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of ReadReq MSHR uncacheable cycles 3093system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3477966008 # number of ReadReq MSHR uncacheable cycles 3094system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6312000 # number of ReadReq MSHR uncacheable cycles 3095system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2478199000 # number of ReadReq MSHR uncacheable cycles 3096system.l2c.ReadReq_mshr_uncacheable_latency::total 9282561008 # number of ReadReq MSHR uncacheable cycles 3097system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles 3098system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3477966008 # number of overall MSHR uncacheable cycles 3099system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6312000 # number of overall MSHR uncacheable cycles 3100system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2478199000 # number of overall MSHR uncacheable cycles 3101system.l2c.overall_mshr_uncacheable_latency::total 9282561008 # number of overall MSHR uncacheable cycles 3102system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3103system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3104system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.093219 # mshr miss rate for UpgradeReq accesses 3105system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.134678 # mshr miss rate for UpgradeReq accesses 3106system.l2c.UpgradeReq_mshr_miss_rate::total 0.112579 # mshr miss rate for UpgradeReq accesses 3107system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010320 # mshr miss rate for SCUpgradeReq accesses 3108system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011003 # mshr miss rate for SCUpgradeReq accesses 3109system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.010686 # mshr miss rate for SCUpgradeReq accesses 3110system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572702 # mshr miss rate for ReadExReq accesses 3111system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.527134 # mshr miss rate for ReadExReq accesses 3112system.l2c.ReadExReq_mshr_miss_rate::total 0.551760 # mshr miss rate for ReadExReq accesses 3113system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for ReadSharedReq accesses 3114system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for ReadSharedReq accesses 3115system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for ReadSharedReq accesses 3116system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184563 # mshr miss rate for ReadSharedReq accesses 3117system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for ReadSharedReq accesses 3118system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for ReadSharedReq accesses 3119system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for ReadSharedReq accesses 3120system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for ReadSharedReq accesses 3121system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192553 # mshr miss rate for ReadSharedReq accesses 3122system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for ReadSharedReq accesses 3123system.l2c.ReadSharedReq_mshr_miss_rate::total 0.223735 # mshr miss rate for ReadSharedReq accesses 3124system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.769896 # mshr miss rate for InvalidateReq accesses 3125system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489397 # mshr miss rate for InvalidateReq accesses 3126system.l2c.InvalidateReq_mshr_miss_rate::total 0.682634 # mshr miss rate for InvalidateReq accesses 3127system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for demand accesses 3128system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for demand accesses 3129system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for demand accesses 3130system.l2c.demand_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for demand accesses 3131system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for demand accesses 3132system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for demand accesses 3133system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for demand accesses 3134system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for demand accesses 3135system.l2c.demand_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for demand accesses 3136system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for demand accesses 3137system.l2c.demand_mshr_miss_rate::total 0.242775 # mshr miss rate for demand accesses 3138system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for overall accesses 3139system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for overall accesses 3140system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for overall accesses 3141system.l2c.overall_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for overall accesses 3142system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for overall accesses 3143system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for overall accesses 3144system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for overall accesses 3145system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for overall accesses 3146system.l2c.overall_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for overall accesses 3147system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for overall accesses 3148system.l2c.overall_mshr_miss_rate::total 0.242775 # mshr miss rate for overall accesses 3149system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081 # average UpgradeReq mshr miss latency 3150system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459 # average UpgradeReq mshr miss latency 3151system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194 # average UpgradeReq mshr miss latency 3152system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768 # average SCUpgradeReq mshr miss latency 3153system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547 # average SCUpgradeReq mshr miss latency 3154system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917 # average SCUpgradeReq mshr miss latency 3155system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475 # average ReadExReq mshr miss latency 3156system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603 # average ReadExReq mshr miss latency 3157system.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552 # average ReadExReq mshr miss latency 3158system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average ReadSharedReq mshr miss latency 3159system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average ReadSharedReq mshr miss latency 3160system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average ReadSharedReq mshr miss latency 3161system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971 # average ReadSharedReq mshr miss latency 3162system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average ReadSharedReq mshr miss latency 3163system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average ReadSharedReq mshr miss latency 3164system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average ReadSharedReq mshr miss latency 3165system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average ReadSharedReq mshr miss latency 3166system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451 # average ReadSharedReq mshr miss latency 3167system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average ReadSharedReq mshr miss latency 3168system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496 # average ReadSharedReq mshr miss latency 3169system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643 # average InvalidateReq mshr miss latency 3170system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556 # average InvalidateReq mshr miss latency 3171system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685 # average InvalidateReq mshr miss latency 3172system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency 3173system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency 3174system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency 3175system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency 3176system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency 3177system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency 3178system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency 3179system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency 3180system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency 3181system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency 3182system.l2c.demand_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency 3183system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency 3184system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency 3185system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency 3186system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency 3187system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency 3188system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency 3189system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency 3190system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency 3191system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency 3192system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency 3193system.l2c.overall_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency 3194system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency 3195system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615 # average ReadReq mshr uncacheable latency 3196system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average ReadReq mshr uncacheable latency 3197system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417 # average ReadReq mshr uncacheable latency 3198system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217 # average ReadReq mshr uncacheable latency 3199system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency 3200system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285 # average overall mshr uncacheable latency 3201system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average overall mshr uncacheable latency 3202system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396 # average overall mshr uncacheable latency 3203system.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208 # average overall mshr uncacheable latency 3204system.membus.snoop_filter.tot_requests 3909047 # Total number of requests made to the snoop filter. 3205system.membus.snoop_filter.hit_single_requests 2292243 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3206system.membus.snoop_filter.hit_multi_requests 2625 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3207system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3208system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3209system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3210system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3211system.membus.trans_dist::ReadReq 90635 # Transaction distribution 3212system.membus.trans_dist::ReadResp 999620 # Transaction distribution 3213system.membus.trans_dist::WriteReq 38128 # Transaction distribution 3214system.membus.trans_dist::WriteResp 38128 # Transaction distribution 3215system.membus.trans_dist::WritebackDirty 1272553 # Transaction distribution 3216system.membus.trans_dist::CleanEvict 289712 # Transaction distribution 3217system.membus.trans_dist::UpgradeReq 348270 # Transaction distribution 3218system.membus.trans_dist::SCUpgradeReq 267748 # Transaction distribution 3219system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3220system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3221system.membus.trans_dist::ReadExReq 152656 # Transaction distribution 3222system.membus.trans_dist::ReadExResp 136047 # Transaction distribution 3223system.membus.trans_dist::ReadSharedReq 908985 # Transaction distribution 3224system.membus.trans_dist::InvalidateReq 669058 # Transaction distribution 3225system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122572 # Packet count per connected master and slave (bytes) 3226system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 3227system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24944 # Packet count per connected master and slave (bytes) 3228system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4823028 # Packet count per connected master and slave (bytes) 3229system.membus.pkt_count_system.l2c.mem_side::total 4970598 # Packet count per connected master and slave (bytes) 3230system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238389 # Packet count per connected master and slave (bytes) 3231system.membus.pkt_count_system.iocache.mem_side::total 238389 # Packet count per connected master and slave (bytes) 3232system.membus.pkt_count::total 5208987 # Packet count per connected master and slave (bytes) 3233system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155679 # Cumulative packet size per connected master and slave (bytes) 3234system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 3235system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49888 # Cumulative packet size per connected master and slave (bytes) 3236system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144251456 # Cumulative packet size per connected master and slave (bytes) 3237system.membus.pkt_size_system.l2c.mem_side::total 144458411 # Cumulative packet size per connected master and slave (bytes) 3238system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283200 # Cumulative packet size per connected master and slave (bytes) 3239system.membus.pkt_size_system.iocache.mem_side::total 7283200 # Cumulative packet size per connected master and slave (bytes) 3240system.membus.pkt_size::total 151741611 # Cumulative packet size per connected master and slave (bytes) 3241system.membus.snoops 583612 # Total snoops (count) 3242system.membus.snoopTraffic 163584 # Total snoop traffic (bytes) 3243system.membus.snoop_fanout::samples 2475487 # Request fanout histogram 3244system.membus.snoop_fanout::mean 0.012229 # Request fanout histogram 3245system.membus.snoop_fanout::stdev 0.109905 # Request fanout histogram 3246system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3247system.membus.snoop_fanout::0 2445215 98.78% 98.78% # Request fanout histogram 3248system.membus.snoop_fanout::1 30272 1.22% 100.00% # Request fanout histogram 3249system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3250system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3251system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3252system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3253system.membus.snoop_fanout::total 2475487 # Request fanout histogram 3254system.membus.reqLayer0.occupancy 102607988 # Layer occupancy (ticks) 3255system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3256system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 3257system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3258system.membus.reqLayer2.occupancy 20962995 # Layer occupancy (ticks) 3259system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3260system.membus.reqLayer5.occupancy 8793410200 # Layer occupancy (ticks) 3261system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3262system.membus.respLayer2.occupancy 5849158337 # Layer occupancy (ticks) 3263system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3264system.membus.respLayer3.occupancy 45598905 # Layer occupancy (ticks) 3265system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3266system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3267system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3268system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3269system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3270system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3271system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3272system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3273system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3274system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3275system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3276system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3277system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3278system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3279system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3280system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3281system.realview.ethernet.txBytes 966 # Bytes Transmitted 3282system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3283system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3284system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3285system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3286system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3287system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3288system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3289system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3290system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3291system.realview.ethernet.totPackets 3 # Total Packets 3292system.realview.ethernet.totBytes 966 # Total Bytes 3293system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3294system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3295system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3296system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3297system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3298system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3299system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3300system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3301system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3302system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3303system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3304system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3305system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3306system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3307system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3308system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3309system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3310system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3311system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3312system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3313system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3314system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3315system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3316system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3317system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3318system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3319system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3320system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3321system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3322system.realview.ethernet.droppedPackets 0 # number of packets dropped 3323system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3324system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3325system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3326system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3327system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3328system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3329system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3330system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3331system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3332system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3333system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3334system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3335system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3336system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3337system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3338system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3339system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3340system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3341system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3342system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3343system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3344system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3345system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3346system.toL2Bus.snoop_filter.tot_requests 12529275 # Total number of requests made to the snoop filter. 3347system.toL2Bus.snoop_filter.hit_single_requests 6783970 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3348system.toL2Bus.snoop_filter.hit_multi_requests 2045593 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3349system.toL2Bus.snoop_filter.tot_snoops 207524 # Total number of snoops made to the snoop filter. 3350system.toL2Bus.snoop_filter.hit_single_snoops 190768 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3351system.toL2Bus.snoop_filter.hit_multi_snoops 16756 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3352system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states 3353system.toL2Bus.trans_dist::ReadReq 90637 # Transaction distribution 3354system.toL2Bus.trans_dist::ReadResp 4878287 # Transaction distribution 3355system.toL2Bus.trans_dist::WriteReq 38128 # Transaction distribution 3356system.toL2Bus.trans_dist::WriteResp 38128 # Transaction distribution 3357system.toL2Bus.trans_dist::WritebackDirty 3994832 # Transaction distribution 3358system.toL2Bus.trans_dist::CleanEvict 3079472 # Transaction distribution 3359system.toL2Bus.trans_dist::UpgradeReq 721673 # Transaction distribution 3360system.toL2Bus.trans_dist::SCUpgradeReq 374590 # Transaction distribution 3361system.toL2Bus.trans_dist::UpgradeResp 1096263 # Transaction distribution 3362system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution 3363system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 3364system.toL2Bus.trans_dist::ReadExReq 301835 # Transaction distribution 3365system.toL2Bus.trans_dist::ReadExResp 301835 # Transaction distribution 3366system.toL2Bus.trans_dist::ReadSharedReq 4787847 # Transaction distribution 3367system.toL2Bus.trans_dist::InvalidateReq 854297 # Transaction distribution 3368system.toL2Bus.trans_dist::InvalidateResp 826693 # Transaction distribution 3369system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9608901 # Packet count per connected master and slave (bytes) 3370system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8808719 # Packet count per connected master and slave (bytes) 3371system.toL2Bus.pkt_count::total 18417620 # Packet count per connected master and slave (bytes) 3372system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240252134 # Cumulative packet size per connected master and slave (bytes) 3373system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 217815813 # Cumulative packet size per connected master and slave (bytes) 3374system.toL2Bus.pkt_size::total 458067947 # Cumulative packet size per connected master and slave (bytes) 3375system.toL2Bus.snoops 2968837 # Total snoops (count) 3376system.toL2Bus.snoopTraffic 127024720 # Total snoop traffic (bytes) 3377system.toL2Bus.snoop_fanout::samples 8725155 # Request fanout histogram 3378system.toL2Bus.snoop_fanout::mean 0.358566 # Request fanout histogram 3379system.toL2Bus.snoop_fanout::stdev 0.483567 # Request fanout histogram 3380system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3381system.toL2Bus.snoop_fanout::0 5613365 64.34% 64.34% # Request fanout histogram 3382system.toL2Bus.snoop_fanout::1 3095034 35.47% 99.81% # Request fanout histogram 3383system.toL2Bus.snoop_fanout::2 16756 0.19% 100.00% # Request fanout histogram 3384system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3385system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3386system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3387system.toL2Bus.snoop_fanout::total 8725155 # Request fanout histogram 3388system.toL2Bus.reqLayer0.occupancy 9593262018 # Layer occupancy (ticks) 3389system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3390system.toL2Bus.snoopLayer0.occupancy 2632911 # Layer occupancy (ticks) 3391system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3392system.toL2Bus.respLayer0.occupancy 4411209152 # Layer occupancy (ticks) 3393system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3394system.toL2Bus.respLayer1.occupancy 4336941336 # Layer occupancy (ticks) 3395system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3396 3397---------- End Simulation Statistics ---------- 3398