xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.573912                       # Number of seconds simulated
sim_ticks                                47573912126000                       # Number of ticks simulated
final_tick                               47573912126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125865                       # Simulator instruction rate (inst/s)
host_op_rate                                   148024                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6578075559                       # Simulator tick rate (ticks/s)
host_mem_usage                                 723980                       # Number of bytes of host memory used
host_seconds                                  7232.19                       # Real time elapsed on the host
sim_insts                                   910282032                       # Number of instructions simulated
sim_ops                                    1070541696                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       153088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       136640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7678784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         42964232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     17895808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       154176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       129664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3679616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         16152336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     14975872                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        446400                       # Number of bytes read from this memory
system.physmem.bytes_read::total            104366616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7678784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3679616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11358400                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     83323200                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          83343784                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2392                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2135                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            119981                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            671329                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       279622                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2409                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2026                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             57494                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            252393                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       233998                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6975                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1630754                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1301925                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1304499                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3218                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              161407                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              903105                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       376169                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3241                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2726                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               77345                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              339521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       314792                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9383                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2193778                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         161407                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          77345                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             238753                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1751447                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1751880                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1751447                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3218                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2872                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             161407                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             903537                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       376169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3241                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2726                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              77345                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             339521                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       314792                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9383                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3945658                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1630754                       # Number of read requests accepted
system.physmem.writeReqs                      1304499                       # Number of write requests accepted
system.physmem.readBursts                     1630754                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1304499                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                104327040                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     41216                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  83343168                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 104366616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               83343784                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      644                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         221732                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               95834                       # Per bank write bursts
system.physmem.perBankRdBursts::1              103052                       # Per bank write bursts
system.physmem.perBankRdBursts::2               97330                       # Per bank write bursts
system.physmem.perBankRdBursts::3              103782                       # Per bank write bursts
system.physmem.perBankRdBursts::4              100129                       # Per bank write bursts
system.physmem.perBankRdBursts::5              106515                       # Per bank write bursts
system.physmem.perBankRdBursts::6               99389                       # Per bank write bursts
system.physmem.perBankRdBursts::7               99717                       # Per bank write bursts
system.physmem.perBankRdBursts::8               91352                       # Per bank write bursts
system.physmem.perBankRdBursts::9              148680                       # Per bank write bursts
system.physmem.perBankRdBursts::10              90509                       # Per bank write bursts
system.physmem.perBankRdBursts::11              96337                       # Per bank write bursts
system.physmem.perBankRdBursts::12              96747                       # Per bank write bursts
system.physmem.perBankRdBursts::13             106196                       # Per bank write bursts
system.physmem.perBankRdBursts::14              95843                       # Per bank write bursts
system.physmem.perBankRdBursts::15              98698                       # Per bank write bursts
system.physmem.perBankWrBursts::0               79474                       # Per bank write bursts
system.physmem.perBankWrBursts::1               83004                       # Per bank write bursts
system.physmem.perBankWrBursts::2               79696                       # Per bank write bursts
system.physmem.perBankWrBursts::3               83932                       # Per bank write bursts
system.physmem.perBankWrBursts::4               80263                       # Per bank write bursts
system.physmem.perBankWrBursts::5               85902                       # Per bank write bursts
system.physmem.perBankWrBursts::6               82233                       # Per bank write bursts
system.physmem.perBankWrBursts::7               81457                       # Per bank write bursts
system.physmem.perBankWrBursts::8               76873                       # Per bank write bursts
system.physmem.perBankWrBursts::9               82502                       # Per bank write bursts
system.physmem.perBankWrBursts::10              77306                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81622                       # Per bank write bursts
system.physmem.perBankWrBursts::12              79893                       # Per bank write bursts
system.physmem.perBankWrBursts::13              86888                       # Per bank write bursts
system.physmem.perBankWrBursts::14              78601                       # Per bank write bursts
system.physmem.perBankWrBursts::15              82591                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          61                       # Number of times write queue was full causing retry
system.physmem.totGap                    47573910147500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1630724                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1301925                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    998903                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    383381                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     53687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     39143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     33585                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     31320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     28483                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     25807                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     22337                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      5097                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2530                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1505                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1220                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      913                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      542                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      453                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      350                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       81                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    18448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    20938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    44352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    64725                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    69469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    74724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    78159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    81831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    83061                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    84591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    90322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    87643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    87918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    95292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    88789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    82985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    78170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      169                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1008532                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      186.082044                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     114.846498                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     242.592795                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         603416     59.83%     59.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       198742     19.71%     79.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        66381      6.58%     86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35101      3.48%     89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23988      2.38%     91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        15328      1.52%     93.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10269      1.02%     94.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9973      0.99%     95.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        45334      4.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1008532                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         74360                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.921678                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      319.874978                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          74357    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::81920-86015            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           74360                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         74360                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.512601                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.043743                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.433062                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           70224     94.44%     94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1905      2.56%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             313      0.42%     97.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             309      0.42%     97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              95      0.13%     97.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             310      0.42%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             189      0.25%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              82      0.11%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              85      0.11%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             110      0.15%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              46      0.06%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              59      0.08%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             410      0.55%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              26      0.03%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              24      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             107      0.14%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            28      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           74360                       # Writes before turning the bus around for reads
system.physmem.totQLat                    52515283986                       # Total ticks spent queuing
system.physmem.totMemAccLat               83079846486                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8150550000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32215.79                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  50965.79                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.75                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.75                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1305984                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    617830                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  47.44                       # Row buffer hit rate for writes
system.physmem.avgGap                     16207771.58                       # Average gap between requests
system.physmem.pageHitRate                      65.61                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3848576760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2099917875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6284834400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4250627280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3107296514400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1215004983300                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27478552093500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31817337547515                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.798037                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45712218150079                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1588597400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    273094361171                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3775925160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2060276625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6429961200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4187868480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3107296514400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1217449094850                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27476408136000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31817607776715                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.803717                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45708592383178                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1588597400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    276721037822                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              141076080                       # Number of BP lookups
system.cpu0.branchPred.condPredicted        100250771                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6354710                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           105662880                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               77608899                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            73.449540                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16417680                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1072595                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   302583                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               302583                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11677                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        91984                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       302583                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         302583    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       302583                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       103661                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       102356     98.74%     98.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          167      0.16%     98.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          962      0.93%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           38      0.04%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           45      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           22      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           45      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       103661                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   -910187592                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -910187592    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   -910187592                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        91984     88.74%     88.74% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11677     11.26%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       103661                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       302583                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       302583                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       103661                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       103661                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       406244                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    91224751                       # DTB read hits
system.cpu0.dtb.read_misses                    252123                       # DTB read misses
system.cpu0.dtb.write_hits                   79969156                       # DTB write hits
system.cpu0.dtb.write_misses                    50460                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   39295                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      989                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                 11229                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    11007                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                91476874                       # DTB read accesses
system.cpu0.dtb.write_accesses               80019616                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        171193907                       # DTB hits
system.cpu0.dtb.misses                         302583                       # DTB misses
system.cpu0.dtb.accesses                    171496490                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    69790                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                69790                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          704                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        58261                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        69790                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          69790    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        69790                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        58965                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        57570     97.63%     97.63% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071            8      0.01%     97.65% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1255      2.13%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           40      0.07%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           50      0.08%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           25      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           12      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        58965                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -911302092                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -911302092    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -911302092                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        58261     98.81%     98.81% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          704      1.19%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        58965                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        69790                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        69790                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58965                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58965                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       128755                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   253370493                       # ITB inst hits
system.cpu0.itb.inst_misses                     69790                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   28357                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   216294                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               253440283                       # ITB inst accesses
system.cpu0.itb.hits                        253370493                       # DTB hits
system.cpu0.itb.misses                          69790                       # DTB misses
system.cpu0.itb.accesses                    253440283                       # DTB accesses
system.cpu0.numCycles                      1081338531                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  467223626                       # Number of instructions committed
system.cpu0.committedOps                    548903732                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     48040966                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     5433                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 94067362325                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.314392                       # CPI: cycles per instruction
system.cpu0.ipc                              0.432079                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5510                       # number of quiesce instructions executed
system.cpu0.tickCycles                      755200178                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      326138353                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements          5943709                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          508.631098                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          162232873                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5944219                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.292546                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       7690193000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.631098                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993420                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.993420                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        345517845                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       345517845                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     83485003                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       83485003                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     74196086                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      74196086                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       250296                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       250296                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       125849                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       125849                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1837182                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1837182                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1810329                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1810329                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    157681089                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       157681089                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    157931385                       # number of overall hits
system.cpu0.dcache.overall_hits::total      157931385                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3676950                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3676950                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2497111                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2497111                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       700297                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       700297                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       789920                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       789920                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       172643                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       172643                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197460                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       197460                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      6174061                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       6174061                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6874358                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6874358                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  65602264000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  65602264000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  59773944000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  59773944000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  75379073500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  75379073500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2981608500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2981608500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4714245500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4714245500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5404500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5404500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125376208000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125376208000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     87161953                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     87161953                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     76693197                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     76693197                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       950593                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       950593                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       915769                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       915769                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2009825                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2009825                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2007789                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2007789                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    163855150                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    163855150                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    164805743                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    164805743                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.042185                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.042185                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032560                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.032560                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.736695                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.736695                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.862576                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.862576                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085900                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085900                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098347                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098347                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037680                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.037680                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041712                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.041712                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3994886                       # number of writebacks
system.cpu0.dcache.writebacks::total          3994886                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       471328                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       471328                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1040644                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1040644                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           61                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total           61                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43748                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43748                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           50                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           50                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1511972                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1511972                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1511972                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1511972                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3205622                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3205622                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1456467                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1456467                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       694705                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       694705                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       789859                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       789859                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128895                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128895                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197410                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       197410                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4662089                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4662089                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5356794                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5356794                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14687                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14687                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15563                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        15563                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30250                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        30250                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  51339121000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  51339121000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  33967610000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33967610000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18528677500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18528677500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  74583001500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  74583001500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1907396500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1907396500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4514361000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4514361000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5031000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5031000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  85306731000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  85306731000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2448224000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2448224000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2535196500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2535196500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4983420500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4983420500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036778                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036778                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018991                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018991                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.730812                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.730812                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.862509                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.862509                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064132                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064132                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028453                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028453                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032504                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032504                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          9691826                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.890260                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          243455405                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9692338                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            25.118336                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      41394292000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.890260                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999786                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999786                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        515987824                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       515987824                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    243455405                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      243455405                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    243455405                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       243455405                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    243455405                       # number of overall hits
system.cpu0.icache.overall_hits::total      243455405                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9692338                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9692338                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9692338                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9692338                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9692338                       # number of overall misses
system.cpu0.icache.overall_misses::total      9692338                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 102847685000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 102847685000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 102847685000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    253147743                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    253147743                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    253147743                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    253147743                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    253147743                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    253147743                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038287                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.038287                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038287                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.038287                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038287                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.038287                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10611.235906                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10611.235906                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9692338                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9692338                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9692338                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9692338                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9692338                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9692338                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  98001516000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  98001516000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  98001516000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  98001516000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  98001516000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  98001516000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7413401000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7413401000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7413401000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   7413401000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038287                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.038287                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.038287                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10111.235906                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10111.235906                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7930582                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7930908                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          287                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1050332                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2927796                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16250.045097                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          27328553                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2943246                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.285175                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     38485430000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6649.492221                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    85.492855                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    83.778044                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4952.378154                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3516.424447                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   962.479377                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.405853                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005218                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005113                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.302269                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.214626                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.058745                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.991824                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1206                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14158                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          762                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          258                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           60                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4796                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6589                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2552                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.073608                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.864136                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       526684633                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      526684633                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       557343                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       169839                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        727182                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3994885                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3994885                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       109927                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       109927                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36134                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        36134                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       948378                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       948378                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8870174                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      8870174                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2952679                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2952679                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       197136                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       197136                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       557343                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       169839                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      8870174                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3901057                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       13498413                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       557343                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       169839                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      8870174                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3901057                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      13498413                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12614                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8790                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        21404                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       135802                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       135802                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       161268                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       161268                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       273569                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       273569                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       822163                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       822163                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1076215                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1076215                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       591539                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       591539                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12614                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8790                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       822163                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1349784                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2193351                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12614                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8790                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       822163                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1349784                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2193351                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    603588000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    473780500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1077368500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   4108799000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   4108799000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3792069500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3792069500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4938499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4938499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  19118794000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  19118794000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  30594179000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  30594179000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  46332518496                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  46332518496                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  71985941000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  71985941000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    603588000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    473780500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  30594179000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  65451312496                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  97122859996                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    603588000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    473780500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  30594179000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  65451312496                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  97122859996                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       569957                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       178629                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       748586                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3994886                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3994886                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       245729                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       245729                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197402                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       197402                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1221947                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1221947                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9692337                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      9692337                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4028894                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4028894                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       788675                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       788675                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       569957                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       178629                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9692337                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5250841                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     15691764                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       569957                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       178629                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9692337                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5250841                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     15691764                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.028593                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.552649                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.552649                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.816952                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.816952                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.223880                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.223880                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.084826                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.084826                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.267124                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.267124                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.750042                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.750042                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.084826                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.257061                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.139777                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.084826                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.257061                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.139777                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50334.914035                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30255.806247                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30255.806247                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23514.085249                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23514.085249                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 617312.375000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 617312.375000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69886.551473                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69886.551473                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37211.816878                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37211.816878                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43051.359158                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43051.359158                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 121692.637341                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 121692.637341                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37211.816878                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48490.212135                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 44280.582541                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37211.816878                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48490.212135                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 44280.582541                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          189                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          189                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1489447                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1489447                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9633                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         9633                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         1299                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         1299                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10932                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        10941                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            6                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10932                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        10941                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12613                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8788                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        21401                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       120619                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total       120619                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       765315                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       765315                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       135802                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       135802                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       161268                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       161268                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       263936                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       263936                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       822157                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       822157                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1074916                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1074916                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       591539                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       591539                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12613                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8788                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       822157                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1338852                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2182410                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12613                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8788                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       822157                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1338852                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       765315                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2947725                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        14687                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        66996                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        15563                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        15563                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        30250                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        82559                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    948901500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  53668708822                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  53668708822                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4760934499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4760934499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3014472000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3014472000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4572499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4572499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16016983500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16016983500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  25660880000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  25660880000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  39766543496                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  39766543496                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  68436707000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  68436707000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  25660880000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  55783526996                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  82393308496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  25660880000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  55783526996                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  53668708822                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 136062017318                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6994929000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2330678000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9325607000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2418455500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2418455500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6994929000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4749133500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11744062500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028589                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.552649                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.552649                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.816952                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.816952                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.215996                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.215996                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.084825                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.266802                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.266802                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.750042                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.750042                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.254979                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.139080                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.254979                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.187852                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     32152230                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16420555                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       569005                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       568969                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           36                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        939547                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     14756064                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        15563                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        15563                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      5525670                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict     13869690                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1023479                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       455350                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       356742                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       509038                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1302016                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1231079                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9692338                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5147566                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       792720                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       788675                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     29179671                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19139148                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       387023                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1234112                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         49939954                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    623657344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    598500446                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1429032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4559656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1228146478                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6651761                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     39123003                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.023394                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.151159                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          38207781     97.66%     97.66% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            915186      2.34%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                36      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      39123003                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   20385491499                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    189810874                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14619906616                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8517245437                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    208413461                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    664225858                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              135994038                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         97681271                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5923294                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups           101767942                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               74881085                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            73.580229                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               15572056                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect           1048784                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   278179                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               278179                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9856                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        80934                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       278179                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         278179    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       278179                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        90790                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        89574     98.66%     98.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          162      0.18%     98.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          899      0.99%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           22      0.02%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           47      0.05%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           21      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           36      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        90790                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1613488760                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1613488760    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1613488760                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        80934     89.14%     89.14% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         9856     10.86%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        90790                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       278179                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       278179                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        90790                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        90790                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       368969                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    86408994                       # DTB read hits
system.cpu1.dtb.read_misses                    229031                       # DTB read misses
system.cpu1.dtb.write_hits                   76265809                       # DTB write hits
system.cpu1.dtb.write_misses                    49148                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   36480                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1565                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7972                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11612                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                86638025                       # DTB read accesses
system.cpu1.dtb.write_accesses               76314957                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        162674803                       # DTB hits
system.cpu1.dtb.misses                         278179                       # DTB misses
system.cpu1.dtb.accesses                    162952982                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    61280                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                61280                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          546                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52744                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        61280                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          61280    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        61280                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        53290                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        52075     97.72%     97.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071            7      0.01%     97.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1075      2.02%     99.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           37      0.07%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           53      0.10%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           27      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           12      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        53290                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1612594260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1612594260    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1612594260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        52744     98.98%     98.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          546      1.02%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        53290                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61280                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61280                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       114570                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   242169117                       # ITB inst hits
system.cpu1.itb.inst_misses                     61280                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25722                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   205735                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               242230397                       # ITB inst accesses
system.cpu1.itb.hits                        242169117                       # DTB hits
system.cpu1.itb.misses                          61280                       # DTB misses
system.cpu1.itb.accesses                    242230397                       # DTB accesses
system.cpu1.numCycles                       953928196                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  443058406                       # Number of instructions committed
system.cpu1.committedOps                    521637964                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     48259182                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     4720                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 94194636881                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.153053                       # CPI: cycles per instruction
system.cpu1.ipc                              0.464457                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13665                       # number of quiesce instructions executed
system.cpu1.tickCycles                      720990302                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      232937894                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements          5271409                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          430.049497                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          154587010                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5271921                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.322710                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8389845325000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.049497                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839940                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.839940                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          399                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           38                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        327906694                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       327906694                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     79069141                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79069141                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     70951579                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      70951579                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       254478                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       254478                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       200049                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       200049                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1835496                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1835496                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1797284                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1797284                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    150020720                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       150020720                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    150275198                       # number of overall hits
system.cpu1.dcache.overall_hits::total      150275198                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3348164                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3348164                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2321727                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2321727                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       675333                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       675333                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       453842                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       453842                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       163069                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       163069                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       199393                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       199393                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5669891                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5669891                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6345224                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6345224                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  55281073500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  55281073500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  48428743000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  48428743000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20617335000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  20617335000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2629405000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2629405000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4686368500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4686368500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4186500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4186500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 103709816500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 103709816500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 103709816500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 103709816500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     82417305                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     82417305                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     73273306                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     73273306                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       929811                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       929811                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       653891                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       653891                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1998565                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1998565                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1996677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1996677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    155690611                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    155690611                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    156620422                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    156620422                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040625                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.040625                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.031686                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.031686                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.726312                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.726312                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.694064                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.694064                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081593                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.081593                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.099862                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.099862                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036418                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.036418                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040513                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040513                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3447609                       # number of writebacks
system.cpu1.dcache.writebacks::total          3447609                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       379178                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       379178                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       964484                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       964484                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           92                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total           92                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41281                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41281                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           68                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           68                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1343662                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1343662                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1343662                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1343662                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2968986                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2968986                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1357243                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1357243                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       675071                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       675071                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       453750                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       453750                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       121788                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       121788                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       199325                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       199325                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4326229                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4326229                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5001300                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5001300                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        23522                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        23522                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        22517                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        22517                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        46039                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        46039                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  44110385000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  44110385000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  27847514500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  27847514500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16178845000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16178845000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20154706000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20154706000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1764852000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1764852000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4482506000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4482506000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3997500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3997500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  71957899500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  71957899500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88136744500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  88136744500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4055697500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4055697500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3925636000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3925636000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7981333500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7981333500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036024                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036024                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018523                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018523                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.726030                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.726030                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.693923                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.693923                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060938                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060938                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.099828                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.099828                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027787                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027787                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031933                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031933                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14857.053890                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14857.053890                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20517.707220                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20517.707220                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23966.138377                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23966.138377                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44418.084848                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44418.084848                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14491.181397                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14491.181397                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22488.428446                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22488.428446                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          9020173                       # number of replacements
system.cpu1.icache.tags.tagsinuse          506.865133                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          232936753                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          9020685                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            25.822513                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8389731746000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.865133                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989971                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.989971                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        492935590                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       492935590                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    232936753                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      232936753                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    232936753                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       232936753                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    232936753                       # number of overall hits
system.cpu1.icache.overall_hits::total      232936753                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      9020695                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      9020695                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      9020695                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       9020695                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      9020695                       # number of overall misses
system.cpu1.icache.overall_misses::total      9020695                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  95573427500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  95573427500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  95573427500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  95573427500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  95573427500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  95573427500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    241957448                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    241957448                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    241957448                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    241957448                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    241957448                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    241957448                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037282                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.037282                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037282                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.037282                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037282                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.037282                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10594.907321                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10594.907321                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10594.907321                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10594.907321                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10594.907321                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10594.907321                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9020695                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      9020695                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      9020695                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      9020695                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      9020695                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      9020695                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           92                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           92                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91063080500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  91063080500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91063080500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  91063080500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91063080500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  91063080500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12520000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     12520000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     12520000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     12520000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037282                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.037282                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.037282                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10094.907377                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7367099                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7368207                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit          970                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       915185                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2451047                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13486.856931                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          25401363                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2467204                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           10.295607                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9750772511500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5534.671535                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.865878                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.759865                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3715.594887                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3131.532678                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   956.432088                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.337810                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004447                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004624                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.226782                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.191134                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.058376                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.823172                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1547                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14551                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           27                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          141                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          670                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          709                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1114                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2381                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4908                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6029                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.094421                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.888123                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       480485557                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      480485557                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       478608                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141054                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        619662                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3447607                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3447607                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        76833                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        76833                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        38108                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        38108                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       900678                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       900678                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8234691                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      8234691                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2752869                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2752869                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       182879                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       182879                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       478608                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141054                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8234691                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3653547                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       12507900                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       478608                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141054                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8234691                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3653547                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      12507900                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12194                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8418                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        20612                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       132767                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       132767                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       161216                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       161216                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       249202                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       249202                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       786004                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       786004                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1012720                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1012720                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       269177                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       269177                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12194                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8418                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       786004                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1261922                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2068538                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12194                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8418                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       786004                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1261922                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2068538                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    602053500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    457478000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1059531500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   4022613999                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   4022613999                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3766406500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3766406500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3914500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3914500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  14165693998                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  14165693998                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  28461637500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  28461637500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  38316841993                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  38316841993                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18196585000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  18196585000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    602053500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    457478000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  28461637500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  52482535991                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  82003704991                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    602053500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    457478000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  28461637500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  52482535991                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  82003704991                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       490802                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149472                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       640274                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3447608                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3447608                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       209600                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       209600                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       199324                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       199324                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1149880                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1149880                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9020695                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      9020695                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3765589                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3765589                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       452056                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       452056                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       490802                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149472                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      9020695                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4915469                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     14576438                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       490802                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149472                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      9020695                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4915469                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     14576438                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.032192                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.633430                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.633430                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808814                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808814                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.216720                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.216720                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087133                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087133                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.268941                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.268941                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.595451                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.595451                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087133                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256725                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.141910                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087133                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.256725                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.141910                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51403.624102                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30298.297009                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30298.297009                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23362.485733                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23362.485733                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3914500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3914500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56844.222751                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56844.222751                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36210.550455                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36210.550455                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37835.573498                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37835.573498                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67600.816563                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67600.816563                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36210.550455                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41589.366055                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 39643.315709                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36210.550455                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41589.366055                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 39643.315709                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1067557                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1067557                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         9451                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         9451                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         1057                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         1057                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            5                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            6                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        10508                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        10515                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            6                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        10508                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        10515                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12194                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8417                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        20611                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       115832                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total       115832                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       735652                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       735652                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       132767                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       132767                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       161216                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       161216                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       239751                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       239751                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       785998                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       785998                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1011663                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1011663                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       269172                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       269172                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12194                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8417                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       785998                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1251414                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      2058023                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12194                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8417                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       785998                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1251414                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       735652                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2793675                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        23522                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        23614                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        22517                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        22517                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        46039                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        46131                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    935852500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  46172311210                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  46172311210                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4497693492                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4497693492                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2967096500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2967096500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3584500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3584500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  11268741998                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  11268741998                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  23745516000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  23745516000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  32172501493                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  32172501493                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16580751000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16580751000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  23745516000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  43441243491                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  68122611991                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  23745516000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  43441243491                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  46172311210                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 114294923201                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     11784000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3867463500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3879247500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3756742500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3756742500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     11784000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7624206000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7635990000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032191                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.633430                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.633430                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808814                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808814                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.208501                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.208501                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087133                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.268660                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.268660                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.595440                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.595440                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.254587                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.141188                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.254587                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191657                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3584500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3584500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     29416501                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15028447                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2391                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       554511                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       554502                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            9                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        803941                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     13684916                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        22517                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        22517                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4553047                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict     13043260                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       982334                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       414162                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       358438                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       473685                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1229561                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1158646                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9020695                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4893253                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       460729                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       452056                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27060072                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17084009                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332493                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1088108                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         45564682                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    577330304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    542008212                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1195776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3926416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1124460708                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    6177589                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     35784390                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.024790                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.155485                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          34897315     97.52%     97.52% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            887066      2.48%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 9      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      35784390                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   18416469994                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    187934075                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  13533732383                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7841048470                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    183047447                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    597345920                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40341                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40341                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136603                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136603                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47670                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122552                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231256                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231256                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353888                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47690                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339040                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339040                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496808                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36193000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           566159223                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92680000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147952000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115609                       # number of replacements
system.iocache.tags.tagsinuse               11.261931                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115625                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9146785142000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.823570                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.438361                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.238973                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.464898                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.703871                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041009                       # Number of tag accesses
system.iocache.tags.data_accesses             1041009                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8900                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8937                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8900                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8940                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8900                       # number of overall misses
system.iocache.overall_misses::total             8940                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1696302972                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1701497972                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13913628251                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13913628251                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1696302972                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1701866972                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1696302972                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1701866972                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8900                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8937                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8900                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8940                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8900                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8940                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190388.046548                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 190595.839551                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190365.433110                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 190595.839551                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190365.433110                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         34247                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3593                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.531589                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8900                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8937                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8900                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8940                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8900                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8940                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1251302972                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1254647972                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8577228251                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8577228251                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1251302972                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1254866972                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1251302972                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1254866972                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140595.839551                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140388.046548                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140365.433110                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140365.433110                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1566664                       # number of replacements
system.l2c.tags.tagsinuse                63931.901156                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6426547                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1627093                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.949711                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   17340.299819                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   183.189406                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   209.040410                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5130.513561                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11368.638005                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11382.688685                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   175.831777                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   202.455245                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3752.541531                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4974.040380                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9212.662336                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.264592                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002795                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003190                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.078285                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.173472                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173686                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002683                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003089                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.057259                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.075898                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140574                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.975523                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9887                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          204                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50338                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          102                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          389                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9395                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          202                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1895                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5328                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        42935                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.150864                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003113                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.768097                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 77438610                       # Number of tag accesses
system.l2c.tags.data_accesses                77438610                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2557006                       # number of Writeback hits
system.l2c.Writeback_hits::total              2557006                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           27501                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           32544                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               60045                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6218                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5959                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             12177                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           161499                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           176783                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               338282                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6423                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4133                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       754192                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       613728                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       292319                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6682                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4427                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       728293                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       606746                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       315465                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3332408                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6423                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4133                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              754192                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              775227                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       292319                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6682                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4427                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              728293                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              783529                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       315465                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3670690                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6423                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4133                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             754192                       # number of overall hits
system.l2c.overall_hits::cpu0.data             775227                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       292319                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6682                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4427                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             728293                       # number of overall hits
system.l2c.overall_hits::cpu1.data             783529                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       315465                       # number of overall hits
system.l2c.overall_hits::total                3670690                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         45718                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         43728                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             89446                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         9327                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8734                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           18061                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         514166                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         145895                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             660061                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2392                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2135                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        67965                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       161112                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       279683                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2412                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2026                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        57704                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       110574                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       234171                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         920174                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2392                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2135                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             67965                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            675278                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       279683                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2412                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2026                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             57704                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            256469                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       234171                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1580235                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2392                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2135                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            67965                       # number of overall misses
system.l2c.overall_misses::cpu0.data           675278                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       279683                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2412                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2026                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            57704                       # number of overall misses
system.l2c.overall_misses::cpu1.data           256469                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       234171                       # number of overall misses
system.l2c.overall_misses::total              1580235                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    695263000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    645953500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1341216500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    147547000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    132765000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    280312000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  74695360000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  20188019500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  94883379500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    336047000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    299166500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   9148970000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  22699764499                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    341784000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    288119000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7798345000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  15621099500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 145463674622                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    336047000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    299166500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   9148970000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  97395124499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    341784000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    288119000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   7798345000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  35809119000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    240347054122                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    336047000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    299166500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   9148970000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  97395124499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    341784000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    288119000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   7798345000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  35809119000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   240347054122                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2557006                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2557006                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        73219                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        76272                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          149491                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        15545                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        14693                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         30238                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       675665                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       322678                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           998343                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8815                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6268                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       822157                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       774840                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       572002                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9094                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6453                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       785997                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       717320                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       549636                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      4252582                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8815                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6268                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          822157                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1450505                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       572002                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9094                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6453                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          785997                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1039998                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       549636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             5250925                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8815                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6268                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         822157                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1450505                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       572002                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9094                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6453                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         785997                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1039998                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       549636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            5250925                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.624401                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.573317                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.598337                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.600000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.594433                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.597295                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.760978                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.452138                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.661157                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.082667                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.207929                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.073415                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.154149                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.216380                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.082667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.465547                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.073415                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.246605                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.300944                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.082667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.465547                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.073415                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.246605                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.300944                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15207.642504                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14772.079674                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14994.706303                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15819.341696                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15200.938860                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15520.292343                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145274.794522                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138373.621440                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 143749.410282                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134612.962554                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140894.312646                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135143.924165                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141272.808255                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 158082.791539                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134612.962554                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 144229.672074                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135143.924165                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 139623.576339                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 152095.766846                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134612.962554                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 144229.672074                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135143.924165                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 139623.576339                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 152095.766846                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              4391                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       34                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    129.147059                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1195231                       # number of writebacks
system.l2c.writebacks::total                  1195231                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          267                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           23                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          293                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           44                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          630                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            267                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            293                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             44                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                630                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           267                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           293                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            44                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               630                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        55441                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        55441                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        45718                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        43728                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        89446                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9327                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8734                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        18061                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       514166                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       145895                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        660061                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2392                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2135                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        67698                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       161089                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       279683                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2409                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2026                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        57411                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       110530                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       919544                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2392                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2135                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        67698                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       675255                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       279683                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2409                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2026                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        57411                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       256425                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1579605                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2392                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2135                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        67698                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       675255                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       279683                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2409                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2026                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        57411                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       256425                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1579605                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14687                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        23520                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        90608                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15563                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        22517                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38080                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30250                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        46037                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       128688                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   3363963001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   3216758006                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   6580721007                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    713326000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    668745000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1382071000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  69553700000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18729069500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  88282769500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    312127000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    277816500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   8440331000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  21085969999                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  45554283314                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    317283000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    267859000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   7188979000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  14510492000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  38237555809                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 136192696622                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    312127000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    277816500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   8440331000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  90639669999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  45554283314                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    317283000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    267859000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   7188979000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  33239561500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  38237555809                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 224475466122                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    312127000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    277816500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   8440331000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  90639669999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  45554283314                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    317283000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    267859000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   7188979000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  33239561500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  38237555809                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 224475466122                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5896440000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2066285000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      9850500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3444063500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  11416639000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2153864000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3373941000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5527805000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   5896440000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4220149000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9850500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6818004500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  16944444000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.624401                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.573317                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.598337                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.594433                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.597295                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.760978                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.452138                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.661157                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.271356                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.340619                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.207900                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.264900                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.313962                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.154087                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.216232                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.271356                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.340619                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.465531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.264900                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.313962                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.246563                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.300824                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.271356                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.340619                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.465531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.264900                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.313962                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.246563                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.300824                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73580.712214                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73562.888904                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73571.998826                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76479.682642                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76568.010076                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76522.396324                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135274.794522                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128373.621440                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 133749.410282                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130896.398879                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131281.027775                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 148108.950330                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 134230.283373                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 142108.606976                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 142108.606976                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               90608                       # Transaction distribution
system.membus.trans_dist::ReadResp            1019089                       # Transaction distribution
system.membus.trans_dist::WriteReq              38080                       # Transaction distribution
system.membus.trans_dist::WriteResp             38080                       # Transaction distribution
system.membus.trans_dist::Writeback           1301925                       # Transaction distribution
system.membus.trans_dist::CleanEvict           271570                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           429176                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         310200                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          115027                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            674063                       # Transaction distribution
system.membus.trans_dist::ReadExResp           652544                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        928481                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24802                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5589312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5736718                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342877                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342877                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6079595                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155682                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49604                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    180435584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    180642194                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7274816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7274816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               187917010                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           648574                       # Total snoops (count)
system.membus.snoop_fanout::samples           4152999                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4152999    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4152999                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109607499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            20503498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9125026082                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         8873044520                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          230408874                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     12411375                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6308416                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2241470                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         182770                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       168316                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        14454                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              90610                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           5207811                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38080                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38080                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          3858986                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1729776                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          481704                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        322377                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         804081                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          116                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1151274                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1151274                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      5124442                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9065091                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7602046                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              16667137                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    281816078                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    221579908                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              503395986                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3440017                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         14338060                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.337750                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.475069                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                9509841     66.33%     66.33% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                4813765     33.57%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  14454      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           14338060                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9248164097                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2627637                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        5363594791                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4586237114                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------