stats.txt revision 11167
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.573912 # Number of seconds simulated 4sim_ticks 47573912126000 # Number of ticks simulated 5final_tick 47573912126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125865 # Simulator instruction rate (inst/s) 8host_op_rate 148024 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6578075559 # Simulator tick rate (ticks/s) 10host_mem_usage 723980 # Number of bytes of host memory used 11host_seconds 7232.19 # Real time elapsed on the host 12sim_insts 910282032 # Number of instructions simulated 13sim_ops 1070541696 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 153088 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 136640 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7678784 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 42964232 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 17895808 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 154176 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 129664 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3679616 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 16152336 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14975872 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 446400 # Number of bytes read from this memory 27system.physmem.bytes_read::total 104366616 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7678784 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3679616 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11358400 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 83323200 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 83343784 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2392 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2135 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 119981 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 671329 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 279622 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2409 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2026 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 57494 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 252393 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 233998 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6975 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1630754 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1301925 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1304499 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3218 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2872 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 161407 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 903105 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 376169 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3241 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 77345 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 339521 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 314792 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2193778 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 161407 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 77345 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 238753 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1751447 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1751880 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1751447 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3218 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2872 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 161407 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 903537 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 376169 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3241 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 77345 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 339521 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 314792 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3945658 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1630754 # Number of read requests accepted 84system.physmem.writeReqs 1304499 # Number of write requests accepted 85system.physmem.readBursts 1630754 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1304499 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 104327040 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 41216 # Total number of bytes read from write queue 89system.physmem.bytesWritten 83343168 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 104366616 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 83343784 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 644 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 221732 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 95834 # Per bank write bursts 96system.physmem.perBankRdBursts::1 103052 # Per bank write bursts 97system.physmem.perBankRdBursts::2 97330 # Per bank write bursts 98system.physmem.perBankRdBursts::3 103782 # Per bank write bursts 99system.physmem.perBankRdBursts::4 100129 # Per bank write bursts 100system.physmem.perBankRdBursts::5 106515 # Per bank write bursts 101system.physmem.perBankRdBursts::6 99389 # Per bank write bursts 102system.physmem.perBankRdBursts::7 99717 # Per bank write bursts 103system.physmem.perBankRdBursts::8 91352 # Per bank write bursts 104system.physmem.perBankRdBursts::9 148680 # Per bank write bursts 105system.physmem.perBankRdBursts::10 90509 # Per bank write bursts 106system.physmem.perBankRdBursts::11 96337 # Per bank write bursts 107system.physmem.perBankRdBursts::12 96747 # Per bank write bursts 108system.physmem.perBankRdBursts::13 106196 # Per bank write bursts 109system.physmem.perBankRdBursts::14 95843 # Per bank write bursts 110system.physmem.perBankRdBursts::15 98698 # Per bank write bursts 111system.physmem.perBankWrBursts::0 79474 # Per bank write bursts 112system.physmem.perBankWrBursts::1 83004 # Per bank write bursts 113system.physmem.perBankWrBursts::2 79696 # Per bank write bursts 114system.physmem.perBankWrBursts::3 83932 # Per bank write bursts 115system.physmem.perBankWrBursts::4 80263 # Per bank write bursts 116system.physmem.perBankWrBursts::5 85902 # Per bank write bursts 117system.physmem.perBankWrBursts::6 82233 # Per bank write bursts 118system.physmem.perBankWrBursts::7 81457 # Per bank write bursts 119system.physmem.perBankWrBursts::8 76873 # Per bank write bursts 120system.physmem.perBankWrBursts::9 82502 # Per bank write bursts 121system.physmem.perBankWrBursts::10 77306 # Per bank write bursts 122system.physmem.perBankWrBursts::11 81622 # Per bank write bursts 123system.physmem.perBankWrBursts::12 79893 # Per bank write bursts 124system.physmem.perBankWrBursts::13 86888 # Per bank write bursts 125system.physmem.perBankWrBursts::14 78601 # Per bank write bursts 126system.physmem.perBankWrBursts::15 82591 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 61 # Number of times write queue was full causing retry 129system.physmem.totGap 47573910147500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1630724 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1301925 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 998903 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 383381 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 53687 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 39143 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 33585 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 31320 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 28483 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 25807 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 22337 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 5097 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 2530 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1505 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1220 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 637 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 542 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 453 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 125 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 81 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 18448 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 20938 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 44352 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 56882 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 64725 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 69469 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 74724 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 78159 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 81831 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 83061 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 84591 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 90322 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 87643 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 87918 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 95292 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 88789 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 82985 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 78170 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 2650 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1644 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1156 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 850 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 729 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 450 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 362 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 272 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 281 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 360 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 251 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 174 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 172 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 137 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 105 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1008532 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 186.082044 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 114.846498 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 242.592795 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 603416 59.83% 59.83% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 198742 19.71% 79.54% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 66381 6.58% 86.12% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 35101 3.48% 89.60% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 23988 2.38% 91.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 15328 1.52% 93.50% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 10269 1.02% 94.52% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 9973 0.99% 95.50% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 45334 4.50% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1008532 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 74360 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.921678 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 319.874978 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 74357 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 74360 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 74360 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.512601 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.043743 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 6.433062 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 70224 94.44% 94.44% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1905 2.56% 97.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 313 0.42% 97.42% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 309 0.42% 97.84% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 95 0.13% 97.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 310 0.42% 98.38% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 189 0.25% 98.64% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 82 0.11% 98.75% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 85 0.11% 98.86% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 110 0.15% 99.01% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 46 0.06% 99.07% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 59 0.08% 99.15% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 410 0.55% 99.70% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 26 0.03% 99.74% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 24 0.03% 99.77% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 107 0.14% 99.91% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 4 0.01% 99.92% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 3 0.00% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 74360 # Writes before turning the bus around for reads 298system.physmem.totQLat 52515283986 # Total ticks spent queuing 299system.physmem.totMemAccLat 83079846486 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 8150550000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 32215.79 # Average queueing delay per DRAM burst 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 303system.physmem.avgMemAccLat 50965.79 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 2.19 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 309system.physmem.busUtil 0.03 # Data bus utilization in percentage 310system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing 314system.physmem.readRowHits 1305984 # Number of row buffer hits during reads 315system.physmem.writeRowHits 617830 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 47.44 # Row buffer hit rate for writes 318system.physmem.avgGap 16207771.58 # Average gap between requests 319system.physmem.pageHitRate 65.61 # Row buffer hit rate, read and write combined 320system.physmem_0.actEnergy 3848576760 # Energy for activate commands per rank (pJ) 321system.physmem_0.preEnergy 2099917875 # Energy for precharge commands per rank (pJ) 322system.physmem_0.readEnergy 6284834400 # Energy for read commands per rank (pJ) 323system.physmem_0.writeEnergy 4250627280 # Energy for write commands per rank (pJ) 324system.physmem_0.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) 325system.physmem_0.actBackEnergy 1215004983300 # Energy for active background per rank (pJ) 326system.physmem_0.preBackEnergy 27478552093500 # Energy for precharge background per rank (pJ) 327system.physmem_0.totalEnergy 31817337547515 # Total energy per rank (pJ) 328system.physmem_0.averagePower 668.798037 # Core power per rank (mW) 329system.physmem_0.memoryStateTime::IDLE 45712218150079 # Time in different power states 330system.physmem_0.memoryStateTime::REF 1588597400000 # Time in different power states 331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 332system.physmem_0.memoryStateTime::ACT 273094361171 # Time in different power states 333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.physmem_1.actEnergy 3775925160 # Energy for activate commands per rank (pJ) 335system.physmem_1.preEnergy 2060276625 # Energy for precharge commands per rank (pJ) 336system.physmem_1.readEnergy 6429961200 # Energy for read commands per rank (pJ) 337system.physmem_1.writeEnergy 4187868480 # Energy for write commands per rank (pJ) 338system.physmem_1.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) 339system.physmem_1.actBackEnergy 1217449094850 # Energy for active background per rank (pJ) 340system.physmem_1.preBackEnergy 27476408136000 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 31817607776715 # Total energy per rank (pJ) 342system.physmem_1.averagePower 668.803717 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 45708592383178 # Time in different power states 344system.physmem_1.memoryStateTime::REF 1588597400000 # Time in different power states 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 346system.physmem_1.memoryStateTime::ACT 276721037822 # Time in different power states 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 348system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 356system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 361system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 374system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 375system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 376system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 377system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 378system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 379system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 380system.cpu0.branchPred.lookups 141076080 # Number of BP lookups 381system.cpu0.branchPred.condPredicted 100250771 # Number of conditional branches predicted 382system.cpu0.branchPred.condIncorrect 6354710 # Number of conditional branches incorrect 383system.cpu0.branchPred.BTBLookups 105662880 # Number of BTB lookups 384system.cpu0.branchPred.BTBHits 77608899 # Number of BTB hits 385system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 386system.cpu0.branchPred.BTBHitPct 73.449540 # BTB Hit Percentage 387system.cpu0.branchPred.usedRAS 16417680 # Number of times the RAS was used to get a target. 388system.cpu0.branchPred.RASInCorrect 1072595 # Number of incorrect RAS predictions. 389system.cpu_clk_domain.clock 500 # Clock period in ticks 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 399system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 400system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 401system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 402system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 403system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 404system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 409system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 414system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 415system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 416system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 417system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 418system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 419system.cpu0.dtb.walker.walks 302583 # Table walker walks requested 420system.cpu0.dtb.walker.walksLong 302583 # Table walker walks initiated with long descriptors 421system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11677 # Level at which table walker walks with long descriptors terminate 422system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91984 # Level at which table walker walks with long descriptors terminate 423system.cpu0.dtb.walker.walkWaitTime::samples 302583 # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::0 302583 100.00% 100.00% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::total 302583 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkCompletionTime::samples 103661 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::0-65535 102356 98.74% 98.74% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.90% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::131072-196607 962 0.93% 99.83% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::196608-262143 38 0.04% 99.87% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::262144-327679 45 0.04% 99.91% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.02% 99.93% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.04% 99.97% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::total 103661 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution 445system.cpu0.dtb.walker.walkPageSizes::4K 91984 88.74% 88.74% # Table walker page sizes translated 446system.cpu0.dtb.walker.walkPageSizes::2M 11677 11.26% 100.00% # Table walker page sizes translated 447system.cpu0.dtb.walker.walkPageSizes::total 103661 # Table walker page sizes translated 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302583 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302583 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103661 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103661 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin::total 406244 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.inst_hits 0 # ITB inst hits 456system.cpu0.dtb.inst_misses 0 # ITB inst misses 457system.cpu0.dtb.read_hits 91224751 # DTB read hits 458system.cpu0.dtb.read_misses 252123 # DTB read misses 459system.cpu0.dtb.write_hits 79969156 # DTB write hits 460system.cpu0.dtb.write_misses 50460 # DTB write misses 461system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 462system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu0.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID 464system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 465system.cpu0.dtb.flush_entries 39295 # Number of entries that have been flushed from TLB 466system.cpu0.dtb.align_faults 989 # Number of TLB faults due to alignment restrictions 467system.cpu0.dtb.prefetch_faults 11229 # Number of TLB faults due to prefetch 468system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu0.dtb.perms_faults 11007 # Number of TLB faults due to permissions restrictions 470system.cpu0.dtb.read_accesses 91476874 # DTB read accesses 471system.cpu0.dtb.write_accesses 80019616 # DTB write accesses 472system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 473system.cpu0.dtb.hits 171193907 # DTB hits 474system.cpu0.dtb.misses 302583 # DTB misses 475system.cpu0.dtb.accesses 171496490 # DTB accesses 476system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 485system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 486system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 487system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 488system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 489system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 493system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 494system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 495system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 496system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 497system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 498system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 499system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 500system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 501system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 502system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 503system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 504system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 505system.cpu0.itb.walker.walks 69790 # Table walker walks requested 506system.cpu0.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors 507system.cpu0.itb.walker.walksLongTerminationLevel::Level2 704 # Level at which table walker walks with long descriptors terminate 508system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58261 # Level at which table walker walks with long descriptors terminate 509system.cpu0.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency 511system.cpu0.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency 512system.cpu0.itb.walker.walkCompletionTime::samples 58965 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034 # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024 # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::0-65535 57570 97.63% 97.63% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.65% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::131072-196607 1255 2.13% 99.78% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::196608-262143 40 0.07% 99.84% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.08% 99.93% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.04% 99.97% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::total 58965 # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution 527system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution 528system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution 529system.cpu0.itb.walker.walkPageSizes::4K 58261 98.81% 98.81% # Table walker page sizes translated 530system.cpu0.itb.walker.walkPageSizes::2M 704 1.19% 100.00% # Table walker page sizes translated 531system.cpu0.itb.walker.walkPageSizes::total 58965 # Table walker page sizes translated 532system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 536system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58965 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58965 # Table walker requests started/completed, data/inst 538system.cpu0.itb.walker.walkRequestOrigin::total 128755 # Table walker requests started/completed, data/inst 539system.cpu0.itb.inst_hits 253370493 # ITB inst hits 540system.cpu0.itb.inst_misses 69790 # ITB inst misses 541system.cpu0.itb.read_hits 0 # DTB read hits 542system.cpu0.itb.read_misses 0 # DTB read misses 543system.cpu0.itb.write_hits 0 # DTB write hits 544system.cpu0.itb.write_misses 0 # DTB write misses 545system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 546system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 547system.cpu0.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID 548system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 549system.cpu0.itb.flush_entries 28357 # Number of entries that have been flushed from TLB 550system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu0.itb.perms_faults 216294 # Number of TLB faults due to permissions restrictions 554system.cpu0.itb.read_accesses 0 # DTB read accesses 555system.cpu0.itb.write_accesses 0 # DTB write accesses 556system.cpu0.itb.inst_accesses 253440283 # ITB inst accesses 557system.cpu0.itb.hits 253370493 # DTB hits 558system.cpu0.itb.misses 69790 # DTB misses 559system.cpu0.itb.accesses 253440283 # DTB accesses 560system.cpu0.numCycles 1081338531 # number of cpu cycles simulated 561system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 562system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 563system.cpu0.committedInsts 467223626 # Number of instructions committed 564system.cpu0.committedOps 548903732 # Number of ops (including micro ops) committed 565system.cpu0.discardedOps 48040966 # Number of ops (including micro ops) which were discarded before commit 566system.cpu0.numFetchSuspends 5433 # Number of times Execute suspended instruction fetching 567system.cpu0.quiesceCycles 94067362325 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 568system.cpu0.cpi 2.314392 # CPI: cycles per instruction 569system.cpu0.ipc 0.432079 # IPC: instructions per cycle 570system.cpu0.kern.inst.arm 0 # number of arm instructions executed 571system.cpu0.kern.inst.quiesce 5510 # number of quiesce instructions executed 572system.cpu0.tickCycles 755200178 # Number of cycles that the object actually ticked 573system.cpu0.idleCycles 326138353 # Total number of cycles that the object has spent stopped 574system.cpu0.dcache.tags.replacements 5943709 # number of replacements 575system.cpu0.dcache.tags.tagsinuse 508.631098 # Cycle average of tags in use 576system.cpu0.dcache.tags.total_refs 162232873 # Total number of references to valid blocks. 577system.cpu0.dcache.tags.sampled_refs 5944219 # Sample count of references to valid blocks. 578system.cpu0.dcache.tags.avg_refs 27.292546 # Average number of references to valid blocks. 579system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. 580system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.631098 # Average occupied blocks per requestor 581system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993420 # Average percentage of cache occupancy 582system.cpu0.dcache.tags.occ_percent::total 0.993420 # Average percentage of cache occupancy 583system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 584system.cpu0.dcache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 585system.cpu0.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 586system.cpu0.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id 587system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 588system.cpu0.dcache.tags.tag_accesses 345517845 # Number of tag accesses 589system.cpu0.dcache.tags.data_accesses 345517845 # Number of data accesses 590system.cpu0.dcache.ReadReq_hits::cpu0.data 83485003 # number of ReadReq hits 591system.cpu0.dcache.ReadReq_hits::total 83485003 # number of ReadReq hits 592system.cpu0.dcache.WriteReq_hits::cpu0.data 74196086 # number of WriteReq hits 593system.cpu0.dcache.WriteReq_hits::total 74196086 # number of WriteReq hits 594system.cpu0.dcache.SoftPFReq_hits::cpu0.data 250296 # number of SoftPFReq hits 595system.cpu0.dcache.SoftPFReq_hits::total 250296 # number of SoftPFReq hits 596system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125849 # number of WriteLineReq hits 597system.cpu0.dcache.WriteLineReq_hits::total 125849 # number of WriteLineReq hits 598system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1837182 # number of LoadLockedReq hits 599system.cpu0.dcache.LoadLockedReq_hits::total 1837182 # number of LoadLockedReq hits 600system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1810329 # number of StoreCondReq hits 601system.cpu0.dcache.StoreCondReq_hits::total 1810329 # number of StoreCondReq hits 602system.cpu0.dcache.demand_hits::cpu0.data 157681089 # number of demand (read+write) hits 603system.cpu0.dcache.demand_hits::total 157681089 # number of demand (read+write) hits 604system.cpu0.dcache.overall_hits::cpu0.data 157931385 # number of overall hits 605system.cpu0.dcache.overall_hits::total 157931385 # number of overall hits 606system.cpu0.dcache.ReadReq_misses::cpu0.data 3676950 # number of ReadReq misses 607system.cpu0.dcache.ReadReq_misses::total 3676950 # number of ReadReq misses 608system.cpu0.dcache.WriteReq_misses::cpu0.data 2497111 # number of WriteReq misses 609system.cpu0.dcache.WriteReq_misses::total 2497111 # number of WriteReq misses 610system.cpu0.dcache.SoftPFReq_misses::cpu0.data 700297 # number of SoftPFReq misses 611system.cpu0.dcache.SoftPFReq_misses::total 700297 # number of SoftPFReq misses 612system.cpu0.dcache.WriteLineReq_misses::cpu0.data 789920 # number of WriteLineReq misses 613system.cpu0.dcache.WriteLineReq_misses::total 789920 # number of WriteLineReq misses 614system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172643 # number of LoadLockedReq misses 615system.cpu0.dcache.LoadLockedReq_misses::total 172643 # number of LoadLockedReq misses 616system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197460 # number of StoreCondReq misses 617system.cpu0.dcache.StoreCondReq_misses::total 197460 # number of StoreCondReq misses 618system.cpu0.dcache.demand_misses::cpu0.data 6174061 # number of demand (read+write) misses 619system.cpu0.dcache.demand_misses::total 6174061 # number of demand (read+write) misses 620system.cpu0.dcache.overall_misses::cpu0.data 6874358 # number of overall misses 621system.cpu0.dcache.overall_misses::total 6874358 # number of overall misses 622system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 65602264000 # number of ReadReq miss cycles 623system.cpu0.dcache.ReadReq_miss_latency::total 65602264000 # number of ReadReq miss cycles 624system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59773944000 # number of WriteReq miss cycles 625system.cpu0.dcache.WriteReq_miss_latency::total 59773944000 # number of WriteReq miss cycles 626system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 75379073500 # number of WriteLineReq miss cycles 627system.cpu0.dcache.WriteLineReq_miss_latency::total 75379073500 # number of WriteLineReq miss cycles 628system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2981608500 # number of LoadLockedReq miss cycles 629system.cpu0.dcache.LoadLockedReq_miss_latency::total 2981608500 # number of LoadLockedReq miss cycles 630system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4714245500 # number of StoreCondReq miss cycles 631system.cpu0.dcache.StoreCondReq_miss_latency::total 4714245500 # number of StoreCondReq miss cycles 632system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5404500 # number of StoreCondFailReq miss cycles 633system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5404500 # number of StoreCondFailReq miss cycles 634system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000 # number of demand (read+write) miss cycles 635system.cpu0.dcache.demand_miss_latency::total 125376208000 # number of demand (read+write) miss cycles 636system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000 # number of overall miss cycles 637system.cpu0.dcache.overall_miss_latency::total 125376208000 # number of overall miss cycles 638system.cpu0.dcache.ReadReq_accesses::cpu0.data 87161953 # number of ReadReq accesses(hits+misses) 639system.cpu0.dcache.ReadReq_accesses::total 87161953 # number of ReadReq accesses(hits+misses) 640system.cpu0.dcache.WriteReq_accesses::cpu0.data 76693197 # number of WriteReq accesses(hits+misses) 641system.cpu0.dcache.WriteReq_accesses::total 76693197 # number of WriteReq accesses(hits+misses) 642system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 950593 # number of SoftPFReq accesses(hits+misses) 643system.cpu0.dcache.SoftPFReq_accesses::total 950593 # number of SoftPFReq accesses(hits+misses) 644system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 915769 # number of WriteLineReq accesses(hits+misses) 645system.cpu0.dcache.WriteLineReq_accesses::total 915769 # number of WriteLineReq accesses(hits+misses) 646system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009825 # number of LoadLockedReq accesses(hits+misses) 647system.cpu0.dcache.LoadLockedReq_accesses::total 2009825 # number of LoadLockedReq accesses(hits+misses) 648system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2007789 # number of StoreCondReq accesses(hits+misses) 649system.cpu0.dcache.StoreCondReq_accesses::total 2007789 # number of StoreCondReq accesses(hits+misses) 650system.cpu0.dcache.demand_accesses::cpu0.data 163855150 # number of demand (read+write) accesses 651system.cpu0.dcache.demand_accesses::total 163855150 # number of demand (read+write) accesses 652system.cpu0.dcache.overall_accesses::cpu0.data 164805743 # number of overall (read+write) accesses 653system.cpu0.dcache.overall_accesses::total 164805743 # number of overall (read+write) accesses 654system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.042185 # miss rate for ReadReq accesses 655system.cpu0.dcache.ReadReq_miss_rate::total 0.042185 # miss rate for ReadReq accesses 656system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032560 # miss rate for WriteReq accesses 657system.cpu0.dcache.WriteReq_miss_rate::total 0.032560 # miss rate for WriteReq accesses 658system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.736695 # miss rate for SoftPFReq accesses 659system.cpu0.dcache.SoftPFReq_miss_rate::total 0.736695 # miss rate for SoftPFReq accesses 660system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.862576 # miss rate for WriteLineReq accesses 661system.cpu0.dcache.WriteLineReq_miss_rate::total 0.862576 # miss rate for WriteLineReq accesses 662system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085900 # miss rate for LoadLockedReq accesses 663system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085900 # miss rate for LoadLockedReq accesses 664system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098347 # miss rate for StoreCondReq accesses 665system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098347 # miss rate for StoreCondReq accesses 666system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037680 # miss rate for demand accesses 667system.cpu0.dcache.demand_miss_rate::total 0.037680 # miss rate for demand accesses 668system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041712 # miss rate for overall accesses 669system.cpu0.dcache.overall_miss_rate::total 0.041712 # miss rate for overall accesses 670system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278 # average ReadReq miss latency 671system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278 # average ReadReq miss latency 672system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474 # average WriteReq miss latency 673system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474 # average WriteReq miss latency 674system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148 # average WriteLineReq miss latency 675system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148 # average WriteLineReq miss latency 676system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070 # average LoadLockedReq miss latency 677system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070 # average LoadLockedReq miss latency 678system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797 # average StoreCondReq miss latency 679system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797 # average StoreCondReq miss latency 680system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 681system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 682system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321 # average overall miss latency 683system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321 # average overall miss latency 684system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466 # average overall miss latency 685system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466 # average overall miss latency 686system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 687system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 688system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 689system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 690system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 691system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 692system.cpu0.dcache.fast_writes 0 # number of fast writes performed 693system.cpu0.dcache.cache_copies 0 # number of cache copies performed 694system.cpu0.dcache.writebacks::writebacks 3994886 # number of writebacks 695system.cpu0.dcache.writebacks::total 3994886 # number of writebacks 696system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471328 # number of ReadReq MSHR hits 697system.cpu0.dcache.ReadReq_mshr_hits::total 471328 # number of ReadReq MSHR hits 698system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1040644 # number of WriteReq MSHR hits 699system.cpu0.dcache.WriteReq_mshr_hits::total 1040644 # number of WriteReq MSHR hits 700system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 61 # number of WriteLineReq MSHR hits 701system.cpu0.dcache.WriteLineReq_mshr_hits::total 61 # number of WriteLineReq MSHR hits 702system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43748 # number of LoadLockedReq MSHR hits 703system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43748 # number of LoadLockedReq MSHR hits 704system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 50 # number of StoreCondReq MSHR hits 705system.cpu0.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits 706system.cpu0.dcache.demand_mshr_hits::cpu0.data 1511972 # number of demand (read+write) MSHR hits 707system.cpu0.dcache.demand_mshr_hits::total 1511972 # number of demand (read+write) MSHR hits 708system.cpu0.dcache.overall_mshr_hits::cpu0.data 1511972 # number of overall MSHR hits 709system.cpu0.dcache.overall_mshr_hits::total 1511972 # number of overall MSHR hits 710system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3205622 # number of ReadReq MSHR misses 711system.cpu0.dcache.ReadReq_mshr_misses::total 3205622 # number of ReadReq MSHR misses 712system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1456467 # number of WriteReq MSHR misses 713system.cpu0.dcache.WriteReq_mshr_misses::total 1456467 # number of WriteReq MSHR misses 714system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694705 # number of SoftPFReq MSHR misses 715system.cpu0.dcache.SoftPFReq_mshr_misses::total 694705 # number of SoftPFReq MSHR misses 716system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 789859 # number of WriteLineReq MSHR misses 717system.cpu0.dcache.WriteLineReq_mshr_misses::total 789859 # number of WriteLineReq MSHR misses 718system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128895 # number of LoadLockedReq MSHR misses 719system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128895 # number of LoadLockedReq MSHR misses 720system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197410 # number of StoreCondReq MSHR misses 721system.cpu0.dcache.StoreCondReq_mshr_misses::total 197410 # number of StoreCondReq MSHR misses 722system.cpu0.dcache.demand_mshr_misses::cpu0.data 4662089 # number of demand (read+write) MSHR misses 723system.cpu0.dcache.demand_mshr_misses::total 4662089 # number of demand (read+write) MSHR misses 724system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356794 # number of overall MSHR misses 725system.cpu0.dcache.overall_mshr_misses::total 5356794 # number of overall MSHR misses 726system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14687 # number of ReadReq MSHR uncacheable 727system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14687 # number of ReadReq MSHR uncacheable 728system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15563 # number of WriteReq MSHR uncacheable 729system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15563 # number of WriteReq MSHR uncacheable 730system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30250 # number of overall MSHR uncacheable misses 731system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30250 # number of overall MSHR uncacheable misses 732system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51339121000 # number of ReadReq MSHR miss cycles 733system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51339121000 # number of ReadReq MSHR miss cycles 734system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33967610000 # number of WriteReq MSHR miss cycles 735system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33967610000 # number of WriteReq MSHR miss cycles 736system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18528677500 # number of SoftPFReq MSHR miss cycles 737system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18528677500 # number of SoftPFReq MSHR miss cycles 738system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 74583001500 # number of WriteLineReq MSHR miss cycles 739system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 74583001500 # number of WriteLineReq MSHR miss cycles 740system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1907396500 # number of LoadLockedReq MSHR miss cycles 741system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1907396500 # number of LoadLockedReq MSHR miss cycles 742system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4514361000 # number of StoreCondReq MSHR miss cycles 743system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4514361000 # number of StoreCondReq MSHR miss cycles 744system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5031000 # number of StoreCondFailReq MSHR miss cycles 745system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5031000 # number of StoreCondFailReq MSHR miss cycles 746system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85306731000 # number of demand (read+write) MSHR miss cycles 747system.cpu0.dcache.demand_mshr_miss_latency::total 85306731000 # number of demand (read+write) MSHR miss cycles 748system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500 # number of overall MSHR miss cycles 749system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500 # number of overall MSHR miss cycles 750system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2448224000 # number of ReadReq MSHR uncacheable cycles 751system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2448224000 # number of ReadReq MSHR uncacheable cycles 752system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535196500 # number of WriteReq MSHR uncacheable cycles 753system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2535196500 # number of WriteReq MSHR uncacheable cycles 754system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4983420500 # number of overall MSHR uncacheable cycles 755system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4983420500 # number of overall MSHR uncacheable cycles 756system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036778 # mshr miss rate for ReadReq accesses 757system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036778 # mshr miss rate for ReadReq accesses 758system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018991 # mshr miss rate for WriteReq accesses 759system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018991 # mshr miss rate for WriteReq accesses 760system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.730812 # mshr miss rate for SoftPFReq accesses 761system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.730812 # mshr miss rate for SoftPFReq accesses 762system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.862509 # mshr miss rate for WriteLineReq accesses 763system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.862509 # mshr miss rate for WriteLineReq accesses 764system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064132 # mshr miss rate for LoadLockedReq accesses 765system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064132 # mshr miss rate for LoadLockedReq accesses 766system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098322 # mshr miss rate for StoreCondReq accesses 767system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098322 # mshr miss rate for StoreCondReq accesses 768system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses 769system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses 770system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032504 # mshr miss rate for overall accesses 771system.cpu0.dcache.overall_mshr_miss_rate::total 0.032504 # mshr miss rate for overall accesses 772system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365 # average ReadReq mshr miss latency 773system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365 # average ReadReq mshr miss latency 774system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158 # average WriteReq mshr miss latency 775system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158 # average WriteReq mshr miss latency 776system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533 # average SoftPFReq mshr miss latency 777system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533 # average SoftPFReq mshr miss latency 778system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856 # average WriteLineReq mshr miss latency 779system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856 # average WriteLineReq mshr miss latency 780system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316 # average LoadLockedReq mshr miss latency 781system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316 # average LoadLockedReq mshr miss latency 782system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886 # average StoreCondReq mshr miss latency 783system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886 # average StoreCondReq mshr miss latency 784system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 785system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 786system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780 # average overall mshr miss latency 787system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780 # average overall mshr miss latency 788system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864 # average overall mshr miss latency 789system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864 # average overall mshr miss latency 790system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154 # average ReadReq mshr uncacheable latency 791system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154 # average ReadReq mshr uncacheable latency 792system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070 # average WriteReq mshr uncacheable latency 793system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070 # average WriteReq mshr uncacheable latency 794system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554 # average overall mshr uncacheable latency 795system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554 # average overall mshr uncacheable latency 796system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 797system.cpu0.icache.tags.replacements 9691826 # number of replacements 798system.cpu0.icache.tags.tagsinuse 511.890260 # Cycle average of tags in use 799system.cpu0.icache.tags.total_refs 243455405 # Total number of references to valid blocks. 800system.cpu0.icache.tags.sampled_refs 9692338 # Sample count of references to valid blocks. 801system.cpu0.icache.tags.avg_refs 25.118336 # Average number of references to valid blocks. 802system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit. 803system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890260 # Average occupied blocks per requestor 804system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999786 # Average percentage of cache occupancy 805system.cpu0.icache.tags.occ_percent::total 0.999786 # Average percentage of cache occupancy 806system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 807system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 808system.cpu0.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id 809system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id 810system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 811system.cpu0.icache.tags.tag_accesses 515987824 # Number of tag accesses 812system.cpu0.icache.tags.data_accesses 515987824 # Number of data accesses 813system.cpu0.icache.ReadReq_hits::cpu0.inst 243455405 # number of ReadReq hits 814system.cpu0.icache.ReadReq_hits::total 243455405 # number of ReadReq hits 815system.cpu0.icache.demand_hits::cpu0.inst 243455405 # number of demand (read+write) hits 816system.cpu0.icache.demand_hits::total 243455405 # number of demand (read+write) hits 817system.cpu0.icache.overall_hits::cpu0.inst 243455405 # number of overall hits 818system.cpu0.icache.overall_hits::total 243455405 # number of overall hits 819system.cpu0.icache.ReadReq_misses::cpu0.inst 9692338 # number of ReadReq misses 820system.cpu0.icache.ReadReq_misses::total 9692338 # number of ReadReq misses 821system.cpu0.icache.demand_misses::cpu0.inst 9692338 # number of demand (read+write) misses 822system.cpu0.icache.demand_misses::total 9692338 # number of demand (read+write) misses 823system.cpu0.icache.overall_misses::cpu0.inst 9692338 # number of overall misses 824system.cpu0.icache.overall_misses::total 9692338 # number of overall misses 825system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000 # number of ReadReq miss cycles 826system.cpu0.icache.ReadReq_miss_latency::total 102847685000 # number of ReadReq miss cycles 827system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000 # number of demand (read+write) miss cycles 828system.cpu0.icache.demand_miss_latency::total 102847685000 # number of demand (read+write) miss cycles 829system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000 # number of overall miss cycles 830system.cpu0.icache.overall_miss_latency::total 102847685000 # number of overall miss cycles 831system.cpu0.icache.ReadReq_accesses::cpu0.inst 253147743 # number of ReadReq accesses(hits+misses) 832system.cpu0.icache.ReadReq_accesses::total 253147743 # number of ReadReq accesses(hits+misses) 833system.cpu0.icache.demand_accesses::cpu0.inst 253147743 # number of demand (read+write) accesses 834system.cpu0.icache.demand_accesses::total 253147743 # number of demand (read+write) accesses 835system.cpu0.icache.overall_accesses::cpu0.inst 253147743 # number of overall (read+write) accesses 836system.cpu0.icache.overall_accesses::total 253147743 # number of overall (read+write) accesses 837system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038287 # miss rate for ReadReq accesses 838system.cpu0.icache.ReadReq_miss_rate::total 0.038287 # miss rate for ReadReq accesses 839system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038287 # miss rate for demand accesses 840system.cpu0.icache.demand_miss_rate::total 0.038287 # miss rate for demand accesses 841system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038287 # miss rate for overall accesses 842system.cpu0.icache.overall_miss_rate::total 0.038287 # miss rate for overall accesses 843system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906 # average ReadReq miss latency 844system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906 # average ReadReq miss latency 845system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency 846system.cpu0.icache.demand_avg_miss_latency::total 10611.235906 # average overall miss latency 847system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency 848system.cpu0.icache.overall_avg_miss_latency::total 10611.235906 # average overall miss latency 849system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 850system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 851system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 852system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 853system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 854system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 855system.cpu0.icache.fast_writes 0 # number of fast writes performed 856system.cpu0.icache.cache_copies 0 # number of cache copies performed 857system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9692338 # number of ReadReq MSHR misses 858system.cpu0.icache.ReadReq_mshr_misses::total 9692338 # number of ReadReq MSHR misses 859system.cpu0.icache.demand_mshr_misses::cpu0.inst 9692338 # number of demand (read+write) MSHR misses 860system.cpu0.icache.demand_mshr_misses::total 9692338 # number of demand (read+write) MSHR misses 861system.cpu0.icache.overall_mshr_misses::cpu0.inst 9692338 # number of overall MSHR misses 862system.cpu0.icache.overall_mshr_misses::total 9692338 # number of overall MSHR misses 863system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 864system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 865system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 866system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 867system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 98001516000 # number of ReadReq MSHR miss cycles 868system.cpu0.icache.ReadReq_mshr_miss_latency::total 98001516000 # number of ReadReq MSHR miss cycles 869system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 98001516000 # number of demand (read+write) MSHR miss cycles 870system.cpu0.icache.demand_mshr_miss_latency::total 98001516000 # number of demand (read+write) MSHR miss cycles 871system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 98001516000 # number of overall MSHR miss cycles 872system.cpu0.icache.overall_mshr_miss_latency::total 98001516000 # number of overall MSHR miss cycles 873system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles 874system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles 875system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles 876system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles 877system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for ReadReq accesses 878system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038287 # mshr miss rate for ReadReq accesses 879system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for demand accesses 880system.cpu0.icache.demand_mshr_miss_rate::total 0.038287 # mshr miss rate for demand accesses 881system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for overall accesses 882system.cpu0.icache.overall_mshr_miss_rate::total 0.038287 # mshr miss rate for overall accesses 883system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average ReadReq mshr miss latency 884system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10111.235906 # average ReadReq mshr miss latency 885system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency 886system.cpu0.icache.demand_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency 887system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency 888system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency 889system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency 890system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency 891system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency 892system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency 893system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 894system.cpu0.l2cache.prefetcher.num_hwpf_issued 7930582 # number of hwpf issued 895system.cpu0.l2cache.prefetcher.pfIdentified 7930908 # number of prefetch candidates identified 896system.cpu0.l2cache.prefetcher.pfBufferHit 287 # number of redundant prefetches already in prefetch queue 897system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 898system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 899system.cpu0.l2cache.prefetcher.pfSpanPage 1050332 # number of prefetches not generated due to page crossing 900system.cpu0.l2cache.tags.replacements 2927796 # number of replacements 901system.cpu0.l2cache.tags.tagsinuse 16250.045097 # Cycle average of tags in use 902system.cpu0.l2cache.tags.total_refs 27328553 # Total number of references to valid blocks. 903system.cpu0.l2cache.tags.sampled_refs 2943246 # Sample count of references to valid blocks. 904system.cpu0.l2cache.tags.avg_refs 9.285175 # Average number of references to valid blocks. 905system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit. 906system.cpu0.l2cache.tags.occ_blocks::writebacks 6649.492221 # Average occupied blocks per requestor 907system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.492855 # Average occupied blocks per requestor 908system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 83.778044 # Average occupied blocks per requestor 909system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4952.378154 # Average occupied blocks per requestor 910system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3516.424447 # Average occupied blocks per requestor 911system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 962.479377 # Average occupied blocks per requestor 912system.cpu0.l2cache.tags.occ_percent::writebacks 0.405853 # Average percentage of cache occupancy 913system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005218 # Average percentage of cache occupancy 914system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005113 # Average percentage of cache occupancy 915system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.302269 # Average percentage of cache occupancy 916system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.214626 # Average percentage of cache occupancy 917system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058745 # Average percentage of cache occupancy 918system.cpu0.l2cache.tags.occ_percent::total 0.991824 # Average percentage of cache occupancy 919system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1206 # Occupied blocks per task id 920system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id 921system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14158 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 923system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id 924system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 60 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4796 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6589 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2552 # Occupied blocks per task id 934system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073608 # Percentage of cache occupancy per task id 935system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id 936system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.864136 # Percentage of cache occupancy per task id 937system.cpu0.l2cache.tags.tag_accesses 526684633 # Number of tag accesses 938system.cpu0.l2cache.tags.data_accesses 526684633 # Number of data accesses 939system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 557343 # number of ReadReq hits 940system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 169839 # number of ReadReq hits 941system.cpu0.l2cache.ReadReq_hits::total 727182 # number of ReadReq hits 942system.cpu0.l2cache.Writeback_hits::writebacks 3994885 # number of Writeback hits 943system.cpu0.l2cache.Writeback_hits::total 3994885 # number of Writeback hits 944system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 109927 # number of UpgradeReq hits 945system.cpu0.l2cache.UpgradeReq_hits::total 109927 # number of UpgradeReq hits 946system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36134 # number of SCUpgradeReq hits 947system.cpu0.l2cache.SCUpgradeReq_hits::total 36134 # number of SCUpgradeReq hits 948system.cpu0.l2cache.ReadExReq_hits::cpu0.data 948378 # number of ReadExReq hits 949system.cpu0.l2cache.ReadExReq_hits::total 948378 # number of ReadExReq hits 950system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8870174 # number of ReadCleanReq hits 951system.cpu0.l2cache.ReadCleanReq_hits::total 8870174 # number of ReadCleanReq hits 952system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2952679 # number of ReadSharedReq hits 953system.cpu0.l2cache.ReadSharedReq_hits::total 2952679 # number of ReadSharedReq hits 954system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 197136 # number of InvalidateReq hits 955system.cpu0.l2cache.InvalidateReq_hits::total 197136 # number of InvalidateReq hits 956system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 557343 # number of demand (read+write) hits 957system.cpu0.l2cache.demand_hits::cpu0.itb.walker 169839 # number of demand (read+write) hits 958system.cpu0.l2cache.demand_hits::cpu0.inst 8870174 # number of demand (read+write) hits 959system.cpu0.l2cache.demand_hits::cpu0.data 3901057 # number of demand (read+write) hits 960system.cpu0.l2cache.demand_hits::total 13498413 # number of demand (read+write) hits 961system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 557343 # number of overall hits 962system.cpu0.l2cache.overall_hits::cpu0.itb.walker 169839 # number of overall hits 963system.cpu0.l2cache.overall_hits::cpu0.inst 8870174 # number of overall hits 964system.cpu0.l2cache.overall_hits::cpu0.data 3901057 # number of overall hits 965system.cpu0.l2cache.overall_hits::total 13498413 # number of overall hits 966system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12614 # number of ReadReq misses 967system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8790 # number of ReadReq misses 968system.cpu0.l2cache.ReadReq_misses::total 21404 # number of ReadReq misses 969system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 970system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 971system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 135802 # number of UpgradeReq misses 972system.cpu0.l2cache.UpgradeReq_misses::total 135802 # number of UpgradeReq misses 973system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 161268 # number of SCUpgradeReq misses 974system.cpu0.l2cache.SCUpgradeReq_misses::total 161268 # number of SCUpgradeReq misses 975system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 976system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 977system.cpu0.l2cache.ReadExReq_misses::cpu0.data 273569 # number of ReadExReq misses 978system.cpu0.l2cache.ReadExReq_misses::total 273569 # number of ReadExReq misses 979system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 822163 # number of ReadCleanReq misses 980system.cpu0.l2cache.ReadCleanReq_misses::total 822163 # number of ReadCleanReq misses 981system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1076215 # number of ReadSharedReq misses 982system.cpu0.l2cache.ReadSharedReq_misses::total 1076215 # number of ReadSharedReq misses 983system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 591539 # number of InvalidateReq misses 984system.cpu0.l2cache.InvalidateReq_misses::total 591539 # number of InvalidateReq misses 985system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12614 # number of demand (read+write) misses 986system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8790 # number of demand (read+write) misses 987system.cpu0.l2cache.demand_misses::cpu0.inst 822163 # number of demand (read+write) misses 988system.cpu0.l2cache.demand_misses::cpu0.data 1349784 # number of demand (read+write) misses 989system.cpu0.l2cache.demand_misses::total 2193351 # number of demand (read+write) misses 990system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12614 # number of overall misses 991system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8790 # number of overall misses 992system.cpu0.l2cache.overall_misses::cpu0.inst 822163 # number of overall misses 993system.cpu0.l2cache.overall_misses::cpu0.data 1349784 # number of overall misses 994system.cpu0.l2cache.overall_misses::total 2193351 # number of overall misses 995system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 603588000 # number of ReadReq miss cycles 996system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 473780500 # number of ReadReq miss cycles 997system.cpu0.l2cache.ReadReq_miss_latency::total 1077368500 # number of ReadReq miss cycles 998system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4108799000 # number of UpgradeReq miss cycles 999system.cpu0.l2cache.UpgradeReq_miss_latency::total 4108799000 # number of UpgradeReq miss cycles 1000system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3792069500 # number of SCUpgradeReq miss cycles 1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3792069500 # number of SCUpgradeReq miss cycles 1002system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4938499 # number of SCUpgradeFailReq miss cycles 1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4938499 # number of SCUpgradeFailReq miss cycles 1004system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19118794000 # number of ReadExReq miss cycles 1005system.cpu0.l2cache.ReadExReq_miss_latency::total 19118794000 # number of ReadExReq miss cycles 1006system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30594179000 # number of ReadCleanReq miss cycles 1007system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30594179000 # number of ReadCleanReq miss cycles 1008system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46332518496 # number of ReadSharedReq miss cycles 1009system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46332518496 # number of ReadSharedReq miss cycles 1010system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 71985941000 # number of InvalidateReq miss cycles 1011system.cpu0.l2cache.InvalidateReq_miss_latency::total 71985941000 # number of InvalidateReq miss cycles 1012system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 603588000 # number of demand (read+write) miss cycles 1013system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 473780500 # number of demand (read+write) miss cycles 1014system.cpu0.l2cache.demand_miss_latency::cpu0.inst 30594179000 # number of demand (read+write) miss cycles 1015system.cpu0.l2cache.demand_miss_latency::cpu0.data 65451312496 # number of demand (read+write) miss cycles 1016system.cpu0.l2cache.demand_miss_latency::total 97122859996 # number of demand (read+write) miss cycles 1017system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 603588000 # number of overall miss cycles 1018system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 473780500 # number of overall miss cycles 1019system.cpu0.l2cache.overall_miss_latency::cpu0.inst 30594179000 # number of overall miss cycles 1020system.cpu0.l2cache.overall_miss_latency::cpu0.data 65451312496 # number of overall miss cycles 1021system.cpu0.l2cache.overall_miss_latency::total 97122859996 # number of overall miss cycles 1022system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 569957 # number of ReadReq accesses(hits+misses) 1023system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 178629 # number of ReadReq accesses(hits+misses) 1024system.cpu0.l2cache.ReadReq_accesses::total 748586 # number of ReadReq accesses(hits+misses) 1025system.cpu0.l2cache.Writeback_accesses::writebacks 3994886 # number of Writeback accesses(hits+misses) 1026system.cpu0.l2cache.Writeback_accesses::total 3994886 # number of Writeback accesses(hits+misses) 1027system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 245729 # number of UpgradeReq accesses(hits+misses) 1028system.cpu0.l2cache.UpgradeReq_accesses::total 245729 # number of UpgradeReq accesses(hits+misses) 1029system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197402 # number of SCUpgradeReq accesses(hits+misses) 1030system.cpu0.l2cache.SCUpgradeReq_accesses::total 197402 # number of SCUpgradeReq accesses(hits+misses) 1031system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1032system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1033system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1221947 # number of ReadExReq accesses(hits+misses) 1034system.cpu0.l2cache.ReadExReq_accesses::total 1221947 # number of ReadExReq accesses(hits+misses) 1035system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9692337 # number of ReadCleanReq accesses(hits+misses) 1036system.cpu0.l2cache.ReadCleanReq_accesses::total 9692337 # number of ReadCleanReq accesses(hits+misses) 1037system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4028894 # number of ReadSharedReq accesses(hits+misses) 1038system.cpu0.l2cache.ReadSharedReq_accesses::total 4028894 # number of ReadSharedReq accesses(hits+misses) 1039system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 788675 # number of InvalidateReq accesses(hits+misses) 1040system.cpu0.l2cache.InvalidateReq_accesses::total 788675 # number of InvalidateReq accesses(hits+misses) 1041system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 569957 # number of demand (read+write) accesses 1042system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 178629 # number of demand (read+write) accesses 1043system.cpu0.l2cache.demand_accesses::cpu0.inst 9692337 # number of demand (read+write) accesses 1044system.cpu0.l2cache.demand_accesses::cpu0.data 5250841 # number of demand (read+write) accesses 1045system.cpu0.l2cache.demand_accesses::total 15691764 # number of demand (read+write) accesses 1046system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 569957 # number of overall (read+write) accesses 1047system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 178629 # number of overall (read+write) accesses 1048system.cpu0.l2cache.overall_accesses::cpu0.inst 9692337 # number of overall (read+write) accesses 1049system.cpu0.l2cache.overall_accesses::cpu0.data 5250841 # number of overall (read+write) accesses 1050system.cpu0.l2cache.overall_accesses::total 15691764 # number of overall (read+write) accesses 1051system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022131 # miss rate for ReadReq accesses 1052system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049208 # miss rate for ReadReq accesses 1053system.cpu0.l2cache.ReadReq_miss_rate::total 0.028593 # miss rate for ReadReq accesses 1054system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1055system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1056system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.552649 # miss rate for UpgradeReq accesses 1057system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.552649 # miss rate for UpgradeReq accesses 1058system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.816952 # miss rate for SCUpgradeReq accesses 1059system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.816952 # miss rate for SCUpgradeReq accesses 1060system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1061system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1062system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.223880 # miss rate for ReadExReq accesses 1063system.cpu0.l2cache.ReadExReq_miss_rate::total 0.223880 # miss rate for ReadExReq accesses 1064system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.084826 # miss rate for ReadCleanReq accesses 1065system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.084826 # miss rate for ReadCleanReq accesses 1066system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267124 # miss rate for ReadSharedReq accesses 1067system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267124 # miss rate for ReadSharedReq accesses 1068system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.750042 # miss rate for InvalidateReq accesses 1069system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.750042 # miss rate for InvalidateReq accesses 1070system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022131 # miss rate for demand accesses 1071system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049208 # miss rate for demand accesses 1072system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.084826 # miss rate for demand accesses 1073system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.257061 # miss rate for demand accesses 1074system.cpu0.l2cache.demand_miss_rate::total 0.139777 # miss rate for demand accesses 1075system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022131 # miss rate for overall accesses 1076system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049208 # miss rate for overall accesses 1077system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.084826 # miss rate for overall accesses 1078system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.257061 # miss rate for overall accesses 1079system.cpu0.l2cache.overall_miss_rate::total 0.139777 # miss rate for overall accesses 1080system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47850.642144 # average ReadReq miss latency 1081system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 53899.943117 # average ReadReq miss latency 1082system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50334.914035 # average ReadReq miss latency 1083system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30255.806247 # average UpgradeReq miss latency 1084system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30255.806247 # average UpgradeReq miss latency 1085system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23514.085249 # average SCUpgradeReq miss latency 1086system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23514.085249 # average SCUpgradeReq miss latency 1087system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 617312.375000 # average SCUpgradeFailReq miss latency 1088system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 617312.375000 # average SCUpgradeFailReq miss latency 1089system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69886.551473 # average ReadExReq miss latency 1090system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69886.551473 # average ReadExReq miss latency 1091system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37211.816878 # average ReadCleanReq miss latency 1092system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37211.816878 # average ReadCleanReq miss latency 1093system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43051.359158 # average ReadSharedReq miss latency 1094system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43051.359158 # average ReadSharedReq miss latency 1095system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 121692.637341 # average InvalidateReq miss latency 1096system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 121692.637341 # average InvalidateReq miss latency 1097system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47850.642144 # average overall miss latency 1098system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 53899.943117 # average overall miss latency 1099system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37211.816878 # average overall miss latency 1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48490.212135 # average overall miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::total 44280.582541 # average overall miss latency 1102system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47850.642144 # average overall miss latency 1103system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 53899.943117 # average overall miss latency 1104system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37211.816878 # average overall miss latency 1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48490.212135 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::total 44280.582541 # average overall miss latency 1107system.cpu0.l2cache.blocked_cycles::no_mshrs 189 # number of cycles access was blocked 1108system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1109system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1110system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1111system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 189 # average number of cycles each access was blocked 1112system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1113system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1114system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1115system.cpu0.l2cache.writebacks::writebacks 1489447 # number of writebacks 1116system.cpu0.l2cache.writebacks::total 1489447 # number of writebacks 1117system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1118system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1119system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1120system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9633 # number of ReadExReq MSHR hits 1121system.cpu0.l2cache.ReadExReq_mshr_hits::total 9633 # number of ReadExReq MSHR hits 1122system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits 1123system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 1124system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1299 # number of ReadSharedReq MSHR hits 1125system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1299 # number of ReadSharedReq MSHR hits 1126system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1127system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1128system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits 1129system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10932 # number of demand (read+write) MSHR hits 1130system.cpu0.l2cache.demand_mshr_hits::total 10941 # number of demand (read+write) MSHR hits 1131system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1132system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1133system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits 1134system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10932 # number of overall MSHR hits 1135system.cpu0.l2cache.overall_mshr_hits::total 10941 # number of overall MSHR hits 1136system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12613 # number of ReadReq MSHR misses 1137system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8788 # number of ReadReq MSHR misses 1138system.cpu0.l2cache.ReadReq_mshr_misses::total 21401 # number of ReadReq MSHR misses 1139system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1140system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1141system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 120619 # number of CleanEvict MSHR misses 1142system.cpu0.l2cache.CleanEvict_mshr_misses::total 120619 # number of CleanEvict MSHR misses 1143system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 765315 # number of HardPFReq MSHR misses 1144system.cpu0.l2cache.HardPFReq_mshr_misses::total 765315 # number of HardPFReq MSHR misses 1145system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 135802 # number of UpgradeReq MSHR misses 1146system.cpu0.l2cache.UpgradeReq_mshr_misses::total 135802 # number of UpgradeReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 161268 # number of SCUpgradeReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 161268 # number of SCUpgradeReq MSHR misses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1150system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1151system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 263936 # number of ReadExReq MSHR misses 1152system.cpu0.l2cache.ReadExReq_mshr_misses::total 263936 # number of ReadExReq MSHR misses 1153system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 822157 # number of ReadCleanReq MSHR misses 1154system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 822157 # number of ReadCleanReq MSHR misses 1155system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074916 # number of ReadSharedReq MSHR misses 1156system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074916 # number of ReadSharedReq MSHR misses 1157system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 591539 # number of InvalidateReq MSHR misses 1158system.cpu0.l2cache.InvalidateReq_mshr_misses::total 591539 # number of InvalidateReq MSHR misses 1159system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12613 # number of demand (read+write) MSHR misses 1160system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8788 # number of demand (read+write) MSHR misses 1161system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 822157 # number of demand (read+write) MSHR misses 1162system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1338852 # number of demand (read+write) MSHR misses 1163system.cpu0.l2cache.demand_mshr_misses::total 2182410 # number of demand (read+write) MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12613 # number of overall MSHR misses 1165system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8788 # number of overall MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 822157 # number of overall MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1338852 # number of overall MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 765315 # number of overall MSHR misses 1169system.cpu0.l2cache.overall_mshr_misses::total 2947725 # number of overall MSHR misses 1170system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1171system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14687 # number of ReadReq MSHR uncacheable 1172system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 66996 # number of ReadReq MSHR uncacheable 1173system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15563 # number of WriteReq MSHR uncacheable 1174system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15563 # number of WriteReq MSHR uncacheable 1175system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1176system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30250 # number of overall MSHR uncacheable misses 1177system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 82559 # number of overall MSHR uncacheable misses 1178system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 527895500 # number of ReadReq MSHR miss cycles 1179system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 421006000 # number of ReadReq MSHR miss cycles 1180system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 948901500 # number of ReadReq MSHR miss cycles 1181system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 53668708822 # number of HardPFReq MSHR miss cycles 1182system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 53668708822 # number of HardPFReq MSHR miss cycles 1183system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4760934499 # number of UpgradeReq MSHR miss cycles 1184system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4760934499 # number of UpgradeReq MSHR miss cycles 1185system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3014472000 # number of SCUpgradeReq MSHR miss cycles 1186system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3014472000 # number of SCUpgradeReq MSHR miss cycles 1187system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4572499 # number of SCUpgradeFailReq MSHR miss cycles 1188system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4572499 # number of SCUpgradeFailReq MSHR miss cycles 1189system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16016983500 # number of ReadExReq MSHR miss cycles 1190system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16016983500 # number of ReadExReq MSHR miss cycles 1191system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25660880000 # number of ReadCleanReq MSHR miss cycles 1192system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25660880000 # number of ReadCleanReq MSHR miss cycles 1193system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39766543496 # number of ReadSharedReq MSHR miss cycles 1194system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39766543496 # number of ReadSharedReq MSHR miss cycles 1195system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 68436707000 # number of InvalidateReq MSHR miss cycles 1196system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 68436707000 # number of InvalidateReq MSHR miss cycles 1197system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 527895500 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 421006000 # number of demand (read+write) MSHR miss cycles 1199system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25660880000 # number of demand (read+write) MSHR miss cycles 1200system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 55783526996 # number of demand (read+write) MSHR miss cycles 1201system.cpu0.l2cache.demand_mshr_miss_latency::total 82393308496 # number of demand (read+write) MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 527895500 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 421006000 # number of overall MSHR miss cycles 1204system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25660880000 # number of overall MSHR miss cycles 1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 55783526996 # number of overall MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 53668708822 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.overall_mshr_miss_latency::total 136062017318 # number of overall MSHR miss cycles 1208system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of ReadReq MSHR uncacheable cycles 1209system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2330678000 # number of ReadReq MSHR uncacheable cycles 1210system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9325607000 # number of ReadReq MSHR uncacheable cycles 1211system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2418455500 # number of WriteReq MSHR uncacheable cycles 1212system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2418455500 # number of WriteReq MSHR uncacheable cycles 1213system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of overall MSHR uncacheable cycles 1214system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4749133500 # number of overall MSHR uncacheable cycles 1215system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11744062500 # number of overall MSHR uncacheable cycles 1216system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for ReadReq accesses 1217system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for ReadReq accesses 1218system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028589 # mshr miss rate for ReadReq accesses 1219system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 1220system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 1221system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1222system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1223system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1224system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1225system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552649 # mshr miss rate for UpgradeReq accesses 1226system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552649 # mshr miss rate for UpgradeReq accesses 1227system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.816952 # mshr miss rate for SCUpgradeReq accesses 1228system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816952 # mshr miss rate for SCUpgradeReq accesses 1229system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1230system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1231system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215996 # mshr miss rate for ReadExReq accesses 1232system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215996 # mshr miss rate for ReadExReq accesses 1233system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for ReadCleanReq accesses 1234system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084825 # mshr miss rate for ReadCleanReq accesses 1235system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.266802 # mshr miss rate for ReadSharedReq accesses 1236system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266802 # mshr miss rate for ReadSharedReq accesses 1237system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.750042 # mshr miss rate for InvalidateReq accesses 1238system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.750042 # mshr miss rate for InvalidateReq accesses 1239system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for demand accesses 1240system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for demand accesses 1241system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for demand accesses 1242system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for demand accesses 1243system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139080 # mshr miss rate for demand accesses 1244system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for overall accesses 1245system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for overall accesses 1246system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for overall accesses 1247system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for overall accesses 1248system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1249system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187852 # mshr miss rate for overall accesses 1250system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average ReadReq mshr miss latency 1251system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average ReadReq mshr miss latency 1252system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667 # average ReadReq mshr miss latency 1253system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average HardPFReq mshr miss latency 1254system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396 # average HardPFReq mshr miss latency 1255system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511 # average UpgradeReq mshr miss latency 1256system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511 # average UpgradeReq mshr miss latency 1257system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416 # average SCUpgradeReq mshr miss latency 1258system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416 # average SCUpgradeReq mshr miss latency 1259system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000 # average SCUpgradeFailReq mshr miss latency 1260system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000 # average SCUpgradeFailReq mshr miss latency 1261system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586 # average ReadExReq mshr miss latency 1262system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586 # average ReadExReq mshr miss latency 1263system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average ReadCleanReq mshr miss latency 1264system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222 # average ReadCleanReq mshr miss latency 1265system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259 # average ReadSharedReq mshr miss latency 1266system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259 # average ReadSharedReq mshr miss latency 1267system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341 # average InvalidateReq mshr miss latency 1268system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341 # average InvalidateReq mshr miss latency 1269system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency 1270system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency 1271system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency 1272system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency 1273system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129 # average overall mshr miss latency 1274system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency 1275system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency 1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency 1277system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency 1278system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average overall mshr miss latency 1279system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401 # average overall mshr miss latency 1280system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency 1281system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783 # average ReadReq mshr uncacheable latency 1282system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416 # average ReadReq mshr uncacheable latency 1283system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353 # average WriteReq mshr uncacheable latency 1284system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353 # average WriteReq mshr uncacheable latency 1285system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency 1286system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760 # average overall mshr uncacheable latency 1287system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037 # average overall mshr uncacheable latency 1288system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1289system.cpu0.toL2Bus.snoop_filter.tot_requests 32152230 # Total number of requests made to the snoop filter. 1290system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16420555 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1291system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1292system.cpu0.toL2Bus.snoop_filter.tot_snoops 569005 # Total number of snoops made to the snoop filter. 1293system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 568969 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1294system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1295system.cpu0.toL2Bus.trans_dist::ReadReq 939547 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::ReadResp 14756064 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::WriteReq 15563 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::WriteResp 15563 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::Writeback 5525670 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::CleanEvict 13869690 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::HardPFReq 1023479 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::UpgradeReq 455350 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 356742 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::UpgradeResp 509038 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::ReadExReq 1302016 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::ReadExResp 1231079 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9692338 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5147566 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::InvalidateReq 792720 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::InvalidateResp 788675 # Transaction distribution 1314system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29179671 # Packet count per connected master and slave (bytes) 1315system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19139148 # Packet count per connected master and slave (bytes) 1316system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 387023 # Packet count per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1234112 # Packet count per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_count::total 49939954 # Packet count per connected master and slave (bytes) 1319system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623657344 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598500446 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1429032 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4559656 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu0.toL2Bus.pkt_size::total 1228146478 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu0.toL2Bus.snoops 6651761 # Total snoops (count) 1325system.cpu0.toL2Bus.snoop_fanout::samples 39123003 # Request fanout histogram 1326system.cpu0.toL2Bus.snoop_fanout::mean 0.023394 # Request fanout histogram 1327system.cpu0.toL2Bus.snoop_fanout::stdev 0.151159 # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::0 38207781 97.66% 97.66% # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::1 915186 2.34% 100.00% # Request fanout histogram 1331system.cpu0.toL2Bus.snoop_fanout::2 36 0.00% 100.00% # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1333system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1334system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1335system.cpu0.toL2Bus.snoop_fanout::total 39123003 # Request fanout histogram 1336system.cpu0.toL2Bus.reqLayer0.occupancy 20385491499 # Layer occupancy (ticks) 1337system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1338system.cpu0.toL2Bus.snoopLayer0.occupancy 189810874 # Layer occupancy (ticks) 1339system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1340system.cpu0.toL2Bus.respLayer0.occupancy 14619906616 # Layer occupancy (ticks) 1341system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1342system.cpu0.toL2Bus.respLayer1.occupancy 8517245437 # Layer occupancy (ticks) 1343system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1344system.cpu0.toL2Bus.respLayer2.occupancy 208413461 # Layer occupancy (ticks) 1345system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1346system.cpu0.toL2Bus.respLayer3.occupancy 664225858 # Layer occupancy (ticks) 1347system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1348system.cpu1.branchPred.lookups 135994038 # Number of BP lookups 1349system.cpu1.branchPred.condPredicted 97681271 # Number of conditional branches predicted 1350system.cpu1.branchPred.condIncorrect 5923294 # Number of conditional branches incorrect 1351system.cpu1.branchPred.BTBLookups 101767942 # Number of BTB lookups 1352system.cpu1.branchPred.BTBHits 74881085 # Number of BTB hits 1353system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1354system.cpu1.branchPred.BTBHitPct 73.580229 # BTB Hit Percentage 1355system.cpu1.branchPred.usedRAS 15572056 # Number of times the RAS was used to get a target. 1356system.cpu1.branchPred.RASInCorrect 1048784 # Number of incorrect RAS predictions. 1357system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1358system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1360system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1361system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1362system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1366system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1367system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1368system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1369system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1370system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1371system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1372system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1373system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1374system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1375system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1376system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1377system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1378system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1379system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1380system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1381system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1382system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1383system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1384system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1385system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1386system.cpu1.dtb.walker.walks 278179 # Table walker walks requested 1387system.cpu1.dtb.walker.walksLong 278179 # Table walker walks initiated with long descriptors 1388system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9856 # Level at which table walker walks with long descriptors terminate 1389system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80934 # Level at which table walker walks with long descriptors terminate 1390system.cpu1.dtb.walker.walkWaitTime::samples 278179 # Table walker wait (enqueue to first request) latency 1391system.cpu1.dtb.walker.walkWaitTime::0 278179 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1392system.cpu1.dtb.walker.walkWaitTime::total 278179 # Table walker wait (enqueue to first request) latency 1393system.cpu1.dtb.walker.walkCompletionTime::samples 90790 # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880 # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361 # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882 # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::0-65535 89574 98.66% 98.66% # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::65536-131071 162 0.18% 98.84% # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::131072-196607 899 0.99% 99.83% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.85% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::262144-327679 47 0.05% 99.91% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::327680-393215 21 0.02% 99.93% # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::393216-458751 36 0.04% 99.97% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::total 90790 # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution 1409system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution 1410system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution 1411system.cpu1.dtb.walker.walkPageSizes::4K 80934 89.14% 89.14% # Table walker page sizes translated 1412system.cpu1.dtb.walker.walkPageSizes::2M 9856 10.86% 100.00% # Table walker page sizes translated 1413system.cpu1.dtb.walker.walkPageSizes::total 90790 # Table walker page sizes translated 1414system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 278179 # Table walker requests started/completed, data/inst 1415system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 278179 # Table walker requests started/completed, data/inst 1417system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90790 # Table walker requests started/completed, data/inst 1418system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90790 # Table walker requests started/completed, data/inst 1420system.cpu1.dtb.walker.walkRequestOrigin::total 368969 # Table walker requests started/completed, data/inst 1421system.cpu1.dtb.inst_hits 0 # ITB inst hits 1422system.cpu1.dtb.inst_misses 0 # ITB inst misses 1423system.cpu1.dtb.read_hits 86408994 # DTB read hits 1424system.cpu1.dtb.read_misses 229031 # DTB read misses 1425system.cpu1.dtb.write_hits 76265809 # DTB write hits 1426system.cpu1.dtb.write_misses 49148 # DTB write misses 1427system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1428system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1429system.cpu1.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID 1430system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 1431system.cpu1.dtb.flush_entries 36480 # Number of entries that have been flushed from TLB 1432system.cpu1.dtb.align_faults 1565 # Number of TLB faults due to alignment restrictions 1433system.cpu1.dtb.prefetch_faults 7972 # Number of TLB faults due to prefetch 1434system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1435system.cpu1.dtb.perms_faults 11612 # Number of TLB faults due to permissions restrictions 1436system.cpu1.dtb.read_accesses 86638025 # DTB read accesses 1437system.cpu1.dtb.write_accesses 76314957 # DTB write accesses 1438system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1439system.cpu1.dtb.hits 162674803 # DTB hits 1440system.cpu1.dtb.misses 278179 # DTB misses 1441system.cpu1.dtb.accesses 162952982 # DTB accesses 1442system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1443system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1444system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1445system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1446system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1447system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1448system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1449system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1450system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1451system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1452system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1453system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1454system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1455system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1456system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1457system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1458system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1459system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1460system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1461system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1462system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1463system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1464system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1465system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1466system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1467system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1468system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1469system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1470system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1471system.cpu1.itb.walker.walks 61280 # Table walker walks requested 1472system.cpu1.itb.walker.walksLong 61280 # Table walker walks initiated with long descriptors 1473system.cpu1.itb.walker.walksLongTerminationLevel::Level2 546 # Level at which table walker walks with long descriptors terminate 1474system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52744 # Level at which table walker walks with long descriptors terminate 1475system.cpu1.itb.walker.walkWaitTime::samples 61280 # Table walker wait (enqueue to first request) latency 1476system.cpu1.itb.walker.walkWaitTime::0 61280 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1477system.cpu1.itb.walker.walkWaitTime::total 61280 # Table walker wait (enqueue to first request) latency 1478system.cpu1.itb.walker.walkCompletionTime::samples 53290 # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278 # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296 # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343 # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::0-65535 52075 97.72% 97.72% # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.73% # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::131072-196607 1075 2.02% 99.75% # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.82% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.92% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.05% 99.97% # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::total 53290 # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution 1495system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution 1496system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution 1497system.cpu1.itb.walker.walkPageSizes::4K 52744 98.98% 98.98% # Table walker page sizes translated 1498system.cpu1.itb.walker.walkPageSizes::2M 546 1.02% 100.00% # Table walker page sizes translated 1499system.cpu1.itb.walker.walkPageSizes::total 53290 # Table walker page sizes translated 1500system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1501system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61280 # Table walker requests started/completed, data/inst 1502system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61280 # Table walker requests started/completed, data/inst 1503system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1504system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53290 # Table walker requests started/completed, data/inst 1505system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53290 # Table walker requests started/completed, data/inst 1506system.cpu1.itb.walker.walkRequestOrigin::total 114570 # Table walker requests started/completed, data/inst 1507system.cpu1.itb.inst_hits 242169117 # ITB inst hits 1508system.cpu1.itb.inst_misses 61280 # ITB inst misses 1509system.cpu1.itb.read_hits 0 # DTB read hits 1510system.cpu1.itb.read_misses 0 # DTB read misses 1511system.cpu1.itb.write_hits 0 # DTB write hits 1512system.cpu1.itb.write_misses 0 # DTB write misses 1513system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1514system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1515system.cpu1.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID 1516system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID 1517system.cpu1.itb.flush_entries 25722 # Number of entries that have been flushed from TLB 1518system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1519system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1520system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1521system.cpu1.itb.perms_faults 205735 # Number of TLB faults due to permissions restrictions 1522system.cpu1.itb.read_accesses 0 # DTB read accesses 1523system.cpu1.itb.write_accesses 0 # DTB write accesses 1524system.cpu1.itb.inst_accesses 242230397 # ITB inst accesses 1525system.cpu1.itb.hits 242169117 # DTB hits 1526system.cpu1.itb.misses 61280 # DTB misses 1527system.cpu1.itb.accesses 242230397 # DTB accesses 1528system.cpu1.numCycles 953928196 # number of cpu cycles simulated 1529system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1530system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1531system.cpu1.committedInsts 443058406 # Number of instructions committed 1532system.cpu1.committedOps 521637964 # Number of ops (including micro ops) committed 1533system.cpu1.discardedOps 48259182 # Number of ops (including micro ops) which were discarded before commit 1534system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching 1535system.cpu1.quiesceCycles 94194636881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1536system.cpu1.cpi 2.153053 # CPI: cycles per instruction 1537system.cpu1.ipc 0.464457 # IPC: instructions per cycle 1538system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1539system.cpu1.kern.inst.quiesce 13665 # number of quiesce instructions executed 1540system.cpu1.tickCycles 720990302 # Number of cycles that the object actually ticked 1541system.cpu1.idleCycles 232937894 # Total number of cycles that the object has spent stopped 1542system.cpu1.dcache.tags.replacements 5271409 # number of replacements 1543system.cpu1.dcache.tags.tagsinuse 430.049497 # Cycle average of tags in use 1544system.cpu1.dcache.tags.total_refs 154587010 # Total number of references to valid blocks. 1545system.cpu1.dcache.tags.sampled_refs 5271921 # Sample count of references to valid blocks. 1546system.cpu1.dcache.tags.avg_refs 29.322710 # Average number of references to valid blocks. 1547system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. 1548system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.049497 # Average occupied blocks per requestor 1549system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839940 # Average percentage of cache occupancy 1550system.cpu1.dcache.tags.occ_percent::total 0.839940 # Average percentage of cache occupancy 1551system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1552system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1553system.cpu1.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 1554system.cpu1.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 1555system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1556system.cpu1.dcache.tags.tag_accesses 327906694 # Number of tag accesses 1557system.cpu1.dcache.tags.data_accesses 327906694 # Number of data accesses 1558system.cpu1.dcache.ReadReq_hits::cpu1.data 79069141 # number of ReadReq hits 1559system.cpu1.dcache.ReadReq_hits::total 79069141 # number of ReadReq hits 1560system.cpu1.dcache.WriteReq_hits::cpu1.data 70951579 # number of WriteReq hits 1561system.cpu1.dcache.WriteReq_hits::total 70951579 # number of WriteReq hits 1562system.cpu1.dcache.SoftPFReq_hits::cpu1.data 254478 # number of SoftPFReq hits 1563system.cpu1.dcache.SoftPFReq_hits::total 254478 # number of SoftPFReq hits 1564system.cpu1.dcache.WriteLineReq_hits::cpu1.data 200049 # number of WriteLineReq hits 1565system.cpu1.dcache.WriteLineReq_hits::total 200049 # number of WriteLineReq hits 1566system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1835496 # number of LoadLockedReq hits 1567system.cpu1.dcache.LoadLockedReq_hits::total 1835496 # number of LoadLockedReq hits 1568system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1797284 # number of StoreCondReq hits 1569system.cpu1.dcache.StoreCondReq_hits::total 1797284 # number of StoreCondReq hits 1570system.cpu1.dcache.demand_hits::cpu1.data 150020720 # number of demand (read+write) hits 1571system.cpu1.dcache.demand_hits::total 150020720 # number of demand (read+write) hits 1572system.cpu1.dcache.overall_hits::cpu1.data 150275198 # number of overall hits 1573system.cpu1.dcache.overall_hits::total 150275198 # number of overall hits 1574system.cpu1.dcache.ReadReq_misses::cpu1.data 3348164 # number of ReadReq misses 1575system.cpu1.dcache.ReadReq_misses::total 3348164 # number of ReadReq misses 1576system.cpu1.dcache.WriteReq_misses::cpu1.data 2321727 # number of WriteReq misses 1577system.cpu1.dcache.WriteReq_misses::total 2321727 # number of WriteReq misses 1578system.cpu1.dcache.SoftPFReq_misses::cpu1.data 675333 # number of SoftPFReq misses 1579system.cpu1.dcache.SoftPFReq_misses::total 675333 # number of SoftPFReq misses 1580system.cpu1.dcache.WriteLineReq_misses::cpu1.data 453842 # number of WriteLineReq misses 1581system.cpu1.dcache.WriteLineReq_misses::total 453842 # number of WriteLineReq misses 1582system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 163069 # number of LoadLockedReq misses 1583system.cpu1.dcache.LoadLockedReq_misses::total 163069 # number of LoadLockedReq misses 1584system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199393 # number of StoreCondReq misses 1585system.cpu1.dcache.StoreCondReq_misses::total 199393 # number of StoreCondReq misses 1586system.cpu1.dcache.demand_misses::cpu1.data 5669891 # number of demand (read+write) misses 1587system.cpu1.dcache.demand_misses::total 5669891 # number of demand (read+write) misses 1588system.cpu1.dcache.overall_misses::cpu1.data 6345224 # number of overall misses 1589system.cpu1.dcache.overall_misses::total 6345224 # number of overall misses 1590system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55281073500 # number of ReadReq miss cycles 1591system.cpu1.dcache.ReadReq_miss_latency::total 55281073500 # number of ReadReq miss cycles 1592system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 48428743000 # number of WriteReq miss cycles 1593system.cpu1.dcache.WriteReq_miss_latency::total 48428743000 # number of WriteReq miss cycles 1594system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20617335000 # number of WriteLineReq miss cycles 1595system.cpu1.dcache.WriteLineReq_miss_latency::total 20617335000 # number of WriteLineReq miss cycles 1596system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2629405000 # number of LoadLockedReq miss cycles 1597system.cpu1.dcache.LoadLockedReq_miss_latency::total 2629405000 # number of LoadLockedReq miss cycles 1598system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4686368500 # number of StoreCondReq miss cycles 1599system.cpu1.dcache.StoreCondReq_miss_latency::total 4686368500 # number of StoreCondReq miss cycles 1600system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4186500 # number of StoreCondFailReq miss cycles 1601system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4186500 # number of StoreCondFailReq miss cycles 1602system.cpu1.dcache.demand_miss_latency::cpu1.data 103709816500 # number of demand (read+write) miss cycles 1603system.cpu1.dcache.demand_miss_latency::total 103709816500 # number of demand (read+write) miss cycles 1604system.cpu1.dcache.overall_miss_latency::cpu1.data 103709816500 # number of overall miss cycles 1605system.cpu1.dcache.overall_miss_latency::total 103709816500 # number of overall miss cycles 1606system.cpu1.dcache.ReadReq_accesses::cpu1.data 82417305 # number of ReadReq accesses(hits+misses) 1607system.cpu1.dcache.ReadReq_accesses::total 82417305 # number of ReadReq accesses(hits+misses) 1608system.cpu1.dcache.WriteReq_accesses::cpu1.data 73273306 # number of WriteReq accesses(hits+misses) 1609system.cpu1.dcache.WriteReq_accesses::total 73273306 # number of WriteReq accesses(hits+misses) 1610system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 929811 # number of SoftPFReq accesses(hits+misses) 1611system.cpu1.dcache.SoftPFReq_accesses::total 929811 # number of SoftPFReq accesses(hits+misses) 1612system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653891 # number of WriteLineReq accesses(hits+misses) 1613system.cpu1.dcache.WriteLineReq_accesses::total 653891 # number of WriteLineReq accesses(hits+misses) 1614system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998565 # number of LoadLockedReq accesses(hits+misses) 1615system.cpu1.dcache.LoadLockedReq_accesses::total 1998565 # number of LoadLockedReq accesses(hits+misses) 1616system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1996677 # number of StoreCondReq accesses(hits+misses) 1617system.cpu1.dcache.StoreCondReq_accesses::total 1996677 # number of StoreCondReq accesses(hits+misses) 1618system.cpu1.dcache.demand_accesses::cpu1.data 155690611 # number of demand (read+write) accesses 1619system.cpu1.dcache.demand_accesses::total 155690611 # number of demand (read+write) accesses 1620system.cpu1.dcache.overall_accesses::cpu1.data 156620422 # number of overall (read+write) accesses 1621system.cpu1.dcache.overall_accesses::total 156620422 # number of overall (read+write) accesses 1622system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040625 # miss rate for ReadReq accesses 1623system.cpu1.dcache.ReadReq_miss_rate::total 0.040625 # miss rate for ReadReq accesses 1624system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031686 # miss rate for WriteReq accesses 1625system.cpu1.dcache.WriteReq_miss_rate::total 0.031686 # miss rate for WriteReq accesses 1626system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.726312 # miss rate for SoftPFReq accesses 1627system.cpu1.dcache.SoftPFReq_miss_rate::total 0.726312 # miss rate for SoftPFReq accesses 1628system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.694064 # miss rate for WriteLineReq accesses 1629system.cpu1.dcache.WriteLineReq_miss_rate::total 0.694064 # miss rate for WriteLineReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081593 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081593 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099862 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099862 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036418 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.036418 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040513 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.040513 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873 # average WriteReq miss latency 1642system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057 # average WriteLineReq miss latency 1643system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057 # average WriteLineReq miss latency 1644system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313 # average LoadLockedReq miss latency 1645system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313 # average LoadLockedReq miss latency 1646system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635 # average StoreCondReq miss latency 1647system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635 # average StoreCondReq miss latency 1648system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1649system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1650system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560 # average overall miss latency 1651system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560 # average overall miss latency 1652system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726 # average overall miss latency 1653system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726 # average overall miss latency 1654system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1655system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1656system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1657system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1658system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1659system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1660system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1661system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1662system.cpu1.dcache.writebacks::writebacks 3447609 # number of writebacks 1663system.cpu1.dcache.writebacks::total 3447609 # number of writebacks 1664system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379178 # number of ReadReq MSHR hits 1665system.cpu1.dcache.ReadReq_mshr_hits::total 379178 # number of ReadReq MSHR hits 1666system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 964484 # number of WriteReq MSHR hits 1667system.cpu1.dcache.WriteReq_mshr_hits::total 964484 # number of WriteReq MSHR hits 1668system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 92 # number of WriteLineReq MSHR hits 1669system.cpu1.dcache.WriteLineReq_mshr_hits::total 92 # number of WriteLineReq MSHR hits 1670system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41281 # number of LoadLockedReq MSHR hits 1671system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41281 # number of LoadLockedReq MSHR hits 1672system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits 1673system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits 1674system.cpu1.dcache.demand_mshr_hits::cpu1.data 1343662 # number of demand (read+write) MSHR hits 1675system.cpu1.dcache.demand_mshr_hits::total 1343662 # number of demand (read+write) MSHR hits 1676system.cpu1.dcache.overall_mshr_hits::cpu1.data 1343662 # number of overall MSHR hits 1677system.cpu1.dcache.overall_mshr_hits::total 1343662 # number of overall MSHR hits 1678system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2968986 # number of ReadReq MSHR misses 1679system.cpu1.dcache.ReadReq_mshr_misses::total 2968986 # number of ReadReq MSHR misses 1680system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1357243 # number of WriteReq MSHR misses 1681system.cpu1.dcache.WriteReq_mshr_misses::total 1357243 # number of WriteReq MSHR misses 1682system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 675071 # number of SoftPFReq MSHR misses 1683system.cpu1.dcache.SoftPFReq_mshr_misses::total 675071 # number of SoftPFReq MSHR misses 1684system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 453750 # number of WriteLineReq MSHR misses 1685system.cpu1.dcache.WriteLineReq_mshr_misses::total 453750 # number of WriteLineReq MSHR misses 1686system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121788 # number of LoadLockedReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121788 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199325 # number of StoreCondReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::total 199325 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326229 # number of demand (read+write) MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::total 4326229 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.overall_mshr_misses::cpu1.data 5001300 # number of overall MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::total 5001300 # number of overall MSHR misses 1694system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23522 # number of ReadReq MSHR uncacheable 1695system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23522 # number of ReadReq MSHR uncacheable 1696system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22517 # number of WriteReq MSHR uncacheable 1697system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22517 # number of WriteReq MSHR uncacheable 1698system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46039 # number of overall MSHR uncacheable misses 1699system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46039 # number of overall MSHR uncacheable misses 1700system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44110385000 # number of ReadReq MSHR miss cycles 1701system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44110385000 # number of ReadReq MSHR miss cycles 1702system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27847514500 # number of WriteReq MSHR miss cycles 1703system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27847514500 # number of WriteReq MSHR miss cycles 1704system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16178845000 # number of SoftPFReq MSHR miss cycles 1705system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16178845000 # number of SoftPFReq MSHR miss cycles 1706system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20154706000 # number of WriteLineReq MSHR miss cycles 1707system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20154706000 # number of WriteLineReq MSHR miss cycles 1708system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1764852000 # number of LoadLockedReq MSHR miss cycles 1709system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1764852000 # number of LoadLockedReq MSHR miss cycles 1710system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4482506000 # number of StoreCondReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4482506000 # number of StoreCondReq MSHR miss cycles 1712system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3997500 # number of StoreCondFailReq MSHR miss cycles 1713system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3997500 # number of StoreCondFailReq MSHR miss cycles 1714system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71957899500 # number of demand (read+write) MSHR miss cycles 1715system.cpu1.dcache.demand_mshr_miss_latency::total 71957899500 # number of demand (read+write) MSHR miss cycles 1716system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88136744500 # number of overall MSHR miss cycles 1717system.cpu1.dcache.overall_mshr_miss_latency::total 88136744500 # number of overall MSHR miss cycles 1718system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4055697500 # number of ReadReq MSHR uncacheable cycles 1719system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4055697500 # number of ReadReq MSHR uncacheable cycles 1720system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3925636000 # number of WriteReq MSHR uncacheable cycles 1721system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3925636000 # number of WriteReq MSHR uncacheable cycles 1722system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7981333500 # number of overall MSHR uncacheable cycles 1723system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7981333500 # number of overall MSHR uncacheable cycles 1724system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036024 # mshr miss rate for ReadReq accesses 1725system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036024 # mshr miss rate for ReadReq accesses 1726system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018523 # mshr miss rate for WriteReq accesses 1727system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018523 # mshr miss rate for WriteReq accesses 1728system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.726030 # mshr miss rate for SoftPFReq accesses 1729system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.726030 # mshr miss rate for SoftPFReq accesses 1730system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.693923 # mshr miss rate for WriteLineReq accesses 1731system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.693923 # mshr miss rate for WriteLineReq accesses 1732system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060938 # mshr miss rate for LoadLockedReq accesses 1733system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060938 # mshr miss rate for LoadLockedReq accesses 1734system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099828 # mshr miss rate for StoreCondReq accesses 1735system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099828 # mshr miss rate for StoreCondReq accesses 1736system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027787 # mshr miss rate for demand accesses 1737system.cpu1.dcache.demand_mshr_miss_rate::total 0.027787 # mshr miss rate for demand accesses 1738system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031933 # mshr miss rate for overall accesses 1739system.cpu1.dcache.overall_mshr_miss_rate::total 0.031933 # mshr miss rate for overall accesses 1740system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14857.053890 # average ReadReq mshr miss latency 1741system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14857.053890 # average ReadReq mshr miss latency 1742system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20517.707220 # average WriteReq mshr miss latency 1743system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20517.707220 # average WriteReq mshr miss latency 1744system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23966.138377 # average SoftPFReq mshr miss latency 1745system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23966.138377 # average SoftPFReq mshr miss latency 1746system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44418.084848 # average WriteLineReq mshr miss latency 1747system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44418.084848 # average WriteLineReq mshr miss latency 1748system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14491.181397 # average LoadLockedReq mshr miss latency 1749system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14491.181397 # average LoadLockedReq mshr miss latency 1750system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22488.428446 # average StoreCondReq mshr miss latency 1751system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22488.428446 # average StoreCondReq mshr miss latency 1752system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1753system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1754system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178 # average overall mshr miss latency 1755system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178 # average overall mshr miss latency 1756system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981 # average overall mshr miss latency 1757system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981 # average overall mshr miss latency 1758system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509 # average ReadReq mshr uncacheable latency 1759system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509 # average ReadReq mshr uncacheable latency 1760system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810 # average WriteReq mshr uncacheable latency 1761system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810 # average WriteReq mshr uncacheable latency 1762system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640 # average overall mshr uncacheable latency 1763system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640 # average overall mshr uncacheable latency 1764system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1765system.cpu1.icache.tags.replacements 9020173 # number of replacements 1766system.cpu1.icache.tags.tagsinuse 506.865133 # Cycle average of tags in use 1767system.cpu1.icache.tags.total_refs 232936753 # Total number of references to valid blocks. 1768system.cpu1.icache.tags.sampled_refs 9020685 # Sample count of references to valid blocks. 1769system.cpu1.icache.tags.avg_refs 25.822513 # Average number of references to valid blocks. 1770system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. 1771system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.865133 # Average occupied blocks per requestor 1772system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989971 # Average percentage of cache occupancy 1773system.cpu1.icache.tags.occ_percent::total 0.989971 # Average percentage of cache occupancy 1774system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 1776system.cpu1.icache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 1778system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1779system.cpu1.icache.tags.tag_accesses 492935590 # Number of tag accesses 1780system.cpu1.icache.tags.data_accesses 492935590 # Number of data accesses 1781system.cpu1.icache.ReadReq_hits::cpu1.inst 232936753 # number of ReadReq hits 1782system.cpu1.icache.ReadReq_hits::total 232936753 # number of ReadReq hits 1783system.cpu1.icache.demand_hits::cpu1.inst 232936753 # number of demand (read+write) hits 1784system.cpu1.icache.demand_hits::total 232936753 # number of demand (read+write) hits 1785system.cpu1.icache.overall_hits::cpu1.inst 232936753 # number of overall hits 1786system.cpu1.icache.overall_hits::total 232936753 # number of overall hits 1787system.cpu1.icache.ReadReq_misses::cpu1.inst 9020695 # number of ReadReq misses 1788system.cpu1.icache.ReadReq_misses::total 9020695 # number of ReadReq misses 1789system.cpu1.icache.demand_misses::cpu1.inst 9020695 # number of demand (read+write) misses 1790system.cpu1.icache.demand_misses::total 9020695 # number of demand (read+write) misses 1791system.cpu1.icache.overall_misses::cpu1.inst 9020695 # number of overall misses 1792system.cpu1.icache.overall_misses::total 9020695 # number of overall misses 1793system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95573427500 # number of ReadReq miss cycles 1794system.cpu1.icache.ReadReq_miss_latency::total 95573427500 # number of ReadReq miss cycles 1795system.cpu1.icache.demand_miss_latency::cpu1.inst 95573427500 # number of demand (read+write) miss cycles 1796system.cpu1.icache.demand_miss_latency::total 95573427500 # number of demand (read+write) miss cycles 1797system.cpu1.icache.overall_miss_latency::cpu1.inst 95573427500 # number of overall miss cycles 1798system.cpu1.icache.overall_miss_latency::total 95573427500 # number of overall miss cycles 1799system.cpu1.icache.ReadReq_accesses::cpu1.inst 241957448 # number of ReadReq accesses(hits+misses) 1800system.cpu1.icache.ReadReq_accesses::total 241957448 # number of ReadReq accesses(hits+misses) 1801system.cpu1.icache.demand_accesses::cpu1.inst 241957448 # number of demand (read+write) accesses 1802system.cpu1.icache.demand_accesses::total 241957448 # number of demand (read+write) accesses 1803system.cpu1.icache.overall_accesses::cpu1.inst 241957448 # number of overall (read+write) accesses 1804system.cpu1.icache.overall_accesses::total 241957448 # number of overall (read+write) accesses 1805system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037282 # miss rate for ReadReq accesses 1806system.cpu1.icache.ReadReq_miss_rate::total 0.037282 # miss rate for ReadReq accesses 1807system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037282 # miss rate for demand accesses 1808system.cpu1.icache.demand_miss_rate::total 0.037282 # miss rate for demand accesses 1809system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037282 # miss rate for overall accesses 1810system.cpu1.icache.overall_miss_rate::total 0.037282 # miss rate for overall accesses 1811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10594.907321 # average ReadReq miss latency 1812system.cpu1.icache.ReadReq_avg_miss_latency::total 10594.907321 # average ReadReq miss latency 1813system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency 1814system.cpu1.icache.demand_avg_miss_latency::total 10594.907321 # average overall miss latency 1815system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency 1816system.cpu1.icache.overall_avg_miss_latency::total 10594.907321 # average overall miss latency 1817system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1819system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1821system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1822system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1823system.cpu1.icache.fast_writes 0 # number of fast writes performed 1824system.cpu1.icache.cache_copies 0 # number of cache copies performed 1825system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9020695 # number of ReadReq MSHR misses 1826system.cpu1.icache.ReadReq_mshr_misses::total 9020695 # number of ReadReq MSHR misses 1827system.cpu1.icache.demand_mshr_misses::cpu1.inst 9020695 # number of demand (read+write) MSHR misses 1828system.cpu1.icache.demand_mshr_misses::total 9020695 # number of demand (read+write) MSHR misses 1829system.cpu1.icache.overall_mshr_misses::cpu1.inst 9020695 # number of overall MSHR misses 1830system.cpu1.icache.overall_mshr_misses::total 9020695 # number of overall MSHR misses 1831system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 1832system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 1833system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 1834system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 1835system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91063080500 # number of ReadReq MSHR miss cycles 1836system.cpu1.icache.ReadReq_mshr_miss_latency::total 91063080500 # number of ReadReq MSHR miss cycles 1837system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91063080500 # number of demand (read+write) MSHR miss cycles 1838system.cpu1.icache.demand_mshr_miss_latency::total 91063080500 # number of demand (read+write) MSHR miss cycles 1839system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91063080500 # number of overall MSHR miss cycles 1840system.cpu1.icache.overall_mshr_miss_latency::total 91063080500 # number of overall MSHR miss cycles 1841system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles 1842system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles 1843system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles 1844system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles 1845system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for ReadReq accesses 1846system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037282 # mshr miss rate for ReadReq accesses 1847system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for demand accesses 1848system.cpu1.icache.demand_mshr_miss_rate::total 0.037282 # mshr miss rate for demand accesses 1849system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for overall accesses 1850system.cpu1.icache.overall_mshr_miss_rate::total 0.037282 # mshr miss rate for overall accesses 1851system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average ReadReq mshr miss latency 1852system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10094.907377 # average ReadReq mshr miss latency 1853system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency 1854system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency 1855system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency 1856system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency 1857system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency 1858system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency 1859system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency 1860system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency 1861system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1862system.cpu1.l2cache.prefetcher.num_hwpf_issued 7367099 # number of hwpf issued 1863system.cpu1.l2cache.prefetcher.pfIdentified 7368207 # number of prefetch candidates identified 1864system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue 1865system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1866system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1867system.cpu1.l2cache.prefetcher.pfSpanPage 915185 # number of prefetches not generated due to page crossing 1868system.cpu1.l2cache.tags.replacements 2451047 # number of replacements 1869system.cpu1.l2cache.tags.tagsinuse 13486.856931 # Cycle average of tags in use 1870system.cpu1.l2cache.tags.total_refs 25401363 # Total number of references to valid blocks. 1871system.cpu1.l2cache.tags.sampled_refs 2467204 # Sample count of references to valid blocks. 1872system.cpu1.l2cache.tags.avg_refs 10.295607 # Average number of references to valid blocks. 1873system.cpu1.l2cache.tags.warmup_cycle 9750772511500 # Cycle when the warmup percentage was hit. 1874system.cpu1.l2cache.tags.occ_blocks::writebacks 5534.671535 # Average occupied blocks per requestor 1875system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.865878 # Average occupied blocks per requestor 1876system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.759865 # Average occupied blocks per requestor 1877system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3715.594887 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3131.532678 # Average occupied blocks per requestor 1879system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 956.432088 # Average occupied blocks per requestor 1880system.cpu1.l2cache.tags.occ_percent::writebacks 0.337810 # Average percentage of cache occupancy 1881system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004447 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004624 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.226782 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.191134 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.058376 # Average percentage of cache occupancy 1886system.cpu1.l2cache.tags.occ_percent::total 0.823172 # Average percentage of cache occupancy 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14551 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 709 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2381 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4908 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6029 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id 1904system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 1905system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888123 # Percentage of cache occupancy per task id 1906system.cpu1.l2cache.tags.tag_accesses 480485557 # Number of tag accesses 1907system.cpu1.l2cache.tags.data_accesses 480485557 # Number of data accesses 1908system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 478608 # number of ReadReq hits 1909system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141054 # number of ReadReq hits 1910system.cpu1.l2cache.ReadReq_hits::total 619662 # number of ReadReq hits 1911system.cpu1.l2cache.Writeback_hits::writebacks 3447607 # number of Writeback hits 1912system.cpu1.l2cache.Writeback_hits::total 3447607 # number of Writeback hits 1913system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 76833 # number of UpgradeReq hits 1914system.cpu1.l2cache.UpgradeReq_hits::total 76833 # number of UpgradeReq hits 1915system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 38108 # number of SCUpgradeReq hits 1916system.cpu1.l2cache.SCUpgradeReq_hits::total 38108 # number of SCUpgradeReq hits 1917system.cpu1.l2cache.ReadExReq_hits::cpu1.data 900678 # number of ReadExReq hits 1918system.cpu1.l2cache.ReadExReq_hits::total 900678 # number of ReadExReq hits 1919system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8234691 # number of ReadCleanReq hits 1920system.cpu1.l2cache.ReadCleanReq_hits::total 8234691 # number of ReadCleanReq hits 1921system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2752869 # number of ReadSharedReq hits 1922system.cpu1.l2cache.ReadSharedReq_hits::total 2752869 # number of ReadSharedReq hits 1923system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 182879 # number of InvalidateReq hits 1924system.cpu1.l2cache.InvalidateReq_hits::total 182879 # number of InvalidateReq hits 1925system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 478608 # number of demand (read+write) hits 1926system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141054 # number of demand (read+write) hits 1927system.cpu1.l2cache.demand_hits::cpu1.inst 8234691 # number of demand (read+write) hits 1928system.cpu1.l2cache.demand_hits::cpu1.data 3653547 # number of demand (read+write) hits 1929system.cpu1.l2cache.demand_hits::total 12507900 # number of demand (read+write) hits 1930system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 478608 # number of overall hits 1931system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141054 # number of overall hits 1932system.cpu1.l2cache.overall_hits::cpu1.inst 8234691 # number of overall hits 1933system.cpu1.l2cache.overall_hits::cpu1.data 3653547 # number of overall hits 1934system.cpu1.l2cache.overall_hits::total 12507900 # number of overall hits 1935system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12194 # number of ReadReq misses 1936system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8418 # number of ReadReq misses 1937system.cpu1.l2cache.ReadReq_misses::total 20612 # number of ReadReq misses 1938system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1939system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 1940system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 132767 # number of UpgradeReq misses 1941system.cpu1.l2cache.UpgradeReq_misses::total 132767 # number of UpgradeReq misses 1942system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161216 # number of SCUpgradeReq misses 1943system.cpu1.l2cache.SCUpgradeReq_misses::total 161216 # number of SCUpgradeReq misses 1944system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1945system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1946system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249202 # number of ReadExReq misses 1947system.cpu1.l2cache.ReadExReq_misses::total 249202 # number of ReadExReq misses 1948system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 786004 # number of ReadCleanReq misses 1949system.cpu1.l2cache.ReadCleanReq_misses::total 786004 # number of ReadCleanReq misses 1950system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1012720 # number of ReadSharedReq misses 1951system.cpu1.l2cache.ReadSharedReq_misses::total 1012720 # number of ReadSharedReq misses 1952system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 269177 # number of InvalidateReq misses 1953system.cpu1.l2cache.InvalidateReq_misses::total 269177 # number of InvalidateReq misses 1954system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12194 # number of demand (read+write) misses 1955system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8418 # number of demand (read+write) misses 1956system.cpu1.l2cache.demand_misses::cpu1.inst 786004 # number of demand (read+write) misses 1957system.cpu1.l2cache.demand_misses::cpu1.data 1261922 # number of demand (read+write) misses 1958system.cpu1.l2cache.demand_misses::total 2068538 # number of demand (read+write) misses 1959system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12194 # number of overall misses 1960system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8418 # number of overall misses 1961system.cpu1.l2cache.overall_misses::cpu1.inst 786004 # number of overall misses 1962system.cpu1.l2cache.overall_misses::cpu1.data 1261922 # number of overall misses 1963system.cpu1.l2cache.overall_misses::total 2068538 # number of overall misses 1964system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 602053500 # number of ReadReq miss cycles 1965system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 457478000 # number of ReadReq miss cycles 1966system.cpu1.l2cache.ReadReq_miss_latency::total 1059531500 # number of ReadReq miss cycles 1967system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4022613999 # number of UpgradeReq miss cycles 1968system.cpu1.l2cache.UpgradeReq_miss_latency::total 4022613999 # number of UpgradeReq miss cycles 1969system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3766406500 # number of SCUpgradeReq miss cycles 1970system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3766406500 # number of SCUpgradeReq miss cycles 1971system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3914500 # number of SCUpgradeFailReq miss cycles 1972system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3914500 # number of SCUpgradeFailReq miss cycles 1973system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14165693998 # number of ReadExReq miss cycles 1974system.cpu1.l2cache.ReadExReq_miss_latency::total 14165693998 # number of ReadExReq miss cycles 1975system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 28461637500 # number of ReadCleanReq miss cycles 1976system.cpu1.l2cache.ReadCleanReq_miss_latency::total 28461637500 # number of ReadCleanReq miss cycles 1977system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38316841993 # number of ReadSharedReq miss cycles 1978system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38316841993 # number of ReadSharedReq miss cycles 1979system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18196585000 # number of InvalidateReq miss cycles 1980system.cpu1.l2cache.InvalidateReq_miss_latency::total 18196585000 # number of InvalidateReq miss cycles 1981system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 602053500 # number of demand (read+write) miss cycles 1982system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 457478000 # number of demand (read+write) miss cycles 1983system.cpu1.l2cache.demand_miss_latency::cpu1.inst 28461637500 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.data 52482535991 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::total 82003704991 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 602053500 # number of overall miss cycles 1987system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 457478000 # number of overall miss cycles 1988system.cpu1.l2cache.overall_miss_latency::cpu1.inst 28461637500 # number of overall miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.data 52482535991 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::total 82003704991 # number of overall miss cycles 1991system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 490802 # number of ReadReq accesses(hits+misses) 1992system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149472 # number of ReadReq accesses(hits+misses) 1993system.cpu1.l2cache.ReadReq_accesses::total 640274 # number of ReadReq accesses(hits+misses) 1994system.cpu1.l2cache.Writeback_accesses::writebacks 3447608 # number of Writeback accesses(hits+misses) 1995system.cpu1.l2cache.Writeback_accesses::total 3447608 # number of Writeback accesses(hits+misses) 1996system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209600 # number of UpgradeReq accesses(hits+misses) 1997system.cpu1.l2cache.UpgradeReq_accesses::total 209600 # number of UpgradeReq accesses(hits+misses) 1998system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199324 # number of SCUpgradeReq accesses(hits+misses) 1999system.cpu1.l2cache.SCUpgradeReq_accesses::total 199324 # number of SCUpgradeReq accesses(hits+misses) 2000system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2001system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2002system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1149880 # number of ReadExReq accesses(hits+misses) 2003system.cpu1.l2cache.ReadExReq_accesses::total 1149880 # number of ReadExReq accesses(hits+misses) 2004system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9020695 # number of ReadCleanReq accesses(hits+misses) 2005system.cpu1.l2cache.ReadCleanReq_accesses::total 9020695 # number of ReadCleanReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3765589 # number of ReadSharedReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadSharedReq_accesses::total 3765589 # number of ReadSharedReq accesses(hits+misses) 2008system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452056 # number of InvalidateReq accesses(hits+misses) 2009system.cpu1.l2cache.InvalidateReq_accesses::total 452056 # number of InvalidateReq accesses(hits+misses) 2010system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 490802 # number of demand (read+write) accesses 2011system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149472 # number of demand (read+write) accesses 2012system.cpu1.l2cache.demand_accesses::cpu1.inst 9020695 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.data 4915469 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::total 14576438 # number of demand (read+write) accesses 2015system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 490802 # number of overall (read+write) accesses 2016system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149472 # number of overall (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.inst 9020695 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.data 4915469 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::total 14576438 # number of overall (read+write) accesses 2020system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024845 # miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.056318 # miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::total 0.032192 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 2024system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 2025system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.633430 # miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633430 # miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808814 # miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808814 # miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2031system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.216720 # miss rate for ReadExReq accesses 2032system.cpu1.l2cache.ReadExReq_miss_rate::total 0.216720 # miss rate for ReadExReq accesses 2033system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087133 # miss rate for ReadCleanReq accesses 2034system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087133 # miss rate for ReadCleanReq accesses 2035system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.268941 # miss rate for ReadSharedReq accesses 2036system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.268941 # miss rate for ReadSharedReq accesses 2037system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.595451 # miss rate for InvalidateReq accesses 2038system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.595451 # miss rate for InvalidateReq accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024845 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.056318 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087133 # miss rate for demand accesses 2042system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256725 # miss rate for demand accesses 2043system.cpu1.l2cache.demand_miss_rate::total 0.141910 # miss rate for demand accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024845 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.056318 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087133 # miss rate for overall accesses 2047system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256725 # miss rate for overall accesses 2048system.cpu1.l2cache.overall_miss_rate::total 0.141910 # miss rate for overall accesses 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49372.929309 # average ReadReq miss latency 2050system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54345.212640 # average ReadReq miss latency 2051system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51403.624102 # average ReadReq miss latency 2052system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30298.297009 # average UpgradeReq miss latency 2053system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30298.297009 # average UpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23362.485733 # average SCUpgradeReq miss latency 2055system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23362.485733 # average SCUpgradeReq miss latency 2056system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3914500 # average SCUpgradeFailReq miss latency 2057system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3914500 # average SCUpgradeFailReq miss latency 2058system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56844.222751 # average ReadExReq miss latency 2059system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56844.222751 # average ReadExReq miss latency 2060system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36210.550455 # average ReadCleanReq miss latency 2061system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36210.550455 # average ReadCleanReq miss latency 2062system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37835.573498 # average ReadSharedReq miss latency 2063system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37835.573498 # average ReadSharedReq miss latency 2064system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67600.816563 # average InvalidateReq miss latency 2065system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67600.816563 # average InvalidateReq miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49372.929309 # average overall miss latency 2067system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54345.212640 # average overall miss latency 2068system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36210.550455 # average overall miss latency 2069system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41589.366055 # average overall miss latency 2070system.cpu1.l2cache.demand_avg_miss_latency::total 39643.315709 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49372.929309 # average overall miss latency 2072system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54345.212640 # average overall miss latency 2073system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36210.550455 # average overall miss latency 2074system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41589.366055 # average overall miss latency 2075system.cpu1.l2cache.overall_avg_miss_latency::total 39643.315709 # average overall miss latency 2076system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2077system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2078system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2079system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2080system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2081system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2082system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2083system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2084system.cpu1.l2cache.writebacks::writebacks 1067557 # number of writebacks 2085system.cpu1.l2cache.writebacks::total 1067557 # number of writebacks 2086system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2087system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2088system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 9451 # number of ReadExReq MSHR hits 2089system.cpu1.l2cache.ReadExReq_mshr_hits::total 9451 # number of ReadExReq MSHR hits 2090system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits 2091system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 2092system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1057 # number of ReadSharedReq MSHR hits 2093system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1057 # number of ReadSharedReq MSHR hits 2094system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2095system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2096system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2097system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 2098system.cpu1.l2cache.demand_mshr_hits::cpu1.data 10508 # number of demand (read+write) MSHR hits 2099system.cpu1.l2cache.demand_mshr_hits::total 10515 # number of demand (read+write) MSHR hits 2100system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2101system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 2102system.cpu1.l2cache.overall_mshr_hits::cpu1.data 10508 # number of overall MSHR hits 2103system.cpu1.l2cache.overall_mshr_hits::total 10515 # number of overall MSHR hits 2104system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12194 # number of ReadReq MSHR misses 2105system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8417 # number of ReadReq MSHR misses 2106system.cpu1.l2cache.ReadReq_mshr_misses::total 20611 # number of ReadReq MSHR misses 2107system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 2108system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 2109system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 115832 # number of CleanEvict MSHR misses 2110system.cpu1.l2cache.CleanEvict_mshr_misses::total 115832 # number of CleanEvict MSHR misses 2111system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 735652 # number of HardPFReq MSHR misses 2112system.cpu1.l2cache.HardPFReq_mshr_misses::total 735652 # number of HardPFReq MSHR misses 2113system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 132767 # number of UpgradeReq MSHR misses 2114system.cpu1.l2cache.UpgradeReq_mshr_misses::total 132767 # number of UpgradeReq MSHR misses 2115system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 161216 # number of SCUpgradeReq MSHR misses 2116system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 161216 # number of SCUpgradeReq MSHR misses 2117system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2118system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2119system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 239751 # number of ReadExReq MSHR misses 2120system.cpu1.l2cache.ReadExReq_mshr_misses::total 239751 # number of ReadExReq MSHR misses 2121system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 785998 # number of ReadCleanReq MSHR misses 2122system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 785998 # number of ReadCleanReq MSHR misses 2123system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1011663 # number of ReadSharedReq MSHR misses 2124system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1011663 # number of ReadSharedReq MSHR misses 2125system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 269172 # number of InvalidateReq MSHR misses 2126system.cpu1.l2cache.InvalidateReq_mshr_misses::total 269172 # number of InvalidateReq MSHR misses 2127system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12194 # number of demand (read+write) MSHR misses 2128system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8417 # number of demand (read+write) MSHR misses 2129system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 785998 # number of demand (read+write) MSHR misses 2130system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1251414 # number of demand (read+write) MSHR misses 2131system.cpu1.l2cache.demand_mshr_misses::total 2058023 # number of demand (read+write) MSHR misses 2132system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12194 # number of overall MSHR misses 2133system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8417 # number of overall MSHR misses 2134system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 785998 # number of overall MSHR misses 2135system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1251414 # number of overall MSHR misses 2136system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 735652 # number of overall MSHR misses 2137system.cpu1.l2cache.overall_mshr_misses::total 2793675 # number of overall MSHR misses 2138system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2139system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23522 # number of ReadReq MSHR uncacheable 2140system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23614 # number of ReadReq MSHR uncacheable 2141system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22517 # number of WriteReq MSHR uncacheable 2142system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22517 # number of WriteReq MSHR uncacheable 2143system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2144system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46039 # number of overall MSHR uncacheable misses 2145system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46131 # number of overall MSHR uncacheable misses 2146system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 528889500 # number of ReadReq MSHR miss cycles 2147system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 406963000 # number of ReadReq MSHR miss cycles 2148system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 935852500 # number of ReadReq MSHR miss cycles 2149system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46172311210 # number of HardPFReq MSHR miss cycles 2150system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46172311210 # number of HardPFReq MSHR miss cycles 2151system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4497693492 # number of UpgradeReq MSHR miss cycles 2152system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4497693492 # number of UpgradeReq MSHR miss cycles 2153system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2967096500 # number of SCUpgradeReq MSHR miss cycles 2154system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2967096500 # number of SCUpgradeReq MSHR miss cycles 2155system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3584500 # number of SCUpgradeFailReq MSHR miss cycles 2156system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3584500 # number of SCUpgradeFailReq MSHR miss cycles 2157system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11268741998 # number of ReadExReq MSHR miss cycles 2158system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11268741998 # number of ReadExReq MSHR miss cycles 2159system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 23745516000 # number of ReadCleanReq MSHR miss cycles 2160system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 23745516000 # number of ReadCleanReq MSHR miss cycles 2161system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32172501493 # number of ReadSharedReq MSHR miss cycles 2162system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32172501493 # number of ReadSharedReq MSHR miss cycles 2163system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16580751000 # number of InvalidateReq MSHR miss cycles 2164system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16580751000 # number of InvalidateReq MSHR miss cycles 2165system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 528889500 # number of demand (read+write) MSHR miss cycles 2166system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 406963000 # number of demand (read+write) MSHR miss cycles 2167system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 23745516000 # number of demand (read+write) MSHR miss cycles 2168system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43441243491 # number of demand (read+write) MSHR miss cycles 2169system.cpu1.l2cache.demand_mshr_miss_latency::total 68122611991 # number of demand (read+write) MSHR miss cycles 2170system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 528889500 # number of overall MSHR miss cycles 2171system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 406963000 # number of overall MSHR miss cycles 2172system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 23745516000 # number of overall MSHR miss cycles 2173system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43441243491 # number of overall MSHR miss cycles 2174system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46172311210 # number of overall MSHR miss cycles 2175system.cpu1.l2cache.overall_mshr_miss_latency::total 114294923201 # number of overall MSHR miss cycles 2176system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11784000 # number of ReadReq MSHR uncacheable cycles 2177system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3867463500 # number of ReadReq MSHR uncacheable cycles 2178system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3879247500 # number of ReadReq MSHR uncacheable cycles 2179system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3756742500 # number of WriteReq MSHR uncacheable cycles 2180system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3756742500 # number of WriteReq MSHR uncacheable cycles 2181system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 11784000 # number of overall MSHR uncacheable cycles 2182system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7624206000 # number of overall MSHR uncacheable cycles 2183system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7635990000 # number of overall MSHR uncacheable cycles 2184system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for ReadReq accesses 2185system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for ReadReq accesses 2186system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032191 # mshr miss rate for ReadReq accesses 2187system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 2188system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 2189system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2190system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2191system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2192system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2193system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.633430 # mshr miss rate for UpgradeReq accesses 2194system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.633430 # mshr miss rate for UpgradeReq accesses 2195system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808814 # mshr miss rate for SCUpgradeReq accesses 2196system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808814 # mshr miss rate for SCUpgradeReq accesses 2197system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2198system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2199system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208501 # mshr miss rate for ReadExReq accesses 2200system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208501 # mshr miss rate for ReadExReq accesses 2201system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for ReadCleanReq accesses 2202system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087133 # mshr miss rate for ReadCleanReq accesses 2203system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268660 # mshr miss rate for ReadSharedReq accesses 2204system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268660 # mshr miss rate for ReadSharedReq accesses 2205system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595440 # mshr miss rate for InvalidateReq accesses 2206system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595440 # mshr miss rate for InvalidateReq accesses 2207system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for demand accesses 2208system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for demand accesses 2209system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for demand accesses 2210system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for demand accesses 2211system.cpu1.l2cache.demand_mshr_miss_rate::total 0.141188 # mshr miss rate for demand accesses 2212system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for overall accesses 2213system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for overall accesses 2214system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for overall accesses 2215system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for overall accesses 2216system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2217system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191657 # mshr miss rate for overall accesses 2218system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average ReadReq mshr miss latency 2219system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average ReadReq mshr miss latency 2220system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361 # average ReadReq mshr miss latency 2221system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average HardPFReq mshr miss latency 2222system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851 # average HardPFReq mshr miss latency 2223system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015 # average UpgradeReq mshr miss latency 2224system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015 # average UpgradeReq mshr miss latency 2225system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084 # average SCUpgradeReq mshr miss latency 2226system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084 # average SCUpgradeReq mshr miss latency 2227system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3584500 # average SCUpgradeFailReq mshr miss latency 2228system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3584500 # average SCUpgradeFailReq mshr miss latency 2229system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084 # average ReadExReq mshr miss latency 2230system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084 # average ReadExReq mshr miss latency 2231system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average ReadCleanReq mshr miss latency 2232system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025 # average ReadCleanReq mshr miss latency 2233system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439 # average ReadSharedReq mshr miss latency 2234system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439 # average ReadSharedReq mshr miss latency 2235system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773 # average InvalidateReq mshr miss latency 2236system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773 # average InvalidateReq mshr miss latency 2237system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency 2238system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency 2239system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency 2240system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency 2241system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437 # average overall mshr miss latency 2242system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency 2243system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency 2244system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency 2245system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency 2246system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average overall mshr miss latency 2247system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789 # average overall mshr miss latency 2248system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency 2249system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732 # average ReadReq mshr uncacheable latency 2250system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348 # average ReadReq mshr uncacheable latency 2251system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236 # average WriteReq mshr uncacheable latency 2252system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236 # average WriteReq mshr uncacheable latency 2253system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency 2254system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978 # average overall mshr uncacheable latency 2255system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551 # average overall mshr uncacheable latency 2256system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2257system.cpu1.toL2Bus.snoop_filter.tot_requests 29416501 # Total number of requests made to the snoop filter. 2258system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15028447 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2259system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2260system.cpu1.toL2Bus.snoop_filter.tot_snoops 554511 # Total number of snoops made to the snoop filter. 2261system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 554502 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2262system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 9 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2263system.cpu1.toL2Bus.trans_dist::ReadReq 803941 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::ReadResp 13684916 # Transaction distribution 2265system.cpu1.toL2Bus.trans_dist::WriteReq 22517 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::WriteResp 22517 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::Writeback 4553047 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::CleanEvict 13043260 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::HardPFReq 982334 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::UpgradeReq 414162 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358438 # Transaction distribution 2273system.cpu1.toL2Bus.trans_dist::UpgradeResp 473685 # Transaction distribution 2274system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution 2275system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 2276system.cpu1.toL2Bus.trans_dist::ReadExReq 1229561 # Transaction distribution 2277system.cpu1.toL2Bus.trans_dist::ReadExResp 1158646 # Transaction distribution 2278system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9020695 # Transaction distribution 2279system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4893253 # Transaction distribution 2280system.cpu1.toL2Bus.trans_dist::InvalidateReq 460729 # Transaction distribution 2281system.cpu1.toL2Bus.trans_dist::InvalidateResp 452056 # Transaction distribution 2282system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27060072 # Packet count per connected master and slave (bytes) 2283system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17084009 # Packet count per connected master and slave (bytes) 2284system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332493 # Packet count per connected master and slave (bytes) 2285system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1088108 # Packet count per connected master and slave (bytes) 2286system.cpu1.toL2Bus.pkt_count::total 45564682 # Packet count per connected master and slave (bytes) 2287system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 577330304 # Cumulative packet size per connected master and slave (bytes) 2288system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 542008212 # Cumulative packet size per connected master and slave (bytes) 2289system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1195776 # Cumulative packet size per connected master and slave (bytes) 2290system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3926416 # Cumulative packet size per connected master and slave (bytes) 2291system.cpu1.toL2Bus.pkt_size::total 1124460708 # Cumulative packet size per connected master and slave (bytes) 2292system.cpu1.toL2Bus.snoops 6177589 # Total snoops (count) 2293system.cpu1.toL2Bus.snoop_fanout::samples 35784390 # Request fanout histogram 2294system.cpu1.toL2Bus.snoop_fanout::mean 0.024790 # Request fanout histogram 2295system.cpu1.toL2Bus.snoop_fanout::stdev 0.155485 # Request fanout histogram 2296system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2297system.cpu1.toL2Bus.snoop_fanout::0 34897315 97.52% 97.52% # Request fanout histogram 2298system.cpu1.toL2Bus.snoop_fanout::1 887066 2.48% 100.00% # Request fanout histogram 2299system.cpu1.toL2Bus.snoop_fanout::2 9 0.00% 100.00% # Request fanout histogram 2300system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2301system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2302system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2303system.cpu1.toL2Bus.snoop_fanout::total 35784390 # Request fanout histogram 2304system.cpu1.toL2Bus.reqLayer0.occupancy 18416469994 # Layer occupancy (ticks) 2305system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2306system.cpu1.toL2Bus.snoopLayer0.occupancy 187934075 # Layer occupancy (ticks) 2307system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2308system.cpu1.toL2Bus.respLayer0.occupancy 13533732383 # Layer occupancy (ticks) 2309system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2310system.cpu1.toL2Bus.respLayer1.occupancy 7841048470 # Layer occupancy (ticks) 2311system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2312system.cpu1.toL2Bus.respLayer2.occupancy 183047447 # Layer occupancy (ticks) 2313system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2314system.cpu1.toL2Bus.respLayer3.occupancy 597345920 # Layer occupancy (ticks) 2315system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2316system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 2317system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 2318system.iobus.trans_dist::WriteReq 136603 # Transaction distribution 2319system.iobus.trans_dist::WriteResp 136603 # Transaction distribution 2320system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47670 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2333system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2334system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2335system.iobus.pkt_count_system.bridge.master::total 122552 # Packet count per connected master and slave (bytes) 2336system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231256 # Packet count per connected master and slave (bytes) 2337system.iobus.pkt_count_system.realview.ide.dma::total 231256 # Packet count per connected master and slave (bytes) 2338system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2339system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2340system.iobus.pkt_count::total 353888 # Packet count per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47690 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2354system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2355system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2356system.iobus.pkt_size_system.bridge.master::total 155682 # Cumulative packet size per connected master and slave (bytes) 2357system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339040 # Cumulative packet size per connected master and slave (bytes) 2358system.iobus.pkt_size_system.realview.ide.dma::total 7339040 # Cumulative packet size per connected master and slave (bytes) 2359system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2360system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2361system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) 2362system.iobus.reqLayer0.occupancy 36193000 # Layer occupancy (ticks) 2363system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2365system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2367system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2369system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2371system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2373system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2375system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2377system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2379system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2380system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2381system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2382system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 2383system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2384system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2385system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2386system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2387system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2388system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2389system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2390system.iobus.reqLayer27.occupancy 566159223 # Layer occupancy (ticks) 2391system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2392system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2393system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2394system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) 2395system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2396system.iobus.respLayer3.occupancy 147952000 # Layer occupancy (ticks) 2397system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2398system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2399system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2400system.iocache.tags.replacements 115609 # number of replacements 2401system.iocache.tags.tagsinuse 11.261931 # Cycle average of tags in use 2402system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2403system.iocache.tags.sampled_refs 115625 # Sample count of references to valid blocks. 2404system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2405system.iocache.tags.warmup_cycle 9146785142000 # Cycle when the warmup percentage was hit. 2406system.iocache.tags.occ_blocks::realview.ethernet 3.823570 # Average occupied blocks per requestor 2407system.iocache.tags.occ_blocks::realview.ide 7.438361 # Average occupied blocks per requestor 2408system.iocache.tags.occ_percent::realview.ethernet 0.238973 # Average percentage of cache occupancy 2409system.iocache.tags.occ_percent::realview.ide 0.464898 # Average percentage of cache occupancy 2410system.iocache.tags.occ_percent::total 0.703871 # Average percentage of cache occupancy 2411system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2412system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2413system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2414system.iocache.tags.tag_accesses 1041009 # Number of tag accesses 2415system.iocache.tags.data_accesses 1041009 # Number of data accesses 2416system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2417system.iocache.ReadReq_misses::realview.ide 8900 # number of ReadReq misses 2418system.iocache.ReadReq_misses::total 8937 # number of ReadReq misses 2419system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2420system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2421system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2422system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2423system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2424system.iocache.demand_misses::realview.ide 8900 # number of demand (read+write) misses 2425system.iocache.demand_misses::total 8940 # number of demand (read+write) misses 2426system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2427system.iocache.overall_misses::realview.ide 8900 # number of overall misses 2428system.iocache.overall_misses::total 8940 # number of overall misses 2429system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2430system.iocache.ReadReq_miss_latency::realview.ide 1696302972 # number of ReadReq miss cycles 2431system.iocache.ReadReq_miss_latency::total 1701497972 # number of ReadReq miss cycles 2432system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2433system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2434system.iocache.WriteLineReq_miss_latency::realview.ide 13913628251 # number of WriteLineReq miss cycles 2435system.iocache.WriteLineReq_miss_latency::total 13913628251 # number of WriteLineReq miss cycles 2436system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2437system.iocache.demand_miss_latency::realview.ide 1696302972 # number of demand (read+write) miss cycles 2438system.iocache.demand_miss_latency::total 1701866972 # number of demand (read+write) miss cycles 2439system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2440system.iocache.overall_miss_latency::realview.ide 1696302972 # number of overall miss cycles 2441system.iocache.overall_miss_latency::total 1701866972 # number of overall miss cycles 2442system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2443system.iocache.ReadReq_accesses::realview.ide 8900 # number of ReadReq accesses(hits+misses) 2444system.iocache.ReadReq_accesses::total 8937 # number of ReadReq accesses(hits+misses) 2445system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2446system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2447system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2448system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2449system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2450system.iocache.demand_accesses::realview.ide 8900 # number of demand (read+write) accesses 2451system.iocache.demand_accesses::total 8940 # number of demand (read+write) accesses 2452system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2453system.iocache.overall_accesses::realview.ide 8900 # number of overall (read+write) accesses 2454system.iocache.overall_accesses::total 8940 # number of overall (read+write) accesses 2455system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2456system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2457system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2458system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2459system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2460system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2461system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2462system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2463system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2464system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2465system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2466system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2467system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2468system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2469system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551 # average ReadReq miss latency 2470system.iocache.ReadReq_avg_miss_latency::total 190388.046548 # average ReadReq miss latency 2471system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2472system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2473system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803 # average WriteLineReq miss latency 2474system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803 # average WriteLineReq miss latency 2475system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2476system.iocache.demand_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency 2477system.iocache.demand_avg_miss_latency::total 190365.433110 # average overall miss latency 2478system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2479system.iocache.overall_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency 2480system.iocache.overall_avg_miss_latency::total 190365.433110 # average overall miss latency 2481system.iocache.blocked_cycles::no_mshrs 34247 # number of cycles access was blocked 2482system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2483system.iocache.blocked::no_mshrs 3593 # number of cycles access was blocked 2484system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2485system.iocache.avg_blocked_cycles::no_mshrs 9.531589 # average number of cycles each access was blocked 2486system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2487system.iocache.fast_writes 0 # number of fast writes performed 2488system.iocache.cache_copies 0 # number of cache copies performed 2489system.iocache.writebacks::writebacks 106694 # number of writebacks 2490system.iocache.writebacks::total 106694 # number of writebacks 2491system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2492system.iocache.ReadReq_mshr_misses::realview.ide 8900 # number of ReadReq MSHR misses 2493system.iocache.ReadReq_mshr_misses::total 8937 # number of ReadReq MSHR misses 2494system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2495system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2496system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2497system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2498system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2499system.iocache.demand_mshr_misses::realview.ide 8900 # number of demand (read+write) MSHR misses 2500system.iocache.demand_mshr_misses::total 8940 # number of demand (read+write) MSHR misses 2501system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2502system.iocache.overall_mshr_misses::realview.ide 8900 # number of overall MSHR misses 2503system.iocache.overall_mshr_misses::total 8940 # number of overall MSHR misses 2504system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2505system.iocache.ReadReq_mshr_miss_latency::realview.ide 1251302972 # number of ReadReq MSHR miss cycles 2506system.iocache.ReadReq_mshr_miss_latency::total 1254647972 # number of ReadReq MSHR miss cycles 2507system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2508system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2509system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8577228251 # number of WriteLineReq MSHR miss cycles 2510system.iocache.WriteLineReq_mshr_miss_latency::total 8577228251 # number of WriteLineReq MSHR miss cycles 2511system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2512system.iocache.demand_mshr_miss_latency::realview.ide 1251302972 # number of demand (read+write) MSHR miss cycles 2513system.iocache.demand_mshr_miss_latency::total 1254866972 # number of demand (read+write) MSHR miss cycles 2514system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2515system.iocache.overall_mshr_miss_latency::realview.ide 1251302972 # number of overall MSHR miss cycles 2516system.iocache.overall_mshr_miss_latency::total 1254866972 # number of overall MSHR miss cycles 2517system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2518system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2519system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2520system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2521system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2522system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2523system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2524system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2525system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2526system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2527system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2528system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2529system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2530system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2531system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140595.839551 # average ReadReq mshr miss latency 2532system.iocache.ReadReq_avg_mshr_miss_latency::total 140388.046548 # average ReadReq mshr miss latency 2533system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2534system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2535system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803 # average WriteLineReq mshr miss latency 2536system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803 # average WriteLineReq mshr miss latency 2537system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2538system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency 2539system.iocache.demand_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency 2540system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2541system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency 2542system.iocache.overall_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency 2543system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2544system.l2c.tags.replacements 1566664 # number of replacements 2545system.l2c.tags.tagsinuse 63931.901156 # Cycle average of tags in use 2546system.l2c.tags.total_refs 6426547 # Total number of references to valid blocks. 2547system.l2c.tags.sampled_refs 1627093 # Sample count of references to valid blocks. 2548system.l2c.tags.avg_refs 3.949711 # Average number of references to valid blocks. 2549system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2550system.l2c.tags.occ_blocks::writebacks 17340.299819 # Average occupied blocks per requestor 2551system.l2c.tags.occ_blocks::cpu0.dtb.walker 183.189406 # Average occupied blocks per requestor 2552system.l2c.tags.occ_blocks::cpu0.itb.walker 209.040410 # Average occupied blocks per requestor 2553system.l2c.tags.occ_blocks::cpu0.inst 5130.513561 # Average occupied blocks per requestor 2554system.l2c.tags.occ_blocks::cpu0.data 11368.638005 # Average occupied blocks per requestor 2555system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11382.688685 # Average occupied blocks per requestor 2556system.l2c.tags.occ_blocks::cpu1.dtb.walker 175.831777 # Average occupied blocks per requestor 2557system.l2c.tags.occ_blocks::cpu1.itb.walker 202.455245 # Average occupied blocks per requestor 2558system.l2c.tags.occ_blocks::cpu1.inst 3752.541531 # Average occupied blocks per requestor 2559system.l2c.tags.occ_blocks::cpu1.data 4974.040380 # Average occupied blocks per requestor 2560system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9212.662336 # Average occupied blocks per requestor 2561system.l2c.tags.occ_percent::writebacks 0.264592 # Average percentage of cache occupancy 2562system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002795 # Average percentage of cache occupancy 2563system.l2c.tags.occ_percent::cpu0.itb.walker 0.003190 # Average percentage of cache occupancy 2564system.l2c.tags.occ_percent::cpu0.inst 0.078285 # Average percentage of cache occupancy 2565system.l2c.tags.occ_percent::cpu0.data 0.173472 # Average percentage of cache occupancy 2566system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173686 # Average percentage of cache occupancy 2567system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002683 # Average percentage of cache occupancy 2568system.l2c.tags.occ_percent::cpu1.itb.walker 0.003089 # Average percentage of cache occupancy 2569system.l2c.tags.occ_percent::cpu1.inst 0.057259 # Average percentage of cache occupancy 2570system.l2c.tags.occ_percent::cpu1.data 0.075898 # Average percentage of cache occupancy 2571system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140574 # Average percentage of cache occupancy 2572system.l2c.tags.occ_percent::total 0.975523 # Average percentage of cache occupancy 2573system.l2c.tags.occ_task_id_blocks::1022 9887 # Occupied blocks per task id 2574system.l2c.tags.occ_task_id_blocks::1023 204 # Occupied blocks per task id 2575system.l2c.tags.occ_task_id_blocks::1024 50338 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2577system.l2c.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id 2578system.l2c.tags.age_task_id_blocks_1022::3 389 # Occupied blocks per task id 2579system.l2c.tags.age_task_id_blocks_1022::4 9395 # Occupied blocks per task id 2580system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2581system.l2c.tags.age_task_id_blocks_1023::4 202 # Occupied blocks per task id 2582system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 2583system.l2c.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 2584system.l2c.tags.age_task_id_blocks_1024::2 1895 # Occupied blocks per task id 2585system.l2c.tags.age_task_id_blocks_1024::3 5328 # Occupied blocks per task id 2586system.l2c.tags.age_task_id_blocks_1024::4 42935 # Occupied blocks per task id 2587system.l2c.tags.occ_task_id_percent::1022 0.150864 # Percentage of cache occupancy per task id 2588system.l2c.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 2589system.l2c.tags.occ_task_id_percent::1024 0.768097 # Percentage of cache occupancy per task id 2590system.l2c.tags.tag_accesses 77438610 # Number of tag accesses 2591system.l2c.tags.data_accesses 77438610 # Number of data accesses 2592system.l2c.Writeback_hits::writebacks 2557006 # number of Writeback hits 2593system.l2c.Writeback_hits::total 2557006 # number of Writeback hits 2594system.l2c.UpgradeReq_hits::cpu0.data 27501 # number of UpgradeReq hits 2595system.l2c.UpgradeReq_hits::cpu1.data 32544 # number of UpgradeReq hits 2596system.l2c.UpgradeReq_hits::total 60045 # number of UpgradeReq hits 2597system.l2c.SCUpgradeReq_hits::cpu0.data 6218 # number of SCUpgradeReq hits 2598system.l2c.SCUpgradeReq_hits::cpu1.data 5959 # number of SCUpgradeReq hits 2599system.l2c.SCUpgradeReq_hits::total 12177 # number of SCUpgradeReq hits 2600system.l2c.ReadExReq_hits::cpu0.data 161499 # number of ReadExReq hits 2601system.l2c.ReadExReq_hits::cpu1.data 176783 # number of ReadExReq hits 2602system.l2c.ReadExReq_hits::total 338282 # number of ReadExReq hits 2603system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6423 # number of ReadSharedReq hits 2604system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4133 # number of ReadSharedReq hits 2605system.l2c.ReadSharedReq_hits::cpu0.inst 754192 # number of ReadSharedReq hits 2606system.l2c.ReadSharedReq_hits::cpu0.data 613728 # number of ReadSharedReq hits 2607system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292319 # number of ReadSharedReq hits 2608system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6682 # number of ReadSharedReq hits 2609system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4427 # number of ReadSharedReq hits 2610system.l2c.ReadSharedReq_hits::cpu1.inst 728293 # number of ReadSharedReq hits 2611system.l2c.ReadSharedReq_hits::cpu1.data 606746 # number of ReadSharedReq hits 2612system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 315465 # number of ReadSharedReq hits 2613system.l2c.ReadSharedReq_hits::total 3332408 # number of ReadSharedReq hits 2614system.l2c.demand_hits::cpu0.dtb.walker 6423 # number of demand (read+write) hits 2615system.l2c.demand_hits::cpu0.itb.walker 4133 # number of demand (read+write) hits 2616system.l2c.demand_hits::cpu0.inst 754192 # number of demand (read+write) hits 2617system.l2c.demand_hits::cpu0.data 775227 # number of demand (read+write) hits 2618system.l2c.demand_hits::cpu0.l2cache.prefetcher 292319 # number of demand (read+write) hits 2619system.l2c.demand_hits::cpu1.dtb.walker 6682 # number of demand (read+write) hits 2620system.l2c.demand_hits::cpu1.itb.walker 4427 # number of demand (read+write) hits 2621system.l2c.demand_hits::cpu1.inst 728293 # number of demand (read+write) hits 2622system.l2c.demand_hits::cpu1.data 783529 # number of demand (read+write) hits 2623system.l2c.demand_hits::cpu1.l2cache.prefetcher 315465 # number of demand (read+write) hits 2624system.l2c.demand_hits::total 3670690 # number of demand (read+write) hits 2625system.l2c.overall_hits::cpu0.dtb.walker 6423 # number of overall hits 2626system.l2c.overall_hits::cpu0.itb.walker 4133 # number of overall hits 2627system.l2c.overall_hits::cpu0.inst 754192 # number of overall hits 2628system.l2c.overall_hits::cpu0.data 775227 # number of overall hits 2629system.l2c.overall_hits::cpu0.l2cache.prefetcher 292319 # number of overall hits 2630system.l2c.overall_hits::cpu1.dtb.walker 6682 # number of overall hits 2631system.l2c.overall_hits::cpu1.itb.walker 4427 # number of overall hits 2632system.l2c.overall_hits::cpu1.inst 728293 # number of overall hits 2633system.l2c.overall_hits::cpu1.data 783529 # number of overall hits 2634system.l2c.overall_hits::cpu1.l2cache.prefetcher 315465 # number of overall hits 2635system.l2c.overall_hits::total 3670690 # number of overall hits 2636system.l2c.UpgradeReq_misses::cpu0.data 45718 # number of UpgradeReq misses 2637system.l2c.UpgradeReq_misses::cpu1.data 43728 # number of UpgradeReq misses 2638system.l2c.UpgradeReq_misses::total 89446 # number of UpgradeReq misses 2639system.l2c.SCUpgradeReq_misses::cpu0.data 9327 # number of SCUpgradeReq misses 2640system.l2c.SCUpgradeReq_misses::cpu1.data 8734 # number of SCUpgradeReq misses 2641system.l2c.SCUpgradeReq_misses::total 18061 # number of SCUpgradeReq misses 2642system.l2c.ReadExReq_misses::cpu0.data 514166 # number of ReadExReq misses 2643system.l2c.ReadExReq_misses::cpu1.data 145895 # number of ReadExReq misses 2644system.l2c.ReadExReq_misses::total 660061 # number of ReadExReq misses 2645system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2392 # number of ReadSharedReq misses 2646system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2135 # number of ReadSharedReq misses 2647system.l2c.ReadSharedReq_misses::cpu0.inst 67965 # number of ReadSharedReq misses 2648system.l2c.ReadSharedReq_misses::cpu0.data 161112 # number of ReadSharedReq misses 2649system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 279683 # number of ReadSharedReq misses 2650system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2412 # number of ReadSharedReq misses 2651system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2026 # number of ReadSharedReq misses 2652system.l2c.ReadSharedReq_misses::cpu1.inst 57704 # number of ReadSharedReq misses 2653system.l2c.ReadSharedReq_misses::cpu1.data 110574 # number of ReadSharedReq misses 2654system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 234171 # number of ReadSharedReq misses 2655system.l2c.ReadSharedReq_misses::total 920174 # number of ReadSharedReq misses 2656system.l2c.demand_misses::cpu0.dtb.walker 2392 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu0.itb.walker 2135 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu0.inst 67965 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu0.data 675278 # number of demand (read+write) misses 2660system.l2c.demand_misses::cpu0.l2cache.prefetcher 279683 # number of demand (read+write) misses 2661system.l2c.demand_misses::cpu1.dtb.walker 2412 # number of demand (read+write) misses 2662system.l2c.demand_misses::cpu1.itb.walker 2026 # number of demand (read+write) misses 2663system.l2c.demand_misses::cpu1.inst 57704 # number of demand (read+write) misses 2664system.l2c.demand_misses::cpu1.data 256469 # number of demand (read+write) misses 2665system.l2c.demand_misses::cpu1.l2cache.prefetcher 234171 # number of demand (read+write) misses 2666system.l2c.demand_misses::total 1580235 # number of demand (read+write) misses 2667system.l2c.overall_misses::cpu0.dtb.walker 2392 # number of overall misses 2668system.l2c.overall_misses::cpu0.itb.walker 2135 # number of overall misses 2669system.l2c.overall_misses::cpu0.inst 67965 # number of overall misses 2670system.l2c.overall_misses::cpu0.data 675278 # number of overall misses 2671system.l2c.overall_misses::cpu0.l2cache.prefetcher 279683 # number of overall misses 2672system.l2c.overall_misses::cpu1.dtb.walker 2412 # number of overall misses 2673system.l2c.overall_misses::cpu1.itb.walker 2026 # number of overall misses 2674system.l2c.overall_misses::cpu1.inst 57704 # number of overall misses 2675system.l2c.overall_misses::cpu1.data 256469 # number of overall misses 2676system.l2c.overall_misses::cpu1.l2cache.prefetcher 234171 # number of overall misses 2677system.l2c.overall_misses::total 1580235 # number of overall misses 2678system.l2c.UpgradeReq_miss_latency::cpu0.data 695263000 # number of UpgradeReq miss cycles 2679system.l2c.UpgradeReq_miss_latency::cpu1.data 645953500 # number of UpgradeReq miss cycles 2680system.l2c.UpgradeReq_miss_latency::total 1341216500 # number of UpgradeReq miss cycles 2681system.l2c.SCUpgradeReq_miss_latency::cpu0.data 147547000 # number of SCUpgradeReq miss cycles 2682system.l2c.SCUpgradeReq_miss_latency::cpu1.data 132765000 # number of SCUpgradeReq miss cycles 2683system.l2c.SCUpgradeReq_miss_latency::total 280312000 # number of SCUpgradeReq miss cycles 2684system.l2c.ReadExReq_miss_latency::cpu0.data 74695360000 # number of ReadExReq miss cycles 2685system.l2c.ReadExReq_miss_latency::cpu1.data 20188019500 # number of ReadExReq miss cycles 2686system.l2c.ReadExReq_miss_latency::total 94883379500 # number of ReadExReq miss cycles 2687system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 336047000 # number of ReadSharedReq miss cycles 2688system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 299166500 # number of ReadSharedReq miss cycles 2689system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9148970000 # number of ReadSharedReq miss cycles 2690system.l2c.ReadSharedReq_miss_latency::cpu0.data 22699764499 # number of ReadSharedReq miss cycles 2691system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 48351113314 # number of ReadSharedReq miss cycles 2692system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 341784000 # number of ReadSharedReq miss cycles 2693system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 288119000 # number of ReadSharedReq miss cycles 2694system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7798345000 # number of ReadSharedReq miss cycles 2695system.l2c.ReadSharedReq_miss_latency::cpu1.data 15621099500 # number of ReadSharedReq miss cycles 2696system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40579265809 # number of ReadSharedReq miss cycles 2697system.l2c.ReadSharedReq_miss_latency::total 145463674622 # number of ReadSharedReq miss cycles 2698system.l2c.demand_miss_latency::cpu0.dtb.walker 336047000 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu0.itb.walker 299166500 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu0.inst 9148970000 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu0.data 97395124499 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48351113314 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.dtb.walker 341784000 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::cpu1.itb.walker 288119000 # number of demand (read+write) miss cycles 2705system.l2c.demand_miss_latency::cpu1.inst 7798345000 # number of demand (read+write) miss cycles 2706system.l2c.demand_miss_latency::cpu1.data 35809119000 # number of demand (read+write) miss cycles 2707system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40579265809 # number of demand (read+write) miss cycles 2708system.l2c.demand_miss_latency::total 240347054122 # number of demand (read+write) miss cycles 2709system.l2c.overall_miss_latency::cpu0.dtb.walker 336047000 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu0.itb.walker 299166500 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu0.inst 9148970000 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu0.data 97395124499 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48351113314 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.dtb.walker 341784000 # number of overall miss cycles 2715system.l2c.overall_miss_latency::cpu1.itb.walker 288119000 # number of overall miss cycles 2716system.l2c.overall_miss_latency::cpu1.inst 7798345000 # number of overall miss cycles 2717system.l2c.overall_miss_latency::cpu1.data 35809119000 # number of overall miss cycles 2718system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40579265809 # number of overall miss cycles 2719system.l2c.overall_miss_latency::total 240347054122 # number of overall miss cycles 2720system.l2c.Writeback_accesses::writebacks 2557006 # number of Writeback accesses(hits+misses) 2721system.l2c.Writeback_accesses::total 2557006 # number of Writeback accesses(hits+misses) 2722system.l2c.UpgradeReq_accesses::cpu0.data 73219 # number of UpgradeReq accesses(hits+misses) 2723system.l2c.UpgradeReq_accesses::cpu1.data 76272 # number of UpgradeReq accesses(hits+misses) 2724system.l2c.UpgradeReq_accesses::total 149491 # number of UpgradeReq accesses(hits+misses) 2725system.l2c.SCUpgradeReq_accesses::cpu0.data 15545 # number of SCUpgradeReq accesses(hits+misses) 2726system.l2c.SCUpgradeReq_accesses::cpu1.data 14693 # number of SCUpgradeReq accesses(hits+misses) 2727system.l2c.SCUpgradeReq_accesses::total 30238 # number of SCUpgradeReq accesses(hits+misses) 2728system.l2c.ReadExReq_accesses::cpu0.data 675665 # number of ReadExReq accesses(hits+misses) 2729system.l2c.ReadExReq_accesses::cpu1.data 322678 # number of ReadExReq accesses(hits+misses) 2730system.l2c.ReadExReq_accesses::total 998343 # number of ReadExReq accesses(hits+misses) 2731system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8815 # number of ReadSharedReq accesses(hits+misses) 2732system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6268 # number of ReadSharedReq accesses(hits+misses) 2733system.l2c.ReadSharedReq_accesses::cpu0.inst 822157 # number of ReadSharedReq accesses(hits+misses) 2734system.l2c.ReadSharedReq_accesses::cpu0.data 774840 # number of ReadSharedReq accesses(hits+misses) 2735system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 572002 # number of ReadSharedReq accesses(hits+misses) 2736system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9094 # number of ReadSharedReq accesses(hits+misses) 2737system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6453 # number of ReadSharedReq accesses(hits+misses) 2738system.l2c.ReadSharedReq_accesses::cpu1.inst 785997 # number of ReadSharedReq accesses(hits+misses) 2739system.l2c.ReadSharedReq_accesses::cpu1.data 717320 # number of ReadSharedReq accesses(hits+misses) 2740system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 549636 # number of ReadSharedReq accesses(hits+misses) 2741system.l2c.ReadSharedReq_accesses::total 4252582 # number of ReadSharedReq accesses(hits+misses) 2742system.l2c.demand_accesses::cpu0.dtb.walker 8815 # number of demand (read+write) accesses 2743system.l2c.demand_accesses::cpu0.itb.walker 6268 # number of demand (read+write) accesses 2744system.l2c.demand_accesses::cpu0.inst 822157 # number of demand (read+write) accesses 2745system.l2c.demand_accesses::cpu0.data 1450505 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu0.l2cache.prefetcher 572002 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu1.dtb.walker 9094 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::cpu1.itb.walker 6453 # number of demand (read+write) accesses 2749system.l2c.demand_accesses::cpu1.inst 785997 # number of demand (read+write) accesses 2750system.l2c.demand_accesses::cpu1.data 1039998 # number of demand (read+write) accesses 2751system.l2c.demand_accesses::cpu1.l2cache.prefetcher 549636 # number of demand (read+write) accesses 2752system.l2c.demand_accesses::total 5250925 # number of demand (read+write) accesses 2753system.l2c.overall_accesses::cpu0.dtb.walker 8815 # number of overall (read+write) accesses 2754system.l2c.overall_accesses::cpu0.itb.walker 6268 # number of overall (read+write) accesses 2755system.l2c.overall_accesses::cpu0.inst 822157 # number of overall (read+write) accesses 2756system.l2c.overall_accesses::cpu0.data 1450505 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu0.l2cache.prefetcher 572002 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu1.dtb.walker 9094 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::cpu1.itb.walker 6453 # number of overall (read+write) accesses 2760system.l2c.overall_accesses::cpu1.inst 785997 # number of overall (read+write) accesses 2761system.l2c.overall_accesses::cpu1.data 1039998 # number of overall (read+write) accesses 2762system.l2c.overall_accesses::cpu1.l2cache.prefetcher 549636 # number of overall (read+write) accesses 2763system.l2c.overall_accesses::total 5250925 # number of overall (read+write) accesses 2764system.l2c.UpgradeReq_miss_rate::cpu0.data 0.624401 # miss rate for UpgradeReq accesses 2765system.l2c.UpgradeReq_miss_rate::cpu1.data 0.573317 # miss rate for UpgradeReq accesses 2766system.l2c.UpgradeReq_miss_rate::total 0.598337 # miss rate for UpgradeReq accesses 2767system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.600000 # miss rate for SCUpgradeReq accesses 2768system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.594433 # miss rate for SCUpgradeReq accesses 2769system.l2c.SCUpgradeReq_miss_rate::total 0.597295 # miss rate for SCUpgradeReq accesses 2770system.l2c.ReadExReq_miss_rate::cpu0.data 0.760978 # miss rate for ReadExReq accesses 2771system.l2c.ReadExReq_miss_rate::cpu1.data 0.452138 # miss rate for ReadExReq accesses 2772system.l2c.ReadExReq_miss_rate::total 0.661157 # miss rate for ReadExReq accesses 2773system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.271356 # miss rate for ReadSharedReq accesses 2774system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.340619 # miss rate for ReadSharedReq accesses 2775system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.082667 # miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.207929 # miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.488955 # miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.265230 # miss rate for ReadSharedReq accesses 2779system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.313962 # miss rate for ReadSharedReq accesses 2780system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.073415 # miss rate for ReadSharedReq accesses 2781system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.154149 # miss rate for ReadSharedReq accesses 2782system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.426047 # miss rate for ReadSharedReq accesses 2783system.l2c.ReadSharedReq_miss_rate::total 0.216380 # miss rate for ReadSharedReq accesses 2784system.l2c.demand_miss_rate::cpu0.dtb.walker 0.271356 # miss rate for demand accesses 2785system.l2c.demand_miss_rate::cpu0.itb.walker 0.340619 # miss rate for demand accesses 2786system.l2c.demand_miss_rate::cpu0.inst 0.082667 # miss rate for demand accesses 2787system.l2c.demand_miss_rate::cpu0.data 0.465547 # miss rate for demand accesses 2788system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.488955 # miss rate for demand accesses 2789system.l2c.demand_miss_rate::cpu1.dtb.walker 0.265230 # miss rate for demand accesses 2790system.l2c.demand_miss_rate::cpu1.itb.walker 0.313962 # miss rate for demand accesses 2791system.l2c.demand_miss_rate::cpu1.inst 0.073415 # miss rate for demand accesses 2792system.l2c.demand_miss_rate::cpu1.data 0.246605 # miss rate for demand accesses 2793system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.426047 # miss rate for demand accesses 2794system.l2c.demand_miss_rate::total 0.300944 # miss rate for demand accesses 2795system.l2c.overall_miss_rate::cpu0.dtb.walker 0.271356 # miss rate for overall accesses 2796system.l2c.overall_miss_rate::cpu0.itb.walker 0.340619 # miss rate for overall accesses 2797system.l2c.overall_miss_rate::cpu0.inst 0.082667 # miss rate for overall accesses 2798system.l2c.overall_miss_rate::cpu0.data 0.465547 # miss rate for overall accesses 2799system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.488955 # miss rate for overall accesses 2800system.l2c.overall_miss_rate::cpu1.dtb.walker 0.265230 # miss rate for overall accesses 2801system.l2c.overall_miss_rate::cpu1.itb.walker 0.313962 # miss rate for overall accesses 2802system.l2c.overall_miss_rate::cpu1.inst 0.073415 # miss rate for overall accesses 2803system.l2c.overall_miss_rate::cpu1.data 0.246605 # miss rate for overall accesses 2804system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.426047 # miss rate for overall accesses 2805system.l2c.overall_miss_rate::total 0.300944 # miss rate for overall accesses 2806system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15207.642504 # average UpgradeReq miss latency 2807system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14772.079674 # average UpgradeReq miss latency 2808system.l2c.UpgradeReq_avg_miss_latency::total 14994.706303 # average UpgradeReq miss latency 2809system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15819.341696 # average SCUpgradeReq miss latency 2810system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15200.938860 # average SCUpgradeReq miss latency 2811system.l2c.SCUpgradeReq_avg_miss_latency::total 15520.292343 # average SCUpgradeReq miss latency 2812system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145274.794522 # average ReadExReq miss latency 2813system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138373.621440 # average ReadExReq miss latency 2814system.l2c.ReadExReq_avg_miss_latency::total 143749.410282 # average ReadExReq miss latency 2815system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140487.876254 # average ReadSharedReq miss latency 2816system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140124.824356 # average ReadSharedReq miss latency 2817system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134612.962554 # average ReadSharedReq miss latency 2818system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140894.312646 # average ReadSharedReq miss latency 2819system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449 # average ReadSharedReq miss latency 2820system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141701.492537 # average ReadSharedReq miss latency 2821system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142210.760118 # average ReadSharedReq miss latency 2822system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135143.924165 # average ReadSharedReq miss latency 2823system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141272.808255 # average ReadSharedReq miss latency 2824system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558 # average ReadSharedReq miss latency 2825system.l2c.ReadSharedReq_avg_miss_latency::total 158082.791539 # average ReadSharedReq miss latency 2826system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140487.876254 # average overall miss latency 2827system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140124.824356 # average overall miss latency 2828system.l2c.demand_avg_miss_latency::cpu0.inst 134612.962554 # average overall miss latency 2829system.l2c.demand_avg_miss_latency::cpu0.data 144229.672074 # average overall miss latency 2830system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449 # average overall miss latency 2831system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141701.492537 # average overall miss latency 2832system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142210.760118 # average overall miss latency 2833system.l2c.demand_avg_miss_latency::cpu1.inst 135143.924165 # average overall miss latency 2834system.l2c.demand_avg_miss_latency::cpu1.data 139623.576339 # average overall miss latency 2835system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558 # average overall miss latency 2836system.l2c.demand_avg_miss_latency::total 152095.766846 # average overall miss latency 2837system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140487.876254 # average overall miss latency 2838system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140124.824356 # average overall miss latency 2839system.l2c.overall_avg_miss_latency::cpu0.inst 134612.962554 # average overall miss latency 2840system.l2c.overall_avg_miss_latency::cpu0.data 144229.672074 # average overall miss latency 2841system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449 # average overall miss latency 2842system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141701.492537 # average overall miss latency 2843system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142210.760118 # average overall miss latency 2844system.l2c.overall_avg_miss_latency::cpu1.inst 135143.924165 # average overall miss latency 2845system.l2c.overall_avg_miss_latency::cpu1.data 139623.576339 # average overall miss latency 2846system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558 # average overall miss latency 2847system.l2c.overall_avg_miss_latency::total 152095.766846 # average overall miss latency 2848system.l2c.blocked_cycles::no_mshrs 4391 # number of cycles access was blocked 2849system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2850system.l2c.blocked::no_mshrs 34 # number of cycles access was blocked 2851system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2852system.l2c.avg_blocked_cycles::no_mshrs 129.147059 # average number of cycles each access was blocked 2853system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2854system.l2c.fast_writes 0 # number of fast writes performed 2855system.l2c.cache_copies 0 # number of cache copies performed 2856system.l2c.writebacks::writebacks 1195231 # number of writebacks 2857system.l2c.writebacks::total 1195231 # number of writebacks 2858system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 267 # number of ReadSharedReq MSHR hits 2859system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits 2860system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadSharedReq MSHR hits 2861system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 293 # number of ReadSharedReq MSHR hits 2862system.l2c.ReadSharedReq_mshr_hits::cpu1.data 44 # number of ReadSharedReq MSHR hits 2863system.l2c.ReadSharedReq_mshr_hits::total 630 # number of ReadSharedReq MSHR hits 2864system.l2c.demand_mshr_hits::cpu0.inst 267 # number of demand (read+write) MSHR hits 2865system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits 2866system.l2c.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2867system.l2c.demand_mshr_hits::cpu1.inst 293 # number of demand (read+write) MSHR hits 2868system.l2c.demand_mshr_hits::cpu1.data 44 # number of demand (read+write) MSHR hits 2869system.l2c.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits 2870system.l2c.overall_mshr_hits::cpu0.inst 267 # number of overall MSHR hits 2871system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits 2872system.l2c.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2873system.l2c.overall_mshr_hits::cpu1.inst 293 # number of overall MSHR hits 2874system.l2c.overall_mshr_hits::cpu1.data 44 # number of overall MSHR hits 2875system.l2c.overall_mshr_hits::total 630 # number of overall MSHR hits 2876system.l2c.CleanEvict_mshr_misses::writebacks 55441 # number of CleanEvict MSHR misses 2877system.l2c.CleanEvict_mshr_misses::total 55441 # number of CleanEvict MSHR misses 2878system.l2c.UpgradeReq_mshr_misses::cpu0.data 45718 # number of UpgradeReq MSHR misses 2879system.l2c.UpgradeReq_mshr_misses::cpu1.data 43728 # number of UpgradeReq MSHR misses 2880system.l2c.UpgradeReq_mshr_misses::total 89446 # number of UpgradeReq MSHR misses 2881system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9327 # number of SCUpgradeReq MSHR misses 2882system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8734 # number of SCUpgradeReq MSHR misses 2883system.l2c.SCUpgradeReq_mshr_misses::total 18061 # number of SCUpgradeReq MSHR misses 2884system.l2c.ReadExReq_mshr_misses::cpu0.data 514166 # number of ReadExReq MSHR misses 2885system.l2c.ReadExReq_mshr_misses::cpu1.data 145895 # number of ReadExReq MSHR misses 2886system.l2c.ReadExReq_mshr_misses::total 660061 # number of ReadExReq MSHR misses 2887system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2392 # number of ReadSharedReq MSHR misses 2888system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2135 # number of ReadSharedReq MSHR misses 2889system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 67698 # number of ReadSharedReq MSHR misses 2890system.l2c.ReadSharedReq_mshr_misses::cpu0.data 161089 # number of ReadSharedReq MSHR misses 2891system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 279683 # number of ReadSharedReq MSHR misses 2892system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2409 # number of ReadSharedReq MSHR misses 2893system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2026 # number of ReadSharedReq MSHR misses 2894system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57411 # number of ReadSharedReq MSHR misses 2895system.l2c.ReadSharedReq_mshr_misses::cpu1.data 110530 # number of ReadSharedReq MSHR misses 2896system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 234171 # number of ReadSharedReq MSHR misses 2897system.l2c.ReadSharedReq_mshr_misses::total 919544 # number of ReadSharedReq MSHR misses 2898system.l2c.demand_mshr_misses::cpu0.dtb.walker 2392 # number of demand (read+write) MSHR misses 2899system.l2c.demand_mshr_misses::cpu0.itb.walker 2135 # number of demand (read+write) MSHR misses 2900system.l2c.demand_mshr_misses::cpu0.inst 67698 # number of demand (read+write) MSHR misses 2901system.l2c.demand_mshr_misses::cpu0.data 675255 # number of demand (read+write) MSHR misses 2902system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 279683 # number of demand (read+write) MSHR misses 2903system.l2c.demand_mshr_misses::cpu1.dtb.walker 2409 # number of demand (read+write) MSHR misses 2904system.l2c.demand_mshr_misses::cpu1.itb.walker 2026 # number of demand (read+write) MSHR misses 2905system.l2c.demand_mshr_misses::cpu1.inst 57411 # number of demand (read+write) MSHR misses 2906system.l2c.demand_mshr_misses::cpu1.data 256425 # number of demand (read+write) MSHR misses 2907system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 234171 # number of demand (read+write) MSHR misses 2908system.l2c.demand_mshr_misses::total 1579605 # number of demand (read+write) MSHR misses 2909system.l2c.overall_mshr_misses::cpu0.dtb.walker 2392 # number of overall MSHR misses 2910system.l2c.overall_mshr_misses::cpu0.itb.walker 2135 # number of overall MSHR misses 2911system.l2c.overall_mshr_misses::cpu0.inst 67698 # number of overall MSHR misses 2912system.l2c.overall_mshr_misses::cpu0.data 675255 # number of overall MSHR misses 2913system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 279683 # number of overall MSHR misses 2914system.l2c.overall_mshr_misses::cpu1.dtb.walker 2409 # number of overall MSHR misses 2915system.l2c.overall_mshr_misses::cpu1.itb.walker 2026 # number of overall MSHR misses 2916system.l2c.overall_mshr_misses::cpu1.inst 57411 # number of overall MSHR misses 2917system.l2c.overall_mshr_misses::cpu1.data 256425 # number of overall MSHR misses 2918system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 234171 # number of overall MSHR misses 2919system.l2c.overall_mshr_misses::total 1579605 # number of overall MSHR misses 2920system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 2921system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14687 # number of ReadReq MSHR uncacheable 2922system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2923system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23520 # number of ReadReq MSHR uncacheable 2924system.l2c.ReadReq_mshr_uncacheable::total 90608 # number of ReadReq MSHR uncacheable 2925system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15563 # number of WriteReq MSHR uncacheable 2926system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22517 # number of WriteReq MSHR uncacheable 2927system.l2c.WriteReq_mshr_uncacheable::total 38080 # number of WriteReq MSHR uncacheable 2928system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2929system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30250 # number of overall MSHR uncacheable misses 2930system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2931system.l2c.overall_mshr_uncacheable_misses::cpu1.data 46037 # number of overall MSHR uncacheable misses 2932system.l2c.overall_mshr_uncacheable_misses::total 128688 # number of overall MSHR uncacheable misses 2933system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3363963001 # number of UpgradeReq MSHR miss cycles 2934system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3216758006 # number of UpgradeReq MSHR miss cycles 2935system.l2c.UpgradeReq_mshr_miss_latency::total 6580721007 # number of UpgradeReq MSHR miss cycles 2936system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 713326000 # number of SCUpgradeReq MSHR miss cycles 2937system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 668745000 # number of SCUpgradeReq MSHR miss cycles 2938system.l2c.SCUpgradeReq_mshr_miss_latency::total 1382071000 # number of SCUpgradeReq MSHR miss cycles 2939system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 69553700000 # number of ReadExReq MSHR miss cycles 2940system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18729069500 # number of ReadExReq MSHR miss cycles 2941system.l2c.ReadExReq_mshr_miss_latency::total 88282769500 # number of ReadExReq MSHR miss cycles 2942system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 312127000 # number of ReadSharedReq MSHR miss cycles 2943system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 277816500 # number of ReadSharedReq MSHR miss cycles 2944system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8440331000 # number of ReadSharedReq MSHR miss cycles 2945system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 21085969999 # number of ReadSharedReq MSHR miss cycles 2946system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 45554283314 # number of ReadSharedReq MSHR miss cycles 2947system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 317283000 # number of ReadSharedReq MSHR miss cycles 2948system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 267859000 # number of ReadSharedReq MSHR miss cycles 2949system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7188979000 # number of ReadSharedReq MSHR miss cycles 2950system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14510492000 # number of ReadSharedReq MSHR miss cycles 2951system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38237555809 # number of ReadSharedReq MSHR miss cycles 2952system.l2c.ReadSharedReq_mshr_miss_latency::total 136192696622 # number of ReadSharedReq MSHR miss cycles 2953system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 312127000 # number of demand (read+write) MSHR miss cycles 2954system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 277816500 # number of demand (read+write) MSHR miss cycles 2955system.l2c.demand_mshr_miss_latency::cpu0.inst 8440331000 # number of demand (read+write) MSHR miss cycles 2956system.l2c.demand_mshr_miss_latency::cpu0.data 90639669999 # number of demand (read+write) MSHR miss cycles 2957system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 45554283314 # number of demand (read+write) MSHR miss cycles 2958system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 317283000 # number of demand (read+write) MSHR miss cycles 2959system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 267859000 # number of demand (read+write) MSHR miss cycles 2960system.l2c.demand_mshr_miss_latency::cpu1.inst 7188979000 # number of demand (read+write) MSHR miss cycles 2961system.l2c.demand_mshr_miss_latency::cpu1.data 33239561500 # number of demand (read+write) MSHR miss cycles 2962system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 38237555809 # number of demand (read+write) MSHR miss cycles 2963system.l2c.demand_mshr_miss_latency::total 224475466122 # number of demand (read+write) MSHR miss cycles 2964system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 312127000 # number of overall MSHR miss cycles 2965system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 277816500 # number of overall MSHR miss cycles 2966system.l2c.overall_mshr_miss_latency::cpu0.inst 8440331000 # number of overall MSHR miss cycles 2967system.l2c.overall_mshr_miss_latency::cpu0.data 90639669999 # number of overall MSHR miss cycles 2968system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 45554283314 # number of overall MSHR miss cycles 2969system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 317283000 # number of overall MSHR miss cycles 2970system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 267859000 # number of overall MSHR miss cycles 2971system.l2c.overall_mshr_miss_latency::cpu1.inst 7188979000 # number of overall MSHR miss cycles 2972system.l2c.overall_mshr_miss_latency::cpu1.data 33239561500 # number of overall MSHR miss cycles 2973system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38237555809 # number of overall MSHR miss cycles 2974system.l2c.overall_mshr_miss_latency::total 224475466122 # number of overall MSHR miss cycles 2975system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of ReadReq MSHR uncacheable cycles 2976system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2066285000 # number of ReadReq MSHR uncacheable cycles 2977system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9850500 # number of ReadReq MSHR uncacheable cycles 2978system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3444063500 # number of ReadReq MSHR uncacheable cycles 2979system.l2c.ReadReq_mshr_uncacheable_latency::total 11416639000 # number of ReadReq MSHR uncacheable cycles 2980system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153864000 # number of WriteReq MSHR uncacheable cycles 2981system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3373941000 # number of WriteReq MSHR uncacheable cycles 2982system.l2c.WriteReq_mshr_uncacheable_latency::total 5527805000 # number of WriteReq MSHR uncacheable cycles 2983system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of overall MSHR uncacheable cycles 2984system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4220149000 # number of overall MSHR uncacheable cycles 2985system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9850500 # number of overall MSHR uncacheable cycles 2986system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6818004500 # number of overall MSHR uncacheable cycles 2987system.l2c.overall_mshr_uncacheable_latency::total 16944444000 # number of overall MSHR uncacheable cycles 2988system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2989system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2990system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.624401 # mshr miss rate for UpgradeReq accesses 2991system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.573317 # mshr miss rate for UpgradeReq accesses 2992system.l2c.UpgradeReq_mshr_miss_rate::total 0.598337 # mshr miss rate for UpgradeReq accesses 2993system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 2994system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.594433 # mshr miss rate for SCUpgradeReq accesses 2995system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.597295 # mshr miss rate for SCUpgradeReq accesses 2996system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.760978 # mshr miss rate for ReadExReq accesses 2997system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452138 # mshr miss rate for ReadExReq accesses 2998system.l2c.ReadExReq_mshr_miss_rate::total 0.661157 # mshr miss rate for ReadExReq accesses 2999system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for ReadSharedReq accesses 3000system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for ReadSharedReq accesses 3001system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for ReadSharedReq accesses 3002system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207900 # mshr miss rate for ReadSharedReq accesses 3003system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for ReadSharedReq accesses 3004system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for ReadSharedReq accesses 3005system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for ReadSharedReq accesses 3006system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for ReadSharedReq accesses 3007system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.154087 # mshr miss rate for ReadSharedReq accesses 3008system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for ReadSharedReq accesses 3009system.l2c.ReadSharedReq_mshr_miss_rate::total 0.216232 # mshr miss rate for ReadSharedReq accesses 3010system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for demand accesses 3011system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for demand accesses 3012system.l2c.demand_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for demand accesses 3013system.l2c.demand_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for demand accesses 3014system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for demand accesses 3015system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for demand accesses 3016system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for demand accesses 3017system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for demand accesses 3018system.l2c.demand_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for demand accesses 3019system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for demand accesses 3020system.l2c.demand_mshr_miss_rate::total 0.300824 # mshr miss rate for demand accesses 3021system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for overall accesses 3022system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for overall accesses 3023system.l2c.overall_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for overall accesses 3024system.l2c.overall_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for overall accesses 3025system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for overall accesses 3026system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for overall accesses 3027system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for overall accesses 3028system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for overall accesses 3029system.l2c.overall_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for overall accesses 3030system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for overall accesses 3031system.l2c.overall_mshr_miss_rate::total 0.300824 # mshr miss rate for overall accesses 3032system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73580.712214 # average UpgradeReq mshr miss latency 3033system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73562.888904 # average UpgradeReq mshr miss latency 3034system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73571.998826 # average UpgradeReq mshr miss latency 3035system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76479.682642 # average SCUpgradeReq mshr miss latency 3036system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76568.010076 # average SCUpgradeReq mshr miss latency 3037system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76522.396324 # average SCUpgradeReq mshr miss latency 3038system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135274.794522 # average ReadExReq mshr miss latency 3039system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128373.621440 # average ReadExReq mshr miss latency 3040system.l2c.ReadExReq_avg_mshr_miss_latency::total 133749.410282 # average ReadExReq mshr miss latency 3041system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average ReadSharedReq mshr miss latency 3042system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average ReadSharedReq mshr miss latency 3043system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average ReadSharedReq mshr miss latency 3044system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130896.398879 # average ReadSharedReq mshr miss latency 3045system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average ReadSharedReq mshr miss latency 3046system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average ReadSharedReq mshr miss latency 3047system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average ReadSharedReq mshr miss latency 3048system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average ReadSharedReq mshr miss latency 3049system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131281.027775 # average ReadSharedReq mshr miss latency 3050system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average ReadSharedReq mshr miss latency 3051system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 148108.950330 # average ReadSharedReq mshr miss latency 3052system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency 3053system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency 3054system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency 3055system.l2c.demand_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency 3056system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency 3057system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency 3058system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency 3059system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency 3060system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency 3061system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency 3062system.l2c.demand_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency 3063system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency 3064system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency 3065system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency 3066system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency 3067system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency 3068system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency 3069system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency 3070system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency 3071system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency 3072system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency 3073system.l2c.overall_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency 3074system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency 3075system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422 # average ReadReq mshr uncacheable latency 3076system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency 3077system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259 # average ReadReq mshr uncacheable latency 3078system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133 # average ReadReq mshr uncacheable latency 3079system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126 # average WriteReq mshr uncacheable latency 3080system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100 # average WriteReq mshr uncacheable latency 3081system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429 # average WriteReq mshr uncacheable latency 3082system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency 3083system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851 # average overall mshr uncacheable latency 3084system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency 3085system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531 # average overall mshr uncacheable latency 3086system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530 # average overall mshr uncacheable latency 3087system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3088system.membus.trans_dist::ReadReq 90608 # Transaction distribution 3089system.membus.trans_dist::ReadResp 1019089 # Transaction distribution 3090system.membus.trans_dist::WriteReq 38080 # Transaction distribution 3091system.membus.trans_dist::WriteResp 38080 # Transaction distribution 3092system.membus.trans_dist::Writeback 1301925 # Transaction distribution 3093system.membus.trans_dist::CleanEvict 271570 # Transaction distribution 3094system.membus.trans_dist::UpgradeReq 429176 # Transaction distribution 3095system.membus.trans_dist::SCUpgradeReq 310200 # Transaction distribution 3096system.membus.trans_dist::UpgradeResp 115027 # Transaction distribution 3097system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3098system.membus.trans_dist::ReadExReq 674063 # Transaction distribution 3099system.membus.trans_dist::ReadExResp 652544 # Transaction distribution 3100system.membus.trans_dist::ReadSharedReq 928481 # Transaction distribution 3101system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3102system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3103system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122552 # Packet count per connected master and slave (bytes) 3104system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3105system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24802 # Packet count per connected master and slave (bytes) 3106system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5589312 # Packet count per connected master and slave (bytes) 3107system.membus.pkt_count_system.l2c.mem_side::total 5736718 # Packet count per connected master and slave (bytes) 3108system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342877 # Packet count per connected master and slave (bytes) 3109system.membus.pkt_count_system.iocache.mem_side::total 342877 # Packet count per connected master and slave (bytes) 3110system.membus.pkt_count::total 6079595 # Packet count per connected master and slave (bytes) 3111system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155682 # Cumulative packet size per connected master and slave (bytes) 3112system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3113system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49604 # Cumulative packet size per connected master and slave (bytes) 3114system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180435584 # Cumulative packet size per connected master and slave (bytes) 3115system.membus.pkt_size_system.l2c.mem_side::total 180642194 # Cumulative packet size per connected master and slave (bytes) 3116system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274816 # Cumulative packet size per connected master and slave (bytes) 3117system.membus.pkt_size_system.iocache.mem_side::total 7274816 # Cumulative packet size per connected master and slave (bytes) 3118system.membus.pkt_size::total 187917010 # Cumulative packet size per connected master and slave (bytes) 3119system.membus.snoops 648574 # Total snoops (count) 3120system.membus.snoop_fanout::samples 4152999 # Request fanout histogram 3121system.membus.snoop_fanout::mean 1 # Request fanout histogram 3122system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3123system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3124system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3125system.membus.snoop_fanout::1 4152999 100.00% 100.00% # Request fanout histogram 3126system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3127system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3128system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3129system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3130system.membus.snoop_fanout::total 4152999 # Request fanout histogram 3131system.membus.reqLayer0.occupancy 109607499 # Layer occupancy (ticks) 3132system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3133system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3134system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3135system.membus.reqLayer2.occupancy 20503498 # Layer occupancy (ticks) 3136system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3137system.membus.reqLayer5.occupancy 9125026082 # Layer occupancy (ticks) 3138system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3139system.membus.respLayer2.occupancy 8873044520 # Layer occupancy (ticks) 3140system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3141system.membus.respLayer3.occupancy 230408874 # Layer occupancy (ticks) 3142system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3143system.realview.ethernet.txBytes 966 # Bytes Transmitted 3144system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3145system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3146system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3147system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3148system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3149system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3150system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3151system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3152system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 3153system.realview.ethernet.totPackets 3 # Total Packets 3154system.realview.ethernet.totBytes 966 # Total Bytes 3155system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3156system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 3157system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3158system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3159system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3160system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3161system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3162system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3163system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3164system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3165system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3166system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3167system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3168system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3169system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3170system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3171system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3172system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3173system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3174system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3175system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3176system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3177system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3178system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3179system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3180system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3181system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3182system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3183system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3184system.realview.ethernet.droppedPackets 0 # number of packets dropped 3185system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3186system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3187system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3188system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3189system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3190system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3191system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3192system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3193system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3194system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3195system.toL2Bus.snoop_filter.tot_requests 12411375 # Total number of requests made to the snoop filter. 3196system.toL2Bus.snoop_filter.hit_single_requests 6308416 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3197system.toL2Bus.snoop_filter.hit_multi_requests 2241470 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3198system.toL2Bus.snoop_filter.tot_snoops 182770 # Total number of snoops made to the snoop filter. 3199system.toL2Bus.snoop_filter.hit_single_snoops 168316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3200system.toL2Bus.snoop_filter.hit_multi_snoops 14454 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3201system.toL2Bus.trans_dist::ReadReq 90610 # Transaction distribution 3202system.toL2Bus.trans_dist::ReadResp 5207811 # Transaction distribution 3203system.toL2Bus.trans_dist::WriteReq 38080 # Transaction distribution 3204system.toL2Bus.trans_dist::WriteResp 38080 # Transaction distribution 3205system.toL2Bus.trans_dist::Writeback 3858986 # Transaction distribution 3206system.toL2Bus.trans_dist::CleanEvict 1729776 # Transaction distribution 3207system.toL2Bus.trans_dist::UpgradeReq 481704 # Transaction distribution 3208system.toL2Bus.trans_dist::SCUpgradeReq 322377 # Transaction distribution 3209system.toL2Bus.trans_dist::UpgradeResp 804081 # Transaction distribution 3210system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution 3211system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 3212system.toL2Bus.trans_dist::ReadExReq 1151274 # Transaction distribution 3213system.toL2Bus.trans_dist::ReadExResp 1151274 # Transaction distribution 3214system.toL2Bus.trans_dist::ReadSharedReq 5124442 # Transaction distribution 3215system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3216system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9065091 # Packet count per connected master and slave (bytes) 3217system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7602046 # Packet count per connected master and slave (bytes) 3218system.toL2Bus.pkt_count::total 16667137 # Packet count per connected master and slave (bytes) 3219system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 281816078 # Cumulative packet size per connected master and slave (bytes) 3220system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 221579908 # Cumulative packet size per connected master and slave (bytes) 3221system.toL2Bus.pkt_size::total 503395986 # Cumulative packet size per connected master and slave (bytes) 3222system.toL2Bus.snoops 3440017 # Total snoops (count) 3223system.toL2Bus.snoop_fanout::samples 14338060 # Request fanout histogram 3224system.toL2Bus.snoop_fanout::mean 0.337750 # Request fanout histogram 3225system.toL2Bus.snoop_fanout::stdev 0.475069 # Request fanout histogram 3226system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3227system.toL2Bus.snoop_fanout::0 9509841 66.33% 66.33% # Request fanout histogram 3228system.toL2Bus.snoop_fanout::1 4813765 33.57% 99.90% # Request fanout histogram 3229system.toL2Bus.snoop_fanout::2 14454 0.10% 100.00% # Request fanout histogram 3230system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3231system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3232system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3233system.toL2Bus.snoop_fanout::total 14338060 # Request fanout histogram 3234system.toL2Bus.reqLayer0.occupancy 9248164097 # Layer occupancy (ticks) 3235system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3236system.toL2Bus.snoopLayer0.occupancy 2627637 # Layer occupancy (ticks) 3237system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3238system.toL2Bus.respLayer0.occupancy 5363594791 # Layer occupancy (ticks) 3239system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3240system.toL2Bus.respLayer1.occupancy 4586237114 # Layer occupancy (ticks) 3241system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3242 3243---------- End Simulation Statistics ---------- 3244