stats.txt revision 10892
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310892Sandreas.hansson@arm.comsim_seconds 47.482330 # Number of seconds simulated 410892Sandreas.hansson@arm.comsim_ticks 47482329862000 # Number of ticks simulated 510892Sandreas.hansson@arm.comfinal_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 176341 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 207374 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 9393535208 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 769764 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 5054.79 # Real time elapsed on the host 1210892Sandreas.hansson@arm.comsim_insts 891365561 # Number of instructions simulated 1310892Sandreas.hansson@arm.comsim_ops 1048233259 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory 2210892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory 2510892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory 2610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory 2710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 98400600 # Number of bytes read from this memory 2810892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory 2910892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory 3010892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory 3110892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3410892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 78283112 # Number of bytes written to this memory 3510892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory 3610892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory 3710892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory 3810892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory 3910892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory 4010892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory 4110892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory 4210892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory 4310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory 4410892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory 4510892Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory 4610892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory 4710892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5010892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory 5110892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) 5210892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) 5310892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) 5410892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) 5510892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) 5610892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) 5710892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) 5810892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) 5910892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) 6010892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) 6110892Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) 6210892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) 6310892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) 6410892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) 6510892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) 6610892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) 6710852Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6910892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) 7010892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) 7110892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) 7210892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) 7310892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) 7410892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) 7510892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) 7610892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) 7710892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) 7810892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) 7910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) 8010892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) 8110892Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) 8210892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) 8310892Sandreas.hansson@arm.comsystem.physmem.readReqs 1537535 # Number of read requests accepted 8410892Sandreas.hansson@arm.comsystem.physmem.writeReqs 1225426 # Number of write requests accepted 8510892Sandreas.hansson@arm.comsystem.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue 8610892Sandreas.hansson@arm.comsystem.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue 8710892Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM 8810892Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue 8910892Sandreas.hansson@arm.comsystem.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM 9010892Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side 9110892Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side 9210892Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue 9310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 9410892Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write 9510892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 94941 # Per bank write bursts 9610892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 98803 # Per bank write bursts 9710892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 90365 # Per bank write bursts 9810892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 103122 # Per bank write bursts 9910892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 90513 # Per bank write bursts 10010892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 102407 # Per bank write bursts 10110892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 86370 # Per bank write bursts 10210892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 97727 # Per bank write bursts 10310892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 90531 # Per bank write bursts 10410892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 141203 # Per bank write bursts 10510892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 86748 # Per bank write bursts 10610892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 95428 # Per bank write bursts 10710892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 92596 # Per bank write bursts 10810892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 93840 # Per bank write bursts 10910892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 85305 # Per bank write bursts 11010892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 87009 # Per bank write bursts 11110892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 77173 # Per bank write bursts 11210892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 80360 # Per bank write bursts 11310892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 74652 # Per bank write bursts 11410892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 83758 # Per bank write bursts 11510892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 75004 # Per bank write bursts 11610892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 81344 # Per bank write bursts 11710892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 71841 # Per bank write bursts 11810892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 79366 # Per bank write bursts 11910892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 74851 # Per bank write bursts 12010892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 75375 # Per bank write bursts 12110892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 73319 # Per bank write bursts 12210892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 78054 # Per bank write bursts 12310892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 76445 # Per bank write bursts 12410892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 77751 # Per bank write bursts 12510892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 70793 # Per bank write bursts 12610892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 73072 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12810892Sandreas.hansson@arm.comsystem.physmem.numWrRetry 43 # Number of times write queue was full causing retry 12910892Sandreas.hansson@arm.comsystem.physmem.totGap 47482327991500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13610892Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1537505 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14310892Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1222852 # Write request sizes (log2) 14410892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see 14510892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see 14610892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see 14710892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see 14810892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see 14910892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see 15010892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see 15110892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see 15210892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see 15310892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see 15410892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see 15510892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see 15610892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see 15710892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see 15810892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see 15910892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see 16010892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see 16110892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see 16210892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see 16310892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see 16410827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 16510852Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 16610852Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19110892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see 19210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see 19310892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see 19410892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see 19510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see 19610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see 19710892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see 19810892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see 19910892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see 20010892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 79113 # What write queue length does an incoming req see 20110892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 78742 # What write queue length does an incoming req see 20210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 81088 # What write queue length does an incoming req see 20310892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 80039 # What write queue length does an incoming req see 20410892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 81169 # What write queue length does an incoming req see 20510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 88387 # What write queue length does an incoming req see 20610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 80912 # What write queue length does an incoming req see 20710892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 76308 # What write queue length does an incoming req see 20810892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 72380 # What write queue length does an incoming req see 20910892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1847 # What write queue length does an incoming req see 21010892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see 21110892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1076 # What write queue length does an incoming req see 21210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 779 # What write queue length does an incoming req see 21310892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 575 # What write queue length does an incoming req see 21410892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 452 # What write queue length does an incoming req see 21510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 472 # What write queue length does an incoming req see 21610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 442 # What write queue length does an incoming req see 21710892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 426 # What write queue length does an incoming req see 21810892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see 21910892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 352 # What write queue length does an incoming req see 22010892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see 22110892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 360 # What write queue length does an incoming req see 22210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 419 # What write queue length does an incoming req see 22310892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 384 # What write queue length does an incoming req see 22410892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 350 # What write queue length does an incoming req see 22510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see 22610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 317 # What write queue length does an incoming req see 22710892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 378 # What write queue length does an incoming req see 22810892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 306 # What write queue length does an incoming req see 22910892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see 23010892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see 23110892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see 23210892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see 23310892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see 23410892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see 23510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see 23610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 23710892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see 23810892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see 23910892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see 24010892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation 24110892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation 24210892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation 24310892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation 24410892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation 24510892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation 24610892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation 24710892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation 24810892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation 24910892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation 25010892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation 25110892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation 25210892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation 25310892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation 25410892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes 25510892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes 25610892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes 25710892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes 25810892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 26010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 26110892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes 26210892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads 26310892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads 26410892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads 26510892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads 26610892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads 26710892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads 26810892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads 26910892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads 27010892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads 27110892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads 27210892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads 27310892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads 27410892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads 27510892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads 27610892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads 27710892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads 27810892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads 27910892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads 28010892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads 28110892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads 28210892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads 28310892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads 28410892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads 28510892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads 28610892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 28710892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads 28810892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads 28910892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 29010892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads 29110892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads 29210892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 29310892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads 29410892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads 29510892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 29610892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 29710892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 29810892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads 29910892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads 30010892Sandreas.hansson@arm.comsystem.physmem.totQLat 47438420321 # Total ticks spent queuing 30110892Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM 30210892Sandreas.hansson@arm.comsystem.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers 30310892Sandreas.hansson@arm.comsystem.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst 30410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30510892Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst 30610892Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s 30710892Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s 30810892Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s 30910892Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s 31010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31110852Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31210892Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 31310892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31410892Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 31510892Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing 31610892Sandreas.hansson@arm.comsystem.physmem.readRowHits 1237162 # Number of row buffer hits during reads 31710892Sandreas.hansson@arm.comsystem.physmem.writeRowHits 582295 # Number of row buffer hits during writes 31810892Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads 31910892Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes 32010892Sandreas.hansson@arm.comsystem.physmem.avgGap 17185305.18 # Average gap between requests 32110892Sandreas.hansson@arm.comsystem.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined 32210892Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) 32310892Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) 32410892Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) 32510892Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) 32610892Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) 32710892Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) 32810892Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) 32910892Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) 33010892Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.749891 # Core power per rank (mW) 33110892Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states 33210892Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states 33310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33410892Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states 33510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33610892Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) 33710892Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) 33810892Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) 33910892Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) 34010892Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) 34110892Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) 34210892Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) 34310892Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) 34410892Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.711548 # Core power per rank (mW) 34510892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states 34610892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states 34710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34810892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states 34910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35010636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 35110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35210636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 35310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 35510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 35610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 35710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 35810636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 35910636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36010636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36210515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 36410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 36610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 36810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 36910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 37110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 37210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 37610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37910852Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38010852Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38110852Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38210892Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 132987745 # Number of BP lookups 38310892Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted 38410892Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect 38510892Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups 38610892Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits 38710585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 38810892Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage 38910892Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. 39010892Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. 39110515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42110892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 275636 # Table walker walks requested 42210892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors 42310892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate 42410892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate 42510892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency 42610892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42710892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency 42810892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency 42910892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency 43010892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency 43110892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency 43210892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency 43310892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency 43410892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency 43510892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency 43610892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency 43710892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency 43810892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency 43910892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency 44010892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 44110892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency 44210892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 44310892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 44410892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 44510892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44610892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency 44710892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution 44810892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution 44910892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution 45010892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated 45110892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated 45210892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated 45310892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst 45410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45510892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst 45610892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst 45710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45810892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst 45910892Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst 46010585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46110585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46210892Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 84907220 # DTB read hits 46310892Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 227423 # DTB read misses 46410892Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 75575788 # DTB write hits 46510892Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 48213 # DTB write misses 46610585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46710585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46810892Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 46910892Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 47010892Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB 47110892Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions 47210892Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch 47310585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47410892Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions 47510892Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 85134643 # DTB read accesses 47610892Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 75624001 # DTB write accesses 47710585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47810892Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 160483008 # DTB hits 47910892Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 275636 # DTB misses 48010892Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 160758644 # DTB accesses 48110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51010892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 64906 # Table walker walks requested 51110892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors 51210892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate 51310892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate 51410892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency 51510892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51610892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency 51710892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency 51810892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency 51910892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency 52010892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency 52110892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency 52210892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency 52310892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency 52410892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency 52510892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency 52610892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency 52710892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency 52810892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency 52910892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency 53010892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 53110892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 53210892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 53310892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53410892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53510892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53610892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency 53710892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution 53810892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution 53910892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution 54010892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated 54110892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated 54210892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated 54310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54410892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst 54510892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst 54610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54710892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst 54810892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst 54910892Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst 55010892Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 238223958 # ITB inst hits 55110892Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 64906 # ITB inst misses 55210585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 55310585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 55410585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 55510585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 55610585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55710585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55810892Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 55910892Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 56010892Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB 56110585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56210585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56310585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56410892Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions 56510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 56610585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 56710892Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 238288864 # ITB inst accesses 56810892Sandreas.hansson@arm.comsystem.cpu0.itb.hits 238223958 # DTB hits 56910892Sandreas.hansson@arm.comsystem.cpu0.itb.misses 64906 # DTB misses 57010892Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 238288864 # DTB accesses 57110892Sandreas.hansson@arm.comsystem.cpu0.numCycles 971262699 # number of cpu cycles simulated 57210585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 57310585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 57410892Sandreas.hansson@arm.comsystem.cpu0.committedInsts 437915417 # Number of instructions committed 57510892Sandreas.hansson@arm.comsystem.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed 57610892Sandreas.hansson@arm.comsystem.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit 57710892Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching 57810892Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57910892Sandreas.hansson@arm.comsystem.cpu0.cpi 2.217923 # CPI: cycles per instruction 58010892Sandreas.hansson@arm.comsystem.cpu0.ipc 0.450872 # IPC: instructions per cycle 58110585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 58210892Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed 58310892Sandreas.hansson@arm.comsystem.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked 58410892Sandreas.hansson@arm.comsystem.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped 58510892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5570429 # number of replacements 58610892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use 58710892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. 58810892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. 58910892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. 59010892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. 59110892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor 59210892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy 59310892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy 59410892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id 59510892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 59610892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 59710892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 59810892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id 59910892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses 60010892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses 60110892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits 60210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits 60310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits 60410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits 60510892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits 60610892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits 60710892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits 60810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits 60910892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits 61010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits 61110892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits 61210892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits 61310892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits 61410892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits 61510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits 61610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 147839299 # number of overall hits 61710892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses 61810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses 61910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses 62010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses 62110892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses 62210892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses 62310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses 62410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses 62510892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses 62610892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses 62710892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses 62810892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses 62910892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses 63010892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses 63110892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses 63210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6435225 # number of overall misses 63310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles 63410892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles 63510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles 63610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles 63710892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles 63810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles 63910892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles 64010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles 64110892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles 64210892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles 64310892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles 64410892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles 64510892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles 64610892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles 64710892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles 64810892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles 64910892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) 65010892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) 65110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) 65210892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) 65310892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) 65410892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) 65510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) 65610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) 65710892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) 65810892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) 65910892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) 66010892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) 66110892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses 66210892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses 66310892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses 66410892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses 66510892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses 66610892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses 66710892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses 66810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses 66910892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses 67010892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses 67110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses 67210892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses 67310892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses 67410892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses 67510892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses 67610892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses 67710892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses 67810892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses 67910892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses 68010892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses 68110892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency 68210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency 68310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency 68410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency 68510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency 68610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency 68710892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency 68810892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency 68910892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency 69010892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency 69110636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 69210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 69310892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782 # average overall miss latency 69410892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency 69510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency 69610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency 69710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 70010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 70110585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 70210585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 70310585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 70410585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 70510892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3773399 # number of writebacks 70610892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3773399 # number of writebacks 70710892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 430069 # number of ReadReq MSHR hits 70810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 430069 # number of ReadReq MSHR hits 70910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 999795 # number of WriteReq MSHR hits 71010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 999795 # number of WriteReq MSHR hits 71110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 103 # number of WriteLineReq MSHR hits 71210892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 103 # number of WriteLineReq MSHR hits 71310892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40774 # number of LoadLockedReq MSHR hits 71410892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 40774 # number of LoadLockedReq MSHR hits 71510892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits 71610892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits 71710892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1429864 # number of demand (read+write) MSHR hits 71810892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1429864 # number of demand (read+write) MSHR hits 71910892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1429864 # number of overall MSHR hits 72010892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1429864 # number of overall MSHR hits 72110892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2950578 # number of ReadReq MSHR misses 72210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2950578 # number of ReadReq MSHR misses 72310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1384389 # number of WriteReq MSHR misses 72410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1384389 # number of WriteReq MSHR misses 72510892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664773 # number of SoftPFReq MSHR misses 72610892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 664773 # number of SoftPFReq MSHR misses 72710892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 781233 # number of WriteLineReq MSHR misses 72810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 781233 # number of WriteLineReq MSHR misses 72910892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114009 # number of LoadLockedReq MSHR misses 73010892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 114009 # number of LoadLockedReq MSHR misses 73110892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189777 # number of StoreCondReq MSHR misses 73210892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses 73310892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4334967 # number of demand (read+write) MSHR misses 73410892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4334967 # number of demand (read+write) MSHR misses 73510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4999740 # number of overall MSHR misses 73610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4999740 # number of overall MSHR misses 73710892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable 73810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 32882 # number of ReadReq MSHR uncacheable 73910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable 74010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable 74110892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses 74210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 65697 # number of overall MSHR uncacheable misses 74310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40501320500 # number of ReadReq MSHR miss cycles 74410892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 40501320500 # number of ReadReq MSHR miss cycles 74510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25594559000 # number of WriteReq MSHR miss cycles 74610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 25594559000 # number of WriteReq MSHR miss cycles 74710892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15267286500 # number of SoftPFReq MSHR miss cycles 74810892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15267286500 # number of SoftPFReq MSHR miss cycles 74910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 51557242500 # number of WriteLineReq MSHR miss cycles 75010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51557242500 # number of WriteLineReq MSHR miss cycles 75110892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1530630500 # number of LoadLockedReq MSHR miss cycles 75210892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1530630500 # number of LoadLockedReq MSHR miss cycles 75310892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3798446000 # number of StoreCondReq MSHR miss cycles 75410892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3798446000 # number of StoreCondReq MSHR miss cycles 75510892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2841500 # number of StoreCondFailReq MSHR miss cycles 75610892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles 75710892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 66095879500 # number of demand (read+write) MSHR miss cycles 75810892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 66095879500 # number of demand (read+write) MSHR miss cycles 75910892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81363166000 # number of overall MSHR miss cycles 76010892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 81363166000 # number of overall MSHR miss cycles 76110892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5911844500 # number of ReadReq MSHR uncacheable cycles 76210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5911844500 # number of ReadReq MSHR uncacheable cycles 76310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5682739500 # number of WriteReq MSHR uncacheable cycles 76410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5682739500 # number of WriteReq MSHR uncacheable cycles 76510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11594584000 # number of overall MSHR uncacheable cycles 76610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 11594584000 # number of overall MSHR uncacheable cycles 76710892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadReq accesses 76810892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036430 # mshr miss rate for ReadReq accesses 76910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019135 # mshr miss rate for WriteReq accesses 77010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019135 # mshr miss rate for WriteReq accesses 77110892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711871 # mshr miss rate for SoftPFReq accesses 77210892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711871 # mshr miss rate for SoftPFReq accesses 77310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.821508 # mshr miss rate for WriteLineReq accesses 77410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.821508 # mshr miss rate for WriteLineReq accesses 77510892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059591 # mshr miss rate for LoadLockedReq accesses 77610892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059591 # mshr miss rate for LoadLockedReq accesses 77710892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099280 # mshr miss rate for StoreCondReq accesses 77810892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099280 # mshr miss rate for StoreCondReq accesses 77910892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses 78010892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses 78110892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for overall accesses 78210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.032408 # mshr miss rate for overall accesses 78310892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709 # average ReadReq mshr miss latency 78410892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709 # average ReadReq mshr miss latency 78510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063 # average WriteReq mshr miss latency 78610892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063 # average WriteReq mshr miss latency 78710892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142 # average SoftPFReq mshr miss latency 78810892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142 # average SoftPFReq mshr miss latency 78910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445 # average WriteLineReq mshr miss latency 79010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445 # average WriteLineReq mshr miss latency 79110892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424 # average LoadLockedReq mshr miss latency 79210892Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424 # average LoadLockedReq mshr miss latency 79310892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709 # average StoreCondReq mshr miss latency 79410892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709 # average StoreCondReq mshr miss latency 79510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 79610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 79710892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095 # average overall mshr miss latency 79810892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095 # average overall mshr miss latency 79910892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421 # average overall mshr miss latency 80010892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421 # average overall mshr miss latency 80110892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367 # average ReadReq mshr uncacheable latency 80210892Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367 # average ReadReq mshr uncacheable latency 80310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139 # average WriteReq mshr uncacheable latency 80410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139 # average WriteReq mshr uncacheable latency 80510892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163 # average overall mshr uncacheable latency 80610892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163 # average overall mshr uncacheable latency 80710585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80810892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9510825 # number of replacements 80910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.926606 # Cycle average of tags in use 81010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 228501569 # Total number of references to valid blocks. 81110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9511337 # Sample count of references to valid blocks. 81210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 24.024127 # Average number of references to valid blocks. 81310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 29799763000 # Cycle when the warmup percentage was hit. 81410892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926606 # Average occupied blocks per requestor 81510892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy 81610892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy 81710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81810892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 81910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id 82010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 82110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 82210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 485537176 # Number of tag accesses 82310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 485537176 # Number of data accesses 82410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 228501569 # number of ReadReq hits 82510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 228501569 # number of ReadReq hits 82610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 228501569 # number of demand (read+write) hits 82710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 228501569 # number of demand (read+write) hits 82810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 228501569 # number of overall hits 82910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 228501569 # number of overall hits 83010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9511346 # number of ReadReq misses 83110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9511346 # number of ReadReq misses 83210892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9511346 # number of demand (read+write) misses 83310892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9511346 # number of demand (read+write) misses 83410892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9511346 # number of overall misses 83510892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9511346 # number of overall misses 83610892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94734195000 # number of ReadReq miss cycles 83710892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 94734195000 # number of ReadReq miss cycles 83810892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 94734195000 # number of demand (read+write) miss cycles 83910892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 94734195000 # number of demand (read+write) miss cycles 84010892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 94734195000 # number of overall miss cycles 84110892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 94734195000 # number of overall miss cycles 84210892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 238012915 # number of ReadReq accesses(hits+misses) 84310892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 238012915 # number of ReadReq accesses(hits+misses) 84410892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 238012915 # number of demand (read+write) accesses 84510892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 238012915 # number of demand (read+write) accesses 84610892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 238012915 # number of overall (read+write) accesses 84710892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 238012915 # number of overall (read+write) accesses 84810892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039961 # miss rate for ReadReq accesses 84910892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.039961 # miss rate for ReadReq accesses 85010892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.039961 # miss rate for demand accesses 85110892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.039961 # miss rate for demand accesses 85210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.039961 # miss rate for overall accesses 85310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.039961 # miss rate for overall accesses 85410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9960.124992 # average ReadReq miss latency 85510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 9960.124992 # average ReadReq miss latency 85610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency 85710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 9960.124992 # average overall miss latency 85810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency 85910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 9960.124992 # average overall miss latency 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 86210585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 86310585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 86410585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86510585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86610585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 86710585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 86810892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9511346 # number of ReadReq MSHR misses 86910892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9511346 # number of ReadReq MSHR misses 87010892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9511346 # number of demand (read+write) MSHR misses 87110892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9511346 # number of demand (read+write) MSHR misses 87210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9511346 # number of overall MSHR misses 87310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9511346 # number of overall MSHR misses 87410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 87510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable 87610892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 87710892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses 87810892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89978522000 # number of ReadReq MSHR miss cycles 87910892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 89978522000 # number of ReadReq MSHR miss cycles 88010892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89978522000 # number of demand (read+write) MSHR miss cycles 88110892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 89978522000 # number of demand (read+write) MSHR miss cycles 88210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89978522000 # number of overall MSHR miss cycles 88310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 89978522000 # number of overall MSHR miss cycles 88410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles 88510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles 88610892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles 88710892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles 88810892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for ReadReq accesses 88910892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039961 # mshr miss rate for ReadReq accesses 89010892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for demand accesses 89110892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.039961 # mshr miss rate for demand accesses 89210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for overall accesses 89310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.039961 # mshr miss rate for overall accesses 89410892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average ReadReq mshr miss latency 89510892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9460.124992 # average ReadReq mshr miss latency 89610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency 89710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency 89810892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency 89910892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency 90010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency 90110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency 90210892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency 90310892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency 90410585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 90510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7512189 # number of hwpf issued 90610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7515615 # number of prefetch candidates identified 90710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 2942 # number of redundant prefetches already in prefetch queue 90810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 90910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 91010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 975521 # number of prefetches not generated due to page crossing 91110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2798117 # number of replacements 91210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16231.650842 # Cycle average of tags in use 91310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 26314432 # Total number of references to valid blocks. 91410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2814109 # Sample count of references to valid blocks. 91510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 9.350893 # Average number of references to valid blocks. 91610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 27335773000 # Cycle when the warmup percentage was hit. 91710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 6405.405319 # Average occupied blocks per requestor 91810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.558250 # Average occupied blocks per requestor 91910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.359829 # Average occupied blocks per requestor 92010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor 92110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor 92210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor 92310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy 92410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy 92510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy 92610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy 92710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy 92810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy 92910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy 93010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id 93110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id 93210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id 93310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 93410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 685 # Occupied blocks per task id 93510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 484 # Occupied blocks per task id 93610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id 93710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id 93810852Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id 93910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 94010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 94110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id 94210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4037 # Occupied blocks per task id 94310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5036 # Occupied blocks per task id 94410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4531 # Occupied blocks per task id 94510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089417 # Percentage of cache occupancy per task id 94610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id 94710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.881409 # Percentage of cache occupancy per task id 94810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 507029075 # Number of tag accesses 94910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 507029075 # Number of data accesses 95010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 480958 # number of ReadReq hits 95110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155860 # number of ReadReq hits 95210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 636818 # number of ReadReq hits 95310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3773399 # number of Writeback hits 95410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3773399 # number of Writeback hits 95510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 109301 # number of UpgradeReq hits 95610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 109301 # number of UpgradeReq hits 95710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 35296 # number of SCUpgradeReq hits 95810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 35296 # number of SCUpgradeReq hits 95910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 877723 # number of ReadExReq hits 96010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 877723 # number of ReadExReq hits 96110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8733791 # number of ReadCleanReq hits 96210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 8733791 # number of ReadCleanReq hits 96310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2708727 # number of ReadSharedReq hits 96410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2708727 # number of ReadSharedReq hits 96510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 190451 # number of InvalidateReq hits 96610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 190451 # number of InvalidateReq hits 96710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 480958 # number of demand (read+write) hits 96810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 155860 # number of demand (read+write) hits 96910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 8733791 # number of demand (read+write) hits 97010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3586450 # number of demand (read+write) hits 97110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 12957059 # number of demand (read+write) hits 97210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 480958 # number of overall hits 97310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 155860 # number of overall hits 97410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 8733791 # number of overall hits 97510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3586450 # number of overall hits 97610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 12957059 # number of overall hits 97710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12195 # number of ReadReq misses 97810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8813 # number of ReadReq misses 97910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 21008 # number of ReadReq misses 98010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 130468 # number of UpgradeReq misses 98110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 130468 # number of UpgradeReq misses 98210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154478 # number of SCUpgradeReq misses 98310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 154478 # number of SCUpgradeReq misses 98410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 98510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 98610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 278567 # number of ReadExReq misses 98710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 278567 # number of ReadExReq misses 98810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 777554 # number of ReadCleanReq misses 98910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 777554 # number of ReadCleanReq misses 99010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1020411 # number of ReadSharedReq misses 99110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1020411 # number of ReadSharedReq misses 99210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 589182 # number of InvalidateReq misses 99310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 589182 # number of InvalidateReq misses 99410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12195 # number of demand (read+write) misses 99510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8813 # number of demand (read+write) misses 99610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 777554 # number of demand (read+write) misses 99710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1298978 # number of demand (read+write) misses 99810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2097540 # number of demand (read+write) misses 99910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12195 # number of overall misses 100010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8813 # number of overall misses 100110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 777554 # number of overall misses 100210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1298978 # number of overall misses 100310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2097540 # number of overall misses 100410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 429581500 # number of ReadReq miss cycles 100510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 328472000 # number of ReadReq miss cycles 100610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 758053500 # number of ReadReq miss cycles 100710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2811659500 # number of UpgradeReq miss cycles 100810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2811659500 # number of UpgradeReq miss cycles 100910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3201796000 # number of SCUpgradeReq miss cycles 101010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3201796000 # number of SCUpgradeReq miss cycles 101110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2748498 # number of SCUpgradeFailReq miss cycles 101210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2748498 # number of SCUpgradeFailReq miss cycles 101310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13465224999 # number of ReadExReq miss cycles 101410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 13465224999 # number of ReadExReq miss cycles 101510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23641079500 # number of ReadCleanReq miss cycles 101610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 23641079500 # number of ReadCleanReq miss cycles 101710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33953780489 # number of ReadSharedReq miss cycles 101810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 33953780489 # number of ReadSharedReq miss cycles 101910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 49014503000 # number of InvalidateReq miss cycles 102010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 49014503000 # number of InvalidateReq miss cycles 102110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 429581500 # number of demand (read+write) miss cycles 102210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 328472000 # number of demand (read+write) miss cycles 102310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 23641079500 # number of demand (read+write) miss cycles 102410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 47419005488 # number of demand (read+write) miss cycles 102510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 71818138488 # number of demand (read+write) miss cycles 102610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 429581500 # number of overall miss cycles 102710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 328472000 # number of overall miss cycles 102810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 23641079500 # number of overall miss cycles 102910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 47419005488 # number of overall miss cycles 103010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 71818138488 # number of overall miss cycles 103110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 493153 # number of ReadReq accesses(hits+misses) 103210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164673 # number of ReadReq accesses(hits+misses) 103310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 657826 # number of ReadReq accesses(hits+misses) 103410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3773399 # number of Writeback accesses(hits+misses) 103510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3773399 # number of Writeback accesses(hits+misses) 103610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 239769 # number of UpgradeReq accesses(hits+misses) 103710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 239769 # number of UpgradeReq accesses(hits+misses) 103810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189774 # number of SCUpgradeReq accesses(hits+misses) 103910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 189774 # number of SCUpgradeReq accesses(hits+misses) 104010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 104110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 104210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1156290 # number of ReadExReq accesses(hits+misses) 104310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1156290 # number of ReadExReq accesses(hits+misses) 104410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9511345 # number of ReadCleanReq accesses(hits+misses) 104510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9511345 # number of ReadCleanReq accesses(hits+misses) 104610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3729138 # number of ReadSharedReq accesses(hits+misses) 104710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3729138 # number of ReadSharedReq accesses(hits+misses) 104810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 779633 # number of InvalidateReq accesses(hits+misses) 104910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 779633 # number of InvalidateReq accesses(hits+misses) 105010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 493153 # number of demand (read+write) accesses 105110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164673 # number of demand (read+write) accesses 105210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9511345 # number of demand (read+write) accesses 105310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4885428 # number of demand (read+write) accesses 105410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 15054599 # number of demand (read+write) accesses 105510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 493153 # number of overall (read+write) accesses 105610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164673 # number of overall (read+write) accesses 105710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9511345 # number of overall (read+write) accesses 105810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4885428 # number of overall (read+write) accesses 105910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 15054599 # number of overall (read+write) accesses 106010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for ReadReq accesses 106110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053518 # miss rate for ReadReq accesses 106210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.031935 # miss rate for ReadReq accesses 106310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.544140 # miss rate for UpgradeReq accesses 106410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.544140 # miss rate for UpgradeReq accesses 106510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814010 # miss rate for SCUpgradeReq accesses 106610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814010 # miss rate for SCUpgradeReq accesses 106710636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 106810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 106910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240914 # miss rate for ReadExReq accesses 107010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.240914 # miss rate for ReadExReq accesses 107110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.081750 # miss rate for ReadCleanReq accesses 107210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.081750 # miss rate for ReadCleanReq accesses 107310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.273632 # miss rate for ReadSharedReq accesses 107410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.273632 # miss rate for ReadSharedReq accesses 107510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755717 # miss rate for InvalidateReq accesses 107610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755717 # miss rate for InvalidateReq accesses 107710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for demand accesses 107810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053518 # miss rate for demand accesses 107910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.081750 # miss rate for demand accesses 108010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.265888 # miss rate for demand accesses 108110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.139329 # miss rate for demand accesses 108210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for overall accesses 108310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053518 # miss rate for overall accesses 108410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.081750 # miss rate for overall accesses 108510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.265888 # miss rate for overall accesses 108610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.139329 # miss rate for overall accesses 108710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average ReadReq miss latency 108810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37271.303756 # average ReadReq miss latency 108910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 36084.039414 # average ReadReq miss latency 109010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21550.567955 # average UpgradeReq miss latency 109110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21550.567955 # average UpgradeReq miss latency 109210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20726.550059 # average SCUpgradeReq miss latency 109310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20726.550059 # average SCUpgradeReq miss latency 109410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 916166 # average SCUpgradeFailReq miss latency 109510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 916166 # average SCUpgradeFailReq miss latency 109610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48337.473567 # average ReadExReq miss latency 109710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48337.473567 # average ReadExReq miss latency 109810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30404.421429 # average ReadCleanReq miss latency 109910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30404.421429 # average ReadCleanReq miss latency 110010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33274.612376 # average ReadSharedReq miss latency 110110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33274.612376 # average ReadSharedReq miss latency 110210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 83190.767878 # average InvalidateReq miss latency 110310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 83190.767878 # average InvalidateReq miss latency 110410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency 110510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency 110610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency 110710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency 110810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 34239.222369 # average overall miss latency 110910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency 111010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency 111110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency 111210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency 111310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 34239.222369 # average overall miss latency 111410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 112110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 112210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1441697 # number of writebacks 112310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1441697 # number of writebacks 112410852Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 112510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 112610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8436 # number of ReadExReq MSHR hits 112710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 8436 # number of ReadExReq MSHR hits 112810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 8 # number of ReadCleanReq MSHR hits 112910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits 113010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 865 # number of ReadSharedReq MSHR hits 113110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 865 # number of ReadSharedReq MSHR hits 113210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 68 # number of InvalidateReq MSHR hits 113310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 68 # number of InvalidateReq MSHR hits 113410852Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 113510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 113610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 9301 # number of demand (read+write) MSHR hits 113710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 9312 # number of demand (read+write) MSHR hits 113810852Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 113910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 114010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 9301 # number of overall MSHR hits 114110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 9312 # number of overall MSHR hits 114210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12195 # number of ReadReq MSHR misses 114310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8810 # number of ReadReq MSHR misses 114410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 21005 # number of ReadReq MSHR misses 114510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 114790 # number of CleanEvict MSHR misses 114610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_misses::total 114790 # number of CleanEvict MSHR misses 114710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of HardPFReq MSHR misses 114810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 731294 # number of HardPFReq MSHR misses 114910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 130468 # number of UpgradeReq MSHR misses 115010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 130468 # number of UpgradeReq MSHR misses 115110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 154478 # number of SCUpgradeReq MSHR misses 115210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 154478 # number of SCUpgradeReq MSHR misses 115310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 115410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 115510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270131 # number of ReadExReq MSHR misses 115610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 270131 # number of ReadExReq MSHR misses 115710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 777546 # number of ReadCleanReq MSHR misses 115810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 777546 # number of ReadCleanReq MSHR misses 115910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1019546 # number of ReadSharedReq MSHR misses 116010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1019546 # number of ReadSharedReq MSHR misses 116110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 589114 # number of InvalidateReq MSHR misses 116210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 589114 # number of InvalidateReq MSHR misses 116310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12195 # number of demand (read+write) MSHR misses 116410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8810 # number of demand (read+write) MSHR misses 116510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 777546 # number of demand (read+write) MSHR misses 116610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1289677 # number of demand (read+write) MSHR misses 116710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2088228 # number of demand (read+write) MSHR misses 116810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12195 # number of overall MSHR misses 116910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8810 # number of overall MSHR misses 117010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 777546 # number of overall MSHR misses 117110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1289677 # number of overall MSHR misses 117210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of overall MSHR misses 117310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2819522 # number of overall MSHR misses 117410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 117510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable 117610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85174 # number of ReadReq MSHR uncacheable 117710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable 117810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable 117910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 118010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses 118110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 117989 # number of overall MSHR uncacheable misses 118210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of ReadReq MSHR miss cycles 118310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 275560000 # number of ReadReq MSHR miss cycles 118410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 631971500 # number of ReadReq MSHR miss cycles 118510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of HardPFReq MSHR miss cycles 118610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35755952523 # number of HardPFReq MSHR miss cycles 118710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2648670495 # number of UpgradeReq MSHR miss cycles 118810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2648670495 # number of UpgradeReq MSHR miss cycles 118910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2356042000 # number of SCUpgradeReq MSHR miss cycles 119010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2356042000 # number of SCUpgradeReq MSHR miss cycles 119110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2382498 # number of SCUpgradeFailReq MSHR miss cycles 119210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2382498 # number of SCUpgradeFailReq MSHR miss cycles 119310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10796229999 # number of ReadExReq MSHR miss cycles 119410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10796229999 # number of ReadExReq MSHR miss cycles 119510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18975468000 # number of ReadCleanReq MSHR miss cycles 119610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18975468000 # number of ReadCleanReq MSHR miss cycles 119710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27752056489 # number of ReadSharedReq MSHR miss cycles 119810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27752056489 # number of ReadSharedReq MSHR miss cycles 119910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 45478624000 # number of InvalidateReq MSHR miss cycles 120010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 45478624000 # number of InvalidateReq MSHR miss cycles 120110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of demand (read+write) MSHR miss cycles 120210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 275560000 # number of demand (read+write) MSHR miss cycles 120310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18975468000 # number of demand (read+write) MSHR miss cycles 120410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38548286488 # number of demand (read+write) MSHR miss cycles 120510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 58155725988 # number of demand (read+write) MSHR miss cycles 120610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of overall MSHR miss cycles 120710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 275560000 # number of overall MSHR miss cycles 120810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18975468000 # number of overall MSHR miss cycles 120910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38548286488 # number of overall MSHR miss cycles 121010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of overall MSHR miss cycles 121110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 93911678511 # number of overall MSHR miss cycles 121210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles 121310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5648614500 # number of ReadReq MSHR uncacheable cycles 121410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10008059000 # number of ReadReq MSHR uncacheable cycles 121510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5436600500 # number of WriteReq MSHR uncacheable cycles 121610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5436600500 # number of WriteReq MSHR uncacheable cycles 121710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles 121810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11085215000 # number of overall MSHR uncacheable cycles 121910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15444659500 # number of overall MSHR uncacheable cycles 122010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for ReadReq accesses 122110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for ReadReq accesses 122210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031931 # mshr miss rate for ReadReq accesses 122310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 122410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 122510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 122610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 122710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.544140 # mshr miss rate for UpgradeReq accesses 122810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.544140 # mshr miss rate for UpgradeReq accesses 122910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814010 # mshr miss rate for SCUpgradeReq accesses 123010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814010 # mshr miss rate for SCUpgradeReq accesses 123110636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 123210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 123310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for ReadExReq accesses 123410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233619 # mshr miss rate for ReadExReq accesses 123510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses 123610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses 123710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses 123810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses 123910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses 124010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses 124110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses 124210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses 124310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses 124410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses 124510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses 124610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses 124710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses 124810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses 124910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses 125010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 125110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses 125210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency 125310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency 125410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency 125510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency 125610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency 125710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency 125810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency 125910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency 126010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency 126110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency 126210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency 126310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency 126410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency 126510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency 126610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency 126710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency 126810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency 126910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency 127010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency 127110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency 127210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency 127310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency 127410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency 127510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency 127610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency 127710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency 127810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency 127910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency 128010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency 128110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency 128210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency 128310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency 128410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency 128510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency 128610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency 128710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency 128810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency 128910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency 129010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 129110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution 129210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution 129310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 129410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution 129510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution 129610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution 129710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution 129810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution 129910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution 130010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution 130110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution 130210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 130310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution 130410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution 130510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution 130610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution 130710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution 130810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution 130910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) 131010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) 131110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) 131210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) 131310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) 131410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) 131510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) 131610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) 131710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) 131810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) 131910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) 132010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram 132110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram 132210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram 132310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 132410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 132510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram 132610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram 132710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 132810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 132910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 133010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram 133110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) 133210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 133310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) 133410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 133510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) 133610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 133710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) 133810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 133910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) 134010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 134110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) 134210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 134310892Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 137760504 # Number of BP lookups 134410892Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted 134510892Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect 134610892Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups 134710892Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits 134810585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 134910892Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage 135010892Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. 135110892Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. 135210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 135310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 135610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 135710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 135810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 135910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 136010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 136110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 136210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 136310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 136410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 136510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 136610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 136710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 137110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 137210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 137310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 137410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 137510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 137610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 137710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 137810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 137910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 138010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 138110892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 290439 # Table walker walks requested 138210892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors 138310892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate 138410892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate 138510892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency 138610892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency 138710892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency 138810892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency 138910892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency 139010892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency 139110892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency 139210892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency 139310892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency 139410892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency 139510892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency 139610892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency 139710892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency 139810892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 139910892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 140010892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 140110892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 140210892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency 140310892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution 140410892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution 140510892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution 140610892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated 140710892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated 140810892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated 140910892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst 141010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141110892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst 141210892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst 141310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141410892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst 141510892Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst 141610585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 141710585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 141810892Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 89204123 # DTB read hits 141910892Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 242859 # DTB read misses 142010892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 77378465 # DTB write hits 142110892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 47580 # DTB write misses 142210585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 142310585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142410892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 142510892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 142610892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB 142710892Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions 142810892Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch 142910585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143010892Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions 143110892Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 89446982 # DTB read accesses 143210892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 77426045 # DTB write accesses 143310585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 143410892Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 166582588 # DTB hits 143510892Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 290439 # DTB misses 143610892Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 166873027 # DTB accesses 143710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 143810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 144110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 144210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 144410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 144510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 144810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 144910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 145010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 145110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 145310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 145810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 145910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 146010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 146210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 146310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 146410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 146510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146610892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 66791 # Table walker walks requested 146710892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors 146810892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate 146910892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate 147010892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency 147110892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency 147210892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency 147310892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency 147410892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency 147510892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency 147610892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency 147710892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency 147810892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency 147910892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency 148010892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency 148110892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency 148210892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency 148310892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency 148410892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 148510892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency 148610892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency 148710892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 148810892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 148910892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 149010892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 149110892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency 149210892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution 149310892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution 149410892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution 149510892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated 149610892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated 149710892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated 149810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 149910892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst 150010892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst 150110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150210892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst 150310892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst 150410892Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst 150510892Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 246625416 # ITB inst hits 150610892Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 66791 # ITB inst misses 150710585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 150810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 150910585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 151010585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 151110585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 151210585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151310892Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 151410892Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 151510892Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB 151610585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 151710585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 151810585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 151910892Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions 152010585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 152110585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 152210892Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 246692207 # ITB inst accesses 152310892Sandreas.hansson@arm.comsystem.cpu1.itb.hits 246625416 # DTB hits 152410892Sandreas.hansson@arm.comsystem.cpu1.itb.misses 66791 # DTB misses 152510892Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 246692207 # DTB accesses 152610892Sandreas.hansson@arm.comsystem.cpu1.numCycles 916577474 # number of cpu cycles simulated 152710585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 152810585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 152910892Sandreas.hansson@arm.comsystem.cpu1.committedInsts 453450144 # Number of instructions committed 153010892Sandreas.hansson@arm.comsystem.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed 153110892Sandreas.hansson@arm.comsystem.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit 153210892Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching 153310892Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 153410892Sandreas.hansson@arm.comsystem.cpu1.cpi 2.021341 # CPI: cycles per instruction 153510892Sandreas.hansson@arm.comsystem.cpu1.ipc 0.494721 # IPC: instructions per cycle 153610585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 153710892Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed 153810892Sandreas.hansson@arm.comsystem.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked 153910892Sandreas.hansson@arm.comsystem.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped 154010892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5347951 # number of replacements 154110892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use 154210892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. 154310892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. 154410892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. 154510892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. 154610892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor 154710892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy 154810892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy 154910726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 155010892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 155110892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 155210892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 155310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 155410892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses 155510892Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses 155610892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits 155710892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits 155810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits 155910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits 156010892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits 156110892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits 156210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits 156310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits 156410892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits 156510892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits 156610892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits 156710892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits 156810892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits 156910892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits 157010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits 157110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 154303114 # number of overall hits 157210892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses 157310892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses 157410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses 157510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses 157610892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses 157710892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses 157810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses 157910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses 158010892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses 158110892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses 158210892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses 158310892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses 158410892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses 158510892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses 158610892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses 158710892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6364672 # number of overall misses 158810892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles 158910892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles 159010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles 159110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles 159210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles 159310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles 159410892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles 159510892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles 159610892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles 159710892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles 159810892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles 159910892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles 160010892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles 160110892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles 160210892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles 160310892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles 160410892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) 160510892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) 160610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) 160710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) 160810892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) 160910892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) 161010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) 161110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) 161210892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) 161310892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) 161410892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) 161510892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) 161610892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses 161710892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses 161810892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses 161910892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses 162010892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses 162110892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses 162210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses 162310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses 162410892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses 162510892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses 162610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses 162710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses 162810892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses 162910892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses 163010892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses 163110892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses 163210892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses 163310892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses 163410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses 163510892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses 163610892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency 163710892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency 163810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency 163910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency 164010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency 164110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency 164210892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency 164310892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency 164410892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency 164510892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency 164610636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 164710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 164810892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764 # average overall miss latency 164910892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency 165010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency 165110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency 165210585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 165310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 165610585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 165710585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 165810585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 165910585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 166010892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3440440 # number of writebacks 166110892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3440440 # number of writebacks 166210892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392659 # number of ReadReq MSHR hits 166310892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 392659 # number of ReadReq MSHR hits 166410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 925831 # number of WriteReq MSHR hits 166510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 925831 # number of WriteReq MSHR hits 166610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 46 # number of WriteLineReq MSHR hits 166710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 46 # number of WriteLineReq MSHR hits 166810892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41204 # number of LoadLockedReq MSHR hits 166910892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 41204 # number of LoadLockedReq MSHR hits 167010892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 43 # number of StoreCondReq MSHR hits 167110892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits 167210892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1318490 # number of demand (read+write) MSHR hits 167310892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1318490 # number of demand (read+write) MSHR hits 167410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1318490 # number of overall MSHR hits 167510892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1318490 # number of overall MSHR hits 167610892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3076745 # number of ReadReq MSHR misses 167710892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3076745 # number of ReadReq MSHR misses 167810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1328174 # number of WriteReq MSHR misses 167910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1328174 # number of WriteReq MSHR misses 168010892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 640972 # number of SoftPFReq MSHR misses 168110892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 640972 # number of SoftPFReq MSHR misses 168210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 468487 # number of WriteLineReq MSHR misses 168310892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 468487 # number of WriteLineReq MSHR misses 168410892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 131337 # number of LoadLockedReq MSHR misses 168510892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 131337 # number of LoadLockedReq MSHR misses 168610892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196714 # number of StoreCondReq MSHR misses 168710892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 196714 # number of StoreCondReq MSHR misses 168810892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4404919 # number of demand (read+write) MSHR misses 168910892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4404919 # number of demand (read+write) MSHR misses 169010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5045891 # number of overall MSHR misses 169110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5045891 # number of overall MSHR misses 169210892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable 169310892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 5366 # number of ReadReq MSHR uncacheable 169410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable 169510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable 169610892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses 169710892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 10646 # number of overall MSHR uncacheable misses 169810892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41480566500 # number of ReadReq MSHR miss cycles 169910892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 41480566500 # number of ReadReq MSHR miss cycles 170010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21714665000 # number of WriteReq MSHR miss cycles 170110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 21714665000 # number of WriteReq MSHR miss cycles 170210892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12811841000 # number of SoftPFReq MSHR miss cycles 170310892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12811841000 # number of SoftPFReq MSHR miss cycles 170410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16084660000 # number of WriteLineReq MSHR miss cycles 170510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16084660000 # number of WriteLineReq MSHR miss cycles 170610892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751023000 # number of LoadLockedReq MSHR miss cycles 170710892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751023000 # number of LoadLockedReq MSHR miss cycles 170810892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3933903500 # number of StoreCondReq MSHR miss cycles 170910892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3933903500 # number of StoreCondReq MSHR miss cycles 171010892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles 171110892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles 171210892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63195231500 # number of demand (read+write) MSHR miss cycles 171310892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 63195231500 # number of demand (read+write) MSHR miss cycles 171410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76007072500 # number of overall MSHR miss cycles 171510892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 76007072500 # number of overall MSHR miss cycles 171610892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 593786000 # number of ReadReq MSHR uncacheable cycles 171710892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 593786000 # number of ReadReq MSHR uncacheable cycles 171810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 651165500 # number of WriteReq MSHR uncacheable cycles 171910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 651165500 # number of WriteReq MSHR uncacheable cycles 172010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244951500 # number of overall MSHR uncacheable cycles 172110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1244951500 # number of overall MSHR uncacheable cycles 172210892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036067 # mshr miss rate for ReadReq accesses 172310892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036067 # mshr miss rate for ReadReq accesses 172410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017833 # mshr miss rate for WriteReq accesses 172510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017833 # mshr miss rate for WriteReq accesses 172610892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.727739 # mshr miss rate for SoftPFReq accesses 172710892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.727739 # mshr miss rate for SoftPFReq accesses 172810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.763023 # mshr miss rate for WriteLineReq accesses 172910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.763023 # mshr miss rate for WriteLineReq accesses 173010892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067065 # mshr miss rate for LoadLockedReq accesses 173110892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067065 # mshr miss rate for LoadLockedReq accesses 173210892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100543 # mshr miss rate for StoreCondReq accesses 173310892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100543 # mshr miss rate for StoreCondReq accesses 173410892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027567 # mshr miss rate for demand accesses 173510892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027567 # mshr miss rate for demand accesses 173610892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031406 # mshr miss rate for overall accesses 173710892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031406 # mshr miss rate for overall accesses 173810892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381 # average ReadReq mshr miss latency 173910892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381 # average ReadReq mshr miss latency 174010892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220 # average WriteReq mshr miss latency 174110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220 # average WriteReq mshr miss latency 174210892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568 # average SoftPFReq mshr miss latency 174310892Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568 # average SoftPFReq mshr miss latency 174410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550 # average WriteLineReq mshr miss latency 174510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550 # average WriteLineReq mshr miss latency 174610892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215 # average LoadLockedReq mshr miss latency 174710892Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215 # average LoadLockedReq mshr miss latency 174810892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054 # average StoreCondReq mshr miss latency 174910892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054 # average StoreCondReq mshr miss latency 175010636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 175110585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 175210892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency 175310892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency 175410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency 175510892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency 175610892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency 175710892Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency 175810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency 175910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency 176010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # average overall mshr uncacheable latency 176110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878 # average overall mshr uncacheable latency 176210585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 176310892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9156821 # number of replacements 176410892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use 176510892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. 176610892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. 176710892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. 176810892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. 176910892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor 177010892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy 177110892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy 177210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 177310892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 177410892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 177510892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 177610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 177710892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses 177810892Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses 177910892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits 178010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits 178110892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits 178210892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 237244674 # number of demand (read+write) hits 178310892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 237244674 # number of overall hits 178410892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 237244674 # number of overall hits 178510892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9157334 # number of ReadReq misses 178610892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9157334 # number of ReadReq misses 178710892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9157334 # number of demand (read+write) misses 178810892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9157334 # number of demand (read+write) misses 178910892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9157334 # number of overall misses 179010892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9157334 # number of overall misses 179110892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 90409615500 # number of ReadReq miss cycles 179210892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 90409615500 # number of ReadReq miss cycles 179310892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 90409615500 # number of demand (read+write) miss cycles 179410892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 90409615500 # number of demand (read+write) miss cycles 179510892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 90409615500 # number of overall miss cycles 179610892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 90409615500 # number of overall miss cycles 179710892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 246402008 # number of ReadReq accesses(hits+misses) 179810892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 246402008 # number of ReadReq accesses(hits+misses) 179910892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 246402008 # number of demand (read+write) accesses 180010892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 246402008 # number of demand (read+write) accesses 180110892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 246402008 # number of overall (read+write) accesses 180210892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 246402008 # number of overall (read+write) accesses 180310892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037164 # miss rate for ReadReq accesses 180410892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.037164 # miss rate for ReadReq accesses 180510892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.037164 # miss rate for demand accesses 180610892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.037164 # miss rate for demand accesses 180710892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.037164 # miss rate for overall accesses 180810892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.037164 # miss rate for overall accesses 180910892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9872.918854 # average ReadReq miss latency 181010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 9872.918854 # average ReadReq miss latency 181110892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency 181210892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 9872.918854 # average overall miss latency 181310892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency 181410892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 9872.918854 # average overall miss latency 181510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 181810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 181910585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182010585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 182110585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 182210585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 182310892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses 182410892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses 182510892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses 182610892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses 182710892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # number of overall MSHR misses 182810892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9157334 # number of overall MSHR misses 182910892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 183010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 183110892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 183210892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 183310892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85830949000 # number of ReadReq MSHR miss cycles 183410892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 85830949000 # number of ReadReq MSHR miss cycles 183510892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85830949000 # number of demand (read+write) MSHR miss cycles 183610892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 85830949000 # number of demand (read+write) MSHR miss cycles 183710892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85830949000 # number of overall MSHR miss cycles 183810892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 85830949000 # number of overall MSHR miss cycles 183910892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8848000 # number of ReadReq MSHR uncacheable cycles 184010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8848000 # number of ReadReq MSHR uncacheable cycles 184110892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8848000 # number of overall MSHR uncacheable cycles 184210892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8848000 # number of overall MSHR uncacheable cycles 184310892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for ReadReq accesses 184410892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037164 # mshr miss rate for ReadReq accesses 184510892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for demand accesses 184610892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.037164 # mshr miss rate for demand accesses 184710892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for overall accesses 184810892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.037164 # mshr miss rate for overall accesses 184910892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average ReadReq mshr miss latency 185010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9372.918908 # average ReadReq mshr miss latency 185110892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency 185210892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency 185310892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency 185410892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency 185510892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average ReadReq mshr uncacheable latency 185610892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946 # average ReadReq mshr uncacheable latency 185710892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average overall mshr uncacheable latency 185810892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946 # average overall mshr uncacheable latency 185910585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 186010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued 186110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified 186210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue 186310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 186410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 186510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 921370 # number of prefetches not generated due to page crossing 186610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2420449 # number of replacements 186710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13525.501015 # Cycle average of tags in use 186810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 25921683 # Total number of references to valid blocks. 186910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2436577 # Sample count of references to valid blocks. 187010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 10.638565 # Average number of references to valid blocks. 187110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. 187210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor 187310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor 187410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor 187510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor 187610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor 187710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor 187810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy 187910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy 188010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # Average percentage of cache occupancy 188110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.217380 # Average percentage of cache occupancy 188210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229067 # Average percentage of cache occupancy 188310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048899 # Average percentage of cache occupancy 188410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.825531 # Average percentage of cache occupancy 188510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id 188610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 188710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id 188810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 188910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id 189010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 534 # Occupied blocks per task id 189110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 335 # Occupied blocks per task id 189210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 189310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 189410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 189510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 189610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 189710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1163 # Occupied blocks per task id 189810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5423 # Occupied blocks per task id 189910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4799 # Occupied blocks per task id 190010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3398 # Occupied blocks per task id 190110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 190210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 190310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 190410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 488189494 # Number of tag accesses 190510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 488189494 # Number of data accesses 190610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527706 # number of ReadReq hits 190710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160378 # number of ReadReq hits 190810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 688084 # number of ReadReq hits 190910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3440434 # number of Writeback hits 191010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3440434 # number of Writeback hits 191110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 69060 # number of UpgradeReq hits 191210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 69060 # number of UpgradeReq hits 191310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 37815 # number of SCUpgradeReq hits 191410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 37815 # number of SCUpgradeReq hits 191510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 888572 # number of ReadExReq hits 191610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 888572 # number of ReadExReq hits 191710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8367748 # number of ReadCleanReq hits 191810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8367748 # number of ReadCleanReq hits 191910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2856681 # number of ReadSharedReq hits 192010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2856681 # number of ReadSharedReq hits 192110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 194722 # number of InvalidateReq hits 192210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 194722 # number of InvalidateReq hits 192310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527706 # number of demand (read+write) hits 192410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 160378 # number of demand (read+write) hits 192510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8367748 # number of demand (read+write) hits 192610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3745253 # number of demand (read+write) hits 192710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 12801085 # number of demand (read+write) hits 192810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527706 # number of overall hits 192910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 160378 # number of overall hits 193010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8367748 # number of overall hits 193110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3745253 # number of overall hits 193210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 12801085 # number of overall hits 193310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11992 # number of ReadReq misses 193410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses 193510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 20524 # number of ReadReq misses 193610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::writebacks 3 # number of Writeback misses 193710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::total 3 # number of Writeback misses 193810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136249 # number of UpgradeReq misses 193910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 136249 # number of UpgradeReq misses 194010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158895 # number of SCUpgradeReq misses 194110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 158895 # number of SCUpgradeReq misses 194210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 194310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 194410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 235953 # number of ReadExReq misses 194510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 235953 # number of ReadExReq misses 194610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 789586 # number of ReadCleanReq misses 194710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 789586 # number of ReadCleanReq misses 194810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 992043 # number of ReadSharedReq misses 194910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 992043 # number of ReadSharedReq misses 195010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272649 # number of InvalidateReq misses 195110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 272649 # number of InvalidateReq misses 195210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11992 # number of demand (read+write) misses 195310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses 195410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 789586 # number of demand (read+write) misses 195510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1227996 # number of demand (read+write) misses 195610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2038106 # number of demand (read+write) misses 195710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11992 # number of overall misses 195810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses 195910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 789586 # number of overall misses 196010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1227996 # number of overall misses 196110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2038106 # number of overall misses 196210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446382000 # number of ReadReq miss cycles 196310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 354037500 # number of ReadReq miss cycles 196410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 800419500 # number of ReadReq miss cycles 196510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2966896500 # number of UpgradeReq miss cycles 196610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2966896500 # number of UpgradeReq miss cycles 196710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3304625499 # number of SCUpgradeReq miss cycles 196810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3304625499 # number of SCUpgradeReq miss cycles 196910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763998 # number of SCUpgradeFailReq miss cycles 197010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763998 # number of SCUpgradeFailReq miss cycles 197110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9908657497 # number of ReadExReq miss cycles 197210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9908657497 # number of ReadExReq miss cycles 197310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22229315000 # number of ReadCleanReq miss cycles 197410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 22229315000 # number of ReadCleanReq miss cycles 197510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31556071491 # number of ReadSharedReq miss cycles 197610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 31556071491 # number of ReadSharedReq miss cycles 197710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14034162000 # number of InvalidateReq miss cycles 197810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 14034162000 # number of InvalidateReq miss cycles 197910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446382000 # number of demand (read+write) miss cycles 198010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 354037500 # number of demand (read+write) miss cycles 198110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 22229315000 # number of demand (read+write) miss cycles 198210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 41464728988 # number of demand (read+write) miss cycles 198310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 64494463488 # number of demand (read+write) miss cycles 198410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446382000 # number of overall miss cycles 198510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 354037500 # number of overall miss cycles 198610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 22229315000 # number of overall miss cycles 198710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 41464728988 # number of overall miss cycles 198810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 64494463488 # number of overall miss cycles 198910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539698 # number of ReadReq accesses(hits+misses) 199010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168910 # number of ReadReq accesses(hits+misses) 199110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 708608 # number of ReadReq accesses(hits+misses) 199210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3440437 # number of Writeback accesses(hits+misses) 199310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3440437 # number of Writeback accesses(hits+misses) 199410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205309 # number of UpgradeReq accesses(hits+misses) 199510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 205309 # number of UpgradeReq accesses(hits+misses) 199610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 196710 # number of SCUpgradeReq accesses(hits+misses) 199710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 196710 # number of SCUpgradeReq accesses(hits+misses) 199810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 199910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 200010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1124525 # number of ReadExReq accesses(hits+misses) 200110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1124525 # number of ReadExReq accesses(hits+misses) 200210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9157334 # number of ReadCleanReq accesses(hits+misses) 200310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9157334 # number of ReadCleanReq accesses(hits+misses) 200410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3848724 # number of ReadSharedReq accesses(hits+misses) 200510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3848724 # number of ReadSharedReq accesses(hits+misses) 200610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 467371 # number of InvalidateReq accesses(hits+misses) 200710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 467371 # number of InvalidateReq accesses(hits+misses) 200810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539698 # number of demand (read+write) accesses 200910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168910 # number of demand (read+write) accesses 201010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9157334 # number of demand (read+write) accesses 201110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4973249 # number of demand (read+write) accesses 201210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 14839191 # number of demand (read+write) accesses 201310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539698 # number of overall (read+write) accesses 201410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168910 # number of overall (read+write) accesses 201510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9157334 # number of overall (read+write) accesses 201610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4973249 # number of overall (read+write) accesses 201710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 14839191 # number of overall (read+write) accesses 201810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for ReadReq accesses 201910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050512 # miss rate for ReadReq accesses 202010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses 202110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses 202210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses 202310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.663629 # miss rate for UpgradeReq accesses 202410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.663629 # miss rate for UpgradeReq accesses 202510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.807763 # miss rate for SCUpgradeReq accesses 202610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.807763 # miss rate for SCUpgradeReq accesses 202710636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 202810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 202910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.209825 # miss rate for ReadExReq accesses 203010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.209825 # miss rate for ReadExReq accesses 203110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.086224 # miss rate for ReadCleanReq accesses 203210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.086224 # miss rate for ReadCleanReq accesses 203310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.257759 # miss rate for ReadSharedReq accesses 203410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.257759 # miss rate for ReadSharedReq accesses 203510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.583367 # miss rate for InvalidateReq accesses 203610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.583367 # miss rate for InvalidateReq accesses 203710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for demand accesses 203810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050512 # miss rate for demand accesses 203910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086224 # miss rate for demand accesses 204010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246920 # miss rate for demand accesses 204110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.137346 # miss rate for demand accesses 204210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for overall accesses 204310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050512 # miss rate for overall accesses 204410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086224 # miss rate for overall accesses 204510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246920 # miss rate for overall accesses 204610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.137346 # miss rate for overall accesses 204710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average ReadReq miss latency 204810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41495.253165 # average ReadReq miss latency 204910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 38999.196063 # average ReadReq miss latency 205010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21775.546976 # average UpgradeReq miss latency 205110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21775.546976 # average UpgradeReq miss latency 205210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20797.542396 # average SCUpgradeReq miss latency 205310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20797.542396 # average SCUpgradeReq miss latency 205410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 440999.500000 # average SCUpgradeFailReq miss latency 205510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 440999.500000 # average SCUpgradeFailReq miss latency 205610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41994.200103 # average ReadExReq miss latency 205710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41994.200103 # average ReadExReq miss latency 205810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28153.127082 # average ReadCleanReq miss latency 205910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28153.127082 # average ReadCleanReq miss latency 206010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31809.177113 # average ReadSharedReq miss latency 206110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31809.177113 # average ReadSharedReq miss latency 206210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51473.366856 # average InvalidateReq miss latency 206310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51473.366856 # average InvalidateReq miss latency 206410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency 206510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency 206610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency 206710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency 206810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 31644.312655 # average overall miss latency 206910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency 207010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency 207110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency 207210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency 207310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 31644.312655 # average overall miss latency 207410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 207610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 207710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 207810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 207910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 208010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 208110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 208210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1031306 # number of writebacks 208310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1031306 # number of writebacks 208410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 208510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 208610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7033 # number of ReadExReq MSHR hits 208710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 7033 # number of ReadExReq MSHR hits 208810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 208910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 209010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 605 # number of ReadSharedReq MSHR hits 209110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 605 # number of ReadSharedReq MSHR hits 209210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 17 # number of InvalidateReq MSHR hits 209310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 17 # number of InvalidateReq MSHR hits 209410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 209510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 209610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 7638 # number of demand (read+write) MSHR hits 209710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 7641 # number of demand (read+write) MSHR hits 209810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 209910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 210010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 7638 # number of overall MSHR hits 210110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 7641 # number of overall MSHR hits 210210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11992 # number of ReadReq MSHR misses 210310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses 210410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 20522 # number of ReadReq MSHR misses 210510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::writebacks 3 # number of Writeback MSHR misses 210610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::total 3 # number of Writeback MSHR misses 210710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 115811 # number of CleanEvict MSHR misses 210810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_misses::total 115811 # number of CleanEvict MSHR misses 210910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of HardPFReq MSHR misses 211010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 714965 # number of HardPFReq MSHR misses 211110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 136249 # number of UpgradeReq MSHR misses 211210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 136249 # number of UpgradeReq MSHR misses 211310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 158895 # number of SCUpgradeReq MSHR misses 211410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 158895 # number of SCUpgradeReq MSHR misses 211510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 211610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 211710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 228920 # number of ReadExReq MSHR misses 211810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 228920 # number of ReadExReq MSHR misses 211910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 789585 # number of ReadCleanReq MSHR misses 212010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 789585 # number of ReadCleanReq MSHR misses 212110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 991438 # number of ReadSharedReq MSHR misses 212210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 991438 # number of ReadSharedReq MSHR misses 212310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 272632 # number of InvalidateReq MSHR misses 212410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 272632 # number of InvalidateReq MSHR misses 212510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11992 # number of demand (read+write) MSHR misses 212610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses 212710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 789585 # number of demand (read+write) MSHR misses 212810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1220358 # number of demand (read+write) MSHR misses 212910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 2030465 # number of demand (read+write) MSHR misses 213010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11992 # number of overall MSHR misses 213110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses 213210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 789585 # number of overall MSHR misses 213310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1220358 # number of overall MSHR misses 213410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of overall MSHR misses 213510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2745430 # number of overall MSHR misses 213610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 213710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable 213810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5459 # number of ReadReq MSHR uncacheable 213910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable 214010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable 214110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 214210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses 214310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10739 # number of overall MSHR uncacheable misses 214410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of ReadReq MSHR miss cycles 214510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 302816000 # number of ReadReq MSHR miss cycles 214610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 677246000 # number of ReadReq MSHR miss cycles 214710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of HardPFReq MSHR miss cycles 214810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30632454632 # number of HardPFReq MSHR miss cycles 214910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2763352994 # number of UpgradeReq MSHR miss cycles 215010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2763352994 # number of UpgradeReq MSHR miss cycles 215110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2438062999 # number of SCUpgradeReq MSHR miss cycles 215210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2438062999 # number of SCUpgradeReq MSHR miss cycles 215310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1505998 # number of SCUpgradeFailReq MSHR miss cycles 215410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1505998 # number of SCUpgradeFailReq MSHR miss cycles 215510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7634474497 # number of ReadExReq MSHR miss cycles 215610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7634474497 # number of ReadExReq MSHR miss cycles 215710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17491788500 # number of ReadCleanReq MSHR miss cycles 215810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17491788500 # number of ReadCleanReq MSHR miss cycles 215910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25566861991 # number of ReadSharedReq MSHR miss cycles 216010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25566861991 # number of ReadSharedReq MSHR miss cycles 216110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12398047000 # number of InvalidateReq MSHR miss cycles 216210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12398047000 # number of InvalidateReq MSHR miss cycles 216310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of demand (read+write) MSHR miss cycles 216410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 302816000 # number of demand (read+write) MSHR miss cycles 216510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17491788500 # number of demand (read+write) MSHR miss cycles 216610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33201336488 # number of demand (read+write) MSHR miss cycles 216710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 51370370988 # number of demand (read+write) MSHR miss cycles 216810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of overall MSHR miss cycles 216910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 302816000 # number of overall MSHR miss cycles 217010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17491788500 # number of overall MSHR miss cycles 217110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33201336488 # number of overall MSHR miss cycles 217210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of overall MSHR miss cycles 217310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 82002825620 # number of overall MSHR miss cycles 217410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8104000 # number of ReadReq MSHR uncacheable cycles 217510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550842500 # number of ReadReq MSHR uncacheable cycles 217610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 558946500 # number of ReadReq MSHR uncacheable cycles 217710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 611561500 # number of WriteReq MSHR uncacheable cycles 217810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 611561500 # number of WriteReq MSHR uncacheable cycles 217910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8104000 # number of overall MSHR uncacheable cycles 218010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1162404000 # number of overall MSHR uncacheable cycles 218110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1170508000 # number of overall MSHR uncacheable cycles 218210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for ReadReq accesses 218310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for ReadReq accesses 218410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028961 # mshr miss rate for ReadReq accesses 218510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses 218610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses 218710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 218810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 218910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 219010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 219110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.663629 # mshr miss rate for UpgradeReq accesses 219210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.663629 # mshr miss rate for UpgradeReq accesses 219310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.807763 # mshr miss rate for SCUpgradeReq accesses 219410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.807763 # mshr miss rate for SCUpgradeReq accesses 219510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 219610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 219710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.203570 # mshr miss rate for ReadExReq accesses 219810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.203570 # mshr miss rate for ReadExReq accesses 219910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for ReadCleanReq accesses 220010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086224 # mshr miss rate for ReadCleanReq accesses 220110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.257602 # mshr miss rate for ReadSharedReq accesses 220210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257602 # mshr miss rate for ReadSharedReq accesses 220310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.583331 # mshr miss rate for InvalidateReq accesses 220410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.583331 # mshr miss rate for InvalidateReq accesses 220510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for demand accesses 220610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for demand accesses 220710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for demand accesses 220810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for demand accesses 220910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.136831 # mshr miss rate for demand accesses 221010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for overall accesses 221110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses 221210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses 221310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses 221410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 221510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses 221610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency 221710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency 221810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency 221910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency 222010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency 222110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency 222210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency 222310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency 222410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency 222510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency 222610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency 222710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency 222810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency 222910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency 223010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency 223110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency 223210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency 223310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency 223410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency 223510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency 223610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency 223710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency 223810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency 223910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency 224010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency 224110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency 224210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency 224310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency 224410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency 224510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency 224610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency 224710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency 224810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency 224910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency 225010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency 225110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency 225210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency 225310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency 225410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 225510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution 225610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution 225710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 225810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution 225910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution 226010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution 226110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution 226210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution 226310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution 226410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution 226510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution 226610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 226710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution 226810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution 226910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution 227010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution 227110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution 227210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution 227310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) 227410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) 227510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) 227610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) 227710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) 227810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) 227910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) 228010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) 228110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) 228210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) 228310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) 228410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram 228510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram 228610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram 228710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 228810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 228910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram 229010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram 229110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 229210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 229310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 229410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram 229510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) 229610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 229710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) 229810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 229910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) 230010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 230110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) 230210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 230310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) 230410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 230510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) 230610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 230710892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40322 # Transaction distribution 230810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40322 # Transaction distribution 230910892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136608 # Transaction distribution 231010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136608 # Transaction distribution 231110892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) 231210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 231310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 231410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 231510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 231610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 231710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 231810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 231910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 232010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 232110892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 232210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 232310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 232410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 232510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 232610892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) 232710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) 232810892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) 232910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 233010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 233110892Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) 233210892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) 233310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 233410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 233510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 233610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 233710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 234110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234210892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 234310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 234410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 234510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 234610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 234710892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) 234810892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) 234910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) 235010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 235110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 235210892Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) 235310892Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) 235410585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 235510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 235610585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 235710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 235810585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 235910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 236010585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 236110585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 236210585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 236310585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 236410585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 236510585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 236610585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 236710585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 236810585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 236910585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 237010585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 237110585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 237210585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 237310892Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 237410585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 237510585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 237610585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 237710585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 237810585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 237910585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 238010585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 238110892Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) 238210585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 238310585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 238410585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 238510892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) 238610585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 238710892Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) 238810585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 238910892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 239010585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 239110892Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115582 # number of replacements 239210892Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use 239310585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 239410892Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. 239510585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 239610892Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. 239710892Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor 239810892Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor 239910892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy 240010892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy 240110892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy 240210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 240310827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 240410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 240510892Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040766 # Number of tag accesses 240610892Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040766 # Number of data accesses 240710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 240810892Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses 240910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8910 # number of ReadReq misses 241010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 241110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 241210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 241310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 241410585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 241510892Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses 241610892Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8913 # number of demand (read+write) misses 241710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 241810892Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8873 # number of overall misses 241910892Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8913 # number of overall misses 242010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 242110892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles 242210892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles 242310726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 242410726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 242510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles 242610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles 242710892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 242810892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles 242910892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles 243010892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 243110892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles 243210892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles 243310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 243410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) 243510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) 243610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 243710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 243810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 243910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 244010585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 244110892Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses 244210892Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses 244310585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 244410892Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses 244510892Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses 244610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 244710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 244810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 244910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 245010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 245110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 245210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 245310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 245410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 245510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 245610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 245710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 245810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 245910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 246010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency 246110892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency 246210726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 246310726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 246410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency 246510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency 246610892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 246710892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency 246810892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency 246910892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 247010892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency 247110892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency 247210892Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked 247310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247410892Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked 247510585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 247610892Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked 247710585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247810585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 247910585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 248010892Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 248110892Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 248210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 248310892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses 248410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses 248510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 248610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 248710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 248810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 248910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 249010892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8873 # number of demand (read+write) MSHR misses 249110892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8913 # number of demand (read+write) MSHR misses 249210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 249310892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8873 # number of overall MSHR misses 249410892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8913 # number of overall MSHR misses 249510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 249610892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1187443968 # number of ReadReq MSHR miss cycles 249710892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1190788968 # number of ReadReq MSHR miss cycles 249810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 249910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 250010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288182114 # number of WriteLineReq MSHR miss cycles 250110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7288182114 # number of WriteLineReq MSHR miss cycles 250210892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 250310892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1187443968 # number of demand (read+write) MSHR miss cycles 250410892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1191007968 # number of demand (read+write) MSHR miss cycles 250510892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 250610892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1187443968 # number of overall MSHR miss cycles 250710892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1191007968 # number of overall MSHR miss cycles 250810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 250910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 251010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 251110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 251210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 251310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 251410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 251510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 251610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 251710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 251810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 251910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 252010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 252110892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 252210892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency 252310892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency 252410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 252510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 252610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040 # average WriteLineReq mshr miss latency 252710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040 # average WriteLineReq mshr miss latency 252810892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 252910892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency 253010892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency 253110892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 253210892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency 253310892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency 253410585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 253510892Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1460315 # number of replacements 253610892Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63815.106569 # Cycle average of tags in use 253710892Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6243583 # Total number of references to valid blocks. 253810892Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. 253910892Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. 254010892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 254110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor 254210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor 254310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor 254410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor 254510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor 254610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor 254710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor 254810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor 254910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor 255010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor 255110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor 255210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy 255310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy 255410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy 255510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy 255610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy 255710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy 255810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy 255910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # Average percentage of cache occupancy 256010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.060681 # Average percentage of cache occupancy 256110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.151407 # Average percentage of cache occupancy 256210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198735 # Average percentage of cache occupancy 256310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.973741 # Average percentage of cache occupancy 256410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9634 # Occupied blocks per task id 256510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id 256610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50762 # Occupied blocks per task id 256710892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 256810892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 450 # Occupied blocks per task id 256910892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 8970 # Occupied blocks per task id 257010892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 257110892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id 257210892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 257310892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 257410892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id 257510892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id 257610892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id 257710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id 257810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id 257910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id 258010892Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 74931302 # Number of tag accesses 258110892Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 74931302 # Number of data accesses 258210892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits 258310892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2473005 # number of Writeback hits 258410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 29717 # number of UpgradeReq hits 258510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 30251 # number of UpgradeReq hits 258610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 59968 # number of UpgradeReq hits 258710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 5861 # number of SCUpgradeReq hits 258810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 6611 # number of SCUpgradeReq hits 258910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 12472 # number of SCUpgradeReq hits 259010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 174264 # number of ReadExReq hits 259110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 168948 # number of ReadExReq hits 259210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 343212 # number of ReadExReq hits 259310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6955 # number of ReadSharedReq hits 259410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5054 # number of ReadSharedReq hits 259510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 704009 # number of ReadSharedReq hits 259610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 596815 # number of ReadSharedReq hits 259710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296922 # number of ReadSharedReq hits 259810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6236 # number of ReadSharedReq hits 259910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4142 # number of ReadSharedReq hits 260010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 738933 # number of ReadSharedReq hits 260110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 577563 # number of ReadSharedReq hits 260210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 321187 # number of ReadSharedReq hits 260310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 3257816 # number of ReadSharedReq hits 260410892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6955 # number of demand (read+write) hits 260510892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5054 # number of demand (read+write) hits 260610892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 704009 # number of demand (read+write) hits 260710892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 771079 # number of demand (read+write) hits 260810892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 296922 # number of demand (read+write) hits 260910892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits 261010892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4142 # number of demand (read+write) hits 261110892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 738933 # number of demand (read+write) hits 261210892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 746511 # number of demand (read+write) hits 261310892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 321187 # number of demand (read+write) hits 261410892Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3601028 # number of demand (read+write) hits 261510892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6955 # number of overall hits 261610892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5054 # number of overall hits 261710892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 704009 # number of overall hits 261810892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 771079 # number of overall hits 261910892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 296922 # number of overall hits 262010892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits 262110892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4142 # number of overall hits 262210892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 738933 # number of overall hits 262310892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 746511 # number of overall hits 262410892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 321187 # number of overall hits 262510892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3601028 # number of overall hits 262610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 43094 # number of UpgradeReq misses 262710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 44585 # number of UpgradeReq misses 262810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 87679 # number of UpgradeReq misses 262910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 8745 # number of SCUpgradeReq misses 263010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 9538 # number of SCUpgradeReq misses 263110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 18283 # number of SCUpgradeReq misses 263210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 499472 # number of ReadExReq misses 263310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 152688 # number of ReadExReq misses 263410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 652160 # number of ReadExReq misses 263510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq misses 263610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1581 # number of ReadSharedReq misses 263710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 73537 # number of ReadSharedReq misses 263810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 135426 # number of ReadSharedReq misses 263910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq misses 264010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq misses 264110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2077 # number of ReadSharedReq misses 264210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 50651 # number of ReadSharedReq misses 264310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 119141 # number of ReadSharedReq misses 264410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq misses 264510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 834591 # number of ReadSharedReq misses 264610892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1944 # number of demand (read+write) misses 264710892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1581 # number of demand (read+write) misses 264810892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 73537 # number of demand (read+write) misses 264910892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 634898 # number of demand (read+write) misses 265010892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) misses 265110892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2244 # number of demand (read+write) misses 265210892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2077 # number of demand (read+write) misses 265310892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 50651 # number of demand (read+write) misses 265410892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 271829 # number of demand (read+write) misses 265510892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) misses 265610892Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1486751 # number of demand (read+write) misses 265710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1944 # number of overall misses 265810892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1581 # number of overall misses 265910892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 73537 # number of overall misses 266010892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 634898 # number of overall misses 266110892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 239395 # number of overall misses 266210892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2244 # number of overall misses 266310892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2077 # number of overall misses 266410892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 50651 # number of overall misses 266510892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 271829 # number of overall misses 266610892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 208595 # number of overall misses 266710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1486751 # number of overall misses 266810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 260324500 # number of UpgradeReq miss cycles 266910892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 277994500 # number of UpgradeReq miss cycles 267010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 538319000 # number of UpgradeReq miss cycles 267110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 55253500 # number of SCUpgradeReq miss cycles 267210892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 54480000 # number of SCUpgradeReq miss cycles 267310892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 109733500 # number of SCUpgradeReq miss cycles 267410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 46824185500 # number of ReadExReq miss cycles 267510892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 13176547500 # number of ReadExReq miss cycles 267610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 60000733000 # number of ReadExReq miss cycles 267710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 176295500 # number of ReadSharedReq miss cycles 267810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 146583500 # number of ReadSharedReq miss cycles 267910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6133823500 # number of ReadSharedReq miss cycles 268010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 12343951000 # number of ReadSharedReq miss cycles 268110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of ReadSharedReq miss cycles 268210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 201877500 # number of ReadSharedReq miss cycles 268310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 184505000 # number of ReadSharedReq miss cycles 268410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 4199208000 # number of ReadSharedReq miss cycles 268510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 10504090000 # number of ReadSharedReq miss cycles 268610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of ReadSharedReq miss cycles 268710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 89739250464 # number of ReadSharedReq miss cycles 268810892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 176295500 # number of demand (read+write) miss cycles 268910892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 146583500 # number of demand (read+write) miss cycles 269010892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6133823500 # number of demand (read+write) miss cycles 269110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 59168136500 # number of demand (read+write) miss cycles 269210892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of demand (read+write) miss cycles 269310892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 201877500 # number of demand (read+write) miss cycles 269410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 184505000 # number of demand (read+write) miss cycles 269510892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 4199208000 # number of demand (read+write) miss cycles 269610892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 23680637500 # number of demand (read+write) miss cycles 269710892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of demand (read+write) miss cycles 269810892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 149739983464 # number of demand (read+write) miss cycles 269910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 176295500 # number of overall miss cycles 270010892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 146583500 # number of overall miss cycles 270110892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6133823500 # number of overall miss cycles 270210892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 59168136500 # number of overall miss cycles 270310892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of overall miss cycles 270410892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 201877500 # number of overall miss cycles 270510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 184505000 # number of overall miss cycles 270610892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 4199208000 # number of overall miss cycles 270710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 23680637500 # number of overall miss cycles 270810892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of overall miss cycles 270910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 149739983464 # number of overall miss cycles 271010892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2473005 # number of Writeback accesses(hits+misses) 271110892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2473005 # number of Writeback accesses(hits+misses) 271210892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 72811 # number of UpgradeReq accesses(hits+misses) 271310892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 74836 # number of UpgradeReq accesses(hits+misses) 271410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 147647 # number of UpgradeReq accesses(hits+misses) 271510892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 14606 # number of SCUpgradeReq accesses(hits+misses) 271610892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 16149 # number of SCUpgradeReq accesses(hits+misses) 271710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 30755 # number of SCUpgradeReq accesses(hits+misses) 271810892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 673736 # number of ReadExReq accesses(hits+misses) 271910892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 321636 # number of ReadExReq accesses(hits+misses) 272010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 995372 # number of ReadExReq accesses(hits+misses) 272110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8899 # number of ReadSharedReq accesses(hits+misses) 272210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6635 # number of ReadSharedReq accesses(hits+misses) 272310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 777546 # number of ReadSharedReq accesses(hits+misses) 272410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 732241 # number of ReadSharedReq accesses(hits+misses) 272510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 536317 # number of ReadSharedReq accesses(hits+misses) 272610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8480 # number of ReadSharedReq accesses(hits+misses) 272710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6219 # number of ReadSharedReq accesses(hits+misses) 272810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 789584 # number of ReadSharedReq accesses(hits+misses) 272910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 696704 # number of ReadSharedReq accesses(hits+misses) 273010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 529782 # number of ReadSharedReq accesses(hits+misses) 273110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 4092407 # number of ReadSharedReq accesses(hits+misses) 273210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8899 # number of demand (read+write) accesses 273310892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6635 # number of demand (read+write) accesses 273410892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 777546 # number of demand (read+write) accesses 273510892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1405977 # number of demand (read+write) accesses 273610892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 536317 # number of demand (read+write) accesses 273710892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8480 # number of demand (read+write) accesses 273810892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6219 # number of demand (read+write) accesses 273910892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 789584 # number of demand (read+write) accesses 274010892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1018340 # number of demand (read+write) accesses 274110892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 529782 # number of demand (read+write) accesses 274210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 5087779 # number of demand (read+write) accesses 274310892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8899 # number of overall (read+write) accesses 274410892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6635 # number of overall (read+write) accesses 274510892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 777546 # number of overall (read+write) accesses 274610892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1405977 # number of overall (read+write) accesses 274710892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 536317 # number of overall (read+write) accesses 274810892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8480 # number of overall (read+write) accesses 274910892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6219 # number of overall (read+write) accesses 275010892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 789584 # number of overall (read+write) accesses 275110892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1018340 # number of overall (read+write) accesses 275210892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 529782 # number of overall (read+write) accesses 275310892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 5087779 # number of overall (read+write) accesses 275410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.591861 # miss rate for UpgradeReq accesses 275510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.595769 # miss rate for UpgradeReq accesses 275610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.593842 # miss rate for UpgradeReq accesses 275710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598727 # miss rate for SCUpgradeReq accesses 275810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590625 # miss rate for SCUpgradeReq accesses 275910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.594472 # miss rate for SCUpgradeReq accesses 276010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.741347 # miss rate for ReadExReq accesses 276110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.474723 # miss rate for ReadExReq accesses 276210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.655192 # miss rate for ReadExReq accesses 276310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for ReadSharedReq accesses 276410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.238282 # miss rate for ReadSharedReq accesses 276510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.094576 # miss rate for ReadSharedReq accesses 276610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.184947 # miss rate for ReadSharedReq accesses 276710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for ReadSharedReq accesses 276810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for ReadSharedReq accesses 276910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.333977 # miss rate for ReadSharedReq accesses 277010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.064149 # miss rate for ReadSharedReq accesses 277110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171007 # miss rate for ReadSharedReq accesses 277210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for ReadSharedReq accesses 277310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.203936 # miss rate for ReadSharedReq accesses 277410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for demand accesses 277510892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.238282 # miss rate for demand accesses 277610892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.094576 # miss rate for demand accesses 277710892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.451571 # miss rate for demand accesses 277810892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for demand accesses 277910892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for demand accesses 278010892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.333977 # miss rate for demand accesses 278110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.064149 # miss rate for demand accesses 278210892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.266933 # miss rate for demand accesses 278310892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for demand accesses 278410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.292220 # miss rate for demand accesses 278510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for overall accesses 278610892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.238282 # miss rate for overall accesses 278710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.094576 # miss rate for overall accesses 278810892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.451571 # miss rate for overall accesses 278910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for overall accesses 279010892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for overall accesses 279110892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.333977 # miss rate for overall accesses 279210892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.064149 # miss rate for overall accesses 279310892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.266933 # miss rate for overall accesses 279410892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for overall accesses 279510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.292220 # miss rate for overall accesses 279610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6040.852555 # average UpgradeReq miss latency 279710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6235.157564 # average UpgradeReq miss latency 279810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6139.657158 # average UpgradeReq miss latency 279910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6318.296169 # average SCUpgradeReq miss latency 280010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5711.889285 # average SCUpgradeReq miss latency 280110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 6001.941694 # average SCUpgradeReq miss latency 280210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 93747.368221 # average ReadExReq miss latency 280310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 86297.204102 # average ReadExReq miss latency 280410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 92003.086666 # average ReadExReq miss latency 280510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average ReadSharedReq miss latency 280610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92715.686275 # average ReadSharedReq miss latency 280710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83411.391544 # average ReadSharedReq miss latency 280810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91149.048189 # average ReadSharedReq miss latency 280910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average ReadSharedReq miss latency 281010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average ReadSharedReq miss latency 281110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88832.450650 # average ReadSharedReq miss latency 281210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82904.740282 # average ReadSharedReq miss latency 281310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88165.199218 # average ReadSharedReq miss latency 281410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average ReadSharedReq miss latency 281510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 107524.824092 # average ReadSharedReq miss latency 281610892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency 281710892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency 281810892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency 281910892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency 282010892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency 282110892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency 282210892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency 282310892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency 282410892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency 282510892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency 282610892Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 100716.248695 # average overall miss latency 282710892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency 282810892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency 282910892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency 283010892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency 283110892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency 283210892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency 283310892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency 283410892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency 283510892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency 283610892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency 283710892Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 100716.248695 # average overall miss latency 283810892Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 107 # number of cycles access was blocked 283910515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 284010892Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 284110515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 284210892Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked 284310515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 284410515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 284510515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 284610892Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1116158 # number of writebacks 284710892Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1116158 # number of writebacks 284810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 174 # number of ReadSharedReq MSHR hits 284910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits 285010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 157 # number of ReadSharedReq MSHR hits 285110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits 285210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 360 # number of ReadSharedReq MSHR hits 285310892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 174 # number of demand (read+write) MSHR hits 285410892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits 285510892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits 285610892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 10 # number of demand (read+write) MSHR hits 285710892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits 285810892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 174 # number of overall MSHR hits 285910892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits 286010892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits 286110892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 10 # number of overall MSHR hits 286210892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 360 # number of overall MSHR hits 286310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 53748 # number of CleanEvict MSHR misses 286410892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 53748 # number of CleanEvict MSHR misses 286510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 43094 # number of UpgradeReq MSHR misses 286610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 44585 # number of UpgradeReq MSHR misses 286710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 87679 # number of UpgradeReq MSHR misses 286810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8745 # number of SCUpgradeReq MSHR misses 286910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9538 # number of SCUpgradeReq MSHR misses 287010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 18283 # number of SCUpgradeReq MSHR misses 287110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 499472 # number of ReadExReq MSHR misses 287210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 152688 # number of ReadExReq MSHR misses 287310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 652160 # number of ReadExReq MSHR misses 287410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq MSHR misses 287510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1581 # 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mshr miss rate for demand accesses 300410892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for demand accesses 300510892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for demand accesses 300610892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for demand accesses 300710892Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.292149 # mshr miss rate for demand accesses 300810892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for overall accesses 300910892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for overall accesses 301010892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for overall accesses 301110892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for overall accesses 301210892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for overall accesses 301310892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for overall accesses 301410892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for overall accesses 301510892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for overall accesses 301610892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for overall accesses 301710892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for overall accesses 301810892Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.292149 # mshr miss rate for overall accesses 301910892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878 # average UpgradeReq mshr miss latency 302010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136 # average UpgradeReq mshr miss latency 302110892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773 # average UpgradeReq mshr miss latency 302210892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659 # average SCUpgradeReq mshr miss latency 302310892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860 # average SCUpgradeReq mshr miss latency 302410892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207 # average SCUpgradeReq mshr miss latency 302510892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221 # average ReadExReq mshr miss latency 302610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102 # average ReadExReq mshr miss latency 302710892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666 # average ReadExReq mshr miss latency 302810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average ReadSharedReq mshr miss latency 302910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average ReadSharedReq mshr miss latency 303010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average ReadSharedReq mshr miss latency 303110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568 # average ReadSharedReq mshr miss latency 303210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average ReadSharedReq mshr miss latency 303310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average ReadSharedReq mshr miss latency 303410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average ReadSharedReq mshr miss latency 303510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average ReadSharedReq mshr miss latency 303610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712 # average ReadSharedReq mshr miss latency 303710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average ReadSharedReq mshr miss latency 303810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835 # average ReadSharedReq mshr miss latency 303910892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency 304010892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency 304110892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency 304210892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency 304310892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency 304410892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency 304510892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency 304610892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency 304710892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency 304810892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency 304910892Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency 305010892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency 305110892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency 305210892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency 305310892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency 305410892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency 305510892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency 305610892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency 305710892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency 305810892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency 305910892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency 306010892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency 306110892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency 306210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency 306310892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency 306410892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency 306510892Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency 306610892Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency 306710892Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency 306810892Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency 306910892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency 307010892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency 307110892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency 307210892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency 307310892Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency 307410515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 307510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 90631 # Transaction distribution 307610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 933772 # Transaction distribution 307710892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38095 # Transaction distribution 307810892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38095 # Transaction distribution 307910892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1222852 # Transaction distribution 308010892Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 259291 # Transaction distribution 308110892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 429274 # Transaction distribution 308210892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution 308310892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 113465 # Transaction distribution 308410892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 308510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 664837 # Transaction distribution 308610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 644660 # Transaction distribution 308710892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution 308810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 308910892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 309010892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) 309110585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 309210892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) 309310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) 309410892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) 309510892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) 309610892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) 309710892Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) 309810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) 309910585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 310010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) 310110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) 310210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) 310310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) 310410892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) 310510892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) 310610892Sandreas.hansson@arm.comsystem.membus.snoops 639479 # Total snoops (count) 310710892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3957833 # Request fanout histogram 310810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 310910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 311010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 311110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 311210892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram 311310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 311410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 311510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 311610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 311710892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3957833 # Request fanout histogram 311810892Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) 311910585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 312010892Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 312110585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 312210892Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) 312310585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 312410892Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) 312510585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 312610892Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) 312710585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 312810892Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) 312910585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 313010515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 313110515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 313210515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 313310515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 313410515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 313510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 313610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 313710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 313810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 313910515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 314010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 314110515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 314210515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 314310515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 314410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 314510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 314610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 314710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 314810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 314910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 315010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 315110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 315210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 315310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 315410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 315510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 315610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 315710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 315810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 315910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 316010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 316110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 316210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 316310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 316410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 316510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 316610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 316710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 316810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 316910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 317010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 317110515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 317210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution 317310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution 317410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 317510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution 317610892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution 317710892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution 317810892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution 317910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution 318010892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution 318110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution 318210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 318310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution 318410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution 318510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution 318610892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 318710892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) 318810892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) 318910892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) 319010892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) 319110892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) 319210892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) 319310892Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3318184 # Total snoops (count) 319410892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram 319510892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram 319610892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram 319710515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 319810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 319910892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram 320010892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram 320110515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 320210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 320310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 320410892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram 320510892Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) 320610515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 320710892Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) 320810515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 320910892Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) 321010515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 321110892Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) 321210515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 321310515SAli.Saidi@ARM.com 321410515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3215