stats.txt revision 10892
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.482330 # Number of seconds simulated 4sim_ticks 47482329862000 # Number of ticks simulated 5final_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 176341 # Simulator instruction rate (inst/s) 8host_op_rate 207374 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9393535208 # Simulator tick rate (ticks/s) 10host_mem_usage 769764 # Number of bytes of host memory used 11host_seconds 5054.79 # Real time elapsed on the host 12sim_insts 891365561 # Number of instructions simulated 13sim_ops 1048233259 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory 27system.physmem.bytes_read::total 98400600 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 78283112 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1537535 # Number of read requests accepted 84system.physmem.writeReqs 1225426 # Number of write requests accepted 85system.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue 89system.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 94941 # Per bank write bursts 96system.physmem.perBankRdBursts::1 98803 # Per bank write bursts 97system.physmem.perBankRdBursts::2 90365 # Per bank write bursts 98system.physmem.perBankRdBursts::3 103122 # Per bank write bursts 99system.physmem.perBankRdBursts::4 90513 # Per bank write bursts 100system.physmem.perBankRdBursts::5 102407 # Per bank write bursts 101system.physmem.perBankRdBursts::6 86370 # Per bank write bursts 102system.physmem.perBankRdBursts::7 97727 # Per bank write bursts 103system.physmem.perBankRdBursts::8 90531 # Per bank write bursts 104system.physmem.perBankRdBursts::9 141203 # Per bank write bursts 105system.physmem.perBankRdBursts::10 86748 # Per bank write bursts 106system.physmem.perBankRdBursts::11 95428 # Per bank write bursts 107system.physmem.perBankRdBursts::12 92596 # Per bank write bursts 108system.physmem.perBankRdBursts::13 93840 # Per bank write bursts 109system.physmem.perBankRdBursts::14 85305 # Per bank write bursts 110system.physmem.perBankRdBursts::15 87009 # Per bank write bursts 111system.physmem.perBankWrBursts::0 77173 # Per bank write bursts 112system.physmem.perBankWrBursts::1 80360 # Per bank write bursts 113system.physmem.perBankWrBursts::2 74652 # Per bank write bursts 114system.physmem.perBankWrBursts::3 83758 # Per bank write bursts 115system.physmem.perBankWrBursts::4 75004 # Per bank write bursts 116system.physmem.perBankWrBursts::5 81344 # Per bank write bursts 117system.physmem.perBankWrBursts::6 71841 # Per bank write bursts 118system.physmem.perBankWrBursts::7 79366 # Per bank write bursts 119system.physmem.perBankWrBursts::8 74851 # Per bank write bursts 120system.physmem.perBankWrBursts::9 75375 # Per bank write bursts 121system.physmem.perBankWrBursts::10 73319 # Per bank write bursts 122system.physmem.perBankWrBursts::11 78054 # Per bank write bursts 123system.physmem.perBankWrBursts::12 76445 # Per bank write bursts 124system.physmem.perBankWrBursts::13 77751 # Per bank write bursts 125system.physmem.perBankWrBursts::14 70793 # Per bank write bursts 126system.physmem.perBankWrBursts::15 73072 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 43 # Number of times write queue was full causing retry 129system.physmem.totGap 47482327991500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1537505 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1222852 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 79113 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 78742 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 81088 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 80039 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 81169 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 88387 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 80912 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 76308 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 72380 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1847 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1076 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 779 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 575 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 452 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 472 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 442 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 426 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 352 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 360 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 419 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 384 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 350 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 317 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 378 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 306 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads 300system.physmem.totQLat 47438420321 # Total ticks spent queuing 301system.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.03 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing 316system.physmem.readRowHits 1237162 # Number of row buffer hits during reads 317system.physmem.writeRowHits 582295 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes 320system.physmem.avgGap 17185305.18 # Average gap between requests 321system.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) 330system.physmem_0.averagePower 668.749891 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states 332system.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) 344system.physmem_1.averagePower 668.711548 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states 346system.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 357system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 358system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 363system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 376system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 377system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 378system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 379system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 380system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 381system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 382system.cpu0.branchPred.lookups 132987745 # Number of BP lookups 383system.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted 384system.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect 385system.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups 386system.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits 387system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 388system.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage 389system.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. 390system.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. 391system.cpu_clk_domain.clock 500 # Clock period in ticks 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 401system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 402system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 403system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 404system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 405system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 410system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 411system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 416system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 417system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 418system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 419system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 420system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 421system.cpu0.dtb.walker.walks 275636 # Table walker walks requested 422system.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate 425system.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.inst_hits 0 # ITB inst hits 461system.cpu0.dtb.inst_misses 0 # ITB inst misses 462system.cpu0.dtb.read_hits 84907220 # DTB read hits 463system.cpu0.dtb.read_misses 227423 # DTB read misses 464system.cpu0.dtb.write_hits 75575788 # DTB write hits 465system.cpu0.dtb.write_misses 48213 # DTB write misses 466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 468system.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 469system.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 470system.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB 471system.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions 472system.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch 473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions 475system.cpu0.dtb.read_accesses 85134643 # DTB read accesses 476system.cpu0.dtb.write_accesses 75624001 # DTB write accesses 477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 478system.cpu0.dtb.hits 160483008 # DTB hits 479system.cpu0.dtb.misses 275636 # DTB misses 480system.cpu0.dtb.accesses 160758644 # DTB accesses 481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 490system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 491system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 492system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 493system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 494system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 499system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 500system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 501system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 510system.cpu0.itb.walker.walks 64906 # Table walker walks requested 511system.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors 512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate 513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate 514system.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution 538system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution 539system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution 540system.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated 541system.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated 542system.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated 543system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst 550system.cpu0.itb.inst_hits 238223958 # ITB inst hits 551system.cpu0.itb.inst_misses 64906 # ITB inst misses 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 558system.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 559system.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 560system.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses 567system.cpu0.itb.inst_accesses 238288864 # ITB inst accesses 568system.cpu0.itb.hits 238223958 # DTB hits 569system.cpu0.itb.misses 64906 # DTB misses 570system.cpu0.itb.accesses 238288864 # DTB accesses 571system.cpu0.numCycles 971262699 # number of cpu cycles simulated 572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 574system.cpu0.committedInsts 437915417 # Number of instructions committed 575system.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed 576system.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit 577system.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching 578system.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 579system.cpu0.cpi 2.217923 # CPI: cycles per instruction 580system.cpu0.ipc 0.450872 # IPC: instructions per cycle 581system.cpu0.kern.inst.arm 0 # number of arm instructions executed 582system.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed 583system.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked 584system.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped 585system.cpu0.dcache.tags.replacements 5570429 # number of replacements 586system.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use 587system.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. 588system.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. 589system.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. 590system.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. 591system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor 592system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy 593system.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy 594system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 596system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 597system.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 598system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id 599system.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses 600system.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses 601system.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits 602system.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits 603system.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits 604system.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits 605system.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits 606system.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits 607system.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits 608system.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits 609system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits 610system.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits 611system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits 612system.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits 613system.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits 614system.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits 615system.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits 616system.cpu0.dcache.overall_hits::total 147839299 # number of overall hits 617system.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses 618system.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses 619system.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses 620system.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses 621system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses 622system.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses 623system.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses 624system.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses 625system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses 626system.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses 627system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses 628system.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses 629system.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses 630system.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses 631system.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses 632system.cpu0.dcache.overall_misses::total 6435225 # number of overall misses 633system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles 634system.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles 635system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles 636system.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles 637system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles 638system.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles 639system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles 640system.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles 641system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles 642system.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles 643system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles 644system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles 645system.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles 646system.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles 647system.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles 648system.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles 649system.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) 650system.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) 651system.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) 652system.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) 653system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) 654system.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) 655system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) 656system.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) 657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) 661system.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses 662system.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses 663system.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses 664system.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses 665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses 666system.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses 667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses 669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses 672system.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses 673system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses 674system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses 675system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses 676system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses 677system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses 678system.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses 679system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses 680system.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses 681system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency 682system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency 683system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency 684system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency 685system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency 686system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency 687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency 688system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency 689system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency 690system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency 691system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 692system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 693system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782 # average overall miss latency 694system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency 695system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency 696system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency 697system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 698system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 699system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 700system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 701system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 702system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 703system.cpu0.dcache.fast_writes 0 # number of fast writes performed 704system.cpu0.dcache.cache_copies 0 # number of cache copies performed 705system.cpu0.dcache.writebacks::writebacks 3773399 # number of writebacks 706system.cpu0.dcache.writebacks::total 3773399 # number of writebacks 707system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 430069 # number of ReadReq MSHR hits 708system.cpu0.dcache.ReadReq_mshr_hits::total 430069 # number of ReadReq MSHR hits 709system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 999795 # number of WriteReq MSHR hits 710system.cpu0.dcache.WriteReq_mshr_hits::total 999795 # number of WriteReq MSHR hits 711system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 103 # number of WriteLineReq MSHR hits 712system.cpu0.dcache.WriteLineReq_mshr_hits::total 103 # number of WriteLineReq MSHR hits 713system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40774 # number of LoadLockedReq MSHR hits 714system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40774 # number of LoadLockedReq MSHR hits 715system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits 716system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits 717system.cpu0.dcache.demand_mshr_hits::cpu0.data 1429864 # number of demand (read+write) MSHR hits 718system.cpu0.dcache.demand_mshr_hits::total 1429864 # number of demand (read+write) MSHR hits 719system.cpu0.dcache.overall_mshr_hits::cpu0.data 1429864 # number of overall MSHR hits 720system.cpu0.dcache.overall_mshr_hits::total 1429864 # number of overall MSHR hits 721system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2950578 # number of ReadReq MSHR misses 722system.cpu0.dcache.ReadReq_mshr_misses::total 2950578 # number of ReadReq MSHR misses 723system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1384389 # number of WriteReq MSHR misses 724system.cpu0.dcache.WriteReq_mshr_misses::total 1384389 # number of WriteReq MSHR misses 725system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664773 # number of SoftPFReq MSHR misses 726system.cpu0.dcache.SoftPFReq_mshr_misses::total 664773 # number of SoftPFReq MSHR misses 727system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 781233 # number of WriteLineReq MSHR misses 728system.cpu0.dcache.WriteLineReq_mshr_misses::total 781233 # number of WriteLineReq MSHR misses 729system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114009 # number of LoadLockedReq MSHR misses 730system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114009 # number of LoadLockedReq MSHR misses 731system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189777 # number of StoreCondReq MSHR misses 732system.cpu0.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses 733system.cpu0.dcache.demand_mshr_misses::cpu0.data 4334967 # number of demand (read+write) MSHR misses 734system.cpu0.dcache.demand_mshr_misses::total 4334967 # number of demand (read+write) MSHR misses 735system.cpu0.dcache.overall_mshr_misses::cpu0.data 4999740 # number of overall MSHR misses 736system.cpu0.dcache.overall_mshr_misses::total 4999740 # number of overall MSHR misses 737system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable 738system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32882 # number of ReadReq MSHR uncacheable 739system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable 740system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable 741system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses 742system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65697 # number of overall MSHR uncacheable misses 743system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40501320500 # number of ReadReq MSHR miss cycles 744system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40501320500 # number of ReadReq MSHR miss cycles 745system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25594559000 # number of WriteReq MSHR miss cycles 746system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25594559000 # number of WriteReq MSHR miss cycles 747system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15267286500 # number of SoftPFReq MSHR miss cycles 748system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15267286500 # number of SoftPFReq MSHR miss cycles 749system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 51557242500 # number of WriteLineReq MSHR miss cycles 750system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51557242500 # number of WriteLineReq MSHR miss cycles 751system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1530630500 # number of LoadLockedReq MSHR miss cycles 752system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1530630500 # number of LoadLockedReq MSHR miss cycles 753system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3798446000 # number of StoreCondReq MSHR miss cycles 754system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3798446000 # number of StoreCondReq MSHR miss cycles 755system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2841500 # number of StoreCondFailReq MSHR miss cycles 756system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles 757system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 66095879500 # number of demand (read+write) MSHR miss cycles 758system.cpu0.dcache.demand_mshr_miss_latency::total 66095879500 # number of demand (read+write) MSHR miss cycles 759system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81363166000 # number of overall MSHR miss cycles 760system.cpu0.dcache.overall_mshr_miss_latency::total 81363166000 # number of overall MSHR miss cycles 761system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5911844500 # number of ReadReq MSHR uncacheable cycles 762system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5911844500 # number of ReadReq MSHR uncacheable cycles 763system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5682739500 # number of WriteReq MSHR uncacheable cycles 764system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5682739500 # number of WriteReq MSHR uncacheable cycles 765system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11594584000 # number of overall MSHR uncacheable cycles 766system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11594584000 # number of overall MSHR uncacheable cycles 767system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadReq accesses 768system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036430 # mshr miss rate for ReadReq accesses 769system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019135 # mshr miss rate for WriteReq accesses 770system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019135 # mshr miss rate for WriteReq accesses 771system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711871 # mshr miss rate for SoftPFReq accesses 772system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711871 # mshr miss rate for SoftPFReq accesses 773system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.821508 # mshr miss rate for WriteLineReq accesses 774system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.821508 # mshr miss rate for WriteLineReq accesses 775system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059591 # mshr miss rate for LoadLockedReq accesses 776system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059591 # mshr miss rate for LoadLockedReq accesses 777system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099280 # mshr miss rate for StoreCondReq accesses 778system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099280 # mshr miss rate for StoreCondReq accesses 779system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses 780system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses 781system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for overall accesses 782system.cpu0.dcache.overall_mshr_miss_rate::total 0.032408 # mshr miss rate for overall accesses 783system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709 # average ReadReq mshr miss latency 784system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709 # average ReadReq mshr miss latency 785system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063 # average WriteReq mshr miss latency 786system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063 # average WriteReq mshr miss latency 787system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142 # average SoftPFReq mshr miss latency 788system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142 # average SoftPFReq mshr miss latency 789system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445 # average WriteLineReq mshr miss latency 790system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445 # average WriteLineReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424 # average LoadLockedReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709 # average StoreCondReq mshr miss latency 794system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709 # average StoreCondReq mshr miss latency 795system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 796system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 797system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095 # average overall mshr miss latency 798system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095 # average overall mshr miss latency 799system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421 # average overall mshr miss latency 800system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421 # average overall mshr miss latency 801system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367 # average ReadReq mshr uncacheable latency 802system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367 # average ReadReq mshr uncacheable latency 803system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139 # average WriteReq mshr uncacheable latency 804system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139 # average WriteReq mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163 # average overall mshr uncacheable latency 806system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163 # average overall mshr uncacheable latency 807system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu0.icache.tags.replacements 9510825 # number of replacements 809system.cpu0.icache.tags.tagsinuse 511.926606 # Cycle average of tags in use 810system.cpu0.icache.tags.total_refs 228501569 # Total number of references to valid blocks. 811system.cpu0.icache.tags.sampled_refs 9511337 # Sample count of references to valid blocks. 812system.cpu0.icache.tags.avg_refs 24.024127 # Average number of references to valid blocks. 813system.cpu0.icache.tags.warmup_cycle 29799763000 # Cycle when the warmup percentage was hit. 814system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926606 # Average occupied blocks per requestor 815system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy 816system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy 817system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 818system.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 819system.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id 820system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 821system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 822system.cpu0.icache.tags.tag_accesses 485537176 # Number of tag accesses 823system.cpu0.icache.tags.data_accesses 485537176 # Number of data accesses 824system.cpu0.icache.ReadReq_hits::cpu0.inst 228501569 # number of ReadReq hits 825system.cpu0.icache.ReadReq_hits::total 228501569 # number of ReadReq hits 826system.cpu0.icache.demand_hits::cpu0.inst 228501569 # number of demand (read+write) hits 827system.cpu0.icache.demand_hits::total 228501569 # number of demand (read+write) hits 828system.cpu0.icache.overall_hits::cpu0.inst 228501569 # number of overall hits 829system.cpu0.icache.overall_hits::total 228501569 # number of overall hits 830system.cpu0.icache.ReadReq_misses::cpu0.inst 9511346 # number of ReadReq misses 831system.cpu0.icache.ReadReq_misses::total 9511346 # number of ReadReq misses 832system.cpu0.icache.demand_misses::cpu0.inst 9511346 # number of demand (read+write) misses 833system.cpu0.icache.demand_misses::total 9511346 # number of demand (read+write) misses 834system.cpu0.icache.overall_misses::cpu0.inst 9511346 # number of overall misses 835system.cpu0.icache.overall_misses::total 9511346 # number of overall misses 836system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94734195000 # number of ReadReq miss cycles 837system.cpu0.icache.ReadReq_miss_latency::total 94734195000 # number of ReadReq miss cycles 838system.cpu0.icache.demand_miss_latency::cpu0.inst 94734195000 # number of demand (read+write) miss cycles 839system.cpu0.icache.demand_miss_latency::total 94734195000 # number of demand (read+write) miss cycles 840system.cpu0.icache.overall_miss_latency::cpu0.inst 94734195000 # number of overall miss cycles 841system.cpu0.icache.overall_miss_latency::total 94734195000 # number of overall miss cycles 842system.cpu0.icache.ReadReq_accesses::cpu0.inst 238012915 # number of ReadReq accesses(hits+misses) 843system.cpu0.icache.ReadReq_accesses::total 238012915 # number of ReadReq accesses(hits+misses) 844system.cpu0.icache.demand_accesses::cpu0.inst 238012915 # number of demand (read+write) accesses 845system.cpu0.icache.demand_accesses::total 238012915 # number of demand (read+write) accesses 846system.cpu0.icache.overall_accesses::cpu0.inst 238012915 # number of overall (read+write) accesses 847system.cpu0.icache.overall_accesses::total 238012915 # number of overall (read+write) accesses 848system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039961 # miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_miss_rate::total 0.039961 # miss rate for ReadReq accesses 850system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039961 # miss rate for demand accesses 851system.cpu0.icache.demand_miss_rate::total 0.039961 # miss rate for demand accesses 852system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039961 # miss rate for overall accesses 853system.cpu0.icache.overall_miss_rate::total 0.039961 # miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9960.124992 # average ReadReq miss latency 855system.cpu0.icache.ReadReq_avg_miss_latency::total 9960.124992 # average ReadReq miss latency 856system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency 857system.cpu0.icache.demand_avg_miss_latency::total 9960.124992 # average overall miss latency 858system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency 859system.cpu0.icache.overall_avg_miss_latency::total 9960.124992 # average overall miss latency 860system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 861system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 862system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 863system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 864system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 865system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 866system.cpu0.icache.fast_writes 0 # number of fast writes performed 867system.cpu0.icache.cache_copies 0 # number of cache copies performed 868system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9511346 # number of ReadReq MSHR misses 869system.cpu0.icache.ReadReq_mshr_misses::total 9511346 # number of ReadReq MSHR misses 870system.cpu0.icache.demand_mshr_misses::cpu0.inst 9511346 # number of demand (read+write) MSHR misses 871system.cpu0.icache.demand_mshr_misses::total 9511346 # number of demand (read+write) MSHR misses 872system.cpu0.icache.overall_mshr_misses::cpu0.inst 9511346 # number of overall MSHR misses 873system.cpu0.icache.overall_mshr_misses::total 9511346 # number of overall MSHR misses 874system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 875system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable 876system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 877system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses 878system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89978522000 # number of ReadReq MSHR miss cycles 879system.cpu0.icache.ReadReq_mshr_miss_latency::total 89978522000 # number of ReadReq MSHR miss cycles 880system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89978522000 # number of demand (read+write) MSHR miss cycles 881system.cpu0.icache.demand_mshr_miss_latency::total 89978522000 # number of demand (read+write) MSHR miss cycles 882system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89978522000 # number of overall MSHR miss cycles 883system.cpu0.icache.overall_mshr_miss_latency::total 89978522000 # number of overall MSHR miss cycles 884system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles 885system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles 886system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles 887system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles 888system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for ReadReq accesses 889system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039961 # mshr miss rate for ReadReq accesses 890system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for demand accesses 891system.cpu0.icache.demand_mshr_miss_rate::total 0.039961 # mshr miss rate for demand accesses 892system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for overall accesses 893system.cpu0.icache.overall_mshr_miss_rate::total 0.039961 # mshr miss rate for overall accesses 894system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average ReadReq mshr miss latency 895system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9460.124992 # average ReadReq mshr miss latency 896system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency 897system.cpu0.icache.demand_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency 898system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency 899system.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency 900system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency 901system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency 902system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency 903system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency 904system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.cpu0.l2cache.prefetcher.num_hwpf_issued 7512189 # number of hwpf issued 906system.cpu0.l2cache.prefetcher.pfIdentified 7515615 # number of prefetch candidates identified 907system.cpu0.l2cache.prefetcher.pfBufferHit 2942 # number of redundant prefetches already in prefetch queue 908system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 909system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 910system.cpu0.l2cache.prefetcher.pfSpanPage 975521 # number of prefetches not generated due to page crossing 911system.cpu0.l2cache.tags.replacements 2798117 # number of replacements 912system.cpu0.l2cache.tags.tagsinuse 16231.650842 # Cycle average of tags in use 913system.cpu0.l2cache.tags.total_refs 26314432 # Total number of references to valid blocks. 914system.cpu0.l2cache.tags.sampled_refs 2814109 # Sample count of references to valid blocks. 915system.cpu0.l2cache.tags.avg_refs 9.350893 # Average number of references to valid blocks. 916system.cpu0.l2cache.tags.warmup_cycle 27335773000 # Cycle when the warmup percentage was hit. 917system.cpu0.l2cache.tags.occ_blocks::writebacks 6405.405319 # Average occupied blocks per requestor 918system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.558250 # Average occupied blocks per requestor 919system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.359829 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor 921system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor 922system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor 923system.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy 924system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy 925system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy 926system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy 927system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy 928system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy 929system.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy 930system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id 931system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id 932system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 685 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 484 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id 942system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4037 # Occupied blocks per task id 943system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5036 # Occupied blocks per task id 944system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4531 # Occupied blocks per task id 945system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089417 # Percentage of cache occupancy per task id 946system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id 947system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.881409 # Percentage of cache occupancy per task id 948system.cpu0.l2cache.tags.tag_accesses 507029075 # Number of tag accesses 949system.cpu0.l2cache.tags.data_accesses 507029075 # Number of data accesses 950system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 480958 # number of ReadReq hits 951system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155860 # number of ReadReq hits 952system.cpu0.l2cache.ReadReq_hits::total 636818 # number of ReadReq hits 953system.cpu0.l2cache.Writeback_hits::writebacks 3773399 # number of Writeback hits 954system.cpu0.l2cache.Writeback_hits::total 3773399 # number of Writeback hits 955system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 109301 # number of UpgradeReq hits 956system.cpu0.l2cache.UpgradeReq_hits::total 109301 # number of UpgradeReq hits 957system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 35296 # number of SCUpgradeReq hits 958system.cpu0.l2cache.SCUpgradeReq_hits::total 35296 # number of SCUpgradeReq hits 959system.cpu0.l2cache.ReadExReq_hits::cpu0.data 877723 # number of ReadExReq hits 960system.cpu0.l2cache.ReadExReq_hits::total 877723 # number of ReadExReq hits 961system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8733791 # number of ReadCleanReq hits 962system.cpu0.l2cache.ReadCleanReq_hits::total 8733791 # number of ReadCleanReq hits 963system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2708727 # number of ReadSharedReq hits 964system.cpu0.l2cache.ReadSharedReq_hits::total 2708727 # number of ReadSharedReq hits 965system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 190451 # number of InvalidateReq hits 966system.cpu0.l2cache.InvalidateReq_hits::total 190451 # number of InvalidateReq hits 967system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 480958 # number of demand (read+write) hits 968system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155860 # number of demand (read+write) hits 969system.cpu0.l2cache.demand_hits::cpu0.inst 8733791 # number of demand (read+write) hits 970system.cpu0.l2cache.demand_hits::cpu0.data 3586450 # number of demand (read+write) hits 971system.cpu0.l2cache.demand_hits::total 12957059 # number of demand (read+write) hits 972system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 480958 # number of overall hits 973system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155860 # number of overall hits 974system.cpu0.l2cache.overall_hits::cpu0.inst 8733791 # number of overall hits 975system.cpu0.l2cache.overall_hits::cpu0.data 3586450 # number of overall hits 976system.cpu0.l2cache.overall_hits::total 12957059 # number of overall hits 977system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12195 # number of ReadReq misses 978system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8813 # number of ReadReq misses 979system.cpu0.l2cache.ReadReq_misses::total 21008 # number of ReadReq misses 980system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 130468 # number of UpgradeReq misses 981system.cpu0.l2cache.UpgradeReq_misses::total 130468 # number of UpgradeReq misses 982system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154478 # number of SCUpgradeReq misses 983system.cpu0.l2cache.SCUpgradeReq_misses::total 154478 # number of SCUpgradeReq misses 984system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 985system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 986system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278567 # number of ReadExReq misses 987system.cpu0.l2cache.ReadExReq_misses::total 278567 # number of ReadExReq misses 988system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 777554 # number of ReadCleanReq misses 989system.cpu0.l2cache.ReadCleanReq_misses::total 777554 # number of ReadCleanReq misses 990system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1020411 # number of ReadSharedReq misses 991system.cpu0.l2cache.ReadSharedReq_misses::total 1020411 # number of ReadSharedReq misses 992system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 589182 # number of InvalidateReq misses 993system.cpu0.l2cache.InvalidateReq_misses::total 589182 # number of InvalidateReq misses 994system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12195 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8813 # number of demand (read+write) misses 996system.cpu0.l2cache.demand_misses::cpu0.inst 777554 # number of demand (read+write) misses 997system.cpu0.l2cache.demand_misses::cpu0.data 1298978 # number of demand (read+write) misses 998system.cpu0.l2cache.demand_misses::total 2097540 # number of demand (read+write) misses 999system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12195 # number of overall misses 1000system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8813 # number of overall misses 1001system.cpu0.l2cache.overall_misses::cpu0.inst 777554 # number of overall misses 1002system.cpu0.l2cache.overall_misses::cpu0.data 1298978 # number of overall misses 1003system.cpu0.l2cache.overall_misses::total 2097540 # number of overall misses 1004system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 429581500 # number of ReadReq miss cycles 1005system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 328472000 # number of ReadReq miss cycles 1006system.cpu0.l2cache.ReadReq_miss_latency::total 758053500 # number of ReadReq miss cycles 1007system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2811659500 # number of UpgradeReq miss cycles 1008system.cpu0.l2cache.UpgradeReq_miss_latency::total 2811659500 # number of UpgradeReq miss cycles 1009system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3201796000 # number of SCUpgradeReq miss cycles 1010system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3201796000 # number of SCUpgradeReq miss cycles 1011system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2748498 # number of SCUpgradeFailReq miss cycles 1012system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2748498 # number of SCUpgradeFailReq miss cycles 1013system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13465224999 # number of ReadExReq miss cycles 1014system.cpu0.l2cache.ReadExReq_miss_latency::total 13465224999 # number of ReadExReq miss cycles 1015system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23641079500 # number of ReadCleanReq miss cycles 1016system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23641079500 # number of ReadCleanReq miss cycles 1017system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33953780489 # number of ReadSharedReq miss cycles 1018system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33953780489 # number of ReadSharedReq miss cycles 1019system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 49014503000 # number of InvalidateReq miss cycles 1020system.cpu0.l2cache.InvalidateReq_miss_latency::total 49014503000 # number of InvalidateReq miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 429581500 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 328472000 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23641079500 # number of demand (read+write) miss cycles 1024system.cpu0.l2cache.demand_miss_latency::cpu0.data 47419005488 # number of demand (read+write) miss cycles 1025system.cpu0.l2cache.demand_miss_latency::total 71818138488 # number of demand (read+write) miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 429581500 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 328472000 # number of overall miss cycles 1028system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23641079500 # number of overall miss cycles 1029system.cpu0.l2cache.overall_miss_latency::cpu0.data 47419005488 # number of overall miss cycles 1030system.cpu0.l2cache.overall_miss_latency::total 71818138488 # number of overall miss cycles 1031system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 493153 # number of ReadReq accesses(hits+misses) 1032system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164673 # number of ReadReq accesses(hits+misses) 1033system.cpu0.l2cache.ReadReq_accesses::total 657826 # number of ReadReq accesses(hits+misses) 1034system.cpu0.l2cache.Writeback_accesses::writebacks 3773399 # number of Writeback accesses(hits+misses) 1035system.cpu0.l2cache.Writeback_accesses::total 3773399 # number of Writeback accesses(hits+misses) 1036system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 239769 # number of UpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.UpgradeReq_accesses::total 239769 # number of UpgradeReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189774 # number of SCUpgradeReq accesses(hits+misses) 1039system.cpu0.l2cache.SCUpgradeReq_accesses::total 189774 # number of SCUpgradeReq accesses(hits+misses) 1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1041system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1156290 # number of ReadExReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadExReq_accesses::total 1156290 # number of ReadExReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9511345 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadCleanReq_accesses::total 9511345 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3729138 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu0.l2cache.ReadSharedReq_accesses::total 3729138 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 779633 # number of InvalidateReq accesses(hits+misses) 1049system.cpu0.l2cache.InvalidateReq_accesses::total 779633 # number of InvalidateReq accesses(hits+misses) 1050system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 493153 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164673 # number of demand (read+write) accesses 1052system.cpu0.l2cache.demand_accesses::cpu0.inst 9511345 # number of demand (read+write) accesses 1053system.cpu0.l2cache.demand_accesses::cpu0.data 4885428 # number of demand (read+write) accesses 1054system.cpu0.l2cache.demand_accesses::total 15054599 # number of demand (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 493153 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164673 # number of overall (read+write) accesses 1057system.cpu0.l2cache.overall_accesses::cpu0.inst 9511345 # number of overall (read+write) accesses 1058system.cpu0.l2cache.overall_accesses::cpu0.data 4885428 # number of overall (read+write) accesses 1059system.cpu0.l2cache.overall_accesses::total 15054599 # number of overall (read+write) accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053518 # miss rate for ReadReq accesses 1062system.cpu0.l2cache.ReadReq_miss_rate::total 0.031935 # miss rate for ReadReq accesses 1063system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.544140 # miss rate for UpgradeReq accesses 1064system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.544140 # miss rate for UpgradeReq accesses 1065system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814010 # miss rate for SCUpgradeReq accesses 1066system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814010 # miss rate for SCUpgradeReq accesses 1067system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1068system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1069system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240914 # miss rate for ReadExReq accesses 1070system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240914 # miss rate for ReadExReq accesses 1071system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.081750 # miss rate for ReadCleanReq accesses 1072system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.081750 # miss rate for ReadCleanReq accesses 1073system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.273632 # miss rate for ReadSharedReq accesses 1074system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.273632 # miss rate for ReadSharedReq accesses 1075system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755717 # miss rate for InvalidateReq accesses 1076system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755717 # miss rate for InvalidateReq accesses 1077system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for demand accesses 1078system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053518 # miss rate for demand accesses 1079system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.081750 # miss rate for demand accesses 1080system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.265888 # miss rate for demand accesses 1081system.cpu0.l2cache.demand_miss_rate::total 0.139329 # miss rate for demand accesses 1082system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for overall accesses 1083system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053518 # miss rate for overall accesses 1084system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.081750 # miss rate for overall accesses 1085system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.265888 # miss rate for overall accesses 1086system.cpu0.l2cache.overall_miss_rate::total 0.139329 # miss rate for overall accesses 1087system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average ReadReq miss latency 1088system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37271.303756 # average ReadReq miss latency 1089system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36084.039414 # average ReadReq miss latency 1090system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21550.567955 # average UpgradeReq miss latency 1091system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21550.567955 # average UpgradeReq miss latency 1092system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20726.550059 # average SCUpgradeReq miss latency 1093system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20726.550059 # average SCUpgradeReq miss latency 1094system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 916166 # average SCUpgradeFailReq miss latency 1095system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 916166 # average SCUpgradeFailReq miss latency 1096system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48337.473567 # average ReadExReq miss latency 1097system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48337.473567 # average ReadExReq miss latency 1098system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30404.421429 # average ReadCleanReq miss latency 1099system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30404.421429 # average ReadCleanReq miss latency 1100system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33274.612376 # average ReadSharedReq miss latency 1101system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33274.612376 # average ReadSharedReq miss latency 1102system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 83190.767878 # average InvalidateReq miss latency 1103system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 83190.767878 # average InvalidateReq miss latency 1104system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency 1105system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency 1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency 1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::total 34239.222369 # average overall miss latency 1109system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency 1110system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency 1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency 1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::total 34239.222369 # average overall miss latency 1114system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1115system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1116system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1117system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1118system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1119system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1120system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1121system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1122system.cpu0.l2cache.writebacks::writebacks 1441697 # number of writebacks 1123system.cpu0.l2cache.writebacks::total 1441697 # number of writebacks 1124system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 1125system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1126system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8436 # number of ReadExReq MSHR hits 1127system.cpu0.l2cache.ReadExReq_mshr_hits::total 8436 # number of ReadExReq MSHR hits 1128system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 8 # number of ReadCleanReq MSHR hits 1129system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits 1130system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 865 # number of ReadSharedReq MSHR hits 1131system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 865 # number of ReadSharedReq MSHR hits 1132system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 68 # number of InvalidateReq MSHR hits 1133system.cpu0.l2cache.InvalidateReq_mshr_hits::total 68 # number of InvalidateReq MSHR hits 1134system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1135system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9301 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.demand_mshr_hits::total 9312 # number of demand (read+write) MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 1140system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9301 # number of overall MSHR hits 1141system.cpu0.l2cache.overall_mshr_hits::total 9312 # number of overall MSHR hits 1142system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12195 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8810 # number of ReadReq MSHR misses 1144system.cpu0.l2cache.ReadReq_mshr_misses::total 21005 # number of ReadReq MSHR misses 1145system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 114790 # number of CleanEvict MSHR misses 1146system.cpu0.l2cache.CleanEvict_mshr_misses::total 114790 # number of CleanEvict MSHR misses 1147system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of HardPFReq MSHR misses 1148system.cpu0.l2cache.HardPFReq_mshr_misses::total 731294 # number of HardPFReq MSHR misses 1149system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 130468 # number of UpgradeReq MSHR misses 1150system.cpu0.l2cache.UpgradeReq_mshr_misses::total 130468 # number of UpgradeReq MSHR misses 1151system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 154478 # number of SCUpgradeReq MSHR misses 1152system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 154478 # number of SCUpgradeReq MSHR misses 1153system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1154system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1155system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270131 # number of ReadExReq MSHR misses 1156system.cpu0.l2cache.ReadExReq_mshr_misses::total 270131 # number of ReadExReq MSHR misses 1157system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 777546 # number of ReadCleanReq MSHR misses 1158system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 777546 # number of ReadCleanReq MSHR misses 1159system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1019546 # number of ReadSharedReq MSHR misses 1160system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1019546 # number of ReadSharedReq MSHR misses 1161system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 589114 # number of InvalidateReq MSHR misses 1162system.cpu0.l2cache.InvalidateReq_mshr_misses::total 589114 # number of InvalidateReq MSHR misses 1163system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12195 # number of demand (read+write) MSHR misses 1164system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8810 # number of demand (read+write) MSHR misses 1165system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 777546 # number of demand (read+write) MSHR misses 1166system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1289677 # number of demand (read+write) MSHR misses 1167system.cpu0.l2cache.demand_mshr_misses::total 2088228 # number of demand (read+write) MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12195 # number of overall MSHR misses 1169system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8810 # number of overall MSHR misses 1170system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 777546 # number of overall MSHR misses 1171system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1289677 # number of overall MSHR misses 1172system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of overall MSHR misses 1173system.cpu0.l2cache.overall_mshr_misses::total 2819522 # number of overall MSHR misses 1174system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 1175system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable 1176system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85174 # number of ReadReq MSHR uncacheable 1177system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable 1178system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable 1179system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 1180system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses 1181system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 117989 # number of overall MSHR uncacheable misses 1182system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of ReadReq MSHR miss cycles 1183system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 275560000 # number of ReadReq MSHR miss cycles 1184system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 631971500 # number of ReadReq MSHR miss cycles 1185system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of HardPFReq MSHR miss cycles 1186system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35755952523 # number of HardPFReq MSHR miss cycles 1187system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2648670495 # number of UpgradeReq MSHR miss cycles 1188system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2648670495 # number of UpgradeReq MSHR miss cycles 1189system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2356042000 # number of SCUpgradeReq MSHR miss cycles 1190system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2356042000 # number of SCUpgradeReq MSHR miss cycles 1191system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2382498 # number of SCUpgradeFailReq MSHR miss cycles 1192system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2382498 # number of SCUpgradeFailReq MSHR miss cycles 1193system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10796229999 # number of ReadExReq MSHR miss cycles 1194system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10796229999 # number of ReadExReq MSHR miss cycles 1195system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18975468000 # number of ReadCleanReq MSHR miss cycles 1196system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18975468000 # number of ReadCleanReq MSHR miss cycles 1197system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27752056489 # number of ReadSharedReq MSHR miss cycles 1198system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27752056489 # number of ReadSharedReq MSHR miss cycles 1199system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 45478624000 # number of InvalidateReq MSHR miss cycles 1200system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 45478624000 # number of InvalidateReq MSHR miss cycles 1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of demand (read+write) MSHR miss cycles 1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 275560000 # number of demand (read+write) MSHR miss cycles 1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18975468000 # number of demand (read+write) MSHR miss cycles 1204system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38548286488 # number of demand (read+write) MSHR miss cycles 1205system.cpu0.l2cache.demand_mshr_miss_latency::total 58155725988 # number of demand (read+write) MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 275560000 # number of overall MSHR miss cycles 1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18975468000 # number of overall MSHR miss cycles 1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38548286488 # number of overall MSHR miss cycles 1210system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of overall MSHR miss cycles 1211system.cpu0.l2cache.overall_mshr_miss_latency::total 93911678511 # number of overall MSHR miss cycles 1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5648614500 # number of ReadReq MSHR uncacheable cycles 1214system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10008059000 # number of ReadReq MSHR uncacheable cycles 1215system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5436600500 # number of WriteReq MSHR uncacheable cycles 1216system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5436600500 # number of WriteReq MSHR uncacheable cycles 1217system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles 1218system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11085215000 # number of overall MSHR uncacheable cycles 1219system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15444659500 # number of overall MSHR uncacheable cycles 1220system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for ReadReq accesses 1221system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for ReadReq accesses 1222system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031931 # mshr miss rate for ReadReq accesses 1223system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1224system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1225system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1226system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1227system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.544140 # mshr miss rate for UpgradeReq accesses 1228system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.544140 # mshr miss rate for UpgradeReq accesses 1229system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814010 # mshr miss rate for SCUpgradeReq accesses 1230system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814010 # mshr miss rate for SCUpgradeReq accesses 1231system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1232system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1233system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for ReadExReq accesses 1234system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233619 # mshr miss rate for ReadExReq accesses 1235system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses 1236system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses 1237system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses 1238system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses 1239system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses 1240system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses 1241system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses 1242system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses 1243system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses 1244system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses 1245system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses 1246system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses 1247system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses 1248system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses 1249system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses 1250system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1251system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses 1252system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency 1253system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency 1254system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency 1255system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency 1256system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency 1257system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency 1258system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency 1259system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency 1260system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency 1261system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency 1262system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency 1263system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency 1264system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency 1265system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency 1266system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency 1267system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency 1268system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency 1269system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency 1270system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency 1271system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency 1272system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency 1273system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency 1274system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency 1275system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency 1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency 1277system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency 1278system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency 1279system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency 1281system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency 1282system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency 1283system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency 1284system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency 1285system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency 1286system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency 1287system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency 1288system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency 1289system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency 1290system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1291system.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution 1309system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) 1310system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) 1311system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) 1312system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) 1313system.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) 1314system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) 1315system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) 1316system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) 1319system.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) 1320system.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram 1321system.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram 1322system.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram 1323system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1324system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1325system.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram 1326system.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram 1327system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram 1331system.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) 1332system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1333system.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) 1334system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1335system.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) 1336system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1337system.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) 1338system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1339system.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) 1340system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1341system.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) 1342system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1343system.cpu1.branchPred.lookups 137760504 # Number of BP lookups 1344system.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted 1345system.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect 1346system.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups 1347system.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits 1348system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1349system.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage 1350system.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. 1351system.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. 1352system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1357system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1358system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1360system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1361system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1362system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1363system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1364system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1365system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1366system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1367system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1368system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1369system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1370system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1371system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1372system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1373system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1374system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1375system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1376system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1377system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1378system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1379system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1380system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1381system.cpu1.dtb.walker.walks 290439 # Table walker walks requested 1382system.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors 1383system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate 1384system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate 1385system.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency 1386system.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1387system.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency 1388system.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency 1389system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency 1390system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency 1393system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution 1404system.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution 1405system.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution 1406system.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated 1407system.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated 1408system.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated 1409system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst 1410system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1411system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst 1412system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst 1413system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1414system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst 1415system.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst 1416system.cpu1.dtb.inst_hits 0 # ITB inst hits 1417system.cpu1.dtb.inst_misses 0 # ITB inst misses 1418system.cpu1.dtb.read_hits 89204123 # DTB read hits 1419system.cpu1.dtb.read_misses 242859 # DTB read misses 1420system.cpu1.dtb.write_hits 77378465 # DTB write hits 1421system.cpu1.dtb.write_misses 47580 # DTB write misses 1422system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1423system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1424system.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 1425system.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 1426system.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB 1427system.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions 1428system.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch 1429system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1430system.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions 1431system.cpu1.dtb.read_accesses 89446982 # DTB read accesses 1432system.cpu1.dtb.write_accesses 77426045 # DTB write accesses 1433system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1434system.cpu1.dtb.hits 166582588 # DTB hits 1435system.cpu1.dtb.misses 290439 # DTB misses 1436system.cpu1.dtb.accesses 166873027 # DTB accesses 1437system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1441system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1442system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1443system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1444system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1445system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1446system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1447system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1448system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1449system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1450system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1451system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1452system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1453system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1454system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1455system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1456system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1457system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1458system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1459system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1460system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1461system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1462system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1463system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1464system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1465system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1466system.cpu1.itb.walker.walks 66791 # Table walker walks requested 1467system.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors 1468system.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate 1469system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate 1470system.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency 1471system.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1472system.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency 1473system.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency 1477system.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency 1478system.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution 1493system.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution 1494system.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution 1495system.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated 1496system.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated 1497system.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated 1498system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1499system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst 1500system.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst 1501system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1502system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst 1503system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst 1504system.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst 1505system.cpu1.itb.inst_hits 246625416 # ITB inst hits 1506system.cpu1.itb.inst_misses 66791 # ITB inst misses 1507system.cpu1.itb.read_hits 0 # DTB read hits 1508system.cpu1.itb.read_misses 0 # DTB read misses 1509system.cpu1.itb.write_hits 0 # DTB write hits 1510system.cpu1.itb.write_misses 0 # DTB write misses 1511system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1512system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1513system.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID 1514system.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID 1515system.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB 1516system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1517system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1518system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1519system.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions 1520system.cpu1.itb.read_accesses 0 # DTB read accesses 1521system.cpu1.itb.write_accesses 0 # DTB write accesses 1522system.cpu1.itb.inst_accesses 246692207 # ITB inst accesses 1523system.cpu1.itb.hits 246625416 # DTB hits 1524system.cpu1.itb.misses 66791 # DTB misses 1525system.cpu1.itb.accesses 246692207 # DTB accesses 1526system.cpu1.numCycles 916577474 # number of cpu cycles simulated 1527system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1528system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1529system.cpu1.committedInsts 453450144 # Number of instructions committed 1530system.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed 1531system.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit 1532system.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching 1533system.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1534system.cpu1.cpi 2.021341 # CPI: cycles per instruction 1535system.cpu1.ipc 0.494721 # IPC: instructions per cycle 1536system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1537system.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed 1538system.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked 1539system.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped 1540system.cpu1.dcache.tags.replacements 5347951 # number of replacements 1541system.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use 1542system.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. 1543system.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. 1544system.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. 1545system.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. 1546system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor 1547system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy 1548system.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy 1549system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1550system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 1551system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 1552system.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 1553system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1554system.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses 1555system.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses 1556system.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits 1557system.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits 1558system.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits 1559system.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits 1560system.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits 1561system.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits 1562system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits 1563system.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits 1564system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits 1565system.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits 1566system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits 1567system.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits 1568system.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits 1569system.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits 1570system.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits 1571system.cpu1.dcache.overall_hits::total 154303114 # number of overall hits 1572system.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses 1573system.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses 1574system.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses 1575system.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses 1576system.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses 1577system.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses 1578system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses 1579system.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses 1580system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses 1581system.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses 1582system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses 1583system.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses 1584system.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses 1585system.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses 1586system.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses 1587system.cpu1.dcache.overall_misses::total 6364672 # number of overall misses 1588system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles 1589system.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles 1590system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles 1591system.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles 1592system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles 1593system.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles 1594system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles 1595system.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles 1596system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles 1597system.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles 1598system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles 1599system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles 1600system.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles 1601system.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles 1602system.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles 1603system.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles 1604system.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) 1605system.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) 1606system.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) 1607system.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) 1608system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) 1609system.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) 1610system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) 1611system.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) 1612system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) 1613system.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) 1614system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) 1615system.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) 1616system.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses 1617system.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses 1618system.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses 1619system.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses 1620system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses 1621system.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses 1622system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses 1623system.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses 1624system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses 1625system.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses 1626system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses 1627system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses 1628system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses 1629system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses 1630system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses 1631system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses 1632system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses 1633system.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses 1634system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses 1635system.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses 1636system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency 1637system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency 1638system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency 1639system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency 1640system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency 1641system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency 1645system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency 1646system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1647system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1648system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764 # average overall miss latency 1649system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency 1650system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency 1651system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency 1652system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1653system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1654system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1655system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1656system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1657system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1658system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1659system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1660system.cpu1.dcache.writebacks::writebacks 3440440 # number of writebacks 1661system.cpu1.dcache.writebacks::total 3440440 # number of writebacks 1662system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392659 # number of ReadReq MSHR hits 1663system.cpu1.dcache.ReadReq_mshr_hits::total 392659 # number of ReadReq MSHR hits 1664system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 925831 # number of WriteReq MSHR hits 1665system.cpu1.dcache.WriteReq_mshr_hits::total 925831 # number of WriteReq MSHR hits 1666system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 46 # number of WriteLineReq MSHR hits 1667system.cpu1.dcache.WriteLineReq_mshr_hits::total 46 # number of WriteLineReq MSHR hits 1668system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41204 # number of LoadLockedReq MSHR hits 1669system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41204 # number of LoadLockedReq MSHR hits 1670system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 43 # number of StoreCondReq MSHR hits 1671system.cpu1.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits 1672system.cpu1.dcache.demand_mshr_hits::cpu1.data 1318490 # number of demand (read+write) MSHR hits 1673system.cpu1.dcache.demand_mshr_hits::total 1318490 # number of demand (read+write) MSHR hits 1674system.cpu1.dcache.overall_mshr_hits::cpu1.data 1318490 # number of overall MSHR hits 1675system.cpu1.dcache.overall_mshr_hits::total 1318490 # number of overall MSHR hits 1676system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3076745 # number of ReadReq MSHR misses 1677system.cpu1.dcache.ReadReq_mshr_misses::total 3076745 # number of ReadReq MSHR misses 1678system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1328174 # number of WriteReq MSHR misses 1679system.cpu1.dcache.WriteReq_mshr_misses::total 1328174 # number of WriteReq MSHR misses 1680system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 640972 # number of SoftPFReq MSHR misses 1681system.cpu1.dcache.SoftPFReq_mshr_misses::total 640972 # number of SoftPFReq MSHR misses 1682system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 468487 # number of WriteLineReq MSHR misses 1683system.cpu1.dcache.WriteLineReq_mshr_misses::total 468487 # number of WriteLineReq MSHR misses 1684system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 131337 # number of LoadLockedReq MSHR misses 1685system.cpu1.dcache.LoadLockedReq_mshr_misses::total 131337 # number of LoadLockedReq MSHR misses 1686system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196714 # number of StoreCondReq MSHR misses 1687system.cpu1.dcache.StoreCondReq_mshr_misses::total 196714 # number of StoreCondReq MSHR misses 1688system.cpu1.dcache.demand_mshr_misses::cpu1.data 4404919 # number of demand (read+write) MSHR misses 1689system.cpu1.dcache.demand_mshr_misses::total 4404919 # number of demand (read+write) MSHR misses 1690system.cpu1.dcache.overall_mshr_misses::cpu1.data 5045891 # number of overall MSHR misses 1691system.cpu1.dcache.overall_mshr_misses::total 5045891 # number of overall MSHR misses 1692system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable 1693system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5366 # number of ReadReq MSHR uncacheable 1694system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable 1695system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable 1696system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses 1697system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10646 # number of overall MSHR uncacheable misses 1698system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41480566500 # number of ReadReq MSHR miss cycles 1699system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41480566500 # number of ReadReq MSHR miss cycles 1700system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21714665000 # number of WriteReq MSHR miss cycles 1701system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21714665000 # number of WriteReq MSHR miss cycles 1702system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12811841000 # number of SoftPFReq MSHR miss cycles 1703system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12811841000 # number of SoftPFReq MSHR miss cycles 1704system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16084660000 # number of WriteLineReq MSHR miss cycles 1705system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16084660000 # number of WriteLineReq MSHR miss cycles 1706system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751023000 # number of LoadLockedReq MSHR miss cycles 1707system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751023000 # number of LoadLockedReq MSHR miss cycles 1708system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3933903500 # number of StoreCondReq MSHR miss cycles 1709system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3933903500 # number of StoreCondReq MSHR miss cycles 1710system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles 1712system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63195231500 # number of demand (read+write) MSHR miss cycles 1713system.cpu1.dcache.demand_mshr_miss_latency::total 63195231500 # number of demand (read+write) MSHR miss cycles 1714system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76007072500 # number of overall MSHR miss cycles 1715system.cpu1.dcache.overall_mshr_miss_latency::total 76007072500 # number of overall MSHR miss cycles 1716system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 593786000 # number of ReadReq MSHR uncacheable cycles 1717system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 593786000 # number of ReadReq MSHR uncacheable cycles 1718system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 651165500 # number of WriteReq MSHR uncacheable cycles 1719system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 651165500 # number of WriteReq MSHR uncacheable cycles 1720system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244951500 # number of overall MSHR uncacheable cycles 1721system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1244951500 # number of overall MSHR uncacheable cycles 1722system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036067 # mshr miss rate for ReadReq accesses 1723system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036067 # mshr miss rate for ReadReq accesses 1724system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017833 # mshr miss rate for WriteReq accesses 1725system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017833 # mshr miss rate for WriteReq accesses 1726system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.727739 # mshr miss rate for SoftPFReq accesses 1727system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.727739 # mshr miss rate for SoftPFReq accesses 1728system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.763023 # mshr miss rate for WriteLineReq accesses 1729system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.763023 # mshr miss rate for WriteLineReq accesses 1730system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067065 # mshr miss rate for LoadLockedReq accesses 1731system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067065 # mshr miss rate for LoadLockedReq accesses 1732system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100543 # mshr miss rate for StoreCondReq accesses 1733system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100543 # mshr miss rate for StoreCondReq accesses 1734system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027567 # mshr miss rate for demand accesses 1735system.cpu1.dcache.demand_mshr_miss_rate::total 0.027567 # mshr miss rate for demand accesses 1736system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031406 # mshr miss rate for overall accesses 1737system.cpu1.dcache.overall_mshr_miss_rate::total 0.031406 # mshr miss rate for overall accesses 1738system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381 # average ReadReq mshr miss latency 1739system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381 # average ReadReq mshr miss latency 1740system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220 # average WriteReq mshr miss latency 1741system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220 # average WriteReq mshr miss latency 1742system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568 # average SoftPFReq mshr miss latency 1743system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568 # average SoftPFReq mshr miss latency 1744system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550 # average WriteLineReq mshr miss latency 1745system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550 # average WriteLineReq mshr miss latency 1746system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215 # average LoadLockedReq mshr miss latency 1747system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215 # average LoadLockedReq mshr miss latency 1748system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054 # average StoreCondReq mshr miss latency 1749system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054 # average StoreCondReq mshr miss latency 1750system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1751system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1752system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency 1753system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency 1754system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency 1755system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency 1756system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency 1757system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency 1758system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency 1759system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency 1760system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # average overall mshr uncacheable latency 1761system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878 # average overall mshr uncacheable latency 1762system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1763system.cpu1.icache.tags.replacements 9156821 # number of replacements 1764system.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use 1765system.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. 1766system.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. 1767system.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. 1768system.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. 1769system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor 1770system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy 1771system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy 1772system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1773system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 1774system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 1776system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1777system.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses 1778system.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses 1779system.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits 1780system.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits 1781system.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits 1782system.cpu1.icache.demand_hits::total 237244674 # number of demand (read+write) hits 1783system.cpu1.icache.overall_hits::cpu1.inst 237244674 # number of overall hits 1784system.cpu1.icache.overall_hits::total 237244674 # number of overall hits 1785system.cpu1.icache.ReadReq_misses::cpu1.inst 9157334 # number of ReadReq misses 1786system.cpu1.icache.ReadReq_misses::total 9157334 # number of ReadReq misses 1787system.cpu1.icache.demand_misses::cpu1.inst 9157334 # number of demand (read+write) misses 1788system.cpu1.icache.demand_misses::total 9157334 # number of demand (read+write) misses 1789system.cpu1.icache.overall_misses::cpu1.inst 9157334 # number of overall misses 1790system.cpu1.icache.overall_misses::total 9157334 # number of overall misses 1791system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 90409615500 # number of ReadReq miss cycles 1792system.cpu1.icache.ReadReq_miss_latency::total 90409615500 # number of ReadReq miss cycles 1793system.cpu1.icache.demand_miss_latency::cpu1.inst 90409615500 # number of demand (read+write) miss cycles 1794system.cpu1.icache.demand_miss_latency::total 90409615500 # number of demand (read+write) miss cycles 1795system.cpu1.icache.overall_miss_latency::cpu1.inst 90409615500 # number of overall miss cycles 1796system.cpu1.icache.overall_miss_latency::total 90409615500 # number of overall miss cycles 1797system.cpu1.icache.ReadReq_accesses::cpu1.inst 246402008 # number of ReadReq accesses(hits+misses) 1798system.cpu1.icache.ReadReq_accesses::total 246402008 # number of ReadReq accesses(hits+misses) 1799system.cpu1.icache.demand_accesses::cpu1.inst 246402008 # number of demand (read+write) accesses 1800system.cpu1.icache.demand_accesses::total 246402008 # number of demand (read+write) accesses 1801system.cpu1.icache.overall_accesses::cpu1.inst 246402008 # number of overall (read+write) accesses 1802system.cpu1.icache.overall_accesses::total 246402008 # number of overall (read+write) accesses 1803system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037164 # miss rate for ReadReq accesses 1804system.cpu1.icache.ReadReq_miss_rate::total 0.037164 # miss rate for ReadReq accesses 1805system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037164 # miss rate for demand accesses 1806system.cpu1.icache.demand_miss_rate::total 0.037164 # miss rate for demand accesses 1807system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037164 # miss rate for overall accesses 1808system.cpu1.icache.overall_miss_rate::total 0.037164 # miss rate for overall accesses 1809system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9872.918854 # average ReadReq miss latency 1810system.cpu1.icache.ReadReq_avg_miss_latency::total 9872.918854 # average ReadReq miss latency 1811system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency 1812system.cpu1.icache.demand_avg_miss_latency::total 9872.918854 # average overall miss latency 1813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency 1814system.cpu1.icache.overall_avg_miss_latency::total 9872.918854 # average overall miss latency 1815system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1816system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1817system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1819system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1820system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1821system.cpu1.icache.fast_writes 0 # number of fast writes performed 1822system.cpu1.icache.cache_copies 0 # number of cache copies performed 1823system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses 1824system.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses 1825system.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses 1826system.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses 1827system.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # number of overall MSHR misses 1828system.cpu1.icache.overall_mshr_misses::total 9157334 # number of overall MSHR misses 1829system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1830system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1831system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1832system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 1833system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85830949000 # number of ReadReq MSHR miss cycles 1834system.cpu1.icache.ReadReq_mshr_miss_latency::total 85830949000 # number of ReadReq MSHR miss cycles 1835system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85830949000 # number of demand (read+write) MSHR miss cycles 1836system.cpu1.icache.demand_mshr_miss_latency::total 85830949000 # number of demand (read+write) MSHR miss cycles 1837system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85830949000 # number of overall MSHR miss cycles 1838system.cpu1.icache.overall_mshr_miss_latency::total 85830949000 # number of overall MSHR miss cycles 1839system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8848000 # number of ReadReq MSHR uncacheable cycles 1840system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8848000 # number of ReadReq MSHR uncacheable cycles 1841system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8848000 # number of overall MSHR uncacheable cycles 1842system.cpu1.icache.overall_mshr_uncacheable_latency::total 8848000 # number of overall MSHR uncacheable cycles 1843system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for ReadReq accesses 1844system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037164 # mshr miss rate for ReadReq accesses 1845system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for demand accesses 1846system.cpu1.icache.demand_mshr_miss_rate::total 0.037164 # mshr miss rate for demand accesses 1847system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for overall accesses 1848system.cpu1.icache.overall_mshr_miss_rate::total 0.037164 # mshr miss rate for overall accesses 1849system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average ReadReq mshr miss latency 1850system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9372.918908 # average ReadReq mshr miss latency 1851system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency 1852system.cpu1.icache.demand_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency 1853system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency 1854system.cpu1.icache.overall_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency 1855system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average ReadReq mshr uncacheable latency 1856system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946 # average ReadReq mshr uncacheable latency 1857system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average overall mshr uncacheable latency 1858system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946 # average overall mshr uncacheable latency 1859system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1860system.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued 1861system.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified 1862system.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue 1863system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1864system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1865system.cpu1.l2cache.prefetcher.pfSpanPage 921370 # number of prefetches not generated due to page crossing 1866system.cpu1.l2cache.tags.replacements 2420449 # number of replacements 1867system.cpu1.l2cache.tags.tagsinuse 13525.501015 # Cycle average of tags in use 1868system.cpu1.l2cache.tags.total_refs 25921683 # Total number of references to valid blocks. 1869system.cpu1.l2cache.tags.sampled_refs 2436577 # Sample count of references to valid blocks. 1870system.cpu1.l2cache.tags.avg_refs 10.638565 # Average number of references to valid blocks. 1871system.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. 1872system.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor 1873system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor 1874system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor 1875system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor 1876system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor 1877system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy 1879system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy 1880system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # Average percentage of cache occupancy 1881system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.217380 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229067 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048899 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::total 0.825531 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 534 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 335 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1163 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5423 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4799 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3398 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 1902system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 1903system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id 1904system.cpu1.l2cache.tags.tag_accesses 488189494 # Number of tag accesses 1905system.cpu1.l2cache.tags.data_accesses 488189494 # Number of data accesses 1906system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527706 # number of ReadReq hits 1907system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160378 # number of ReadReq hits 1908system.cpu1.l2cache.ReadReq_hits::total 688084 # number of ReadReq hits 1909system.cpu1.l2cache.Writeback_hits::writebacks 3440434 # number of Writeback hits 1910system.cpu1.l2cache.Writeback_hits::total 3440434 # number of Writeback hits 1911system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 69060 # number of UpgradeReq hits 1912system.cpu1.l2cache.UpgradeReq_hits::total 69060 # number of UpgradeReq hits 1913system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 37815 # number of SCUpgradeReq hits 1914system.cpu1.l2cache.SCUpgradeReq_hits::total 37815 # number of SCUpgradeReq hits 1915system.cpu1.l2cache.ReadExReq_hits::cpu1.data 888572 # number of ReadExReq hits 1916system.cpu1.l2cache.ReadExReq_hits::total 888572 # number of ReadExReq hits 1917system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8367748 # number of ReadCleanReq hits 1918system.cpu1.l2cache.ReadCleanReq_hits::total 8367748 # number of ReadCleanReq hits 1919system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2856681 # number of ReadSharedReq hits 1920system.cpu1.l2cache.ReadSharedReq_hits::total 2856681 # number of ReadSharedReq hits 1921system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 194722 # number of InvalidateReq hits 1922system.cpu1.l2cache.InvalidateReq_hits::total 194722 # number of InvalidateReq hits 1923system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527706 # number of demand (read+write) hits 1924system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160378 # number of demand (read+write) hits 1925system.cpu1.l2cache.demand_hits::cpu1.inst 8367748 # number of demand (read+write) hits 1926system.cpu1.l2cache.demand_hits::cpu1.data 3745253 # number of demand (read+write) hits 1927system.cpu1.l2cache.demand_hits::total 12801085 # number of demand (read+write) hits 1928system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527706 # number of overall hits 1929system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160378 # number of overall hits 1930system.cpu1.l2cache.overall_hits::cpu1.inst 8367748 # number of overall hits 1931system.cpu1.l2cache.overall_hits::cpu1.data 3745253 # number of overall hits 1932system.cpu1.l2cache.overall_hits::total 12801085 # number of overall hits 1933system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11992 # number of ReadReq misses 1934system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses 1935system.cpu1.l2cache.ReadReq_misses::total 20524 # number of ReadReq misses 1936system.cpu1.l2cache.Writeback_misses::writebacks 3 # number of Writeback misses 1937system.cpu1.l2cache.Writeback_misses::total 3 # number of Writeback misses 1938system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136249 # number of UpgradeReq misses 1939system.cpu1.l2cache.UpgradeReq_misses::total 136249 # number of UpgradeReq misses 1940system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158895 # number of SCUpgradeReq misses 1941system.cpu1.l2cache.SCUpgradeReq_misses::total 158895 # number of SCUpgradeReq misses 1942system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 1943system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1944system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235953 # number of ReadExReq misses 1945system.cpu1.l2cache.ReadExReq_misses::total 235953 # number of ReadExReq misses 1946system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 789586 # number of ReadCleanReq misses 1947system.cpu1.l2cache.ReadCleanReq_misses::total 789586 # number of ReadCleanReq misses 1948system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 992043 # number of ReadSharedReq misses 1949system.cpu1.l2cache.ReadSharedReq_misses::total 992043 # number of ReadSharedReq misses 1950system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272649 # number of InvalidateReq misses 1951system.cpu1.l2cache.InvalidateReq_misses::total 272649 # number of InvalidateReq misses 1952system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11992 # number of demand (read+write) misses 1953system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses 1954system.cpu1.l2cache.demand_misses::cpu1.inst 789586 # number of demand (read+write) misses 1955system.cpu1.l2cache.demand_misses::cpu1.data 1227996 # number of demand (read+write) misses 1956system.cpu1.l2cache.demand_misses::total 2038106 # number of demand (read+write) misses 1957system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11992 # number of overall misses 1958system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses 1959system.cpu1.l2cache.overall_misses::cpu1.inst 789586 # number of overall misses 1960system.cpu1.l2cache.overall_misses::cpu1.data 1227996 # number of overall misses 1961system.cpu1.l2cache.overall_misses::total 2038106 # number of overall misses 1962system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446382000 # number of ReadReq miss cycles 1963system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 354037500 # number of ReadReq miss cycles 1964system.cpu1.l2cache.ReadReq_miss_latency::total 800419500 # number of ReadReq miss cycles 1965system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2966896500 # number of UpgradeReq miss cycles 1966system.cpu1.l2cache.UpgradeReq_miss_latency::total 2966896500 # number of UpgradeReq miss cycles 1967system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3304625499 # number of SCUpgradeReq miss cycles 1968system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3304625499 # number of SCUpgradeReq miss cycles 1969system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763998 # number of SCUpgradeFailReq miss cycles 1970system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763998 # number of SCUpgradeFailReq miss cycles 1971system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9908657497 # number of ReadExReq miss cycles 1972system.cpu1.l2cache.ReadExReq_miss_latency::total 9908657497 # number of ReadExReq miss cycles 1973system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22229315000 # number of ReadCleanReq miss cycles 1974system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22229315000 # number of ReadCleanReq miss cycles 1975system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31556071491 # number of ReadSharedReq miss cycles 1976system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31556071491 # number of ReadSharedReq miss cycles 1977system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14034162000 # number of InvalidateReq miss cycles 1978system.cpu1.l2cache.InvalidateReq_miss_latency::total 14034162000 # number of InvalidateReq miss cycles 1979system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446382000 # number of demand (read+write) miss cycles 1980system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 354037500 # number of demand (read+write) miss cycles 1981system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22229315000 # number of demand (read+write) miss cycles 1982system.cpu1.l2cache.demand_miss_latency::cpu1.data 41464728988 # number of demand (read+write) miss cycles 1983system.cpu1.l2cache.demand_miss_latency::total 64494463488 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446382000 # number of overall miss cycles 1985system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 354037500 # number of overall miss cycles 1986system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22229315000 # number of overall miss cycles 1987system.cpu1.l2cache.overall_miss_latency::cpu1.data 41464728988 # number of overall miss cycles 1988system.cpu1.l2cache.overall_miss_latency::total 64494463488 # number of overall miss cycles 1989system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539698 # number of ReadReq accesses(hits+misses) 1990system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168910 # number of ReadReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadReq_accesses::total 708608 # number of ReadReq accesses(hits+misses) 1992system.cpu1.l2cache.Writeback_accesses::writebacks 3440437 # number of Writeback accesses(hits+misses) 1993system.cpu1.l2cache.Writeback_accesses::total 3440437 # number of Writeback accesses(hits+misses) 1994system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205309 # number of UpgradeReq accesses(hits+misses) 1995system.cpu1.l2cache.UpgradeReq_accesses::total 205309 # number of UpgradeReq accesses(hits+misses) 1996system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 196710 # number of SCUpgradeReq accesses(hits+misses) 1997system.cpu1.l2cache.SCUpgradeReq_accesses::total 196710 # number of SCUpgradeReq accesses(hits+misses) 1998system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1999system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2000system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1124525 # number of ReadExReq accesses(hits+misses) 2001system.cpu1.l2cache.ReadExReq_accesses::total 1124525 # number of ReadExReq accesses(hits+misses) 2002system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9157334 # number of ReadCleanReq accesses(hits+misses) 2003system.cpu1.l2cache.ReadCleanReq_accesses::total 9157334 # number of ReadCleanReq accesses(hits+misses) 2004system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3848724 # number of ReadSharedReq accesses(hits+misses) 2005system.cpu1.l2cache.ReadSharedReq_accesses::total 3848724 # number of ReadSharedReq accesses(hits+misses) 2006system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 467371 # number of InvalidateReq accesses(hits+misses) 2007system.cpu1.l2cache.InvalidateReq_accesses::total 467371 # number of InvalidateReq accesses(hits+misses) 2008system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539698 # number of demand (read+write) accesses 2009system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168910 # number of demand (read+write) accesses 2010system.cpu1.l2cache.demand_accesses::cpu1.inst 9157334 # number of demand (read+write) accesses 2011system.cpu1.l2cache.demand_accesses::cpu1.data 4973249 # number of demand (read+write) accesses 2012system.cpu1.l2cache.demand_accesses::total 14839191 # number of demand (read+write) accesses 2013system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539698 # number of overall (read+write) accesses 2014system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168910 # number of overall (read+write) accesses 2015system.cpu1.l2cache.overall_accesses::cpu1.inst 9157334 # number of overall (read+write) accesses 2016system.cpu1.l2cache.overall_accesses::cpu1.data 4973249 # number of overall (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::total 14839191 # number of overall (read+write) accesses 2018system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for ReadReq accesses 2019system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050512 # miss rate for ReadReq accesses 2020system.cpu1.l2cache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses 2021system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses 2022system.cpu1.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses 2023system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.663629 # miss rate for UpgradeReq accesses 2024system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.663629 # miss rate for UpgradeReq accesses 2025system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.807763 # miss rate for SCUpgradeReq accesses 2026system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.807763 # miss rate for SCUpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2028system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2029system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.209825 # miss rate for ReadExReq accesses 2030system.cpu1.l2cache.ReadExReq_miss_rate::total 0.209825 # miss rate for ReadExReq accesses 2031system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.086224 # miss rate for ReadCleanReq accesses 2032system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.086224 # miss rate for ReadCleanReq accesses 2033system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.257759 # miss rate for ReadSharedReq accesses 2034system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.257759 # miss rate for ReadSharedReq accesses 2035system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.583367 # miss rate for InvalidateReq accesses 2036system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.583367 # miss rate for InvalidateReq accesses 2037system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for demand accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050512 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086224 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246920 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::total 0.137346 # miss rate for demand accesses 2042system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for overall accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050512 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086224 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246920 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::total 0.137346 # miss rate for overall accesses 2047system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average ReadReq miss latency 2048system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41495.253165 # average ReadReq miss latency 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38999.196063 # average ReadReq miss latency 2050system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21775.546976 # average UpgradeReq miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21775.546976 # average UpgradeReq miss latency 2052system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20797.542396 # average SCUpgradeReq miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20797.542396 # average SCUpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 440999.500000 # average SCUpgradeFailReq miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 440999.500000 # average SCUpgradeFailReq miss latency 2056system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41994.200103 # average ReadExReq miss latency 2057system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41994.200103 # average ReadExReq miss latency 2058system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28153.127082 # average ReadCleanReq miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28153.127082 # average ReadCleanReq miss latency 2060system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31809.177113 # average ReadSharedReq miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31809.177113 # average ReadSharedReq miss latency 2062system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51473.366856 # average InvalidateReq miss latency 2063system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51473.366856 # average InvalidateReq miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency 2065system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency 2067system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency 2068system.cpu1.l2cache.demand_avg_miss_latency::total 31644.312655 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency 2070system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency 2072system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency 2073system.cpu1.l2cache.overall_avg_miss_latency::total 31644.312655 # average overall miss latency 2074system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2075system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2076system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2077system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2078system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2079system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2080system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2081system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2082system.cpu1.l2cache.writebacks::writebacks 1031306 # number of writebacks 2083system.cpu1.l2cache.writebacks::total 1031306 # number of writebacks 2084system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2085system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2086system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7033 # number of ReadExReq MSHR hits 2087system.cpu1.l2cache.ReadExReq_mshr_hits::total 7033 # number of ReadExReq MSHR hits 2088system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 2089system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 2090system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 605 # number of ReadSharedReq MSHR hits 2091system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 605 # number of ReadSharedReq MSHR hits 2092system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 17 # number of InvalidateReq MSHR hits 2093system.cpu1.l2cache.InvalidateReq_mshr_hits::total 17 # number of InvalidateReq MSHR hits 2094system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 2095system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2096system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7638 # number of demand (read+write) MSHR hits 2097system.cpu1.l2cache.demand_mshr_hits::total 7641 # number of demand (read+write) MSHR hits 2098system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 2099system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2100system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7638 # number of overall MSHR hits 2101system.cpu1.l2cache.overall_mshr_hits::total 7641 # number of overall MSHR hits 2102system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11992 # number of ReadReq MSHR misses 2103system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses 2104system.cpu1.l2cache.ReadReq_mshr_misses::total 20522 # number of ReadReq MSHR misses 2105system.cpu1.l2cache.Writeback_mshr_misses::writebacks 3 # number of Writeback MSHR misses 2106system.cpu1.l2cache.Writeback_mshr_misses::total 3 # number of Writeback MSHR misses 2107system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 115811 # number of CleanEvict MSHR misses 2108system.cpu1.l2cache.CleanEvict_mshr_misses::total 115811 # number of CleanEvict MSHR misses 2109system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of HardPFReq MSHR misses 2110system.cpu1.l2cache.HardPFReq_mshr_misses::total 714965 # number of HardPFReq MSHR misses 2111system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 136249 # number of UpgradeReq MSHR misses 2112system.cpu1.l2cache.UpgradeReq_mshr_misses::total 136249 # number of UpgradeReq MSHR misses 2113system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 158895 # number of SCUpgradeReq MSHR misses 2114system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 158895 # number of SCUpgradeReq MSHR misses 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2116system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2117system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 228920 # number of ReadExReq MSHR misses 2118system.cpu1.l2cache.ReadExReq_mshr_misses::total 228920 # number of ReadExReq MSHR misses 2119system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 789585 # number of ReadCleanReq MSHR misses 2120system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 789585 # number of ReadCleanReq MSHR misses 2121system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 991438 # number of ReadSharedReq MSHR misses 2122system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 991438 # number of ReadSharedReq MSHR misses 2123system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 272632 # number of InvalidateReq MSHR misses 2124system.cpu1.l2cache.InvalidateReq_mshr_misses::total 272632 # number of InvalidateReq MSHR misses 2125system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11992 # number of demand (read+write) MSHR misses 2126system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses 2127system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 789585 # number of demand (read+write) MSHR misses 2128system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1220358 # number of demand (read+write) MSHR misses 2129system.cpu1.l2cache.demand_mshr_misses::total 2030465 # number of demand (read+write) MSHR misses 2130system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11992 # number of overall MSHR misses 2131system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses 2132system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 789585 # number of overall MSHR misses 2133system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1220358 # number of overall MSHR misses 2134system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of overall MSHR misses 2135system.cpu1.l2cache.overall_mshr_misses::total 2745430 # number of overall MSHR misses 2136system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2137system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable 2138system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5459 # number of ReadReq MSHR uncacheable 2139system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable 2140system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable 2141system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2142system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses 2143system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10739 # number of overall MSHR uncacheable misses 2144system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of ReadReq MSHR miss cycles 2145system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 302816000 # number of ReadReq MSHR miss cycles 2146system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 677246000 # number of ReadReq MSHR miss cycles 2147system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of HardPFReq MSHR miss cycles 2148system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30632454632 # number of HardPFReq MSHR miss cycles 2149system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2763352994 # number of UpgradeReq MSHR miss cycles 2150system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2763352994 # number of UpgradeReq MSHR miss cycles 2151system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2438062999 # number of SCUpgradeReq MSHR miss cycles 2152system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2438062999 # number of SCUpgradeReq MSHR miss cycles 2153system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1505998 # number of SCUpgradeFailReq MSHR miss cycles 2154system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1505998 # number of SCUpgradeFailReq MSHR miss cycles 2155system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7634474497 # number of ReadExReq MSHR miss cycles 2156system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7634474497 # number of ReadExReq MSHR miss cycles 2157system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17491788500 # number of ReadCleanReq MSHR miss cycles 2158system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17491788500 # number of ReadCleanReq MSHR miss cycles 2159system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25566861991 # number of ReadSharedReq MSHR miss cycles 2160system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25566861991 # number of ReadSharedReq MSHR miss cycles 2161system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12398047000 # number of InvalidateReq MSHR miss cycles 2162system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12398047000 # number of InvalidateReq MSHR miss cycles 2163system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of demand (read+write) MSHR miss cycles 2164system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 302816000 # number of demand (read+write) MSHR miss cycles 2165system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17491788500 # number of demand (read+write) MSHR miss cycles 2166system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33201336488 # number of demand (read+write) MSHR miss cycles 2167system.cpu1.l2cache.demand_mshr_miss_latency::total 51370370988 # number of demand (read+write) MSHR miss cycles 2168system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of overall MSHR miss cycles 2169system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 302816000 # number of overall MSHR miss cycles 2170system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17491788500 # number of overall MSHR miss cycles 2171system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33201336488 # number of overall MSHR miss cycles 2172system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of overall MSHR miss cycles 2173system.cpu1.l2cache.overall_mshr_miss_latency::total 82002825620 # number of overall MSHR miss cycles 2174system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8104000 # number of ReadReq MSHR uncacheable cycles 2175system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550842500 # number of ReadReq MSHR uncacheable cycles 2176system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 558946500 # number of ReadReq MSHR uncacheable cycles 2177system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 611561500 # number of WriteReq MSHR uncacheable cycles 2178system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 611561500 # number of WriteReq MSHR uncacheable cycles 2179system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8104000 # number of overall MSHR uncacheable cycles 2180system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1162404000 # number of overall MSHR uncacheable cycles 2181system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1170508000 # number of overall MSHR uncacheable cycles 2182system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for ReadReq accesses 2183system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for ReadReq accesses 2184system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028961 # mshr miss rate for ReadReq accesses 2185system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses 2186system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses 2187system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2188system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2189system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2190system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2191system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.663629 # mshr miss rate for UpgradeReq accesses 2192system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.663629 # mshr miss rate for UpgradeReq accesses 2193system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.807763 # mshr miss rate for SCUpgradeReq accesses 2194system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.807763 # mshr miss rate for SCUpgradeReq accesses 2195system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2196system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2197system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.203570 # mshr miss rate for ReadExReq accesses 2198system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.203570 # mshr miss rate for ReadExReq accesses 2199system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for ReadCleanReq accesses 2200system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086224 # mshr miss rate for ReadCleanReq accesses 2201system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.257602 # mshr miss rate for ReadSharedReq accesses 2202system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257602 # mshr miss rate for ReadSharedReq accesses 2203system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.583331 # mshr miss rate for InvalidateReq accesses 2204system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.583331 # mshr miss rate for InvalidateReq accesses 2205system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for demand accesses 2206system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for demand accesses 2207system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for demand accesses 2208system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for demand accesses 2209system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136831 # mshr miss rate for demand accesses 2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for overall accesses 2211system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses 2212system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses 2213system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses 2214system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2215system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses 2216system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency 2217system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency 2218system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency 2219system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency 2220system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency 2221system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency 2222system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency 2223system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency 2224system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency 2225system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency 2226system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency 2227system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency 2228system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency 2229system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency 2230system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency 2231system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency 2232system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency 2233system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency 2234system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency 2235system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency 2236system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency 2237system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency 2238system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency 2239system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency 2240system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency 2241system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency 2242system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency 2243system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency 2244system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency 2245system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency 2246system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency 2247system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency 2248system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency 2249system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency 2250system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency 2251system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency 2252system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency 2253system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency 2254system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2255system.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution 2256system.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution 2257system.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 2258system.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution 2259system.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution 2265system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution 2273system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) 2274system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) 2275system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) 2276system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) 2277system.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) 2278system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) 2279system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) 2280system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) 2281system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) 2282system.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) 2283system.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) 2284system.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram 2285system.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram 2286system.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram 2287system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2288system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2289system.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram 2290system.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram 2291system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2292system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2293system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2294system.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram 2295system.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) 2296system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2297system.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) 2298system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2299system.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) 2300system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2301system.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) 2302system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2303system.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) 2304system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2305system.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) 2306system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2307system.iobus.trans_dist::ReadReq 40322 # Transaction distribution 2308system.iobus.trans_dist::ReadResp 40322 # Transaction distribution 2309system.iobus.trans_dist::WriteReq 136608 # Transaction distribution 2310system.iobus.trans_dist::WriteResp 136608 # Transaction distribution 2311system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) 2312system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2314system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) 2333system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) 2354system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2355system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2356system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2357system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2358system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2359system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2360system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2361system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2362system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2363system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2364system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2365system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2366system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2367system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2368system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2369system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2370system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2371system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2372system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2373system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 2374system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2375system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2376system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2377system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2378system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2379system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2380system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2381system.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) 2382system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2383system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2384system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2385system.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) 2386system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2387system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) 2388system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2389system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2390system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2391system.iocache.tags.replacements 115582 # number of replacements 2392system.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use 2393system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2394system.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. 2395system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2396system.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. 2397system.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor 2398system.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor 2399system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy 2400system.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy 2401system.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy 2402system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2403system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2404system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2405system.iocache.tags.tag_accesses 1040766 # Number of tag accesses 2406system.iocache.tags.data_accesses 1040766 # Number of data accesses 2407system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2408system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses 2409system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses 2410system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2411system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2412system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2413system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2414system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2415system.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses 2416system.iocache.demand_misses::total 8913 # number of demand (read+write) misses 2417system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2418system.iocache.overall_misses::realview.ide 8873 # number of overall misses 2419system.iocache.overall_misses::total 8913 # number of overall misses 2420system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2421system.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles 2422system.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles 2423system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2424system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2425system.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles 2426system.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles 2427system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2428system.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles 2429system.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles 2430system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2431system.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles 2432system.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles 2433system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2434system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) 2435system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) 2436system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2437system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2438system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2439system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2440system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2441system.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses 2442system.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses 2443system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2444system.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses 2445system.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses 2446system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2447system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2448system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2449system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2450system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2451system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2452system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2453system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2454system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2455system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2456system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2457system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2458system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2459system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2460system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency 2461system.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency 2462system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2463system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2464system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency 2465system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency 2466system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2467system.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency 2468system.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency 2469system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2470system.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency 2471system.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency 2472system.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked 2473system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2474system.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked 2475system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2476system.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked 2477system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2478system.iocache.fast_writes 0 # number of fast writes performed 2479system.iocache.cache_copies 0 # number of cache copies performed 2480system.iocache.writebacks::writebacks 106694 # number of writebacks 2481system.iocache.writebacks::total 106694 # number of writebacks 2482system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2483system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses 2484system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses 2485system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2486system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2487system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2488system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2489system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2490system.iocache.demand_mshr_misses::realview.ide 8873 # number of demand (read+write) MSHR misses 2491system.iocache.demand_mshr_misses::total 8913 # number of demand (read+write) MSHR misses 2492system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2493system.iocache.overall_mshr_misses::realview.ide 8873 # number of overall MSHR misses 2494system.iocache.overall_mshr_misses::total 8913 # number of overall MSHR misses 2495system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2496system.iocache.ReadReq_mshr_miss_latency::realview.ide 1187443968 # number of ReadReq MSHR miss cycles 2497system.iocache.ReadReq_mshr_miss_latency::total 1190788968 # number of ReadReq MSHR miss cycles 2498system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2499system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2500system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288182114 # number of WriteLineReq MSHR miss cycles 2501system.iocache.WriteLineReq_mshr_miss_latency::total 7288182114 # number of WriteLineReq MSHR miss cycles 2502system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2503system.iocache.demand_mshr_miss_latency::realview.ide 1187443968 # number of demand (read+write) MSHR miss cycles 2504system.iocache.demand_mshr_miss_latency::total 1191007968 # number of demand (read+write) MSHR miss cycles 2505system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2506system.iocache.overall_mshr_miss_latency::realview.ide 1187443968 # number of overall MSHR miss cycles 2507system.iocache.overall_mshr_miss_latency::total 1191007968 # number of overall MSHR miss cycles 2508system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2509system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2510system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2511system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2512system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2513system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2514system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2515system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2516system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2517system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2518system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2519system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2520system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2521system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2522system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency 2523system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency 2524system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2525system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2526system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040 # average WriteLineReq mshr miss latency 2527system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040 # average WriteLineReq mshr miss latency 2528system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2529system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency 2530system.iocache.demand_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency 2531system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2532system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency 2533system.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency 2534system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2535system.l2c.tags.replacements 1460315 # number of replacements 2536system.l2c.tags.tagsinuse 63815.106569 # Cycle average of tags in use 2537system.l2c.tags.total_refs 6243583 # Total number of references to valid blocks. 2538system.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. 2539system.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. 2540system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2541system.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor 2542system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor 2543system.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor 2546system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor 2549system.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor 2550system.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor 2551system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor 2552system.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy 2553system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy 2554system.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy 2555system.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::cpu1.inst 0.060681 # Average percentage of cache occupancy 2561system.l2c.tags.occ_percent::cpu1.data 0.151407 # Average percentage of cache occupancy 2562system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198735 # Average percentage of cache occupancy 2563system.l2c.tags.occ_percent::total 0.973741 # Average percentage of cache occupancy 2564system.l2c.tags.occ_task_id_blocks::1022 9634 # Occupied blocks per task id 2565system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id 2566system.l2c.tags.occ_task_id_blocks::1024 50762 # Occupied blocks per task id 2567system.l2c.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 2568system.l2c.tags.age_task_id_blocks_1022::3 450 # Occupied blocks per task id 2569system.l2c.tags.age_task_id_blocks_1022::4 8970 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id 2575system.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id 2577system.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id 2578system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id 2579system.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id 2580system.l2c.tags.tag_accesses 74931302 # Number of tag accesses 2581system.l2c.tags.data_accesses 74931302 # Number of data accesses 2582system.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits 2583system.l2c.Writeback_hits::total 2473005 # number of Writeback hits 2584system.l2c.UpgradeReq_hits::cpu0.data 29717 # number of UpgradeReq hits 2585system.l2c.UpgradeReq_hits::cpu1.data 30251 # number of UpgradeReq hits 2586system.l2c.UpgradeReq_hits::total 59968 # number of UpgradeReq hits 2587system.l2c.SCUpgradeReq_hits::cpu0.data 5861 # number of SCUpgradeReq hits 2588system.l2c.SCUpgradeReq_hits::cpu1.data 6611 # number of SCUpgradeReq hits 2589system.l2c.SCUpgradeReq_hits::total 12472 # number of SCUpgradeReq hits 2590system.l2c.ReadExReq_hits::cpu0.data 174264 # number of ReadExReq hits 2591system.l2c.ReadExReq_hits::cpu1.data 168948 # number of ReadExReq hits 2592system.l2c.ReadExReq_hits::total 343212 # number of ReadExReq hits 2593system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6955 # number of ReadSharedReq hits 2594system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5054 # number of ReadSharedReq hits 2595system.l2c.ReadSharedReq_hits::cpu0.inst 704009 # number of ReadSharedReq hits 2596system.l2c.ReadSharedReq_hits::cpu0.data 596815 # number of ReadSharedReq hits 2597system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296922 # number of ReadSharedReq hits 2598system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6236 # number of ReadSharedReq hits 2599system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4142 # number of ReadSharedReq hits 2600system.l2c.ReadSharedReq_hits::cpu1.inst 738933 # number of ReadSharedReq hits 2601system.l2c.ReadSharedReq_hits::cpu1.data 577563 # number of ReadSharedReq hits 2602system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 321187 # number of ReadSharedReq hits 2603system.l2c.ReadSharedReq_hits::total 3257816 # number of ReadSharedReq hits 2604system.l2c.demand_hits::cpu0.dtb.walker 6955 # number of demand (read+write) hits 2605system.l2c.demand_hits::cpu0.itb.walker 5054 # number of demand (read+write) hits 2606system.l2c.demand_hits::cpu0.inst 704009 # number of demand (read+write) hits 2607system.l2c.demand_hits::cpu0.data 771079 # number of demand (read+write) hits 2608system.l2c.demand_hits::cpu0.l2cache.prefetcher 296922 # number of demand (read+write) hits 2609system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits 2610system.l2c.demand_hits::cpu1.itb.walker 4142 # number of demand (read+write) hits 2611system.l2c.demand_hits::cpu1.inst 738933 # number of demand (read+write) hits 2612system.l2c.demand_hits::cpu1.data 746511 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu1.l2cache.prefetcher 321187 # number of demand (read+write) hits 2614system.l2c.demand_hits::total 3601028 # number of demand (read+write) hits 2615system.l2c.overall_hits::cpu0.dtb.walker 6955 # number of overall hits 2616system.l2c.overall_hits::cpu0.itb.walker 5054 # number of overall hits 2617system.l2c.overall_hits::cpu0.inst 704009 # number of overall hits 2618system.l2c.overall_hits::cpu0.data 771079 # number of overall hits 2619system.l2c.overall_hits::cpu0.l2cache.prefetcher 296922 # number of overall hits 2620system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits 2621system.l2c.overall_hits::cpu1.itb.walker 4142 # number of overall hits 2622system.l2c.overall_hits::cpu1.inst 738933 # number of overall hits 2623system.l2c.overall_hits::cpu1.data 746511 # number of overall hits 2624system.l2c.overall_hits::cpu1.l2cache.prefetcher 321187 # number of overall hits 2625system.l2c.overall_hits::total 3601028 # number of overall hits 2626system.l2c.UpgradeReq_misses::cpu0.data 43094 # number of UpgradeReq misses 2627system.l2c.UpgradeReq_misses::cpu1.data 44585 # number of UpgradeReq misses 2628system.l2c.UpgradeReq_misses::total 87679 # number of UpgradeReq misses 2629system.l2c.SCUpgradeReq_misses::cpu0.data 8745 # number of SCUpgradeReq misses 2630system.l2c.SCUpgradeReq_misses::cpu1.data 9538 # number of SCUpgradeReq misses 2631system.l2c.SCUpgradeReq_misses::total 18283 # number of SCUpgradeReq misses 2632system.l2c.ReadExReq_misses::cpu0.data 499472 # number of ReadExReq misses 2633system.l2c.ReadExReq_misses::cpu1.data 152688 # number of ReadExReq misses 2634system.l2c.ReadExReq_misses::total 652160 # number of ReadExReq misses 2635system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq misses 2636system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1581 # number of ReadSharedReq misses 2637system.l2c.ReadSharedReq_misses::cpu0.inst 73537 # number of ReadSharedReq misses 2638system.l2c.ReadSharedReq_misses::cpu0.data 135426 # number of ReadSharedReq misses 2639system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq misses 2640system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq misses 2641system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2077 # number of ReadSharedReq misses 2642system.l2c.ReadSharedReq_misses::cpu1.inst 50651 # number of ReadSharedReq misses 2643system.l2c.ReadSharedReq_misses::cpu1.data 119141 # number of ReadSharedReq misses 2644system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq misses 2645system.l2c.ReadSharedReq_misses::total 834591 # number of ReadSharedReq misses 2646system.l2c.demand_misses::cpu0.dtb.walker 1944 # number of demand (read+write) misses 2647system.l2c.demand_misses::cpu0.itb.walker 1581 # number of demand (read+write) misses 2648system.l2c.demand_misses::cpu0.inst 73537 # number of demand (read+write) misses 2649system.l2c.demand_misses::cpu0.data 634898 # number of demand (read+write) misses 2650system.l2c.demand_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) misses 2651system.l2c.demand_misses::cpu1.dtb.walker 2244 # number of demand (read+write) misses 2652system.l2c.demand_misses::cpu1.itb.walker 2077 # number of demand (read+write) misses 2653system.l2c.demand_misses::cpu1.inst 50651 # number of demand (read+write) misses 2654system.l2c.demand_misses::cpu1.data 271829 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) misses 2656system.l2c.demand_misses::total 1486751 # number of demand (read+write) misses 2657system.l2c.overall_misses::cpu0.dtb.walker 1944 # number of overall misses 2658system.l2c.overall_misses::cpu0.itb.walker 1581 # number of overall misses 2659system.l2c.overall_misses::cpu0.inst 73537 # number of overall misses 2660system.l2c.overall_misses::cpu0.data 634898 # number of overall misses 2661system.l2c.overall_misses::cpu0.l2cache.prefetcher 239395 # number of overall misses 2662system.l2c.overall_misses::cpu1.dtb.walker 2244 # number of overall misses 2663system.l2c.overall_misses::cpu1.itb.walker 2077 # number of overall misses 2664system.l2c.overall_misses::cpu1.inst 50651 # number of overall misses 2665system.l2c.overall_misses::cpu1.data 271829 # number of overall misses 2666system.l2c.overall_misses::cpu1.l2cache.prefetcher 208595 # number of overall misses 2667system.l2c.overall_misses::total 1486751 # number of overall misses 2668system.l2c.UpgradeReq_miss_latency::cpu0.data 260324500 # number of UpgradeReq miss cycles 2669system.l2c.UpgradeReq_miss_latency::cpu1.data 277994500 # number of UpgradeReq miss cycles 2670system.l2c.UpgradeReq_miss_latency::total 538319000 # number of UpgradeReq miss cycles 2671system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55253500 # number of SCUpgradeReq miss cycles 2672system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54480000 # number of SCUpgradeReq miss cycles 2673system.l2c.SCUpgradeReq_miss_latency::total 109733500 # number of SCUpgradeReq miss cycles 2674system.l2c.ReadExReq_miss_latency::cpu0.data 46824185500 # number of ReadExReq miss cycles 2675system.l2c.ReadExReq_miss_latency::cpu1.data 13176547500 # number of ReadExReq miss cycles 2676system.l2c.ReadExReq_miss_latency::total 60000733000 # number of ReadExReq miss cycles 2677system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 176295500 # number of ReadSharedReq miss cycles 2678system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 146583500 # number of ReadSharedReq miss cycles 2679system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6133823500 # number of ReadSharedReq miss cycles 2680system.l2c.ReadSharedReq_miss_latency::cpu0.data 12343951000 # number of ReadSharedReq miss cycles 2681system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of ReadSharedReq miss cycles 2682system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 201877500 # number of ReadSharedReq miss cycles 2683system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 184505000 # number of ReadSharedReq miss cycles 2684system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4199208000 # number of ReadSharedReq miss cycles 2685system.l2c.ReadSharedReq_miss_latency::cpu1.data 10504090000 # number of ReadSharedReq miss cycles 2686system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of ReadSharedReq miss cycles 2687system.l2c.ReadSharedReq_miss_latency::total 89739250464 # number of ReadSharedReq miss cycles 2688system.l2c.demand_miss_latency::cpu0.dtb.walker 176295500 # number of demand (read+write) miss cycles 2689system.l2c.demand_miss_latency::cpu0.itb.walker 146583500 # number of demand (read+write) miss cycles 2690system.l2c.demand_miss_latency::cpu0.inst 6133823500 # number of demand (read+write) miss cycles 2691system.l2c.demand_miss_latency::cpu0.data 59168136500 # number of demand (read+write) miss cycles 2692system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of demand (read+write) miss cycles 2693system.l2c.demand_miss_latency::cpu1.dtb.walker 201877500 # number of demand (read+write) miss cycles 2694system.l2c.demand_miss_latency::cpu1.itb.walker 184505000 # number of demand (read+write) miss cycles 2695system.l2c.demand_miss_latency::cpu1.inst 4199208000 # number of demand (read+write) miss cycles 2696system.l2c.demand_miss_latency::cpu1.data 23680637500 # number of demand (read+write) miss cycles 2697system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of demand (read+write) miss cycles 2698system.l2c.demand_miss_latency::total 149739983464 # number of demand (read+write) miss cycles 2699system.l2c.overall_miss_latency::cpu0.dtb.walker 176295500 # number of overall miss cycles 2700system.l2c.overall_miss_latency::cpu0.itb.walker 146583500 # number of overall miss cycles 2701system.l2c.overall_miss_latency::cpu0.inst 6133823500 # number of overall miss cycles 2702system.l2c.overall_miss_latency::cpu0.data 59168136500 # number of overall miss cycles 2703system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of overall miss cycles 2704system.l2c.overall_miss_latency::cpu1.dtb.walker 201877500 # number of overall miss cycles 2705system.l2c.overall_miss_latency::cpu1.itb.walker 184505000 # number of overall miss cycles 2706system.l2c.overall_miss_latency::cpu1.inst 4199208000 # number of overall miss cycles 2707system.l2c.overall_miss_latency::cpu1.data 23680637500 # number of overall miss cycles 2708system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of overall miss cycles 2709system.l2c.overall_miss_latency::total 149739983464 # number of overall miss cycles 2710system.l2c.Writeback_accesses::writebacks 2473005 # number of Writeback accesses(hits+misses) 2711system.l2c.Writeback_accesses::total 2473005 # number of Writeback accesses(hits+misses) 2712system.l2c.UpgradeReq_accesses::cpu0.data 72811 # number of UpgradeReq accesses(hits+misses) 2713system.l2c.UpgradeReq_accesses::cpu1.data 74836 # number of UpgradeReq accesses(hits+misses) 2714system.l2c.UpgradeReq_accesses::total 147647 # number of UpgradeReq accesses(hits+misses) 2715system.l2c.SCUpgradeReq_accesses::cpu0.data 14606 # number of SCUpgradeReq accesses(hits+misses) 2716system.l2c.SCUpgradeReq_accesses::cpu1.data 16149 # number of SCUpgradeReq accesses(hits+misses) 2717system.l2c.SCUpgradeReq_accesses::total 30755 # number of SCUpgradeReq accesses(hits+misses) 2718system.l2c.ReadExReq_accesses::cpu0.data 673736 # number of ReadExReq accesses(hits+misses) 2719system.l2c.ReadExReq_accesses::cpu1.data 321636 # number of ReadExReq accesses(hits+misses) 2720system.l2c.ReadExReq_accesses::total 995372 # number of ReadExReq accesses(hits+misses) 2721system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8899 # number of ReadSharedReq accesses(hits+misses) 2722system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6635 # number of ReadSharedReq accesses(hits+misses) 2723system.l2c.ReadSharedReq_accesses::cpu0.inst 777546 # number of ReadSharedReq accesses(hits+misses) 2724system.l2c.ReadSharedReq_accesses::cpu0.data 732241 # number of ReadSharedReq accesses(hits+misses) 2725system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 536317 # number of ReadSharedReq accesses(hits+misses) 2726system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8480 # number of ReadSharedReq accesses(hits+misses) 2727system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6219 # number of ReadSharedReq accesses(hits+misses) 2728system.l2c.ReadSharedReq_accesses::cpu1.inst 789584 # number of ReadSharedReq accesses(hits+misses) 2729system.l2c.ReadSharedReq_accesses::cpu1.data 696704 # number of ReadSharedReq accesses(hits+misses) 2730system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 529782 # number of ReadSharedReq accesses(hits+misses) 2731system.l2c.ReadSharedReq_accesses::total 4092407 # number of ReadSharedReq accesses(hits+misses) 2732system.l2c.demand_accesses::cpu0.dtb.walker 8899 # number of demand (read+write) accesses 2733system.l2c.demand_accesses::cpu0.itb.walker 6635 # number of demand (read+write) accesses 2734system.l2c.demand_accesses::cpu0.inst 777546 # number of demand (read+write) accesses 2735system.l2c.demand_accesses::cpu0.data 1405977 # number of demand (read+write) accesses 2736system.l2c.demand_accesses::cpu0.l2cache.prefetcher 536317 # number of demand (read+write) accesses 2737system.l2c.demand_accesses::cpu1.dtb.walker 8480 # number of demand (read+write) accesses 2738system.l2c.demand_accesses::cpu1.itb.walker 6219 # number of demand (read+write) accesses 2739system.l2c.demand_accesses::cpu1.inst 789584 # number of demand (read+write) accesses 2740system.l2c.demand_accesses::cpu1.data 1018340 # number of demand (read+write) accesses 2741system.l2c.demand_accesses::cpu1.l2cache.prefetcher 529782 # number of demand (read+write) accesses 2742system.l2c.demand_accesses::total 5087779 # number of demand (read+write) accesses 2743system.l2c.overall_accesses::cpu0.dtb.walker 8899 # number of overall (read+write) accesses 2744system.l2c.overall_accesses::cpu0.itb.walker 6635 # number of overall (read+write) accesses 2745system.l2c.overall_accesses::cpu0.inst 777546 # number of overall (read+write) accesses 2746system.l2c.overall_accesses::cpu0.data 1405977 # number of overall (read+write) accesses 2747system.l2c.overall_accesses::cpu0.l2cache.prefetcher 536317 # number of overall (read+write) accesses 2748system.l2c.overall_accesses::cpu1.dtb.walker 8480 # number of overall (read+write) accesses 2749system.l2c.overall_accesses::cpu1.itb.walker 6219 # number of overall (read+write) accesses 2750system.l2c.overall_accesses::cpu1.inst 789584 # number of overall (read+write) accesses 2751system.l2c.overall_accesses::cpu1.data 1018340 # number of overall (read+write) accesses 2752system.l2c.overall_accesses::cpu1.l2cache.prefetcher 529782 # number of overall (read+write) accesses 2753system.l2c.overall_accesses::total 5087779 # number of overall (read+write) accesses 2754system.l2c.UpgradeReq_miss_rate::cpu0.data 0.591861 # miss rate for UpgradeReq accesses 2755system.l2c.UpgradeReq_miss_rate::cpu1.data 0.595769 # miss rate for UpgradeReq accesses 2756system.l2c.UpgradeReq_miss_rate::total 0.593842 # miss rate for UpgradeReq accesses 2757system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598727 # miss rate for SCUpgradeReq accesses 2758system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590625 # miss rate for SCUpgradeReq accesses 2759system.l2c.SCUpgradeReq_miss_rate::total 0.594472 # miss rate for SCUpgradeReq accesses 2760system.l2c.ReadExReq_miss_rate::cpu0.data 0.741347 # miss rate for ReadExReq accesses 2761system.l2c.ReadExReq_miss_rate::cpu1.data 0.474723 # miss rate for ReadExReq accesses 2762system.l2c.ReadExReq_miss_rate::total 0.655192 # miss rate for ReadExReq accesses 2763system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for ReadSharedReq accesses 2764system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.238282 # miss rate for ReadSharedReq accesses 2765system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.094576 # miss rate for ReadSharedReq accesses 2766system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.184947 # miss rate for ReadSharedReq accesses 2767system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for ReadSharedReq accesses 2768system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for ReadSharedReq accesses 2769system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.333977 # miss rate for ReadSharedReq accesses 2770system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.064149 # miss rate for ReadSharedReq accesses 2771system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171007 # miss rate for ReadSharedReq accesses 2772system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for ReadSharedReq accesses 2773system.l2c.ReadSharedReq_miss_rate::total 0.203936 # miss rate for ReadSharedReq accesses 2774system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for demand accesses 2775system.l2c.demand_miss_rate::cpu0.itb.walker 0.238282 # miss rate for demand accesses 2776system.l2c.demand_miss_rate::cpu0.inst 0.094576 # miss rate for demand accesses 2777system.l2c.demand_miss_rate::cpu0.data 0.451571 # miss rate for demand accesses 2778system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for demand accesses 2779system.l2c.demand_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for demand accesses 2780system.l2c.demand_miss_rate::cpu1.itb.walker 0.333977 # miss rate for demand accesses 2781system.l2c.demand_miss_rate::cpu1.inst 0.064149 # miss rate for demand accesses 2782system.l2c.demand_miss_rate::cpu1.data 0.266933 # miss rate for demand accesses 2783system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for demand accesses 2784system.l2c.demand_miss_rate::total 0.292220 # miss rate for demand accesses 2785system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for overall accesses 2786system.l2c.overall_miss_rate::cpu0.itb.walker 0.238282 # miss rate for overall accesses 2787system.l2c.overall_miss_rate::cpu0.inst 0.094576 # miss rate for overall accesses 2788system.l2c.overall_miss_rate::cpu0.data 0.451571 # miss rate for overall accesses 2789system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for overall accesses 2790system.l2c.overall_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for overall accesses 2791system.l2c.overall_miss_rate::cpu1.itb.walker 0.333977 # miss rate for overall accesses 2792system.l2c.overall_miss_rate::cpu1.inst 0.064149 # miss rate for overall accesses 2793system.l2c.overall_miss_rate::cpu1.data 0.266933 # miss rate for overall accesses 2794system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for overall accesses 2795system.l2c.overall_miss_rate::total 0.292220 # miss rate for overall accesses 2796system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6040.852555 # average UpgradeReq miss latency 2797system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6235.157564 # average UpgradeReq miss latency 2798system.l2c.UpgradeReq_avg_miss_latency::total 6139.657158 # average UpgradeReq miss latency 2799system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6318.296169 # average SCUpgradeReq miss latency 2800system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5711.889285 # average SCUpgradeReq miss latency 2801system.l2c.SCUpgradeReq_avg_miss_latency::total 6001.941694 # average SCUpgradeReq miss latency 2802system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93747.368221 # average ReadExReq miss latency 2803system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86297.204102 # average ReadExReq miss latency 2804system.l2c.ReadExReq_avg_miss_latency::total 92003.086666 # average ReadExReq miss latency 2805system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average ReadSharedReq miss latency 2806system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92715.686275 # average ReadSharedReq miss latency 2807system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83411.391544 # average ReadSharedReq miss latency 2808system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91149.048189 # average ReadSharedReq miss latency 2809system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average ReadSharedReq miss latency 2810system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average ReadSharedReq miss latency 2811system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88832.450650 # average ReadSharedReq miss latency 2812system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82904.740282 # average ReadSharedReq miss latency 2813system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88165.199218 # average ReadSharedReq miss latency 2814system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average ReadSharedReq miss latency 2815system.l2c.ReadSharedReq_avg_miss_latency::total 107524.824092 # average ReadSharedReq miss latency 2816system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency 2817system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency 2818system.l2c.demand_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency 2819system.l2c.demand_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency 2820system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency 2821system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency 2822system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency 2823system.l2c.demand_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency 2824system.l2c.demand_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency 2825system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency 2826system.l2c.demand_avg_miss_latency::total 100716.248695 # average overall miss latency 2827system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency 2828system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency 2829system.l2c.overall_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency 2830system.l2c.overall_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency 2831system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency 2832system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency 2833system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency 2834system.l2c.overall_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency 2835system.l2c.overall_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency 2836system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency 2837system.l2c.overall_avg_miss_latency::total 100716.248695 # average overall miss latency 2838system.l2c.blocked_cycles::no_mshrs 107 # number of cycles access was blocked 2839system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2840system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 2841system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2842system.l2c.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked 2843system.l2c.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR hits 2857system.l2c.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits 2858system.l2c.overall_mshr_hits::cpu0.inst 174 # number of overall MSHR hits 2859system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits 2860system.l2c.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits 2861system.l2c.overall_mshr_hits::cpu1.data 10 # number of overall MSHR hits 2862system.l2c.overall_mshr_hits::total 360 # number of overall MSHR hits 2863system.l2c.CleanEvict_mshr_misses::writebacks 53748 # number of CleanEvict MSHR misses 2864system.l2c.CleanEvict_mshr_misses::total 53748 # number of CleanEvict MSHR misses 2865system.l2c.UpgradeReq_mshr_misses::cpu0.data 43094 # number of UpgradeReq MSHR misses 2866system.l2c.UpgradeReq_mshr_misses::cpu1.data 44585 # number of UpgradeReq MSHR misses 2867system.l2c.UpgradeReq_mshr_misses::total 87679 # number of UpgradeReq MSHR misses 2868system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8745 # number of SCUpgradeReq MSHR misses 2869system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9538 # number of SCUpgradeReq MSHR misses 2870system.l2c.SCUpgradeReq_mshr_misses::total 18283 # number of SCUpgradeReq MSHR misses 2871system.l2c.ReadExReq_mshr_misses::cpu0.data 499472 # number of ReadExReq MSHR misses 2872system.l2c.ReadExReq_mshr_misses::cpu1.data 152688 # number of ReadExReq MSHR misses 2873system.l2c.ReadExReq_mshr_misses::total 652160 # number of ReadExReq MSHR misses 2874system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq MSHR misses 2875system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1581 # number of ReadSharedReq MSHR misses 2876system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 73363 # number of ReadSharedReq MSHR misses 2877system.l2c.ReadSharedReq_mshr_misses::cpu0.data 135407 # number of ReadSharedReq MSHR misses 2878system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq MSHR misses 2879system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq MSHR misses 2880system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2077 # number of ReadSharedReq MSHR misses 2881system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 50494 # number of ReadSharedReq MSHR misses 2882system.l2c.ReadSharedReq_mshr_misses::cpu1.data 119131 # number of ReadSharedReq MSHR misses 2883system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq MSHR misses 2884system.l2c.ReadSharedReq_mshr_misses::total 834231 # number of ReadSharedReq MSHR misses 2885system.l2c.demand_mshr_misses::cpu0.dtb.walker 1944 # number of demand (read+write) MSHR misses 2886system.l2c.demand_mshr_misses::cpu0.itb.walker 1581 # number of demand (read+write) MSHR misses 2887system.l2c.demand_mshr_misses::cpu0.inst 73363 # number of demand (read+write) MSHR misses 2888system.l2c.demand_mshr_misses::cpu0.data 634879 # number of demand (read+write) MSHR misses 2889system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) MSHR misses 2890system.l2c.demand_mshr_misses::cpu1.dtb.walker 2244 # number of demand (read+write) MSHR misses 2891system.l2c.demand_mshr_misses::cpu1.itb.walker 2077 # number of demand (read+write) MSHR misses 2892system.l2c.demand_mshr_misses::cpu1.inst 50494 # number of demand (read+write) MSHR misses 2893system.l2c.demand_mshr_misses::cpu1.data 271819 # number of demand (read+write) MSHR misses 2894system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) MSHR misses 2895system.l2c.demand_mshr_misses::total 1486391 # number of demand (read+write) MSHR misses 2896system.l2c.overall_mshr_misses::cpu0.dtb.walker 1944 # number of overall MSHR misses 2897system.l2c.overall_mshr_misses::cpu0.itb.walker 1581 # number of overall MSHR misses 2898system.l2c.overall_mshr_misses::cpu0.inst 73363 # number of overall MSHR misses 2899system.l2c.overall_mshr_misses::cpu0.data 634879 # number of overall MSHR misses 2900system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of overall MSHR misses 2901system.l2c.overall_mshr_misses::cpu1.dtb.walker 2244 # number of overall MSHR misses 2902system.l2c.overall_mshr_misses::cpu1.itb.walker 2077 # number of overall MSHR misses 2903system.l2c.overall_mshr_misses::cpu1.inst 50494 # number of overall MSHR misses 2904system.l2c.overall_mshr_misses::cpu1.data 271819 # number of overall MSHR misses 2905system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of overall MSHR misses 2906system.l2c.overall_mshr_misses::total 1486391 # number of overall MSHR misses 2907system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable 2908system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable 2909system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2910system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5364 # number of ReadReq MSHR uncacheable 2911system.l2c.ReadReq_mshr_uncacheable::total 90631 # number of ReadReq MSHR uncacheable 2912system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable 2913system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable 2914system.l2c.WriteReq_mshr_uncacheable::total 38095 # number of WriteReq MSHR uncacheable 2915system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses 2916system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses 2917system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2918system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10644 # number of overall MSHR uncacheable misses 2919system.l2c.overall_mshr_uncacheable_misses::total 128726 # number of overall MSHR uncacheable misses 2920system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 895608505 # number of UpgradeReq MSHR miss cycles 2921system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 925545505 # number of UpgradeReq MSHR miss cycles 2922system.l2c.UpgradeReq_mshr_miss_latency::total 1821154010 # number of UpgradeReq MSHR miss cycles 2923system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 181952000 # number of SCUpgradeReq MSHR miss cycles 2924system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 198394500 # number of SCUpgradeReq MSHR miss cycles 2925system.l2c.SCUpgradeReq_mshr_miss_latency::total 380346500 # number of SCUpgradeReq MSHR miss cycles 2926system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 41829465500 # number of ReadExReq MSHR miss cycles 2927system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 11649667500 # number of ReadExReq MSHR miss cycles 2928system.l2c.ReadExReq_mshr_miss_latency::total 53479133000 # number of ReadExReq MSHR miss cycles 2929system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of ReadSharedReq MSHR miss cycles 2930system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 130773500 # number of ReadSharedReq MSHR miss cycles 2931system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5387567000 # number of ReadSharedReq MSHR miss cycles 2932system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10988450500 # number of ReadSharedReq MSHR miss cycles 2933system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of ReadSharedReq MSHR miss cycles 2934system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of ReadSharedReq MSHR miss cycles 2935system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 163735000 # number of ReadSharedReq MSHR miss cycles 2936system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3683448000 # number of ReadSharedReq MSHR miss cycles 2937system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9312099500 # number of ReadSharedReq MSHR miss cycles 2938system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of ReadSharedReq MSHR miss cycles 2939system.l2c.ReadSharedReq_mshr_miss_latency::total 81371382964 # number of ReadSharedReq MSHR miss cycles 2940system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of demand (read+write) MSHR miss cycles 2941system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 130773500 # number of demand (read+write) MSHR miss cycles 2942system.l2c.demand_mshr_miss_latency::cpu0.inst 5387567000 # number of demand (read+write) MSHR miss cycles 2943system.l2c.demand_mshr_miss_latency::cpu0.data 52817916000 # number of demand (read+write) MSHR miss cycles 2944system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of demand (read+write) MSHR miss cycles 2945system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of demand (read+write) MSHR miss cycles 2946system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 163735000 # number of demand (read+write) MSHR miss cycles 2947system.l2c.demand_mshr_miss_latency::cpu1.inst 3683448000 # number of demand (read+write) MSHR miss cycles 2948system.l2c.demand_mshr_miss_latency::cpu1.data 20961767000 # number of demand (read+write) MSHR miss cycles 2949system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of demand (read+write) MSHR miss cycles 2950system.l2c.demand_mshr_miss_latency::total 134850515964 # number of demand (read+write) MSHR miss cycles 2951system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of overall MSHR miss cycles 2952system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 130773500 # number of overall MSHR miss cycles 2953system.l2c.overall_mshr_miss_latency::cpu0.inst 5387567000 # number of overall MSHR miss cycles 2954system.l2c.overall_mshr_miss_latency::cpu0.data 52817916000 # number of overall MSHR miss cycles 2955system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of overall MSHR miss cycles 2956system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of overall MSHR miss cycles 2957system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 163735000 # number of overall MSHR miss cycles 2958system.l2c.overall_mshr_miss_latency::cpu1.inst 3683448000 # number of overall MSHR miss cycles 2959system.l2c.overall_mshr_miss_latency::cpu1.data 20961767000 # number of overall MSHR miss cycles 2960system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of overall MSHR miss cycles 2961system.l2c.overall_mshr_miss_latency::total 134850515964 # number of overall MSHR miss cycles 2962system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of ReadReq MSHR uncacheable cycles 2963system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5056717000 # number of ReadReq MSHR uncacheable cycles 2964system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6149000 # number of ReadReq MSHR uncacheable cycles 2965system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 454250000 # number of ReadReq MSHR uncacheable cycles 2966system.l2c.ReadReq_mshr_uncacheable_latency::total 8778428500 # number of ReadReq MSHR uncacheable cycles 2967system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4878683500 # number of WriteReq MSHR uncacheable cycles 2968system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 521791000 # number of WriteReq MSHR uncacheable cycles 2969system.l2c.WriteReq_mshr_uncacheable_latency::total 5400474500 # number of WriteReq MSHR uncacheable cycles 2970system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of overall MSHR uncacheable cycles 2971system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9935400500 # number of overall MSHR uncacheable cycles 2972system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6149000 # number of overall MSHR uncacheable cycles 2973system.l2c.overall_mshr_uncacheable_latency::cpu1.data 976041000 # number of overall MSHR uncacheable cycles 2974system.l2c.overall_mshr_uncacheable_latency::total 14178903000 # number of overall MSHR uncacheable cycles 2975system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2976system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2977system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.591861 # mshr miss rate for UpgradeReq accesses 2978system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.595769 # mshr miss rate for UpgradeReq accesses 2979system.l2c.UpgradeReq_mshr_miss_rate::total 0.593842 # mshr miss rate for UpgradeReq accesses 2980system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598727 # mshr miss rate for SCUpgradeReq accesses 2981system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590625 # mshr miss rate for SCUpgradeReq accesses 2982system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.594472 # mshr miss rate for SCUpgradeReq accesses 2983system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.741347 # mshr miss rate for ReadExReq accesses 2984system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474723 # mshr miss rate for ReadExReq accesses 2985system.l2c.ReadExReq_mshr_miss_rate::total 0.655192 # mshr miss rate for ReadExReq accesses 2986system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for ReadSharedReq accesses 2987system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for ReadSharedReq accesses 2988system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for ReadSharedReq accesses 2989system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184921 # mshr miss rate for ReadSharedReq accesses 2990system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for ReadSharedReq accesses 2991system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for ReadSharedReq accesses 2992system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for ReadSharedReq accesses 2993system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for ReadSharedReq accesses 2994system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170992 # mshr miss rate for ReadSharedReq accesses 2995system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for ReadSharedReq accesses 2996system.l2c.ReadSharedReq_mshr_miss_rate::total 0.203848 # mshr miss rate for ReadSharedReq accesses 2997system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for demand accesses 2998system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for demand accesses 2999system.l2c.demand_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for demand accesses 3000system.l2c.demand_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for demand accesses 3001system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for demand accesses 3002system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for demand accesses 3003system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for demand accesses 3004system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for demand accesses 3005system.l2c.demand_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for demand accesses 3006system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for demand accesses 3007system.l2c.demand_mshr_miss_rate::total 0.292149 # mshr miss rate for demand accesses 3008system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for overall accesses 3009system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for overall accesses 3010system.l2c.overall_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for overall accesses 3011system.l2c.overall_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for overall accesses 3012system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for overall accesses 3013system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for overall accesses 3014system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for overall accesses 3015system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for overall accesses 3016system.l2c.overall_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for overall accesses 3017system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for overall accesses 3018system.l2c.overall_mshr_miss_rate::total 0.292149 # mshr miss rate for overall accesses 3019system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878 # average UpgradeReq mshr miss latency 3020system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136 # average UpgradeReq mshr miss latency 3021system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773 # average UpgradeReq mshr miss latency 3022system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659 # average SCUpgradeReq mshr miss latency 3023system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860 # average SCUpgradeReq mshr miss latency 3024system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207 # average SCUpgradeReq mshr miss latency 3025system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221 # average ReadExReq mshr miss latency 3026system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102 # average ReadExReq mshr miss latency 3027system.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666 # average ReadExReq mshr miss latency 3028system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average ReadSharedReq mshr miss latency 3029system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average ReadSharedReq mshr miss latency 3030system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average ReadSharedReq mshr miss latency 3031system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568 # average ReadSharedReq mshr miss latency 3032system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average ReadSharedReq mshr miss latency 3033system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average ReadSharedReq mshr miss latency 3034system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average ReadSharedReq mshr miss latency 3035system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average ReadSharedReq mshr miss latency 3036system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712 # average ReadSharedReq mshr miss latency 3037system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average ReadSharedReq mshr miss latency 3038system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835 # average ReadSharedReq mshr miss latency 3039system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency 3040system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency 3041system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency 3042system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency 3043system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency 3044system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency 3045system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency 3046system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency 3047system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency 3048system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency 3049system.l2c.demand_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency 3050system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency 3051system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency 3052system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency 3053system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency 3054system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency 3055system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency 3056system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency 3057system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency 3058system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency 3059system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency 3060system.l2c.overall_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency 3061system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency 3062system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency 3063system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency 3064system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency 3065system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency 3066system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency 3067system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency 3068system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency 3069system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency 3070system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency 3071system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency 3072system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency 3073system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency 3074system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3075system.membus.trans_dist::ReadReq 90631 # Transaction distribution 3076system.membus.trans_dist::ReadResp 933772 # Transaction distribution 3077system.membus.trans_dist::WriteReq 38095 # Transaction distribution 3078system.membus.trans_dist::WriteResp 38095 # Transaction distribution 3079system.membus.trans_dist::Writeback 1222852 # Transaction distribution 3080system.membus.trans_dist::CleanEvict 259291 # Transaction distribution 3081system.membus.trans_dist::UpgradeReq 429274 # Transaction distribution 3082system.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution 3083system.membus.trans_dist::UpgradeResp 113465 # Transaction distribution 3084system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 3085system.membus.trans_dist::ReadExReq 664837 # Transaction distribution 3086system.membus.trans_dist::ReadExResp 644660 # Transaction distribution 3087system.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution 3088system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3089system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3090system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) 3091system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3092system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) 3093system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) 3094system.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) 3095system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) 3096system.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) 3097system.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) 3098system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) 3099system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3100system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) 3101system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) 3102system.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) 3103system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) 3104system.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) 3105system.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) 3106system.membus.snoops 639479 # Total snoops (count) 3107system.membus.snoop_fanout::samples 3957833 # Request fanout histogram 3108system.membus.snoop_fanout::mean 1 # Request fanout histogram 3109system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3110system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3111system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3112system.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram 3113system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3114system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3115system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3116system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3117system.membus.snoop_fanout::total 3957833 # Request fanout histogram 3118system.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) 3119system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3120system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3121system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3122system.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) 3123system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3124system.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) 3125system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3126system.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) 3127system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3128system.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) 3129system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3130system.realview.ethernet.txBytes 966 # Bytes Transmitted 3131system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3132system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3133system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3134system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3135system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3136system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3137system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3138system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3139system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3140system.realview.ethernet.totPackets 3 # Total Packets 3141system.realview.ethernet.totBytes 966 # Total Bytes 3142system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3143system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3144system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3145system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3146system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3147system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3148system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3149system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3150system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3151system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3152system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3153system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3154system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3155system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3156system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3157system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3158system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3159system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3160system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3161system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3162system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3163system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3164system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3165system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3166system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3167system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3168system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3169system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3170system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3171system.realview.ethernet.droppedPackets 0 # number of packets dropped 3172system.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution 3173system.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution 3174system.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution 3175system.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution 3176system.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution 3177system.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution 3178system.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution 3179system.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution 3180system.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution 3181system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution 3182system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution 3183system.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution 3184system.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution 3185system.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution 3186system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3187system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) 3188system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) 3189system.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) 3190system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) 3191system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) 3192system.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) 3193system.toL2Bus.snoops 3318184 # Total snoops (count) 3194system.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram 3195system.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram 3196system.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram 3197system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3198system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3199system.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram 3200system.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram 3201system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3202system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3203system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3204system.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram 3205system.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) 3206system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3207system.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) 3208system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3209system.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) 3210system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3211system.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) 3212system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3213 3214---------- End Simulation Statistics ---------- 3215