stats.txt revision 10628
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 47.355615 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 47355615197500 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 178863 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 210359 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 9462962325 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 759628 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 5004.31 # Real time elapsed on the host 1210628Sandreas.hansson@arm.comsim_insts 895084962 # Number of instructions simulated 1310628Sandreas.hansson@arm.comsim_ops 1052703090 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory 1810628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory 1910628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory 2310628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory 2410628Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory 2510628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67574456 # Number of bytes read from this memory 2610628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory 2710628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory 2810628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory 2910628Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory 3010585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory 3110585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory 3210628Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 78287056 # Number of bytes written to this memory 3310628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory 3410628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory 3510628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory 3610628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory 3710628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory 3810628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory 3910628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory 4010628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory 4110628Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory 4210628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory 4310628Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory 4410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory 4510585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory 4610628Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory 4710628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) 4810628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) 4910628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) 5010628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) 5110628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) 5210628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) 5310628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) 5410628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) 5510628Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) 5610628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) 5710628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) 5810628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) 5910628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) 6010628Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) 6110628Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) 6210585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) 6310628Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) 6410628Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) 6510628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) 6610628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) 6710628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) 6810628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) 6910628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) 7010628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) 7110628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) 7210628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) 7310628Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) 7410628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) 7510628Sandreas.hansson@arm.comsystem.physmem.readReqs 1055887 # Number of read requests accepted 7610628Sandreas.hansson@arm.comsystem.physmem.writeReqs 1888199 # Number of write requests accepted 7710628Sandreas.hansson@arm.comsystem.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue 7810628Sandreas.hansson@arm.comsystem.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue 7910628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM 8010628Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue 8110628Sandreas.hansson@arm.comsystem.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM 8210628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side 8310628Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side 8410628Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue 8510628Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one 8610628Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write 8710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 58784 # Per bank write bursts 8810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 68771 # Per bank write bursts 8910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 59130 # Per bank write bursts 9010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 67531 # Per bank write bursts 9110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 66855 # Per bank write bursts 9210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 75133 # Per bank write bursts 9310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 65903 # Per bank write bursts 9410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 67407 # Per bank write bursts 9510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 54196 # Per bank write bursts 9610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 110706 # Per bank write bursts 9710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 54461 # Per bank write bursts 9810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 64104 # Per bank write bursts 9910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 57097 # Per bank write bursts 10010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 66166 # Per bank write bursts 10110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 60751 # Per bank write bursts 10210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 58597 # Per bank write bursts 10310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 116651 # Per bank write bursts 10410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 125865 # Per bank write bursts 10510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 118664 # Per bank write bursts 10610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 124773 # Per bank write bursts 10710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 121001 # Per bank write bursts 10810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 125597 # Per bank write bursts 10910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 113710 # Per bank write bursts 11010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 116980 # Per bank write bursts 11110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 110183 # Per bank write bursts 11210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 114411 # Per bank write bursts 11310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 109841 # Per bank write bursts 11410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 116847 # Per bank write bursts 11510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 116927 # Per bank write bursts 11610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 118874 # Per bank write bursts 11710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 112844 # Per bank write bursts 11810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 118210 # Per bank write bursts 11910515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12010628Sandreas.hansson@arm.comsystem.physmem.numWrRetry 5 # Number of times write queue was full causing retry 12110628Sandreas.hansson@arm.comsystem.physmem.totGap 47355613259000 # Total gap between requests 12210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 12310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 12410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 12510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 37 # Read request sizes (log2) 12610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 12710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 12810628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1055845 # Read request sizes (log2) 12910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2601 # Write request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 13510628Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1885596 # Write request sizes (log2) 13610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see 13710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see 13810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see 13910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see 14010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see 14110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see 14210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see 14310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see 14410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see 14510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see 14610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see 14710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see 14810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see 14910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see 15010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see 15110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see 15210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see 15310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see 15410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see 15510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see 15610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 15710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 15810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 15910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 16210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 16310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 16410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 16510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 16610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 16710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 16810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 18310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see 18410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see 18510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see 18610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see 18710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see 18810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see 18910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see 19010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see 19110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see 19210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see 19310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see 19410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see 19510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see 19610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see 19710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see 19810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see 19910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see 20010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see 20110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see 20210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see 20310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see 20410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see 20510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see 20610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see 20710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see 20810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see 20910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see 21010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see 21110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see 21210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see 21310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see 21410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see 21510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see 21610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see 21710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see 21810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see 21910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see 22010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see 22110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see 22210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see 22310585Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see 22410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see 22510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 22610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see 22710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 22810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see 22910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 23010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see 23110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see 23210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation 23310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation 23410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation 23510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation 23610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation 23710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation 23810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation 23910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation 24010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation 24110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation 24210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation 24310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation 24410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation 24510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation 24610628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes 24710628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes 24810628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes 24910628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes 25010585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 25110628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 25210628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes 25310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads 25410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads 25510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads 25610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads 25710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads 25810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads 25910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads 26010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads 26110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads 26210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads 26310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads 26410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads 26510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads 26610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads 26710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads 26810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads 26910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads 27010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads 27110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads 27210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads 27310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads 27410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads 27510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads 27610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads 27710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads 27810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads 27910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads 28010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads 28110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads 28210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads 28310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads 28410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads 28510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads 28610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads 28710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads 28810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads 28910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads 29010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads 29110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads 29210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads 29310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads 29410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads 29510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads 29610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads 29710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads 29810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads 29910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads 30010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads 30110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads 30210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads 30310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads 30410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads 30510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads 30610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads 30710628Sandreas.hansson@arm.comsystem.physmem.totQLat 39480003252 # Total ticks spent queuing 30810628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM 30910628Sandreas.hansson@arm.comsystem.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers 31010628Sandreas.hansson@arm.comsystem.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst 31110515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31210628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst 31310628Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s 31410628Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s 31510628Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s 31610628Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s 31710515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31810515SAli.Saidi@ARM.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31910628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32010515SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 32110628Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 32210628Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing 32310628Sandreas.hansson@arm.comsystem.physmem.readRowHits 797783 # Number of row buffer hits during reads 32410628Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1093063 # Number of row buffer hits during writes 32510628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 32610628Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes 32710628Sandreas.hansson@arm.comsystem.physmem.avgGap 16084996.59 # Average gap between requests 32810628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined 32910628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) 33010628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) 33110628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) 33210628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) 33310628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 33410628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) 33510628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) 33610628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) 33710628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.764772 # Core power per rank (mW) 33810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states 33910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states 34010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states 34210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34310628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) 34410628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) 34510628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) 34610628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) 34710628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 34810628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) 34910628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) 35010628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) 35110628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.721243 # Core power per rank (mW) 35210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states 35310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states 35410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states 35610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory 35810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory 35910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 36010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 36110515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 36210515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 36310515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory 36410515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 36610515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) 36710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 36810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 36910515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 37110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 37210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) 37310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 37410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 37510585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37610585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37710585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37810585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 37910585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38010585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38110628Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 131272413 # Number of BP lookups 38210628Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted 38310628Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect 38410628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups 38510628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits 38610585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 38710628Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage 38810628Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. 38910628Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. 39010515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 271399 # Table walker walks requested 42110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors 42210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate 42310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate 42410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency 42510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency 42710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency 42810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency 42910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency 43010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency 43110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency 43210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency 43310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency 43410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency 43510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency 43610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency 43710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency 43810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency 43910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 44010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 44110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 44210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 44310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 44410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 44510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency 44710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution 44810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution 44910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution 45010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated 45110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated 45210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated 45310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst 45410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst 45610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst 45710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst 45910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst 46010585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46110585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46210628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 83830376 # DTB read hits 46310628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 224800 # DTB read misses 46410628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 74836136 # DTB write hits 46510628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 46599 # DTB write misses 46610585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46710585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46810628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 46910628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 47010628Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB 47110628Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions 47210628Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch 47310585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47410628Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions 47510628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 84055176 # DTB read accesses 47610628Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 74882735 # DTB write accesses 47710585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47810628Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 158666512 # DTB hits 47910628Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 271399 # DTB misses 48010628Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 158937911 # DTB accesses 48110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 59516 # Table walker walks requested 51110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors 51210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 51310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate 51410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency 51510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency 51710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency 51810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency 51910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency 52010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency 52110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency 52210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency 52310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency 52410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency 52510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency 52610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency 52710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency 52810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency 52910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 53010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 53110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 53210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 53310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency 53710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution 53810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution 53910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution 54010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated 54110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated 54210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated 54310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst 54510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst 54610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst 54810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst 54910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst 55010628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 234493726 # ITB inst hits 55110628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 59516 # ITB inst misses 55210585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 55310585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 55410585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 55510585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 55610585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55710585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55810628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 55910628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 56010628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB 56110585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56210585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56310585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56410628Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions 56510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 56610585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 56710628Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 234553242 # ITB inst accesses 56810628Sandreas.hansson@arm.comsystem.cpu0.itb.hits 234493726 # DTB hits 56910628Sandreas.hansson@arm.comsystem.cpu0.itb.misses 59516 # DTB misses 57010628Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 234553242 # DTB accesses 57110628Sandreas.hansson@arm.comsystem.cpu0.numCycles 936626399 # number of cpu cycles simulated 57210585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 57310585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 57410628Sandreas.hansson@arm.comsystem.cpu0.committedInsts 433367687 # Number of instructions committed 57510628Sandreas.hansson@arm.comsystem.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed 57610628Sandreas.hansson@arm.comsystem.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit 57710628Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching 57810628Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57910628Sandreas.hansson@arm.comsystem.cpu0.cpi 2.161274 # CPI: cycles per instruction 58010628Sandreas.hansson@arm.comsystem.cpu0.ipc 0.462690 # IPC: instructions per cycle 58110585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 58210628Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed 58310628Sandreas.hansson@arm.comsystem.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked 58410628Sandreas.hansson@arm.comsystem.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped 58510628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5387052 # number of replacements 58610628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use 58710628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. 58810628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. 58910628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. 59010628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. 59110628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor 59210628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy 59310628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy 59410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59510628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 59610628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 59710628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 59810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 59910628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses 60010628Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses 60110628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits 60210628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits 60310628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits 60410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits 60510628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 251432 # number of WriteInvalidateReq hits 60610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits 60710628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1745310 # number of LoadLockedReq hits 60810628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits 60910628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1668274 # number of StoreCondReq hits 61010628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits 61110628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.inst 146466768 # number of demand (read+write) hits 61210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits 61310628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.inst 146466768 # number of overall hits 61410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 146466768 # number of overall hits 61510628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.inst 3852692 # number of ReadReq misses 61610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses 61710628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.inst 2255601 # number of WriteReq misses 61810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses 61910628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 766100 # number of WriteInvalidateReq misses 62010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses 62110628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 104059 # number of LoadLockedReq misses 62210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses 62310628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.inst 180014 # number of StoreCondReq misses 62410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses 62510628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.inst 6108293 # number of demand (read+write) misses 62610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses 62710628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.inst 6108293 # number of overall misses 62810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6108293 # number of overall misses 62910628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54452724607 # number of ReadReq miss cycles 63010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles 63110628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 41906959422 # number of WriteReq miss cycles 63210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles 63310628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 27296991314 # number of WriteInvalidateReq miss cycles 63410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles 63510628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1502404735 # number of LoadLockedReq miss cycles 63610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles 63710628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3769027814 # number of StoreCondReq miss cycles 63810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles 63910628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2840500 # number of StoreCondFailReq miss cycles 64010628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles 64110628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.inst 96359684029 # number of demand (read+write) miss cycles 64210628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles 64310628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.inst 96359684029 # number of overall miss cycles 64410628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles 64510628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.inst 80967470 # number of ReadReq accesses(hits+misses) 64610628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) 64710628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.inst 71607591 # number of WriteReq accesses(hits+misses) 64810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) 64910628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 1017532 # number of WriteInvalidateReq accesses(hits+misses) 65010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) 65110628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1849369 # number of LoadLockedReq accesses(hits+misses) 65210628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) 65310628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1848288 # number of StoreCondReq accesses(hits+misses) 65410628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) 65510628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.inst 152575061 # number of demand (read+write) accesses 65610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses 65710628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.inst 152575061 # number of overall (read+write) accesses 65810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses 65910628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047583 # miss rate for ReadReq accesses 66010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses 66110628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.031499 # miss rate for WriteReq accesses 66210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses 66310628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.752900 # miss rate for WriteInvalidateReq accesses 66410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses 66510628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.056267 # miss rate for LoadLockedReq accesses 66610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses 66710628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.097395 # miss rate for StoreCondReq accesses 66810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses 66910628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.inst 0.040035 # miss rate for demand accesses 67010628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses 67110628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.inst 0.040035 # miss rate for overall accesses 67210628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses 67310628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269 # average ReadReq miss latency 67410628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency 67510628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811 # average WriteReq miss latency 67610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency 67710628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315 # average WriteInvalidateReq miss latency 67810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency 67910628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582 # average LoadLockedReq miss latency 68010628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency 68110628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946 # average StoreCondReq miss latency 68210628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency 68310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 68410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 68510628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency 68610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency 68710628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency 68810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency 68910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 69210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 69310585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 69410585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 69510585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 69610585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 69710628Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks 69810628Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3733142 # number of writebacks 69910628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 361487 # number of ReadReq MSHR hits 70010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits 70110628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 935411 # number of WriteReq MSHR hits 70210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits 70310628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 100 # number of WriteInvalidateReq MSHR hits 70410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits 70510628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 34 # number of LoadLockedReq MSHR hits 70610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits 70710628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 67 # number of StoreCondReq MSHR hits 70810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 70910628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.inst 1296898 # number of demand (read+write) MSHR hits 71010628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits 71110628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.inst 1296898 # number of overall MSHR hits 71210628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits 71310628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3491205 # number of ReadReq MSHR misses 71410628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses 71510628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1320190 # number of WriteReq MSHR misses 71610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses 71710628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 766000 # number of WriteInvalidateReq MSHR misses 71810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses 71910628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 104025 # number of LoadLockedReq MSHR misses 72010628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses 72110628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 179947 # number of StoreCondReq MSHR misses 72210628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses 72310628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.inst 4811395 # number of demand (read+write) MSHR misses 72410628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses 72510628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.inst 4811395 # number of overall MSHR misses 72610628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses 72710628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42113152704 # number of ReadReq MSHR miss cycles 72810628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles 72910628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 22270249828 # number of WriteReq MSHR miss cycles 73010628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles 73110628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 25755951436 # number of WriteInvalidateReq MSHR miss cycles 73210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles 73310628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1293404753 # number of LoadLockedReq MSHR miss cycles 73410628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles 73510628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles 73610628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles 73710628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles 73810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles 73910628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles 74010628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles 74110628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 64383402532 # number of overall MSHR miss cycles 74210628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles 74310628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5824362996 # number of ReadReq MSHR uncacheable cycles 74410628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles 74510628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5586865743 # number of WriteReq MSHR uncacheable cycles 74610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles 74710628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles 74810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles 74910628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses 75010628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses 75110628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses 75210628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses 75310628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses 75410628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses 75510628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses 75610628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses 75710628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses 75810628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses 75910628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses 76010628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses 76110628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses 76210628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses 76310628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency 76410628Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency 76510628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275 # average WriteReq mshr miss latency 76610628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency 76710628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488 # average WriteInvalidateReq mshr miss latency 76810628Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency 76910628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency 77010628Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency 77110628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency 77210628Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency 77310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 77410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 77510628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency 77610628Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 77710628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency 77810628Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 77910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 78010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 78110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 78210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 78310585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 78410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 78510585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 78610628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9463678 # number of replacements 78710628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use 78810628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. 78910628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. 79010628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. 79110628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. 79210628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor 79310628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy 79410628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 79510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 79610628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 79710628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 79810628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 79910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 80010628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses 80110628Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses 80210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits 80310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits 80410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits 80510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits 80610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits 80710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 224826074 # number of overall hits 80810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses 80910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses 81010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses 81110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses 81210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses 81310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9464200 # number of overall misses 81410628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles 81510628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles 81610628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles 81710628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles 81810628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles 81910628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles 82010628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) 82110628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) 82210628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses 82310628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses 82410628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses 82510628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses 82610628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses 82710628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses 82810628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses 82910628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses 83010628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses 83110628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses 83210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency 83310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency 83410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 83510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency 83610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 83710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency 83810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 83910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 84010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 84110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 84210585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 84310585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 84410585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 84510585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 84610628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses 84710628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses 84810628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses 84910628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses 85010628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses 85110628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses 85210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles 85310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles 85410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles 85510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles 85610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles 85710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles 85910585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles 86110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles 86210628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses 86310628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses 86410628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses 86510628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses 86610628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses 86710628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses 86810628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency 86910628Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency 87010628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 87110628Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 87210628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 87310628Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 87410585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 87510585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 87610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 87710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 87810585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 87910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued 88010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified 88110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue 88210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 88310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 88410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1270201 # number of prefetches not generated due to page crossing 88510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2736028 # number of replacements 88610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16197.540138 # Cycle average of tags in use 88710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15248127 # Total number of references to valid blocks. 88810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2752162 # Sample count of references to valid blocks. 88910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.540418 # Average number of references to valid blocks. 89010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cycle when the warmup percentage was hit. 89110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor 89210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor 89310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor 89410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 9438.642805 # Average occupied blocks per requestor 89510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor 89610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy 89710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy 89810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy 89910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.576089 # Average percentage of cache occupancy 90010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy 90110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy 90210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id 90310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id 90410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13544 # Occupied blocks per task id 90510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 133 # Occupied blocks per task id 90610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 367 # Occupied blocks per task id 90710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1060 # Occupied blocks per task id 90810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 959 # Occupied blocks per task id 90910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 91010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 91110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 25 # Occupied blocks per task id 91210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 35 # Occupied blocks per task id 91310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 91410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id 91510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id 91610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id 91710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id 91810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id 91910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id 92010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id 92110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses 92210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses 92310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits 92410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits 92510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 11610557 # number of ReadReq hits 92610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 12212111 # number of ReadReq hits 92710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3733141 # number of Writeback hits 92810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3733141 # number of Writeback hits 92910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 193768 # number of WriteInvalidateReq hits 93010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::total 193768 # number of WriteInvalidateReq hits 93110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 68627 # number of UpgradeReq hits 93210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 68627 # number of UpgradeReq hits 93310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 33597 # number of SCUpgradeReq hits 93410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 33597 # number of SCUpgradeReq hits 93510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.inst 855771 # number of ReadExReq hits 93610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 855771 # number of ReadExReq hits 93710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 463342 # number of demand (read+write) hits 93810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 138212 # number of demand (read+write) hits 93910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 12466328 # number of demand (read+write) hits 94010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 13067882 # number of demand (read+write) hits 94110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 463342 # number of overall hits 94210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 138212 # number of overall hits 94310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 12466328 # number of overall hits 94410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 13067882 # number of overall hits 94510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11843 # number of ReadReq misses 94610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8238 # number of ReadReq misses 94710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 1448613 # number of ReadReq misses 94810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 1468694 # number of ReadReq misses 94910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 570757 # number of WriteInvalidateReq misses 95010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 570757 # number of WriteInvalidateReq misses 95110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 126856 # number of UpgradeReq misses 95210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 126856 # number of UpgradeReq misses 95310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 146340 # number of SCUpgradeReq misses 95410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 146340 # number of SCUpgradeReq misses 95510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 10 # number of SCUpgradeFailReq misses 95610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 95710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.inst 270676 # number of ReadExReq misses 95810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 270676 # number of ReadExReq misses 95910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11843 # number of demand (read+write) misses 96010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8238 # number of demand (read+write) misses 96110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 1719289 # number of demand (read+write) misses 96210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1739370 # number of demand (read+write) misses 96310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11843 # number of overall misses 96410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8238 # number of overall misses 96510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 1719289 # number of overall misses 96610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1739370 # number of overall misses 96710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 383176229 # number of ReadReq miss cycles 96810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 279750987 # number of ReadReq miss cycles 96910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 44923505132 # number of ReadReq miss cycles 97010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 45586432348 # number of ReadReq miss cycles 97110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 223595615 # number of WriteInvalidateReq miss cycles 97210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 223595615 # number of WriteInvalidateReq miss cycles 97310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2548596996 # number of UpgradeReq miss cycles 97410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2548596996 # number of UpgradeReq miss cycles 97510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2948593769 # number of SCUpgradeReq miss cycles 97610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2948593769 # number of SCUpgradeReq miss cycles 97710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2234000 # number of SCUpgradeFailReq miss cycles 97810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2234000 # number of SCUpgradeFailReq miss cycles 97910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 12372799630 # number of ReadExReq miss cycles 98010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12372799630 # number of ReadExReq miss cycles 98110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 383176229 # number of demand (read+write) miss cycles 98210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 279750987 # number of demand (read+write) miss cycles 98310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 57296304762 # number of demand (read+write) miss cycles 98410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 57959231978 # number of demand (read+write) miss cycles 98510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 383176229 # number of overall miss cycles 98610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 279750987 # number of overall miss cycles 98710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 57296304762 # number of overall miss cycles 98810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 57959231978 # number of overall miss cycles 98910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 475185 # number of ReadReq accesses(hits+misses) 99010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146450 # number of ReadReq accesses(hits+misses) 99110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 13059170 # number of ReadReq accesses(hits+misses) 99210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 13680805 # number of ReadReq accesses(hits+misses) 99310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3733141 # number of Writeback accesses(hits+misses) 99410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3733141 # number of Writeback accesses(hits+misses) 99510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 764525 # number of WriteInvalidateReq accesses(hits+misses) 99610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) 99710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 195483 # number of UpgradeReq accesses(hits+misses) 99810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) 99910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 179937 # number of SCUpgradeReq accesses(hits+misses) 100010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) 100110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 10 # number of SCUpgradeFailReq accesses(hits+misses) 100210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 100310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1126447 # number of ReadExReq accesses(hits+misses) 100410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) 100510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses 100610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses 100710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 14185617 # number of demand (read+write) accesses 100810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses 100910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses 101010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses 101110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 14185617 # number of overall (read+write) accesses 101210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses 101310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses 101410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # miss rate for ReadReq accesses 101510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110927 # miss rate for ReadReq accesses 101610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.107354 # miss rate for ReadReq accesses 101710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.746551 # miss rate for WriteInvalidateReq accesses 101810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses 101910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.648936 # miss rate for UpgradeReq accesses 102010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses 102110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813285 # miss rate for SCUpgradeReq accesses 102210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses 102310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 102410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 102510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.240292 # miss rate for ReadExReq accesses 102610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.240292 # miss rate for ReadExReq accesses 102710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for demand accesses 102810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056251 # miss rate for demand accesses 102910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.121199 # miss rate for demand accesses 103010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.117467 # miss rate for demand accesses 103110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for overall accesses 103210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056251 # miss rate for overall accesses 103310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.121199 # miss rate for overall accesses 103410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.117467 # miss rate for overall accesses 103510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average ReadReq miss latency 103610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880 # average ReadReq miss latency 103710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31011.391677 # average ReadReq miss latency 103810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 31038.754395 # average ReadReq miss latency 103910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 391.752734 # average WriteInvalidateReq miss latency 104010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 391.752734 # average WriteInvalidateReq miss latency 104110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20090.472630 # average UpgradeReq miss latency 104210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20090.472630 # average UpgradeReq miss latency 104310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20148.925577 # average SCUpgradeReq miss latency 104410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20148.925577 # average SCUpgradeReq miss latency 104510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 223400 # average SCUpgradeFailReq miss latency 104610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223400 # average SCUpgradeFailReq miss latency 104710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 45710.737672 # average ReadExReq miss latency 104810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45710.737672 # average ReadExReq miss latency 104910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency 105010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency 105110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency 105210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286 # average overall miss latency 105310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency 105410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency 105510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency 105610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286 # average overall miss latency 105710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked 105810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 106010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked 106210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 106410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 106510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1399370 # number of writebacks 106610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1399370 # number of writebacks 106710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 106810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3403 # number of ReadReq MSHR hits 106910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 3404 # number of ReadReq MSHR hits 107010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 156 # number of WriteInvalidateReq MSHR hits 107110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 156 # number of WriteInvalidateReq MSHR hits 107210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9658 # number of ReadExReq MSHR hits 107310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 9658 # number of ReadExReq MSHR hits 107410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 107510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 13061 # number of demand (read+write) MSHR hits 107610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 13062 # number of demand (read+write) MSHR hits 107710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 107810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 13061 # number of overall MSHR hits 107910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 13062 # number of overall MSHR hits 108010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11843 # number of ReadReq MSHR misses 108110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses 108210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 1445210 # number of ReadReq MSHR misses 108310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 1465290 # number of ReadReq MSHR misses 108410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of HardPFReq MSHR misses 108510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 1036981 # number of HardPFReq MSHR misses 108610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 570601 # number of WriteInvalidateReq MSHR misses 108710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570601 # number of WriteInvalidateReq MSHR misses 108810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 126856 # number of UpgradeReq MSHR misses 108910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 126856 # number of UpgradeReq MSHR misses 109010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 146340 # number of SCUpgradeReq MSHR misses 109110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 146340 # number of SCUpgradeReq MSHR misses 109210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 10 # number of SCUpgradeFailReq MSHR misses 109310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 109410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 261018 # number of ReadExReq MSHR misses 109510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 261018 # number of ReadExReq MSHR misses 109610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11843 # number of demand (read+write) MSHR misses 109710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses 109810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1706228 # number of demand (read+write) MSHR misses 109910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses 110010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses 110110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses 110210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1706228 # number of overall MSHR misses 110310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses 110410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2763289 # number of overall MSHR misses 110510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of ReadReq MSHR miss cycles 110610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 221721501 # number of ReadReq MSHR miss cycles 110710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 34355781249 # number of ReadReq MSHR miss cycles 110810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 34877337999 # number of ReadReq MSHR miss cycles 110910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of HardPFReq MSHR miss cycles 111010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47311809533 # number of HardPFReq MSHR miss cycles 111110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 20034543782 # number of WriteInvalidateReq MSHR miss cycles 111210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles 111310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2151275072 # number of UpgradeReq MSHR miss cycles 111410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2151275072 # number of UpgradeReq MSHR miss cycles 111510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1993779824 # number of SCUpgradeReq MSHR miss cycles 111610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1993779824 # number of SCUpgradeReq MSHR miss cycles 111710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1835000 # number of SCUpgradeFailReq MSHR miss cycles 111810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1835000 # number of SCUpgradeFailReq MSHR miss cycles 111910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 9532664011 # number of ReadExReq MSHR miss cycles 112010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9532664011 # number of ReadExReq MSHR miss cycles 112110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of demand (read+write) MSHR miss cycles 112210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 221721501 # number of demand (read+write) MSHR miss cycles 112310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 43888445260 # number of demand (read+write) MSHR miss cycles 112410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles 112510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles 112610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles 112710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 43888445260 # number of overall MSHR miss cycles 112810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles 112910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles 113010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9672004742 # number of ReadReq MSHR uncacheable cycles 113110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles 113210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles 113310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles 113410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles 113510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles 113610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses 113710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses 113810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses 113910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses 114010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 114110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 114210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses 114310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses 114410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses 114510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses 114610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses 114710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses 114810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 114910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 115010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses 115110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses 115210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses 115310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses 115410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses 115510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses 115610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses 115710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses 115810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses 115910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 116010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses 116110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency 116210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency 116310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency 116410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency 116510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency 116610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency 116710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency 116810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency 116910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency 117010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency 117110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency 117210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency 117310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency 117410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency 117510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency 117610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency 117710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 117810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 117910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency 118010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency 118110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 118210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 118310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency 118410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency 118510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency 118610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 118710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 118810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 118910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 119010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 119110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 119210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 119310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution 119410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution 119510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution 119610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution 119710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution 119810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution 119910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 120010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution 120110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution 120210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution 120310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution 120410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution 120510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution 120610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 120710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution 120810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution 120910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) 121010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) 121110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) 121210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) 121310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) 121410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) 121510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) 121610628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) 121710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) 121810628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) 121910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) 122010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram 122110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram 122210628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram 122310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 122510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 122610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 122710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 122810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 122910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram 123010628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram 123110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 123210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 123310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 123410628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram 123510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) 123610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 123710628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) 123810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 123910628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) 124010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 124110628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) 124210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 124310628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) 124410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 124510628Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) 124610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 124710628Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 141025153 # Number of BP lookups 124810628Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted 124910628Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect 125010628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups 125110628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits 125210585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 125310628Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage 125410628Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. 125510628Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. 125610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 125710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 125810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 125910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 126010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 126110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 126310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 126410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 126510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 126610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 126710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 126810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 126910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 127010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 127110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 127310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 127410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 127510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 127610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 127710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 127810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 127910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 128010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 128310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 128410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 128510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 298651 # Table walker walks requested 128610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors 128710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate 128810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate 128910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency 129010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 129110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency 129210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency 129310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency 129410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency 129510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency 129610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency 129710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency 129810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency 129910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 130010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency 130110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 130210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 130310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 130410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 130510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency 130610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution 130710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution 130810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution 130910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated 131010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated 131110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated 131210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst 131310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 131410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst 131510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst 131610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 131710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst 131810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst 131910585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 132010585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 132110628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 90905034 # DTB read hits 132210628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 248418 # DTB read misses 132310628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 78767149 # DTB write hits 132410628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 50233 # DTB write misses 132510585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 132610585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132710628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 132810628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 132910628Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB 133010628Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions 133110628Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch 133210585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 133310628Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions 133410628Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 91153452 # DTB read accesses 133510628Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 78817382 # DTB write accesses 133610585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 133710628Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 169672183 # DTB hits 133810628Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 298651 # DTB misses 133910628Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 169970834 # DTB accesses 134010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 134110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 134410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 134510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 134610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 134910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 135010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 135110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 135210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 135310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 135410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 135510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 135610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 135710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 135810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 135910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 136010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 136110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 136210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 136310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 136410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 136510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 136610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 136710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 136810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 136910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 67610 # Table walker walks requested 137010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors 137110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate 137210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate 137310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency 137410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency 137510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency 137610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency 137710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency 137810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency 137910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency 138010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency 138110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency 138210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency 138310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency 138410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency 138510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency 138610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 138710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 138810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 138910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency 139010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution 139110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution 139210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution 139310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated 139410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated 139510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated 139610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 139710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst 139810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst 139910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 140010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst 140110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst 140210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst 140310628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 252933263 # ITB inst hits 140410628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 67610 # ITB inst misses 140510585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 140610585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 140710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 140810585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 140910585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 141010585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 141110628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 141210628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 141310628Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB 141410585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 141510585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141610585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 141710628Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions 141810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 141910585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 142010628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 253000873 # ITB inst accesses 142110628Sandreas.hansson@arm.comsystem.cpu1.itb.hits 252933263 # DTB hits 142210628Sandreas.hansson@arm.comsystem.cpu1.itb.misses 67610 # DTB misses 142310628Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 253000873 # DTB accesses 142410628Sandreas.hansson@arm.comsystem.cpu1.numCycles 943783669 # number of cpu cycles simulated 142510585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 142610585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 142710628Sandreas.hansson@arm.comsystem.cpu1.committedInsts 461717275 # Number of instructions committed 142810628Sandreas.hansson@arm.comsystem.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed 142910628Sandreas.hansson@arm.comsystem.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit 143010628Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching 143110628Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 143210628Sandreas.hansson@arm.comsystem.cpu1.cpi 2.044073 # CPI: cycles per instruction 143310628Sandreas.hansson@arm.comsystem.cpu1.ipc 0.489219 # IPC: instructions per cycle 143410585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 143510628Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed 143610628Sandreas.hansson@arm.comsystem.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked 143710628Sandreas.hansson@arm.comsystem.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped 143810628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5624476 # number of replacements 143910628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use 144010628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. 144110628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. 144210628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. 144310628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. 144410628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.inst 426.107402 # Average occupied blocks per requestor 144510628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy 144610628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy 144710628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 144810628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 144910628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 145010628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 145110628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 145210628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses 145310628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses 145410628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.inst 83489779 # number of ReadReq hits 145510628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits 145610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.inst 73474609 # number of WriteReq hits 145710628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits 145810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 71990 # number of WriteInvalidateReq hits 145910628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits 146010628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1908367 # number of LoadLockedReq hits 146110628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits 146210628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1854336 # number of StoreCondReq hits 146310628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits 146410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.inst 156964388 # number of demand (read+write) hits 146510628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits 146610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.inst 156964388 # number of overall hits 146710628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 156964388 # number of overall hits 146810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.inst 4311289 # number of ReadReq misses 146910628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses 147010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.inst 2366929 # number of WriteReq misses 147110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses 147210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 476593 # number of WriteInvalidateReq misses 147310628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses 147410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 141331 # number of LoadLockedReq misses 147510628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses 147610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.inst 193852 # number of StoreCondReq misses 147710628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses 147810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.inst 6678218 # number of demand (read+write) misses 147910628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses 148010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.inst 6678218 # number of overall misses 148110628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6678218 # number of overall misses 148210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 60722587231 # number of ReadReq miss cycles 148310628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles 148410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 38093191666 # number of WriteReq miss cycles 148510628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles 148610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 11613108236 # number of WriteInvalidateReq miss cycles 148710628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles 148810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1977833980 # number of LoadLockedReq miss cycles 148910628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles 149010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3982712056 # number of StoreCondReq miss cycles 149110628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles 149210628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2357000 # number of StoreCondFailReq miss cycles 149310628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles 149410628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.inst 98815778897 # number of demand (read+write) miss cycles 149510628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles 149610628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.inst 98815778897 # number of overall miss cycles 149710628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles 149810628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.inst 87801068 # number of ReadReq accesses(hits+misses) 149910628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) 150010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.inst 75841538 # number of WriteReq accesses(hits+misses) 150110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) 150210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 548583 # number of WriteInvalidateReq accesses(hits+misses) 150310628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) 150410628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2049698 # number of LoadLockedReq accesses(hits+misses) 150510628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) 150610628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2048188 # number of StoreCondReq accesses(hits+misses) 150710628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) 150810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.inst 163642606 # number of demand (read+write) accesses 150910628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses 151010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.inst 163642606 # number of overall (read+write) accesses 151110628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses 151210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.049103 # miss rate for ReadReq accesses 151310628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses 151410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.031209 # miss rate for WriteReq accesses 151510628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses 151610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.868771 # miss rate for WriteInvalidateReq accesses 151710628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses 151810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.068952 # miss rate for LoadLockedReq accesses 151910628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses 152010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.094646 # miss rate for StoreCondReq accesses 152110628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses 152210628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.inst 0.040810 # miss rate for demand accesses 152310628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses 152410628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.inst 0.040810 # miss rate for overall accesses 152510628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses 152610628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044 # average ReadReq miss latency 152710628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency 152810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856 # average WriteReq miss latency 152910628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency 153010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930 # average WriteInvalidateReq miss latency 153110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency 153210628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388 # average LoadLockedReq miss latency 153310628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency 153410628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182 # average StoreCondReq miss latency 153510628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency 153610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 153710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 153810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency 153910628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency 154010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency 154110628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency 154210585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 154310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 154410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 154510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 154610585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154710585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 154810585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 154910585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 155010628Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks 155110628Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3711348 # number of writebacks 155210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits 155310628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits 155410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR hits 155510628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits 155610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 60 # number of WriteInvalidateReq MSHR hits 155710628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits 155810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 47 # number of LoadLockedReq MSHR hits 155910628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits 156010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 68 # number of StoreCondReq MSHR hits 156110628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits 156210628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.inst 1368730 # number of demand (read+write) MSHR hits 156310628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits 156410628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.inst 1368730 # number of overall MSHR hits 156510628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits 156610628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3913497 # number of ReadReq MSHR misses 156710628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses 156810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1395991 # number of WriteReq MSHR misses 156910628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses 157010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 476533 # number of WriteInvalidateReq MSHR misses 157110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses 157210628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 141284 # number of LoadLockedReq MSHR misses 157310628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses 157410628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses 157510628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses 157610628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.inst 5309488 # number of demand (read+write) MSHR misses 157710628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses 157810628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.inst 5309488 # number of overall MSHR misses 157910628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses 158010628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 46779736993 # number of ReadReq MSHR miss cycles 158110628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles 158210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20386885918 # number of WriteReq MSHR miss cycles 158310628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles 158410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 10653380764 # number of WriteInvalidateReq MSHR miss cycles 158510628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles 158610628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles 158710628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles 158810628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles 158910628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles 159010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles 159110628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles 159210628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles 159310628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles 159410628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles 159510628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles 159610628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles 159710628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles 159810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles 159910628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles 160010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles 160110628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles 160210628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses 160310628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses 160410628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses 160510628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses 160610628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses 160710628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses 160810628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses 160910628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses 161010628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses 161110628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses 161210628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses 161310628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses 161410628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses 161510628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses 161610628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency 161710628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency 161810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency 161910628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency 162010628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency 162110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency 162210628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency 162310628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency 162410628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency 162510628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency 162610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 162710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 162810628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency 162910628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 163010628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency 163110628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 163210585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 163310585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 163410585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 163510585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 163610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 163710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 163810585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 163910628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9215030 # number of replacements 164010628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use 164110628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. 164210628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. 164310628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. 164410628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. 164510628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor 164610628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy 164710628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy 164810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 164910628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id 165010628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 165110628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 165210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 165310628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses 165410628Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses 165510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits 165610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits 165710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits 165810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits 165910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits 166010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 243489253 # number of overall hits 166110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses 166210628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses 166310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9215542 # number of demand (read+write) misses 166410628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9215542 # number of demand (read+write) misses 166510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9215542 # number of overall misses 166610628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9215542 # number of overall misses 166710628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91468274167 # number of ReadReq miss cycles 166810628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 91468274167 # number of ReadReq miss cycles 166910628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 91468274167 # number of demand (read+write) miss cycles 167010628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles 167110628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles 167210628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles 167310628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) 167410628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) 167510628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses 167610628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses 167710628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses 167810628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses 167910628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses 168010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses 168110628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses 168210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses 168310628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses 168410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses 168510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency 168610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency 168710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 168810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency 168910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 169010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency 169110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 169410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 169510585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 169610585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169710585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 169810585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 169910628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # number of ReadReq MSHR misses 170010628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9215542 # number of ReadReq MSHR misses 170110628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9215542 # number of demand (read+write) MSHR misses 170210628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9215542 # number of demand (read+write) MSHR misses 170310628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9215542 # number of overall MSHR misses 170410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9215542 # number of overall MSHR misses 170510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77617743273 # number of ReadReq MSHR miss cycles 170610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 77617743273 # number of ReadReq MSHR miss cycles 170710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77617743273 # number of demand (read+write) MSHR miss cycles 170810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles 170910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles 171010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles 171110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles 171210628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles 171310628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles 171410628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles 171510628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses 171610628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq accesses 171710628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for demand accesses 171810628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.036468 # mshr miss rate for demand accesses 171910628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for overall accesses 172010628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.036468 # mshr miss rate for overall accesses 172110628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average ReadReq mshr miss latency 172210628Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8422.482722 # average ReadReq mshr miss latency 172310628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 172410628Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 172510628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 172610628Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 172710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 172810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 172910585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 173010585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 173110585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued 173310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified 173410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue 173510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 173610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 173710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing 173810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2569302 # number of replacements 173910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use 174010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. 174110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. 174210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. 174310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. 174410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor 174510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor 174610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor 174710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor 174810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor 174910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy 175010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy 175110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy 175210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy 175310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy 175410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy 175510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id 175610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 175710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id 175810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 175910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id 176010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id 176110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id 176210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 176310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 176410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id 176510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 176610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 176710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 176810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 176910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id 177010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id 177110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id 177210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id 177310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 177410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id 177510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses 177610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses 177710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits 177810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits 177910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 11678610 # number of ReadReq hits 178010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits 178110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits 178210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits 178310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 202419 # number of WriteInvalidateReq hits 178410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits 178510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 77280 # number of UpgradeReq hits 178610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits 178710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41809 # number of SCUpgradeReq hits 178810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits 178910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.inst 939119 # number of ReadExReq hits 179010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits 179110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits 179210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits 179310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 12617729 # number of demand (read+write) hits 179410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits 179510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits 179610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits 179710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 12617729 # number of overall hits 179810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits 179910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses 180010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses 180110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 1591427 # number of ReadReq misses 180210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses 180310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 180410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 180510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 272843 # number of WriteInvalidateReq misses 180610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses 180710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 137034 # number of UpgradeReq misses 180810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses 180910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151974 # number of SCUpgradeReq misses 181010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses 181110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses 181210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 181310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.inst 244121 # number of ReadExReq misses 181410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses 181510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses 181610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses 181710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 1835548 # number of demand (read+write) misses 181810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses 181910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses 182010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses 182110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 1835548 # number of overall misses 182210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses 182310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles 182410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles 182510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 47206598788 # number of ReadReq miss cycles 182610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles 182710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 213581444 # number of WriteInvalidateReq miss cycles 182810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles 182910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2792930491 # number of UpgradeReq miss cycles 183010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles 183110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3071034580 # number of SCUpgradeReq miss cycles 183210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles 183310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 1783500 # number of SCUpgradeFailReq miss cycles 183410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles 183510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9626384839 # number of ReadExReq miss cycles 183610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles 183710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles 183810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles 183910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 56832983627 # number of demand (read+write) miss cycles 184010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles 184110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles 184210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles 184310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 56832983627 # number of overall miss cycles 184410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles 184510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) 184610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) 184710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 13270037 # number of ReadReq accesses(hits+misses) 184810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) 184910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) 185010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) 185110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 475262 # number of WriteInvalidateReq accesses(hits+misses) 185210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) 185310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 214314 # number of UpgradeReq accesses(hits+misses) 185410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) 185510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 193783 # number of SCUpgradeReq accesses(hits+misses) 185610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) 185710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) 185810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 185910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183240 # number of ReadExReq accesses(hits+misses) 186010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) 186110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses 186210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses 186310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 14453277 # number of demand (read+write) accesses 186410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses 186510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses 186610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses 186710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 14453277 # number of overall (read+write) accesses 186810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses 186910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses 187010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses 187110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.119926 # miss rate for ReadReq accesses 187210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses 187310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 187410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 187510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.574090 # miss rate for WriteInvalidateReq accesses 187610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses 187710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.639408 # miss rate for UpgradeReq accesses 187810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses 187910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.784248 # miss rate for SCUpgradeReq accesses 188010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses 188110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 188210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 188310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.206316 # miss rate for ReadExReq accesses 188410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.206316 # miss rate for ReadExReq accesses 188510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for demand accesses 188610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052987 # miss rate for demand accesses 188710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.126999 # miss rate for demand accesses 188810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.122349 # miss rate for demand accesses 188910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for overall accesses 189010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052987 # miss rate for overall accesses 189110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.126999 # miss rate for overall accesses 189210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.122349 # miss rate for overall accesses 189310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average ReadReq miss latency 189410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634 # average ReadReq miss latency 189510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29663.062640 # average ReadReq miss latency 189610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197 # average ReadReq miss latency 189710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 782.799793 # average WriteInvalidateReq miss latency 189810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 782.799793 # average WriteInvalidateReq miss latency 189910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20381.295817 # average UpgradeReq miss latency 190010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817 # average UpgradeReq miss latency 190110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20207.631437 # average SCUpgradeReq miss latency 190210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437 # average SCUpgradeReq miss latency 190310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 1783500 # average SCUpgradeFailReq miss latency 190410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1783500 # average SCUpgradeFailReq miss latency 190510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39432.842070 # average ReadExReq miss latency 190610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070 # average ReadExReq miss latency 190710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 190810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 190910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency 191010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886 # average overall miss latency 191110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 191210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 191310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency 191410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886 # average overall miss latency 191510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 191610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 191710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 191810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 191910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 192010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 192110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 192210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 192310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1092301 # number of writebacks 192410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1092301 # number of writebacks 192510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 192610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1805 # number of ReadReq MSHR hits 192710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits 192810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 45 # number of WriteInvalidateReq MSHR hits 192910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 45 # number of WriteInvalidateReq MSHR hits 193010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 7072 # number of ReadExReq MSHR hits 193110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 7072 # number of ReadExReq MSHR hits 193210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 193310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8877 # number of demand (read+write) MSHR hits 193410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 8878 # number of demand (read+write) MSHR hits 193510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 193610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8877 # number of overall MSHR hits 193710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 8878 # number of overall MSHR hits 193810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12561 # number of ReadReq MSHR misses 193910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8869 # number of ReadReq MSHR misses 194010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 1589622 # number of ReadReq MSHR misses 194110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 1611052 # number of ReadReq MSHR misses 194210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 194310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 194410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of HardPFReq MSHR misses 194510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 1032302 # number of HardPFReq MSHR misses 194610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 272798 # number of WriteInvalidateReq MSHR misses 194710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 272798 # number of WriteInvalidateReq MSHR misses 194810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 137034 # number of UpgradeReq MSHR misses 194910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 137034 # number of UpgradeReq MSHR misses 195010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151974 # number of SCUpgradeReq MSHR misses 195110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151974 # number of SCUpgradeReq MSHR misses 195210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses 195310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 195410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 237049 # number of ReadExReq MSHR misses 195510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 237049 # number of ReadExReq MSHR misses 195610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12561 # number of demand (read+write) MSHR misses 195710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8869 # number of demand (read+write) MSHR misses 195810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1826671 # number of demand (read+write) MSHR misses 195910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1848101 # number of demand (read+write) MSHR misses 196010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12561 # number of overall MSHR misses 196110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8869 # number of overall MSHR misses 196210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1826671 # number of overall MSHR misses 196310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of overall MSHR misses 196410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2880403 # number of overall MSHR misses 196510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of ReadReq MSHR miss cycles 196610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 296231251 # number of ReadReq MSHR miss cycles 196710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 35897455818 # number of ReadReq MSHR miss cycles 196810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36560910324 # number of ReadReq MSHR miss cycles 196910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of HardPFReq MSHR miss cycles 197010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 41289088164 # number of HardPFReq MSHR miss cycles 197110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 7103244766 # number of WriteInvalidateReq MSHR miss cycles 197210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7103244766 # number of WriteInvalidateReq MSHR miss cycles 197310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2312644672 # number of UpgradeReq MSHR miss cycles 197410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2312644672 # number of UpgradeReq MSHR miss cycles 197510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2076231085 # number of SCUpgradeReq MSHR miss cycles 197610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2076231085 # number of SCUpgradeReq MSHR miss cycles 197710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 1461500 # number of SCUpgradeFailReq MSHR miss cycles 197810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1461500 # number of SCUpgradeFailReq MSHR miss cycles 197910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7288633813 # number of ReadExReq MSHR miss cycles 198010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7288633813 # number of ReadExReq MSHR miss cycles 198110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of demand (read+write) MSHR miss cycles 198210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles 198310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 43186089631 # number of demand (read+write) MSHR miss cycles 198410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles 198510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles 198610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles 198710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 43186089631 # number of overall MSHR miss cycles 198810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles 198910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles 199010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 514241998 # number of ReadReq MSHR uncacheable cycles 199110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 514241998 # number of ReadReq MSHR uncacheable cycles 199210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 574249999 # number of WriteReq MSHR uncacheable cycles 199310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 574249999 # number of WriteReq MSHR uncacheable cycles 199410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 1088491997 # number of overall MSHR uncacheable cycles 199510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1088491997 # number of overall MSHR uncacheable cycles 199610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for ReadReq accesses 199710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for ReadReq accesses 199810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.119790 # mshr miss rate for ReadReq accesses 199910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses 200010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 200110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 200210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 200310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 200410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.573995 # mshr miss rate for WriteInvalidateReq accesses 200510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses 200610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.639408 # mshr miss rate for UpgradeReq accesses 200710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses 200810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.784248 # mshr miss rate for SCUpgradeReq accesses 200910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses 201010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 201110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 201210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses 201310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses 201410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses 201510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses 201610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses 201710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses 201810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses 201910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses 202010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses 202110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 202210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses 202310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency 202410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency 202510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency 202610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency 202710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency 202810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency 202910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency 203010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency 203110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency 203210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency 203310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency 203410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency 203510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency 203610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency 203710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency 203810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency 203910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 204010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 204110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency 204210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency 204310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 204410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 204510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency 204610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency 204710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency 204810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 204910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 205010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 205110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 205210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 205310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 205410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 205510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution 205610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution 205710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution 205810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution 205910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution 206010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution 206110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 206210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution 206310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution 206410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution 206510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution 206610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution 206710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution 206810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 206910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution 207010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution 207110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) 207210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) 207310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) 207410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) 207510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) 207610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) 207710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) 207810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) 207910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) 208010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) 208110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) 208210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram 208310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram 208410628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram 208510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 208610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 208710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 208810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 208910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 209010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 209110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram 209210628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram 209310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 209410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 209510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 209610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram 209710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) 209810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 209910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) 210010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 210110628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) 210210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 210310628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) 210410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 210510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) 210610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 210710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) 210810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 210910628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40424 # Transaction distribution 211010628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40424 # Transaction distribution 211110628Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136766 # Transaction distribution 211210628Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30038 # Transaction distribution 211310585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 211410628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) 211510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 211610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 211710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 211810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 211910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 212010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 212110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 212210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 212310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 212410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 212510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 212610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 212710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 212810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 212910628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) 213010628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) 213110628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) 213210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 213310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 213410628Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) 213510628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) 213610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 213710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 213810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 213910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 214010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 214110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 214210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 214310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 214410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 214510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 214610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 214710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 214810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 214910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 215010628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) 215110628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) 215210628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) 215310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 215410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 215510628Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) 215610628Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) 215710585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 215810585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 215910585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 216010585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 216110585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 216210585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 216310585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 216410585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 216510585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 216610585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 216710585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 216810585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 216910585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 217010585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 217110585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 217210585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 217310585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 217410585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 217510585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 217610585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 217710585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 217810585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 217910585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 218010585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 218110585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 218210585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 218310585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 218410628Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) 218510585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 218610585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 218710585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 218810628Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) 218910585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 219010628Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) 219110585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 219210585Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 219310585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 219410628Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115597 # number of replacements 219510628Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use 219610585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 219710628Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. 219810585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 219910628Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. 220010628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor 220110628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor 220210628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy 220310628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy 220410628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy 220510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 220610585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 220710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 220810628Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040901 # Number of tag accesses 220910628Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040901 # Number of data accesses 221010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 221110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses 221210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8925 # number of ReadReq misses 221310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 221410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 221510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 221610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 221710585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 221810628Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses 221910628Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8928 # number of demand (read+write) misses 222010585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 222110628Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8888 # number of overall misses 222210628Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8928 # number of overall misses 222310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles 222410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles 222510628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles 222610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 222710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 222810628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles 222910628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles 223010628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles 223110628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles 223210628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles 223310628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles 223410628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles 223510628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles 223610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 223710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) 223810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) 223910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 224010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 224110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 224210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 224310585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 224410628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses 224510628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses 224610585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 224710628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses 224810628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses 224910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 225010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 225110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 225210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 225310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 225410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 225510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 225610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 225710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 225810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 225910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 226010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 226110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 226210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency 226310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency 226410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency 226510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 226610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 226710628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency 226810628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency 226910628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 227010628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 227110628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency 227210628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 227310628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 227410628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency 227510628Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked 227610585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 227710628Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked 227810585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 227910628Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked 228010585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 228110585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 228210585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 228310585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 228410585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 228510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 228610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses 228710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses 228810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 228910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 229010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 229110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 229210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 229310628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses 229410628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses 229510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 229610628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses 229710628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses 229810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles 229910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles 230010628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles 230110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 230210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 230310628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles 230410628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles 230510628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles 230610628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles 230710628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles 230810628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles 230910628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles 231010628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles 231110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 231210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 231310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 231410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 231510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 231610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 231710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 231810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 231910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 232010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 232110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 232210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 232310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 232410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency 232510628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency 232610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency 232710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 232810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 232910628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency 233010628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency 233110628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 233210628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 233310628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 233410628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 233510628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 233610628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 233710585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 233810628Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1473453 # number of replacements 233910628Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use 234010628Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. 234110628Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. 234210628Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. 234310628Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. 234410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor 234510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor 234610628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor 234710628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7682.914611 # Average occupied blocks per requestor 234810628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor 234910628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor 235010628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor 235110628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor 235210628Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor 235310628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy 235410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy 235510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy 235610628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy 235710628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy 235810628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy 235910628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy 236010628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy 236110628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy 236210628Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy 236310628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id 236410628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id 236510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id 236610628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id 236710628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id 236810628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id 236910628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 237010628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 237110628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 237210628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id 237310628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id 237410628Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id 237510628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id 237610628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 237710628Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id 237810628Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 65568567 # Number of tag accesses 237910628Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 65568567 # Number of data accesses 238010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits 238110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits 238210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 1051842 # number of ReadReq hits 238310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits 238410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits 238510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits 238610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 1187571 # number of ReadReq hits 238710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits 238810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits 238910628Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits 239010628Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2491671 # number of Writeback hits 239110628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu0.inst 125819 # number of WriteInvalidateReq hits 239210628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu1.inst 140505 # number of WriteInvalidateReq hits 239310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits 239410628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.inst 29765 # number of UpgradeReq hits 239510628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.inst 32403 # number of UpgradeReq hits 239610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits 239710628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.inst 5875 # number of SCUpgradeReq hits 239810628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.inst 6386 # number of SCUpgradeReq hits 239910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits 240010628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.inst 56397 # number of ReadExReq hits 240110628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.inst 53337 # number of ReadExReq hits 240210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits 240310628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits 240410628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits 240510628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 1108239 # number of demand (read+write) hits 240610628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits 240710628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits 240810628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits 240910628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 1240908 # number of demand (read+write) hits 241010628Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits 241110628Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3424248 # number of demand (read+write) hits 241210628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits 241310628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits 241410628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 1108239 # number of overall hits 241510628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits 241610628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits 241710628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits 241810628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 1240908 # number of overall hits 241910628Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits 242010628Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3424248 # number of overall hits 242110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses 242210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses 242310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 169093 # number of ReadReq misses 242410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses 242510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses 242610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses 242710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 162223 # number of ReadReq misses 242810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses 242910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 870286 # number of ReadReq misses 243010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu0.inst 435530 # number of WriteInvalidateReq misses 243110628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu1.inst 123517 # number of WriteInvalidateReq misses 243210628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses 243310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.inst 44959 # number of UpgradeReq misses 243410628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.inst 45474 # number of UpgradeReq misses 243510628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses 243610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.inst 8261 # number of SCUpgradeReq misses 243710628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.inst 9038 # number of SCUpgradeReq misses 243810628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses 243910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.inst 76639 # number of ReadExReq misses 244010628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.inst 55158 # number of ReadExReq misses 244110628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses 244210628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses 244310628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses 244410628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 245732 # number of demand (read+write) misses 244510628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses 244610628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses 244710628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses 244810628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 217381 # number of demand (read+write) misses 244910628Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses 245010628Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1002083 # number of demand (read+write) misses 245110628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses 245210628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses 245310628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 245732 # number of overall misses 245410628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses 245510628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses 245610628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses 245710628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 217381 # number of overall misses 245810628Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses 245910628Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1002083 # number of overall misses 246010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles 246110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles 246210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 13556032080 # number of ReadReq miss cycles 246310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles 246410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles 246510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles 246610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 12762094450 # number of ReadReq miss cycles 246710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles 246810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles 246910628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 36612963 # number of WriteInvalidateReq miss cycles 247010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 35758482 # number of WriteInvalidateReq miss cycles 247110628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles 247210628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.inst 213542030 # number of UpgradeReq miss cycles 247310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.inst 216684315 # number of UpgradeReq miss cycles 247410628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles 247510628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.inst 36699987 # number of SCUpgradeReq miss cycles 247610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.inst 41305269 # number of SCUpgradeReq miss cycles 247710628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles 247810628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.inst 6278532917 # number of ReadExReq miss cycles 247910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.inst 4207751582 # number of ReadExReq miss cycles 248010628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles 248110628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles 248210628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles 248310628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 19834564997 # number of demand (read+write) miss cycles 248410628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles 248510628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles 248610628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles 248710628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 16969846032 # number of demand (read+write) miss cycles 248810628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles 248910628Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles 249010628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles 249110628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles 249210628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 19834564997 # number of overall miss cycles 249310628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles 249410628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles 249510628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles 249610628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 16969846032 # number of overall miss cycles 249710628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles 249810628Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 106467817356 # number of overall miss cycles 249910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 8395 # number of ReadReq accesses(hits+misses) 250010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 6043 # number of ReadReq accesses(hits+misses) 250110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 1220935 # number of ReadReq accesses(hits+misses) 250210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 796553 # number of ReadReq accesses(hits+misses) 250310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 9295 # number of ReadReq accesses(hits+misses) 250410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 6808 # number of ReadReq accesses(hits+misses) 250510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 1349794 # number of ReadReq accesses(hits+misses) 250610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 786977 # number of ReadReq accesses(hits+misses) 250710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 4184800 # number of ReadReq accesses(hits+misses) 250810628Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2491671 # number of Writeback accesses(hits+misses) 250910628Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2491671 # number of Writeback accesses(hits+misses) 251010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu0.inst 561349 # number of WriteInvalidateReq accesses(hits+misses) 251110628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu1.inst 264022 # number of WriteInvalidateReq accesses(hits+misses) 251210628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) 251310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.inst 74724 # number of UpgradeReq accesses(hits+misses) 251410628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.inst 77877 # number of UpgradeReq accesses(hits+misses) 251510628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) 251610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.inst 14136 # number of SCUpgradeReq accesses(hits+misses) 251710628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.inst 15424 # number of SCUpgradeReq accesses(hits+misses) 251810628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) 251910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.inst 133036 # number of ReadExReq accesses(hits+misses) 252010628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.inst 108495 # number of ReadExReq accesses(hits+misses) 252110628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 241531 # number of ReadExReq accesses(hits+misses) 252210628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8395 # number of demand (read+write) accesses 252310628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6043 # number of demand (read+write) accesses 252410628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 1353971 # number of demand (read+write) accesses 252510628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 796553 # number of demand (read+write) accesses 252610628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9295 # number of demand (read+write) accesses 252710628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6808 # number of demand (read+write) accesses 252810628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 1458289 # number of demand (read+write) accesses 252910628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 786977 # number of demand (read+write) accesses 253010628Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4426331 # number of demand (read+write) accesses 253110628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8395 # number of overall (read+write) accesses 253210628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6043 # number of overall (read+write) accesses 253310628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 1353971 # number of overall (read+write) accesses 253410628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 796553 # number of overall (read+write) accesses 253510628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9295 # number of overall (read+write) accesses 253610628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6808 # number of overall (read+write) accesses 253710628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 1458289 # number of overall (read+write) accesses 253810628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 786977 # number of overall (read+write) accesses 253910628Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4426331 # number of overall (read+write) accesses 254010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for ReadReq accesses 254110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.215290 # miss rate for ReadReq accesses 254210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.138495 # miss rate for ReadReq accesses 254310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for ReadReq accesses 254410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for ReadReq accesses 254510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.339160 # miss rate for ReadReq accesses 254610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.120184 # miss rate for ReadReq accesses 254710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for ReadReq accesses 254810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.207964 # miss rate for ReadReq accesses 254910628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.775863 # miss rate for WriteInvalidateReq accesses 255010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.467828 # miss rate for WriteInvalidateReq accesses 255110628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.677328 # miss rate for WriteInvalidateReq accesses 255210628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.inst 0.601667 # miss rate for UpgradeReq accesses 255310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.inst 0.583921 # miss rate for UpgradeReq accesses 255410628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.592611 # miss rate for UpgradeReq accesses 255510628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.584394 # miss rate for SCUpgradeReq accesses 255610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.585970 # miss rate for SCUpgradeReq accesses 255710628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.585217 # miss rate for SCUpgradeReq accesses 255810628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.inst 0.576077 # miss rate for ReadExReq accesses 255910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.inst 0.508392 # miss rate for ReadExReq accesses 256010628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.545673 # miss rate for ReadExReq accesses 256110628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for demand accesses 256210628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.215290 # miss rate for demand accesses 256310628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.181490 # miss rate for demand accesses 256410628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for demand accesses 256510628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for demand accesses 256610628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.339160 # miss rate for demand accesses 256710628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.149066 # miss rate for demand accesses 256810628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for demand accesses 256910628Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.226391 # miss rate for demand accesses 257010628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for overall accesses 257110628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.215290 # miss rate for overall accesses 257210628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.181490 # miss rate for overall accesses 257310628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for overall accesses 257410628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for overall accesses 257510628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.339160 # miss rate for overall accesses 257610628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.149066 # miss rate for overall accesses 257710628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for overall accesses 257810628Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.226391 # miss rate for overall accesses 257910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average ReadReq miss latency 258010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191 # average ReadReq miss latency 258110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 80169.090855 # average ReadReq miss latency 258210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average ReadReq miss latency 258310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average ReadReq miss latency 258410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722 # average ReadReq miss latency 258510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 78670.068054 # average ReadReq miss latency 258610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average ReadReq miss latency 258710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 110287.345605 # average ReadReq miss latency 258810628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 84.065307 # average WriteInvalidateReq miss latency 258910628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 289.502514 # average WriteInvalidateReq miss latency 259010628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency 259110628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4749.705954 # average UpgradeReq miss latency 259210628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4765.015503 # average UpgradeReq miss latency 259310628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 4757.404321 # average UpgradeReq miss latency 259410628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 4442.559860 # average SCUpgradeReq miss latency 259510628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4570.178026 # average SCUpgradeReq miss latency 259610628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 4509.234985 # average SCUpgradeReq miss latency 259710628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301 # average ReadExReq miss latency 259810628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.inst 76285.426992 # average ReadExReq miss latency 259910628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 79563.908883 # average ReadExReq miss latency 260010628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency 260110628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency 260210628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency 260310628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency 260410628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency 260510628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency 260610628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency 260710628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency 260810628Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 106246.505884 # average overall miss latency 260910628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency 261010628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency 261110628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency 261210628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency 261310628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency 261410628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency 261510628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency 261610628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency 261710628Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 106246.505884 # average overall miss latency 261810628Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 5735 # number of cycles access was blocked 261910515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 262010628Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 156 # number of cycles access was blocked 262110515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 262210628Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 36.762821 # average number of cycles each access was blocked 262310515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262410515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 262510515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 262610628Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1116216 # number of writebacks 262710628Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1116216 # number of writebacks 262810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 210 # number of ReadReq MSHR hits 262910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 177 # number of ReadReq MSHR hits 263010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::total 387 # number of ReadReq MSHR hits 263110628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 210 # number of demand (read+write) MSHR hits 263210628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 177 # number of demand (read+write) MSHR hits 263310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits 263410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 210 # number of overall MSHR hits 263510628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 177 # number of overall MSHR hits 263610628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 387 # number of overall MSHR hits 263710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1664 # number of ReadReq MSHR misses 263810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1301 # number of ReadReq MSHR misses 263910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 168883 # number of ReadReq MSHR misses 264010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq MSHR misses 264110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2478 # number of ReadReq MSHR misses 264210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2309 # number of ReadReq MSHR misses 264310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 162046 # number of ReadReq MSHR misses 264410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq MSHR misses 264510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 869899 # number of ReadReq MSHR misses 264610628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 435530 # number of WriteInvalidateReq MSHR misses 264710628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 123517 # number of WriteInvalidateReq MSHR misses 264810628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::total 559047 # number of WriteInvalidateReq MSHR misses 264910628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.inst 44959 # number of UpgradeReq MSHR misses 265010628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.inst 45474 # number of UpgradeReq MSHR misses 265110628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 90433 # number of UpgradeReq MSHR misses 265210628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 8261 # number of SCUpgradeReq MSHR misses 265310628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9038 # number of SCUpgradeReq MSHR misses 265410628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 17299 # number of SCUpgradeReq MSHR misses 265510628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.inst 76639 # number of ReadExReq MSHR misses 265610628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.inst 55158 # number of ReadExReq MSHR misses 265710628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 131797 # number of ReadExReq MSHR misses 265810628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1664 # number of demand (read+write) MSHR misses 265910628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1301 # number of demand (read+write) MSHR misses 266010628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 245522 # number of demand (read+write) MSHR misses 266110628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) MSHR misses 266210628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2478 # number of demand (read+write) MSHR misses 266310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2309 # number of demand (read+write) MSHR misses 266410628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 217204 # number of demand (read+write) MSHR misses 266510628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) MSHR misses 266610628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 1001696 # number of demand (read+write) MSHR misses 266710628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1664 # number of overall MSHR misses 266810628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1301 # number of overall MSHR misses 266910628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 245522 # number of overall MSHR misses 267010628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of overall MSHR misses 267110628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2478 # number of overall MSHR misses 267210628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2309 # number of overall MSHR misses 267310628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 217204 # number of overall MSHR misses 267410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of overall MSHR misses 267510628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 1001696 # number of overall MSHR misses 267610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of ReadReq MSHR miss cycles 267710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 94777748 # number of ReadReq MSHR miss cycles 267810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11415126178 # number of ReadReq MSHR miss cycles 267910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of ReadReq MSHR miss cycles 268010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of ReadReq MSHR miss cycles 268110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 156241500 # number of ReadReq MSHR miss cycles 268210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 10713554460 # number of ReadReq MSHR miss cycles 268310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of ReadReq MSHR miss cycles 268410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::total 85169385965 # number of ReadReq MSHR miss cycles 268510628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 9786055012 # number of WriteInvalidateReq MSHR miss cycles 268610628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 2515639470 # number of WriteInvalidateReq MSHR miss cycles 268710628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_latency::total 12301694482 # number of WriteInvalidateReq MSHR miss cycles 268810628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 455524094 # number of UpgradeReq MSHR miss cycles 268910628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 460871563 # number of UpgradeReq MSHR miss cycles 269010628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 916395657 # number of UpgradeReq MSHR miss cycles 269110628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 84887682 # number of SCUpgradeReq MSHR miss cycles 269210628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92374949 # number of SCUpgradeReq MSHR miss cycles 269310628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 177262631 # number of SCUpgradeReq MSHR miss cycles 269410628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5315349505 # number of ReadExReq MSHR miss cycles 269510628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3512186842 # number of ReadExReq MSHR miss cycles 269610628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 8827536347 # number of ReadExReq MSHR miss cycles 269710628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of demand (read+write) MSHR miss cycles 269810628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94777748 # number of demand (read+write) MSHR miss cycles 269910628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 16730475683 # number of demand (read+write) MSHR miss cycles 270010628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of demand (read+write) MSHR miss cycles 270110628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of demand (read+write) MSHR miss cycles 270210628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 156241500 # number of demand (read+write) MSHR miss cycles 270310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 14225741302 # number of demand (read+write) MSHR miss cycles 270410628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of demand (read+write) MSHR miss cycles 270510628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 93996922312 # number of demand (read+write) MSHR miss cycles 270610628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of overall MSHR miss cycles 270710628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles 270810628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 16730475683 # number of overall MSHR miss cycles 270910628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles 271010628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles 271110628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles 271210628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 14225741302 # number of overall MSHR miss cycles 271310628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles 271410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles 271510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7718194748 # number of ReadReq MSHR uncacheable cycles 271610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 418305498 # number of ReadReq MSHR uncacheable cycles 271710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles 271810628Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4773990997 # number of WriteReq MSHR uncacheable cycles 271910628Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 484709502 # number of WriteReq MSHR uncacheable cycles 272010628Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles 272110628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles 272210628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles 272310628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles 272410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses 272510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses 272610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses 272710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses 272810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses 272910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses 273010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses 273110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses 273210628Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses 273310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses 273410628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses 273510628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses 273610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses 273710628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses 273810628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses 273910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses 274010628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses 274110628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses 274210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses 274310628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses 274410628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses 274510628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses 274610628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses 274710628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses 274810628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses 274910628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses 275010628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses 275110628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses 275210628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses 275310628Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses 275410628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses 275510628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses 275610628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses 275710628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses 275810628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses 275910628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses 276010628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses 276110628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses 276210628Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses 276310628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency 276410628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency 276510628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency 276610628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency 276710628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency 276810628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency 276910628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency 277010628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency 277110628Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency 277210628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency 277310628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency 277410628Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency 277510628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency 277610628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency 277710628Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency 277810628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency 277910628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency 278010628Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency 278110628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency 278210628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency 278310628Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency 278410628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 278510628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 278610628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency 278710628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 278810628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 278910628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 279010628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency 279110628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 279210628Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 279310628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 279410628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 279510628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency 279610628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 279710628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 279810628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 279910628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency 280010628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 280110628Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 280210515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 280310515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 280410515SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 280510515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 280610515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 280710515SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 280810515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 280910515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 281010515SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 281110515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 281210628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 969598 # Transaction distribution 281310628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 969598 # Transaction distribution 281410628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38347 # Transaction distribution 281510628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38347 # Transaction distribution 281610628Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1222910 # Transaction distribution 281710628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution 281810628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution 281910628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 426453 # Transaction distribution 282010628Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution 282110628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 115017 # Transaction distribution 282210628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 144468 # Transaction distribution 282310628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 127604 # Transaction distribution 282410628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) 282510585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 282610628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) 282710628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) 282810628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) 282910628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) 283010628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) 283110628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) 283210628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) 283310585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 283410628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) 283510628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) 283610628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) 283710628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) 283810628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) 283910628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) 284010628Sandreas.hansson@arm.comsystem.membus.snoops 617229 # Total snoops (count) 284110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3621307 # Request fanout histogram 284210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 284310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 284410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 284510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 284610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram 284710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 284810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 284910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 285010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 285110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3621307 # Request fanout histogram 285210628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) 285310585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 285410585Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) 285510585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 285610628Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) 285710585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 285810628Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) 285910585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 286010628Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) 286110585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 286210628Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) 286310585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 286410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 286510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 286610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 286710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 286810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 286910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 287010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 287110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 287210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 287310515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 287410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 287510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 287610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 287710515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 287810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 287910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 288010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 288110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 288210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 288310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 288410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 288510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 288610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 288710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 288810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 288910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 289010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 289110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 289210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 289310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 289410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 289510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 289610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 289710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 289810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 289910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 290010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 290110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 290210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 290310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 290410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 290510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 290610628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution 290710628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution 290810628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution 290910628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution 291010628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution 291110628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution 291210628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution 291310628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution 291410628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution 291510628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution 291610628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 291710628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 291810628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution 291910628Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution 292010628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) 292110628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) 292210628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) 292310628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) 292410628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) 292510628Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) 292610628Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1616950 # Total snoops (count) 292710628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram 292810628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram 292910628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram 293010515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 293110515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 293210628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram 293310628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram 293410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 293510515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 293610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 293710628Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram 293810628Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) 293910515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 294010628Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) 294110515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 294210628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) 294310515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 294410628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) 294510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 294610515SAli.Saidi@ARM.com 294710515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 2948