stats.txt revision 10628
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355615 # Number of seconds simulated 4sim_ticks 47355615197500 # Number of ticks simulated 5final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 178863 # Simulator instruction rate (inst/s) 8host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9462962325 # Simulator tick rate (ticks/s) 10host_mem_usage 759628 # Number of bytes of host memory used 11host_seconds 5004.31 # Real time elapsed on the host 12sim_insts 895084962 # Number of instructions simulated 13sim_ops 1052703090 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory 25system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory 32system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 1055887 # Number of read requests accepted 76system.physmem.writeReqs 1888199 # Number of write requests accepted 77system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue 81system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 58784 # Per bank write bursts 88system.physmem.perBankRdBursts::1 68771 # Per bank write bursts 89system.physmem.perBankRdBursts::2 59130 # Per bank write bursts 90system.physmem.perBankRdBursts::3 67531 # Per bank write bursts 91system.physmem.perBankRdBursts::4 66855 # Per bank write bursts 92system.physmem.perBankRdBursts::5 75133 # Per bank write bursts 93system.physmem.perBankRdBursts::6 65903 # Per bank write bursts 94system.physmem.perBankRdBursts::7 67407 # Per bank write bursts 95system.physmem.perBankRdBursts::8 54196 # Per bank write bursts 96system.physmem.perBankRdBursts::9 110706 # Per bank write bursts 97system.physmem.perBankRdBursts::10 54461 # Per bank write bursts 98system.physmem.perBankRdBursts::11 64104 # Per bank write bursts 99system.physmem.perBankRdBursts::12 57097 # Per bank write bursts 100system.physmem.perBankRdBursts::13 66166 # Per bank write bursts 101system.physmem.perBankRdBursts::14 60751 # Per bank write bursts 102system.physmem.perBankRdBursts::15 58597 # Per bank write bursts 103system.physmem.perBankWrBursts::0 116651 # Per bank write bursts 104system.physmem.perBankWrBursts::1 125865 # Per bank write bursts 105system.physmem.perBankWrBursts::2 118664 # Per bank write bursts 106system.physmem.perBankWrBursts::3 124773 # Per bank write bursts 107system.physmem.perBankWrBursts::4 121001 # Per bank write bursts 108system.physmem.perBankWrBursts::5 125597 # Per bank write bursts 109system.physmem.perBankWrBursts::6 113710 # Per bank write bursts 110system.physmem.perBankWrBursts::7 116980 # Per bank write bursts 111system.physmem.perBankWrBursts::8 110183 # Per bank write bursts 112system.physmem.perBankWrBursts::9 114411 # Per bank write bursts 113system.physmem.perBankWrBursts::10 109841 # Per bank write bursts 114system.physmem.perBankWrBursts::11 116847 # Per bank write bursts 115system.physmem.perBankWrBursts::12 116927 # Per bank write bursts 116system.physmem.perBankWrBursts::13 118874 # Per bank write bursts 117system.physmem.perBankWrBursts::14 112844 # Per bank write bursts 118system.physmem.perBankWrBursts::15 118210 # Per bank write bursts 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 121system.physmem.totGap 47355613259000 # Total gap between requests 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 0 # Read request sizes (log2) 125system.physmem.readPktSize::3 37 # Read request sizes (log2) 126system.physmem.readPktSize::4 5 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) 128system.physmem.readPktSize::6 1055845 # Read request sizes (log2) 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 2 # Write request sizes (log2) 132system.physmem.writePktSize::3 2601 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) 135system.physmem.writePktSize::6 1885596 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads 307system.physmem.totQLat 39480003252 # Total ticks spent queuing 308system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM 309system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers 310system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst 311system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 312system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst 313system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s 314system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s 315system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s 316system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s 317system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 318system.physmem.busUtil 0.03 # Data bus utilization in percentage 319system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 320system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 321system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 322system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing 323system.physmem.readRowHits 797783 # Number of row buffer hits during reads 324system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes 325system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 326system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes 327system.physmem.avgGap 16084996.59 # Average gap between requests 328system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined 329system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) 330system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) 331system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) 332system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) 333system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 334system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) 335system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) 336system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) 337system.physmem_0.averagePower 668.764772 # Core power per rank (mW) 338system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states 339system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states 340system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 341system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states 342system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 343system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) 344system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) 345system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) 346system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) 347system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) 348system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) 349system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) 350system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) 351system.physmem_1.averagePower 668.721243 # Core power per rank (mW) 352system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states 353system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states 354system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 355system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states 356system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 357system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 363system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 366system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 381system.cpu0.branchPred.lookups 131272413 # Number of BP lookups 382system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted 383system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect 384system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups 385system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits 386system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 387system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage 388system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. 389system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. 390system.cpu_clk_domain.clock 500 # Clock period in ticks 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 420system.cpu0.dtb.walker.walks 271399 # Table walker walks requested 421system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors 422system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.inst_hits 0 # ITB inst hits 461system.cpu0.dtb.inst_misses 0 # ITB inst misses 462system.cpu0.dtb.read_hits 83830376 # DTB read hits 463system.cpu0.dtb.read_misses 224800 # DTB read misses 464system.cpu0.dtb.write_hits 74836136 # DTB write hits 465system.cpu0.dtb.write_misses 46599 # DTB write misses 466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 468system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 469system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 470system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB 471system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions 472system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch 473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions 475system.cpu0.dtb.read_accesses 84055176 # DTB read accesses 476system.cpu0.dtb.write_accesses 74882735 # DTB write accesses 477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 478system.cpu0.dtb.hits 158666512 # DTB hits 479system.cpu0.dtb.misses 271399 # DTB misses 480system.cpu0.dtb.accesses 158937911 # DTB accesses 481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 490system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 491system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 492system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 493system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 494system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 499system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 500system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 501system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 510system.cpu0.itb.walker.walks 59516 # Table walker walks requested 511system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors 512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate 514system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution 538system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution 539system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution 540system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated 541system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated 542system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated 543system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst 550system.cpu0.itb.inst_hits 234493726 # ITB inst hits 551system.cpu0.itb.inst_misses 59516 # ITB inst misses 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 558system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 559system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 560system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses 567system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses 568system.cpu0.itb.hits 234493726 # DTB hits 569system.cpu0.itb.misses 59516 # DTB misses 570system.cpu0.itb.accesses 234553242 # DTB accesses 571system.cpu0.numCycles 936626399 # number of cpu cycles simulated 572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 574system.cpu0.committedInsts 433367687 # Number of instructions committed 575system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed 576system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit 577system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching 578system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 579system.cpu0.cpi 2.161274 # CPI: cycles per instruction 580system.cpu0.ipc 0.462690 # IPC: instructions per cycle 581system.cpu0.kern.inst.arm 0 # number of arm instructions executed 582system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed 583system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked 584system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped 585system.cpu0.dcache.tags.replacements 5387052 # number of replacements 586system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use 587system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. 588system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. 589system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. 590system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. 591system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor 592system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy 593system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy 594system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 596system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 597system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 598system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 599system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses 600system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses 601system.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits 602system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits 603system.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits 604system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits 605system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 251432 # number of WriteInvalidateReq hits 606system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits 607system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1745310 # number of LoadLockedReq hits 608system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits 609system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1668274 # number of StoreCondReq hits 610system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits 611system.cpu0.dcache.demand_hits::cpu0.inst 146466768 # number of demand (read+write) hits 612system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits 613system.cpu0.dcache.overall_hits::cpu0.inst 146466768 # number of overall hits 614system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits 615system.cpu0.dcache.ReadReq_misses::cpu0.inst 3852692 # number of ReadReq misses 616system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses 617system.cpu0.dcache.WriteReq_misses::cpu0.inst 2255601 # number of WriteReq misses 618system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses 619system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 766100 # number of WriteInvalidateReq misses 620system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses 621system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 104059 # number of LoadLockedReq misses 622system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses 623system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 180014 # number of StoreCondReq misses 624system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses 625system.cpu0.dcache.demand_misses::cpu0.inst 6108293 # number of demand (read+write) misses 626system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses 627system.cpu0.dcache.overall_misses::cpu0.inst 6108293 # number of overall misses 628system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses 629system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54452724607 # number of ReadReq miss cycles 630system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 41906959422 # number of WriteReq miss cycles 632system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles 633system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 27296991314 # number of WriteInvalidateReq miss cycles 634system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles 635system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1502404735 # number of LoadLockedReq miss cycles 636system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles 637system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3769027814 # number of StoreCondReq miss cycles 638system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles 639system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2840500 # number of StoreCondFailReq miss cycles 640system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles 641system.cpu0.dcache.demand_miss_latency::cpu0.inst 96359684029 # number of demand (read+write) miss cycles 642system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles 643system.cpu0.dcache.overall_miss_latency::cpu0.inst 96359684029 # number of overall miss cycles 644system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles 645system.cpu0.dcache.ReadReq_accesses::cpu0.inst 80967470 # number of ReadReq accesses(hits+misses) 646system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) 647system.cpu0.dcache.WriteReq_accesses::cpu0.inst 71607591 # number of WriteReq accesses(hits+misses) 648system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) 649system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 1017532 # number of WriteInvalidateReq accesses(hits+misses) 650system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) 651system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1849369 # number of LoadLockedReq accesses(hits+misses) 652system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) 653system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1848288 # number of StoreCondReq accesses(hits+misses) 654system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) 655system.cpu0.dcache.demand_accesses::cpu0.inst 152575061 # number of demand (read+write) accesses 656system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses 657system.cpu0.dcache.overall_accesses::cpu0.inst 152575061 # number of overall (read+write) accesses 658system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses 659system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047583 # miss rate for ReadReq accesses 660system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses 661system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.031499 # miss rate for WriteReq accesses 662system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses 663system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.752900 # miss rate for WriteInvalidateReq accesses 664system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses 665system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.056267 # miss rate for LoadLockedReq accesses 666system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses 667system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.097395 # miss rate for StoreCondReq accesses 668system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses 669system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.040035 # miss rate for demand accesses 670system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses 671system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.040035 # miss rate for overall accesses 672system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses 673system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269 # average ReadReq miss latency 674system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency 675system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811 # average WriteReq miss latency 676system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency 677system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315 # average WriteInvalidateReq miss latency 678system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency 679system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582 # average LoadLockedReq miss latency 680system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency 681system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946 # average StoreCondReq miss latency 682system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency 683system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 684system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 685system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency 686system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency 687system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency 688system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency 689system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 690system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 691system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 693system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 694system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 695system.cpu0.dcache.fast_writes 0 # number of fast writes performed 696system.cpu0.dcache.cache_copies 0 # number of cache copies performed 697system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks 698system.cpu0.dcache.writebacks::total 3733142 # number of writebacks 699system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 361487 # number of ReadReq MSHR hits 700system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits 701system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 935411 # number of WriteReq MSHR hits 702system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits 703system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 100 # number of WriteInvalidateReq MSHR hits 704system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits 705system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 34 # number of LoadLockedReq MSHR hits 706system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits 707system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 67 # number of StoreCondReq MSHR hits 708system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 709system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1296898 # number of demand (read+write) MSHR hits 710system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits 711system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1296898 # number of overall MSHR hits 712system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits 713system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3491205 # number of ReadReq MSHR misses 714system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses 715system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1320190 # number of WriteReq MSHR misses 716system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses 717system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 766000 # number of WriteInvalidateReq MSHR misses 718system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses 719system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 104025 # number of LoadLockedReq MSHR misses 720system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses 721system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 179947 # number of StoreCondReq MSHR misses 722system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses 723system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4811395 # number of demand (read+write) MSHR misses 724system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses 725system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4811395 # number of overall MSHR misses 726system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses 727system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42113152704 # number of ReadReq MSHR miss cycles 728system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles 729system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 22270249828 # number of WriteReq MSHR miss cycles 730system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles 731system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 25755951436 # number of WriteInvalidateReq MSHR miss cycles 732system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles 733system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1293404753 # number of LoadLockedReq MSHR miss cycles 734system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles 735system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles 736system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles 737system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles 738system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles 739system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles 740system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles 741system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 64383402532 # number of overall MSHR miss cycles 742system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles 743system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5824362996 # number of ReadReq MSHR uncacheable cycles 744system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles 745system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5586865743 # number of WriteReq MSHR uncacheable cycles 746system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles 747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles 748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles 749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses 750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses 751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses 752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses 753system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses 754system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses 755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses 756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses 757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses 758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses 759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses 760system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses 761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses 762system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275 # average WriteReq mshr miss latency 766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency 767system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488 # average WriteInvalidateReq mshr miss latency 768system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency 769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency 770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency 771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency 772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency 773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 782system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 783system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 785system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu0.icache.tags.replacements 9463678 # number of replacements 787system.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use 788system.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. 789system.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. 790system.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. 791system.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. 792system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor 793system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy 794system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 795system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 796system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 797system.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 798system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 799system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 800system.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses 801system.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses 802system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits 803system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits 804system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits 805system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits 806system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits 807system.cpu0.icache.overall_hits::total 224826074 # number of overall hits 808system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses 809system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses 810system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses 811system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses 812system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses 813system.cpu0.icache.overall_misses::total 9464200 # number of overall misses 814system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles 815system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles 816system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles 817system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles 818system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles 819system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles 820system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) 821system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) 822system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses 823system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses 824system.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses 825system.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses 826system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses 827system.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses 828system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses 829system.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses 830system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses 831system.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses 832system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency 833system.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency 834system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 835system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency 836system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency 837system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency 838system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 844system.cpu0.icache.fast_writes 0 # number of fast writes performed 845system.cpu0.icache.cache_copies 0 # number of cache copies performed 846system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses 847system.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses 848system.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses 849system.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses 850system.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses 851system.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses 852system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles 853system.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles 854system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles 855system.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles 856system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles 857system.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles 859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles 860system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles 861system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles 862system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses 863system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses 865system.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses 866system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses 867system.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses 868system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency 870system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 872system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency 874system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 876system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 878system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 879system.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued 880system.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified 881system.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue 882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 884system.cpu0.l2cache.prefetcher.pfSpanPage 1270201 # number of prefetches not generated due to page crossing 885system.cpu0.l2cache.tags.replacements 2736028 # number of replacements 886system.cpu0.l2cache.tags.tagsinuse 16197.540138 # Cycle average of tags in use 887system.cpu0.l2cache.tags.total_refs 15248127 # Total number of references to valid blocks. 888system.cpu0.l2cache.tags.sampled_refs 2752162 # Sample count of references to valid blocks. 889system.cpu0.l2cache.tags.avg_refs 5.540418 # Average number of references to valid blocks. 890system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cycle when the warmup percentage was hit. 891system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor 892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor 893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor 894system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 9438.642805 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy 897system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy 898system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy 899system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.576089 # Average percentage of cache occupancy 900system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy 901system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id 903system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id 904system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13544 # Occupied blocks per task id 905system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 133 # Occupied blocks per task id 906system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 367 # Occupied blocks per task id 907system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1060 # Occupied blocks per task id 908system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 959 # Occupied blocks per task id 909system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 25 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 35 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id 918system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id 919system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id 920system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id 921system.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses 922system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses 923system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits 924system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits 925system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11610557 # number of ReadReq hits 926system.cpu0.l2cache.ReadReq_hits::total 12212111 # number of ReadReq hits 927system.cpu0.l2cache.Writeback_hits::writebacks 3733141 # number of Writeback hits 928system.cpu0.l2cache.Writeback_hits::total 3733141 # number of Writeback hits 929system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 193768 # number of WriteInvalidateReq hits 930system.cpu0.l2cache.WriteInvalidateReq_hits::total 193768 # number of WriteInvalidateReq hits 931system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 68627 # number of UpgradeReq hits 932system.cpu0.l2cache.UpgradeReq_hits::total 68627 # number of UpgradeReq hits 933system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 33597 # number of SCUpgradeReq hits 934system.cpu0.l2cache.SCUpgradeReq_hits::total 33597 # number of SCUpgradeReq hits 935system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 855771 # number of ReadExReq hits 936system.cpu0.l2cache.ReadExReq_hits::total 855771 # number of ReadExReq hits 937system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 463342 # number of demand (read+write) hits 938system.cpu0.l2cache.demand_hits::cpu0.itb.walker 138212 # number of demand (read+write) hits 939system.cpu0.l2cache.demand_hits::cpu0.inst 12466328 # number of demand (read+write) hits 940system.cpu0.l2cache.demand_hits::total 13067882 # number of demand (read+write) hits 941system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 463342 # number of overall hits 942system.cpu0.l2cache.overall_hits::cpu0.itb.walker 138212 # number of overall hits 943system.cpu0.l2cache.overall_hits::cpu0.inst 12466328 # number of overall hits 944system.cpu0.l2cache.overall_hits::total 13067882 # number of overall hits 945system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11843 # number of ReadReq misses 946system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8238 # number of ReadReq misses 947system.cpu0.l2cache.ReadReq_misses::cpu0.inst 1448613 # number of ReadReq misses 948system.cpu0.l2cache.ReadReq_misses::total 1468694 # number of ReadReq misses 949system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 570757 # number of WriteInvalidateReq misses 950system.cpu0.l2cache.WriteInvalidateReq_misses::total 570757 # number of WriteInvalidateReq misses 951system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 126856 # number of UpgradeReq misses 952system.cpu0.l2cache.UpgradeReq_misses::total 126856 # number of UpgradeReq misses 953system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 146340 # number of SCUpgradeReq misses 954system.cpu0.l2cache.SCUpgradeReq_misses::total 146340 # number of SCUpgradeReq misses 955system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 10 # number of SCUpgradeFailReq misses 956system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 957system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 270676 # number of ReadExReq misses 958system.cpu0.l2cache.ReadExReq_misses::total 270676 # number of ReadExReq misses 959system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11843 # number of demand (read+write) misses 960system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8238 # number of demand (read+write) misses 961system.cpu0.l2cache.demand_misses::cpu0.inst 1719289 # number of demand (read+write) misses 962system.cpu0.l2cache.demand_misses::total 1739370 # number of demand (read+write) misses 963system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11843 # number of overall misses 964system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8238 # number of overall misses 965system.cpu0.l2cache.overall_misses::cpu0.inst 1719289 # number of overall misses 966system.cpu0.l2cache.overall_misses::total 1739370 # number of overall misses 967system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 383176229 # number of ReadReq miss cycles 968system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 279750987 # number of ReadReq miss cycles 969system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 44923505132 # number of ReadReq miss cycles 970system.cpu0.l2cache.ReadReq_miss_latency::total 45586432348 # number of ReadReq miss cycles 971system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 223595615 # number of WriteInvalidateReq miss cycles 972system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 223595615 # number of WriteInvalidateReq miss cycles 973system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2548596996 # number of UpgradeReq miss cycles 974system.cpu0.l2cache.UpgradeReq_miss_latency::total 2548596996 # number of UpgradeReq miss cycles 975system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2948593769 # number of SCUpgradeReq miss cycles 976system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2948593769 # number of SCUpgradeReq miss cycles 977system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2234000 # number of SCUpgradeFailReq miss cycles 978system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2234000 # number of SCUpgradeFailReq miss cycles 979system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 12372799630 # number of ReadExReq miss cycles 980system.cpu0.l2cache.ReadExReq_miss_latency::total 12372799630 # number of ReadExReq miss cycles 981system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 383176229 # number of demand (read+write) miss cycles 982system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 279750987 # number of demand (read+write) miss cycles 983system.cpu0.l2cache.demand_miss_latency::cpu0.inst 57296304762 # number of demand (read+write) miss cycles 984system.cpu0.l2cache.demand_miss_latency::total 57959231978 # number of demand (read+write) miss cycles 985system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 383176229 # number of overall miss cycles 986system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 279750987 # number of overall miss cycles 987system.cpu0.l2cache.overall_miss_latency::cpu0.inst 57296304762 # number of overall miss cycles 988system.cpu0.l2cache.overall_miss_latency::total 57959231978 # number of overall miss cycles 989system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 475185 # number of ReadReq accesses(hits+misses) 990system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146450 # number of ReadReq accesses(hits+misses) 991system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 13059170 # number of ReadReq accesses(hits+misses) 992system.cpu0.l2cache.ReadReq_accesses::total 13680805 # number of ReadReq accesses(hits+misses) 993system.cpu0.l2cache.Writeback_accesses::writebacks 3733141 # number of Writeback accesses(hits+misses) 994system.cpu0.l2cache.Writeback_accesses::total 3733141 # number of Writeback accesses(hits+misses) 995system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 764525 # number of WriteInvalidateReq accesses(hits+misses) 996system.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) 997system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 195483 # number of UpgradeReq accesses(hits+misses) 998system.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) 999system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 179937 # number of SCUpgradeReq accesses(hits+misses) 1000system.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) 1001system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 10 # number of SCUpgradeFailReq accesses(hits+misses) 1002system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 1003system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1126447 # number of ReadExReq accesses(hits+misses) 1004system.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) 1005system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses 1006system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses 1007system.cpu0.l2cache.demand_accesses::cpu0.inst 14185617 # number of demand (read+write) accesses 1008system.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses 1009system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses 1010system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses 1011system.cpu0.l2cache.overall_accesses::cpu0.inst 14185617 # number of overall (read+write) accesses 1012system.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses 1013system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses 1014system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # miss rate for ReadReq accesses 1015system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110927 # miss rate for ReadReq accesses 1016system.cpu0.l2cache.ReadReq_miss_rate::total 0.107354 # miss rate for ReadReq accesses 1017system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.746551 # miss rate for WriteInvalidateReq accesses 1018system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses 1019system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.648936 # miss rate for UpgradeReq accesses 1020system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses 1021system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813285 # miss rate for SCUpgradeReq accesses 1022system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses 1023system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 1024system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1025system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.240292 # miss rate for ReadExReq accesses 1026system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240292 # miss rate for ReadExReq accesses 1027system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for demand accesses 1028system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056251 # miss rate for demand accesses 1029system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.121199 # miss rate for demand accesses 1030system.cpu0.l2cache.demand_miss_rate::total 0.117467 # miss rate for demand accesses 1031system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for overall accesses 1032system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056251 # miss rate for overall accesses 1033system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.121199 # miss rate for overall accesses 1034system.cpu0.l2cache.overall_miss_rate::total 0.117467 # miss rate for overall accesses 1035system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average ReadReq miss latency 1036system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880 # average ReadReq miss latency 1037system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31011.391677 # average ReadReq miss latency 1038system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31038.754395 # average ReadReq miss latency 1039system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 391.752734 # average WriteInvalidateReq miss latency 1040system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 391.752734 # average WriteInvalidateReq miss latency 1041system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20090.472630 # average UpgradeReq miss latency 1042system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20090.472630 # average UpgradeReq miss latency 1043system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20148.925577 # average SCUpgradeReq miss latency 1044system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20148.925577 # average SCUpgradeReq miss latency 1045system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 223400 # average SCUpgradeFailReq miss latency 1046system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223400 # average SCUpgradeFailReq miss latency 1047system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 45710.737672 # average ReadExReq miss latency 1048system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45710.737672 # average ReadExReq miss latency 1049system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency 1050system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency 1051system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency 1052system.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286 # average overall miss latency 1053system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency 1054system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency 1055system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency 1056system.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286 # average overall miss latency 1057system.cpu0.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked 1058system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1059system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1060system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1061system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked 1062system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1063system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1064system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1065system.cpu0.l2cache.writebacks::writebacks 1399370 # number of writebacks 1066system.cpu0.l2cache.writebacks::total 1399370 # number of writebacks 1067system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1068system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3403 # number of ReadReq MSHR hits 1069system.cpu0.l2cache.ReadReq_mshr_hits::total 3404 # number of ReadReq MSHR hits 1070system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 156 # number of WriteInvalidateReq MSHR hits 1071system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 156 # number of WriteInvalidateReq MSHR hits 1072system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9658 # number of ReadExReq MSHR hits 1073system.cpu0.l2cache.ReadExReq_mshr_hits::total 9658 # number of ReadExReq MSHR hits 1074system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1075system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 13061 # number of demand (read+write) MSHR hits 1076system.cpu0.l2cache.demand_mshr_hits::total 13062 # number of demand (read+write) MSHR hits 1077system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1078system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 13061 # number of overall MSHR hits 1079system.cpu0.l2cache.overall_mshr_hits::total 13062 # number of overall MSHR hits 1080system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11843 # number of ReadReq MSHR misses 1081system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses 1082system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 1445210 # number of ReadReq MSHR misses 1083system.cpu0.l2cache.ReadReq_mshr_misses::total 1465290 # number of ReadReq MSHR misses 1084system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of HardPFReq MSHR misses 1085system.cpu0.l2cache.HardPFReq_mshr_misses::total 1036981 # number of HardPFReq MSHR misses 1086system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 570601 # number of WriteInvalidateReq MSHR misses 1087system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570601 # number of WriteInvalidateReq MSHR misses 1088system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 126856 # number of UpgradeReq MSHR misses 1089system.cpu0.l2cache.UpgradeReq_mshr_misses::total 126856 # number of UpgradeReq MSHR misses 1090system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 146340 # number of SCUpgradeReq MSHR misses 1091system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 146340 # number of SCUpgradeReq MSHR misses 1092system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 10 # number of SCUpgradeFailReq MSHR misses 1093system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 1094system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 261018 # number of ReadExReq MSHR misses 1095system.cpu0.l2cache.ReadExReq_mshr_misses::total 261018 # number of ReadExReq MSHR misses 1096system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11843 # number of demand (read+write) MSHR misses 1097system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses 1098system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1706228 # number of demand (read+write) MSHR misses 1099system.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses 1100system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses 1101system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses 1102system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1706228 # number of overall MSHR misses 1103system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses 1104system.cpu0.l2cache.overall_mshr_misses::total 2763289 # number of overall MSHR misses 1105system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of ReadReq MSHR miss cycles 1106system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 221721501 # number of ReadReq MSHR miss cycles 1107system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 34355781249 # number of ReadReq MSHR miss cycles 1108system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 34877337999 # number of ReadReq MSHR miss cycles 1109system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of HardPFReq MSHR miss cycles 1110system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47311809533 # number of HardPFReq MSHR miss cycles 1111system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 20034543782 # number of WriteInvalidateReq MSHR miss cycles 1112system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles 1113system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2151275072 # number of UpgradeReq MSHR miss cycles 1114system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2151275072 # number of UpgradeReq MSHR miss cycles 1115system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1993779824 # number of SCUpgradeReq MSHR miss cycles 1116system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1993779824 # number of SCUpgradeReq MSHR miss cycles 1117system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1835000 # number of SCUpgradeFailReq MSHR miss cycles 1118system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1835000 # number of SCUpgradeFailReq MSHR miss cycles 1119system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 9532664011 # number of ReadExReq MSHR miss cycles 1120system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9532664011 # number of ReadExReq MSHR miss cycles 1121system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of demand (read+write) MSHR miss cycles 1122system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 221721501 # number of demand (read+write) MSHR miss cycles 1123system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 43888445260 # number of demand (read+write) MSHR miss cycles 1124system.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles 1127system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 43888445260 # number of overall MSHR miss cycles 1128system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles 1129system.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles 1130system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9672004742 # number of ReadReq MSHR uncacheable cycles 1131system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles 1132system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles 1133system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles 1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles 1135system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles 1136system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses 1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses 1138system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses 1139system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses 1140system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1141system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1142system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses 1143system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses 1144system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses 1145system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1150system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses 1151system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses 1152system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses 1153system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses 1157system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses 1158system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses 1161system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency 1162system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency 1163system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency 1164system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency 1165system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency 1166system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency 1167system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency 1168system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency 1169system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency 1171system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency 1173system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency 1175system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency 1176system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency 1177system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 1178system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 1179system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency 1180system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency 1181system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency 1182system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency 1183system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency 1184system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency 1185system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency 1186system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1187system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1188system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1189system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1190system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1191system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1192system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1193system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution 1194system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution 1195system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution 1196system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution 1197system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution 1198system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution 1209system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) 1210system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) 1211system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) 1212system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) 1220system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram 1221system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram 1222system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram 1223system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1224system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1225system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1226system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1228system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1229system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram 1230system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram 1231system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1232system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1233system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1234system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram 1235system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) 1236system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1237system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) 1238system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1239system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) 1240system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1241system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) 1242system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1243system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) 1244system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1245system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) 1246system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1247system.cpu1.branchPred.lookups 141025153 # Number of BP lookups 1248system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted 1249system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect 1250system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups 1251system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits 1252system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1253system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage 1254system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. 1255system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. 1256system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1257system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1258system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1259system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1260system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1261system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1262system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1263system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1264system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1265system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1266system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1267system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1268system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1269system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1270system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1271system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1272system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1273system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1274system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1275system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1276system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1277system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1278system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1279system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1280system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1281system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1282system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1283system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1284system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1285system.cpu1.dtb.walker.walks 298651 # Table walker walks requested 1286system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors 1287system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate 1288system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate 1289system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency 1290system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1291system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency 1292system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency 1293system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency 1294system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency 1295system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency 1296system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency 1297system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency 1298system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency 1299system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 1300system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency 1301system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 1302system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 1303system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1304system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution 1307system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution 1308system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution 1309system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated 1310system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated 1311system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated 1312system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst 1313system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1314system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst 1315system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst 1316system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1317system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst 1318system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst 1319system.cpu1.dtb.inst_hits 0 # ITB inst hits 1320system.cpu1.dtb.inst_misses 0 # ITB inst misses 1321system.cpu1.dtb.read_hits 90905034 # DTB read hits 1322system.cpu1.dtb.read_misses 248418 # DTB read misses 1323system.cpu1.dtb.write_hits 78767149 # DTB write hits 1324system.cpu1.dtb.write_misses 50233 # DTB write misses 1325system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1326system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1327system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 1328system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1329system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB 1330system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions 1331system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch 1332system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1333system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions 1334system.cpu1.dtb.read_accesses 91153452 # DTB read accesses 1335system.cpu1.dtb.write_accesses 78817382 # DTB write accesses 1336system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1337system.cpu1.dtb.hits 169672183 # DTB hits 1338system.cpu1.dtb.misses 298651 # DTB misses 1339system.cpu1.dtb.accesses 169970834 # DTB accesses 1340system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1341system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1342system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1343system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1344system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1345system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1346system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1347system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1348system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1349system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1350system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1351system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1352system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1353system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1354system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1355system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1356system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1357system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1358system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1359system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1360system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1361system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1362system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1363system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1364system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1365system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1366system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1367system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1368system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1369system.cpu1.itb.walker.walks 67610 # Table walker walks requested 1370system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors 1371system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate 1372system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate 1373system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency 1374system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1375system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency 1376system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency 1377system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency 1378system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency 1379system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency 1380system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency 1381system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency 1382system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency 1383system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency 1384system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency 1385system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution 1391system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution 1392system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution 1393system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated 1394system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated 1395system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated 1396system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1397system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst 1398system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst 1399system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1400system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst 1401system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst 1402system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst 1403system.cpu1.itb.inst_hits 252933263 # ITB inst hits 1404system.cpu1.itb.inst_misses 67610 # ITB inst misses 1405system.cpu1.itb.read_hits 0 # DTB read hits 1406system.cpu1.itb.read_misses 0 # DTB read misses 1407system.cpu1.itb.write_hits 0 # DTB write hits 1408system.cpu1.itb.write_misses 0 # DTB write misses 1409system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1410system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1411system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID 1412system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1413system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB 1414system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1415system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1416system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1417system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions 1418system.cpu1.itb.read_accesses 0 # DTB read accesses 1419system.cpu1.itb.write_accesses 0 # DTB write accesses 1420system.cpu1.itb.inst_accesses 253000873 # ITB inst accesses 1421system.cpu1.itb.hits 252933263 # DTB hits 1422system.cpu1.itb.misses 67610 # DTB misses 1423system.cpu1.itb.accesses 253000873 # DTB accesses 1424system.cpu1.numCycles 943783669 # number of cpu cycles simulated 1425system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1426system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1427system.cpu1.committedInsts 461717275 # Number of instructions committed 1428system.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed 1429system.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit 1430system.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching 1431system.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1432system.cpu1.cpi 2.044073 # CPI: cycles per instruction 1433system.cpu1.ipc 0.489219 # IPC: instructions per cycle 1434system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1435system.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed 1436system.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked 1437system.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped 1438system.cpu1.dcache.tags.replacements 5624476 # number of replacements 1439system.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use 1440system.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. 1441system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. 1442system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. 1443system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. 1444system.cpu1.dcache.tags.occ_blocks::cpu1.inst 426.107402 # Average occupied blocks per requestor 1445system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy 1446system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy 1447system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1448system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 1449system.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 1450system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1451system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1452system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses 1453system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses 1454system.cpu1.dcache.ReadReq_hits::cpu1.inst 83489779 # number of ReadReq hits 1455system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits 1456system.cpu1.dcache.WriteReq_hits::cpu1.inst 73474609 # number of WriteReq hits 1457system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits 1458system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 71990 # number of WriteInvalidateReq hits 1459system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits 1460system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1908367 # number of LoadLockedReq hits 1461system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits 1462system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1854336 # number of StoreCondReq hits 1463system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits 1464system.cpu1.dcache.demand_hits::cpu1.inst 156964388 # number of demand (read+write) hits 1465system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits 1466system.cpu1.dcache.overall_hits::cpu1.inst 156964388 # number of overall hits 1467system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits 1468system.cpu1.dcache.ReadReq_misses::cpu1.inst 4311289 # number of ReadReq misses 1469system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses 1470system.cpu1.dcache.WriteReq_misses::cpu1.inst 2366929 # number of WriteReq misses 1471system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses 1472system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 476593 # number of WriteInvalidateReq misses 1473system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses 1474system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 141331 # number of LoadLockedReq misses 1475system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses 1476system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 193852 # number of StoreCondReq misses 1477system.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses 1478system.cpu1.dcache.demand_misses::cpu1.inst 6678218 # number of demand (read+write) misses 1479system.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses 1480system.cpu1.dcache.overall_misses::cpu1.inst 6678218 # number of overall misses 1481system.cpu1.dcache.overall_misses::total 6678218 # number of overall misses 1482system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 60722587231 # number of ReadReq miss cycles 1483system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles 1484system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 38093191666 # number of WriteReq miss cycles 1485system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles 1486system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 11613108236 # number of WriteInvalidateReq miss cycles 1487system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles 1488system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1977833980 # number of LoadLockedReq miss cycles 1489system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles 1490system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3982712056 # number of StoreCondReq miss cycles 1491system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles 1492system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2357000 # number of StoreCondFailReq miss cycles 1493system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles 1494system.cpu1.dcache.demand_miss_latency::cpu1.inst 98815778897 # number of demand (read+write) miss cycles 1495system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles 1496system.cpu1.dcache.overall_miss_latency::cpu1.inst 98815778897 # number of overall miss cycles 1497system.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles 1498system.cpu1.dcache.ReadReq_accesses::cpu1.inst 87801068 # number of ReadReq accesses(hits+misses) 1499system.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) 1500system.cpu1.dcache.WriteReq_accesses::cpu1.inst 75841538 # number of WriteReq accesses(hits+misses) 1501system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) 1502system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 548583 # number of WriteInvalidateReq accesses(hits+misses) 1503system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) 1504system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2049698 # number of LoadLockedReq accesses(hits+misses) 1505system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) 1506system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2048188 # number of StoreCondReq accesses(hits+misses) 1507system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) 1508system.cpu1.dcache.demand_accesses::cpu1.inst 163642606 # number of demand (read+write) accesses 1509system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses 1510system.cpu1.dcache.overall_accesses::cpu1.inst 163642606 # number of overall (read+write) accesses 1511system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses 1512system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.049103 # miss rate for ReadReq accesses 1513system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses 1514system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.031209 # miss rate for WriteReq accesses 1515system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses 1516system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.868771 # miss rate for WriteInvalidateReq accesses 1517system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses 1518system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.068952 # miss rate for LoadLockedReq accesses 1519system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses 1520system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.094646 # miss rate for StoreCondReq accesses 1521system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses 1522system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.040810 # miss rate for demand accesses 1523system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses 1524system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.040810 # miss rate for overall accesses 1525system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses 1526system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044 # average ReadReq miss latency 1527system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency 1528system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856 # average WriteReq miss latency 1529system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency 1530system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930 # average WriteInvalidateReq miss latency 1531system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency 1532system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388 # average LoadLockedReq miss latency 1533system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency 1534system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182 # average StoreCondReq miss latency 1535system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency 1536system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1537system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1538system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency 1539system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency 1540system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency 1541system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency 1542system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1543system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1544system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1545system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1546system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1547system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1548system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1549system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1550system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks 1551system.cpu1.dcache.writebacks::total 3711348 # number of writebacks 1552system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits 1553system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits 1554system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR hits 1555system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits 1556system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 60 # number of WriteInvalidateReq MSHR hits 1557system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits 1558system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 47 # number of LoadLockedReq MSHR hits 1559system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits 1560system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 68 # number of StoreCondReq MSHR hits 1561system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits 1562system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1368730 # number of demand (read+write) MSHR hits 1563system.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits 1564system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1368730 # number of overall MSHR hits 1565system.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits 1566system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3913497 # number of ReadReq MSHR misses 1567system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses 1568system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1395991 # number of WriteReq MSHR misses 1569system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses 1570system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 476533 # number of WriteInvalidateReq MSHR misses 1571system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses 1572system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 141284 # number of LoadLockedReq MSHR misses 1573system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses 1574system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses 1575system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses 1576system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5309488 # number of demand (read+write) MSHR misses 1577system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses 1578system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5309488 # number of overall MSHR misses 1579system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses 1580system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 46779736993 # number of ReadReq MSHR miss cycles 1581system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles 1582system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20386885918 # number of WriteReq MSHR miss cycles 1583system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles 1584system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 10653380764 # number of WriteInvalidateReq MSHR miss cycles 1585system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles 1586system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles 1587system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles 1588system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles 1589system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles 1590system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles 1591system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles 1592system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles 1593system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles 1594system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles 1595system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles 1596system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles 1597system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles 1598system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles 1599system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles 1600system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles 1601system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles 1602system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses 1603system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses 1604system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses 1605system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses 1606system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses 1607system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses 1608system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses 1609system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses 1610system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses 1611system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses 1612system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses 1613system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses 1614system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses 1615system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses 1616system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency 1617system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency 1618system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency 1619system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency 1620system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency 1621system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency 1622system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency 1623system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency 1624system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency 1625system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency 1626system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1627system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1628system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency 1629system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 1630system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency 1631system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency 1632system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1633system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1634system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1635system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1636system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1637system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1638system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1639system.cpu1.icache.tags.replacements 9215030 # number of replacements 1640system.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use 1641system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. 1642system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. 1643system.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. 1644system.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. 1645system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor 1646system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy 1647system.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy 1648system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1649system.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id 1650system.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 1651system.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 1652system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1653system.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses 1654system.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses 1655system.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits 1656system.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits 1657system.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits 1658system.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits 1659system.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits 1660system.cpu1.icache.overall_hits::total 243489253 # number of overall hits 1661system.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses 1662system.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses 1663system.cpu1.icache.demand_misses::cpu1.inst 9215542 # number of demand (read+write) misses 1664system.cpu1.icache.demand_misses::total 9215542 # number of demand (read+write) misses 1665system.cpu1.icache.overall_misses::cpu1.inst 9215542 # number of overall misses 1666system.cpu1.icache.overall_misses::total 9215542 # number of overall misses 1667system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91468274167 # number of ReadReq miss cycles 1668system.cpu1.icache.ReadReq_miss_latency::total 91468274167 # number of ReadReq miss cycles 1669system.cpu1.icache.demand_miss_latency::cpu1.inst 91468274167 # number of demand (read+write) miss cycles 1670system.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles 1671system.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles 1672system.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles 1673system.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) 1674system.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) 1675system.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses 1676system.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses 1677system.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses 1678system.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses 1679system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses 1680system.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses 1681system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses 1682system.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses 1683system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses 1684system.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses 1685system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency 1686system.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency 1687system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 1688system.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency 1689system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency 1690system.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency 1691system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1692system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1693system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1694system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1695system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1696system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1697system.cpu1.icache.fast_writes 0 # number of fast writes performed 1698system.cpu1.icache.cache_copies 0 # number of cache copies performed 1699system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # number of ReadReq MSHR misses 1700system.cpu1.icache.ReadReq_mshr_misses::total 9215542 # number of ReadReq MSHR misses 1701system.cpu1.icache.demand_mshr_misses::cpu1.inst 9215542 # number of demand (read+write) MSHR misses 1702system.cpu1.icache.demand_mshr_misses::total 9215542 # number of demand (read+write) MSHR misses 1703system.cpu1.icache.overall_mshr_misses::cpu1.inst 9215542 # number of overall MSHR misses 1704system.cpu1.icache.overall_mshr_misses::total 9215542 # number of overall MSHR misses 1705system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77617743273 # number of ReadReq MSHR miss cycles 1706system.cpu1.icache.ReadReq_mshr_miss_latency::total 77617743273 # number of ReadReq MSHR miss cycles 1707system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77617743273 # number of demand (read+write) MSHR miss cycles 1708system.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles 1709system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles 1710system.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles 1711system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles 1712system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles 1713system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles 1714system.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles 1715system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses 1716system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq accesses 1717system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for demand accesses 1718system.cpu1.icache.demand_mshr_miss_rate::total 0.036468 # mshr miss rate for demand accesses 1719system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for overall accesses 1720system.cpu1.icache.overall_mshr_miss_rate::total 0.036468 # mshr miss rate for overall accesses 1721system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average ReadReq mshr miss latency 1722system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8422.482722 # average ReadReq mshr miss latency 1723system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 1724system.cpu1.icache.demand_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 1725system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency 1726system.cpu1.icache.overall_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency 1727system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1728system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1729system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1730system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1731system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1732system.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued 1733system.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified 1734system.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue 1735system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1736system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1737system.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing 1738system.cpu1.l2cache.tags.replacements 2569302 # number of replacements 1739system.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use 1740system.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. 1741system.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. 1742system.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. 1743system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. 1744system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor 1745system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor 1746system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor 1747system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor 1748system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor 1749system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy 1750system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy 1751system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy 1752system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy 1753system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy 1754system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy 1755system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id 1756system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 1757system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id 1758system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 1759system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id 1760system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id 1761system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id 1762system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1763system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1764system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id 1765system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 1766system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 1767system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id 1773system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 1774system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id 1775system.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses 1776system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses 1777system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits 1778system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits 1779system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11678610 # number of ReadReq hits 1780system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits 1781system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits 1782system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits 1783system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 202419 # number of WriteInvalidateReq hits 1784system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits 1785system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 77280 # number of UpgradeReq hits 1786system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits 1787system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41809 # number of SCUpgradeReq hits 1788system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits 1789system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 939119 # number of ReadExReq hits 1790system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits 1791system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits 1792system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits 1793system.cpu1.l2cache.demand_hits::cpu1.inst 12617729 # number of demand (read+write) hits 1794system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits 1795system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits 1796system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits 1797system.cpu1.l2cache.overall_hits::cpu1.inst 12617729 # number of overall hits 1798system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits 1799system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses 1800system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses 1801system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1591427 # number of ReadReq misses 1802system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses 1803system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1804system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 1805system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 272843 # number of WriteInvalidateReq misses 1806system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses 1807system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 137034 # number of UpgradeReq misses 1808system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses 1809system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151974 # number of SCUpgradeReq misses 1810system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses 1811system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses 1812system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1813system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 244121 # number of ReadExReq misses 1814system.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses 1815system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses 1816system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses 1817system.cpu1.l2cache.demand_misses::cpu1.inst 1835548 # number of demand (read+write) misses 1818system.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses 1819system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses 1820system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses 1821system.cpu1.l2cache.overall_misses::cpu1.inst 1835548 # number of overall misses 1822system.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses 1823system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles 1824system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles 1825system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 47206598788 # number of ReadReq miss cycles 1826system.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles 1827system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 213581444 # number of WriteInvalidateReq miss cycles 1828system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles 1829system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2792930491 # number of UpgradeReq miss cycles 1830system.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles 1831system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3071034580 # number of SCUpgradeReq miss cycles 1832system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles 1833system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 1783500 # number of SCUpgradeFailReq miss cycles 1834system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles 1835system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9626384839 # number of ReadExReq miss cycles 1836system.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles 1837system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles 1838system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles 1839system.cpu1.l2cache.demand_miss_latency::cpu1.inst 56832983627 # number of demand (read+write) miss cycles 1840system.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles 1841system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles 1842system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles 1843system.cpu1.l2cache.overall_miss_latency::cpu1.inst 56832983627 # number of overall miss cycles 1844system.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles 1845system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) 1846system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) 1847system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 13270037 # number of ReadReq accesses(hits+misses) 1848system.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) 1849system.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) 1850system.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) 1851system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 475262 # number of WriteInvalidateReq accesses(hits+misses) 1852system.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) 1853system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 214314 # number of UpgradeReq accesses(hits+misses) 1854system.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) 1855system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 193783 # number of SCUpgradeReq accesses(hits+misses) 1856system.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) 1857system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) 1858system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1859system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183240 # number of ReadExReq accesses(hits+misses) 1860system.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) 1861system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses 1862system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses 1863system.cpu1.l2cache.demand_accesses::cpu1.inst 14453277 # number of demand (read+write) accesses 1864system.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses 1865system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses 1866system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses 1867system.cpu1.l2cache.overall_accesses::cpu1.inst 14453277 # number of overall (read+write) accesses 1868system.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses 1869system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses 1870system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses 1871system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.119926 # miss rate for ReadReq accesses 1872system.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses 1873system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1874system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1875system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.574090 # miss rate for WriteInvalidateReq accesses 1876system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses 1877system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.639408 # miss rate for UpgradeReq accesses 1878system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses 1879system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.784248 # miss rate for SCUpgradeReq accesses 1880system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses 1881system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 1882system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1883system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.206316 # miss rate for ReadExReq accesses 1884system.cpu1.l2cache.ReadExReq_miss_rate::total 0.206316 # miss rate for ReadExReq accesses 1885system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for demand accesses 1886system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052987 # miss rate for demand accesses 1887system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.126999 # miss rate for demand accesses 1888system.cpu1.l2cache.demand_miss_rate::total 0.122349 # miss rate for demand accesses 1889system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for overall accesses 1890system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052987 # miss rate for overall accesses 1891system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.126999 # miss rate for overall accesses 1892system.cpu1.l2cache.overall_miss_rate::total 0.122349 # miss rate for overall accesses 1893system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average ReadReq miss latency 1894system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634 # average ReadReq miss latency 1895system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29663.062640 # average ReadReq miss latency 1896system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197 # average ReadReq miss latency 1897system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 782.799793 # average WriteInvalidateReq miss latency 1898system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 782.799793 # average WriteInvalidateReq miss latency 1899system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20381.295817 # average UpgradeReq miss latency 1900system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817 # average UpgradeReq miss latency 1901system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20207.631437 # average SCUpgradeReq miss latency 1902system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437 # average SCUpgradeReq miss latency 1903system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 1783500 # average SCUpgradeFailReq miss latency 1904system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1783500 # average SCUpgradeFailReq miss latency 1905system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39432.842070 # average ReadExReq miss latency 1906system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070 # average ReadExReq miss latency 1907system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 1908system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 1909system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency 1910system.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886 # average overall miss latency 1911system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency 1912system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency 1913system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency 1914system.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886 # average overall miss latency 1915system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1916system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1917system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1918system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1919system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1920system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1921system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1922system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1923system.cpu1.l2cache.writebacks::writebacks 1092301 # number of writebacks 1924system.cpu1.l2cache.writebacks::total 1092301 # number of writebacks 1925system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 1926system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1805 # number of ReadReq MSHR hits 1927system.cpu1.l2cache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits 1928system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 45 # number of WriteInvalidateReq MSHR hits 1929system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 45 # number of WriteInvalidateReq MSHR hits 1930system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 7072 # number of ReadExReq MSHR hits 1931system.cpu1.l2cache.ReadExReq_mshr_hits::total 7072 # number of ReadExReq MSHR hits 1932system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 1933system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8877 # number of demand (read+write) MSHR hits 1934system.cpu1.l2cache.demand_mshr_hits::total 8878 # number of demand (read+write) MSHR hits 1935system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 1936system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8877 # number of overall MSHR hits 1937system.cpu1.l2cache.overall_mshr_hits::total 8878 # number of overall MSHR hits 1938system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12561 # number of ReadReq MSHR misses 1939system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8869 # number of ReadReq MSHR misses 1940system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 1589622 # number of ReadReq MSHR misses 1941system.cpu1.l2cache.ReadReq_mshr_misses::total 1611052 # number of ReadReq MSHR misses 1942system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1943system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1944system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of HardPFReq MSHR misses 1945system.cpu1.l2cache.HardPFReq_mshr_misses::total 1032302 # number of HardPFReq MSHR misses 1946system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 272798 # number of WriteInvalidateReq MSHR misses 1947system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 272798 # number of WriteInvalidateReq MSHR misses 1948system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 137034 # number of UpgradeReq MSHR misses 1949system.cpu1.l2cache.UpgradeReq_mshr_misses::total 137034 # number of UpgradeReq MSHR misses 1950system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151974 # number of SCUpgradeReq MSHR misses 1951system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151974 # number of SCUpgradeReq MSHR misses 1952system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses 1953system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1954system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 237049 # number of ReadExReq MSHR misses 1955system.cpu1.l2cache.ReadExReq_mshr_misses::total 237049 # number of ReadExReq MSHR misses 1956system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12561 # number of demand (read+write) MSHR misses 1957system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8869 # number of demand (read+write) MSHR misses 1958system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1826671 # number of demand (read+write) MSHR misses 1959system.cpu1.l2cache.demand_mshr_misses::total 1848101 # number of demand (read+write) MSHR misses 1960system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12561 # number of overall MSHR misses 1961system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8869 # number of overall MSHR misses 1962system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1826671 # number of overall MSHR misses 1963system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of overall MSHR misses 1964system.cpu1.l2cache.overall_mshr_misses::total 2880403 # number of overall MSHR misses 1965system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of ReadReq MSHR miss cycles 1966system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 296231251 # number of ReadReq MSHR miss cycles 1967system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 35897455818 # number of ReadReq MSHR miss cycles 1968system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36560910324 # number of ReadReq MSHR miss cycles 1969system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of HardPFReq MSHR miss cycles 1970system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 41289088164 # number of HardPFReq MSHR miss cycles 1971system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 7103244766 # number of WriteInvalidateReq MSHR miss cycles 1972system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7103244766 # number of WriteInvalidateReq MSHR miss cycles 1973system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2312644672 # number of UpgradeReq MSHR miss cycles 1974system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2312644672 # number of UpgradeReq MSHR miss cycles 1975system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2076231085 # number of SCUpgradeReq MSHR miss cycles 1976system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2076231085 # number of SCUpgradeReq MSHR miss cycles 1977system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 1461500 # number of SCUpgradeFailReq MSHR miss cycles 1978system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1461500 # number of SCUpgradeFailReq MSHR miss cycles 1979system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7288633813 # number of ReadExReq MSHR miss cycles 1980system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7288633813 # number of ReadExReq MSHR miss cycles 1981system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of demand (read+write) MSHR miss cycles 1982system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles 1983system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 43186089631 # number of demand (read+write) MSHR miss cycles 1984system.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles 1985system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles 1986system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles 1987system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 43186089631 # number of overall MSHR miss cycles 1988system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles 1989system.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles 1990system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 514241998 # number of ReadReq MSHR uncacheable cycles 1991system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 514241998 # number of ReadReq MSHR uncacheable cycles 1992system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 574249999 # number of WriteReq MSHR uncacheable cycles 1993system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 574249999 # number of WriteReq MSHR uncacheable cycles 1994system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 1088491997 # number of overall MSHR uncacheable cycles 1995system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1088491997 # number of overall MSHR uncacheable cycles 1996system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for ReadReq accesses 1997system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for ReadReq accesses 1998system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.119790 # mshr miss rate for ReadReq accesses 1999system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses 2000system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 2001system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 2002system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2003system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2004system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.573995 # mshr miss rate for WriteInvalidateReq accesses 2005system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses 2006system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.639408 # mshr miss rate for UpgradeReq accesses 2007system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses 2008system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.784248 # mshr miss rate for SCUpgradeReq accesses 2009system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses 2010system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 2011system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2012system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses 2013system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses 2014system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses 2015system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses 2016system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses 2017system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses 2018system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses 2019system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses 2020system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses 2021system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2022system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses 2023system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency 2024system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency 2025system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency 2026system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency 2027system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency 2028system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency 2029system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency 2030system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency 2031system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency 2032system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency 2033system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency 2034system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency 2035system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency 2036system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency 2037system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency 2038system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency 2039system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 2040system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 2041system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency 2042system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency 2043system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 2044system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency 2045system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency 2046system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency 2047system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency 2048system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2049system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2050system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2051system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2052system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2053system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2054system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2055system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution 2056system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution 2057system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution 2058system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution 2059system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution 2060system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution 2061system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2062system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution 2063system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution 2064system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution 2065system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution 2066system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution 2067system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution 2068system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 2069system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution 2070system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution 2071system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) 2072system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) 2073system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) 2074system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) 2075system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) 2076system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) 2077system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) 2078system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) 2079system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) 2080system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) 2081system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) 2082system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram 2083system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram 2084system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram 2085system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2086system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2087system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2088system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2089system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2090system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2091system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram 2092system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram 2093system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2094system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2095system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2096system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram 2097system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) 2098system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2099system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) 2100system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2101system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) 2102system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2103system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) 2104system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2105system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) 2106system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2107system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) 2108system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2109system.iobus.trans_dist::ReadReq 40424 # Transaction distribution 2110system.iobus.trans_dist::ReadResp 40424 # Transaction distribution 2111system.iobus.trans_dist::WriteReq 136766 # Transaction distribution 2112system.iobus.trans_dist::WriteResp 30038 # Transaction distribution 2113system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 2114system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) 2115system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2116system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2117system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2118system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2119system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2120system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2121system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2122system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2123system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2124system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 2125system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2126system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2127system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2128system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2129system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) 2130system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) 2131system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) 2132system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2133system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2134system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) 2135system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) 2136system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2137system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2138system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2139system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2140system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2141system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2142system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2143system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2144system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2145system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 2146system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2147system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2148system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2149system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2150system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) 2151system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) 2152system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) 2153system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2154system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2155system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) 2156system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) 2157system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2158system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2159system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2160system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2161system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2162system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2163system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2164system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2165system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2166system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2167system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2168system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2169system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2170system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2171system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2172system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2173system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2174system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2175system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2176system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 2177system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2178system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2179system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2180system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2181system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2182system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2183system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2184system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) 2185system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2186system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2187system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2188system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) 2189system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2190system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) 2191system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2192system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 2193system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2194system.iocache.tags.replacements 115597 # number of replacements 2195system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use 2196system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2197system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. 2198system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2199system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. 2200system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor 2201system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor 2202system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy 2203system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy 2204system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy 2205system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2206system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2207system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2208system.iocache.tags.tag_accesses 1040901 # Number of tag accesses 2209system.iocache.tags.data_accesses 1040901 # Number of data accesses 2210system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2211system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses 2212system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses 2213system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2214system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2215system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 2216system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 2217system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2218system.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses 2219system.iocache.demand_misses::total 8928 # number of demand (read+write) misses 2220system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2221system.iocache.overall_misses::realview.ide 8888 # number of overall misses 2222system.iocache.overall_misses::total 8928 # number of overall misses 2223system.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles 2224system.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles 2225system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles 2226system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2227system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2228system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles 2229system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles 2230system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles 2231system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles 2232system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles 2233system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles 2234system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles 2235system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles 2236system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2237system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) 2238system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) 2239system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2240system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2241system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 2242system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 2243system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2244system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses 2245system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses 2246system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2247system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses 2248system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses 2249system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2250system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2251system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2252system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2253system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2254system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2255system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2256system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2257system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2258system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2259system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2260system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2262system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency 2263system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency 2264system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency 2265system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 2266system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 2267system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency 2268system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency 2269system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 2270system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 2271system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency 2272system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency 2273system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency 2274system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency 2275system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked 2276system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2277system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked 2278system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2279system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked 2280system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2281system.iocache.fast_writes 0 # number of fast writes performed 2282system.iocache.cache_copies 0 # number of cache copies performed 2283system.iocache.writebacks::writebacks 106694 # number of writebacks 2284system.iocache.writebacks::total 106694 # number of writebacks 2285system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2286system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses 2287system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses 2288system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2289system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2290system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 2291system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 2292system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2293system.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses 2294system.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses 2295system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2296system.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses 2297system.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses 2298system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles 2299system.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles 2300system.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles 2301system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 2302system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 2303system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles 2304system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles 2305system.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles 2306system.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles 2307system.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles 2308system.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles 2309system.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles 2310system.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles 2311system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2312system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2313system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2314system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2315system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2316system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2317system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2318system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2319system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2320system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2321system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2322system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2323system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2324system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency 2325system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency 2326system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency 2327system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 2328system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 2329system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency 2330system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency 2331system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 2332system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 2333system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 2334system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency 2335system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency 2336system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency 2337system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2338system.l2c.tags.replacements 1473453 # number of replacements 2339system.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use 2340system.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. 2341system.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. 2342system.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. 2343system.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. 2344system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor 2345system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor 2346system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor 2347system.l2c.tags.occ_blocks::cpu0.inst 7682.914611 # Average occupied blocks per requestor 2348system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor 2349system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor 2350system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor 2351system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor 2352system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor 2353system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy 2354system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy 2355system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy 2356system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy 2357system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy 2358system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy 2359system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy 2360system.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy 2361system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy 2362system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy 2363system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id 2364system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id 2365system.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id 2366system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id 2367system.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id 2368system.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id 2369system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 2370system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 2371system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 2372system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id 2373system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id 2374system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id 2375system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id 2376system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 2377system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id 2378system.l2c.tags.tag_accesses 65568567 # Number of tag accesses 2379system.l2c.tags.data_accesses 65568567 # Number of data accesses 2380system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits 2381system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits 2382system.l2c.ReadReq_hits::cpu0.inst 1051842 # number of ReadReq hits 2383system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits 2384system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits 2385system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits 2386system.l2c.ReadReq_hits::cpu1.inst 1187571 # number of ReadReq hits 2387system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits 2388system.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits 2389system.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits 2390system.l2c.Writeback_hits::total 2491671 # number of Writeback hits 2391system.l2c.WriteInvalidateReq_hits::cpu0.inst 125819 # number of WriteInvalidateReq hits 2392system.l2c.WriteInvalidateReq_hits::cpu1.inst 140505 # number of WriteInvalidateReq hits 2393system.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits 2394system.l2c.UpgradeReq_hits::cpu0.inst 29765 # number of UpgradeReq hits 2395system.l2c.UpgradeReq_hits::cpu1.inst 32403 # number of UpgradeReq hits 2396system.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits 2397system.l2c.SCUpgradeReq_hits::cpu0.inst 5875 # number of SCUpgradeReq hits 2398system.l2c.SCUpgradeReq_hits::cpu1.inst 6386 # number of SCUpgradeReq hits 2399system.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits 2400system.l2c.ReadExReq_hits::cpu0.inst 56397 # number of ReadExReq hits 2401system.l2c.ReadExReq_hits::cpu1.inst 53337 # number of ReadExReq hits 2402system.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits 2403system.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu0.inst 1108239 # number of demand (read+write) hits 2406system.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits 2407system.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits 2408system.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits 2409system.l2c.demand_hits::cpu1.inst 1240908 # number of demand (read+write) hits 2410system.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits 2411system.l2c.demand_hits::total 3424248 # number of demand (read+write) hits 2412system.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits 2413system.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits 2414system.l2c.overall_hits::cpu0.inst 1108239 # number of overall hits 2415system.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits 2416system.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits 2417system.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits 2418system.l2c.overall_hits::cpu1.inst 1240908 # number of overall hits 2419system.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits 2420system.l2c.overall_hits::total 3424248 # number of overall hits 2421system.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses 2422system.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses 2423system.l2c.ReadReq_misses::cpu0.inst 169093 # number of ReadReq misses 2424system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses 2425system.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses 2426system.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses 2427system.l2c.ReadReq_misses::cpu1.inst 162223 # number of ReadReq misses 2428system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses 2429system.l2c.ReadReq_misses::total 870286 # number of ReadReq misses 2430system.l2c.WriteInvalidateReq_misses::cpu0.inst 435530 # number of WriteInvalidateReq misses 2431system.l2c.WriteInvalidateReq_misses::cpu1.inst 123517 # number of WriteInvalidateReq misses 2432system.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses 2433system.l2c.UpgradeReq_misses::cpu0.inst 44959 # number of UpgradeReq misses 2434system.l2c.UpgradeReq_misses::cpu1.inst 45474 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses 2436system.l2c.SCUpgradeReq_misses::cpu0.inst 8261 # number of SCUpgradeReq misses 2437system.l2c.SCUpgradeReq_misses::cpu1.inst 9038 # number of SCUpgradeReq misses 2438system.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses 2439system.l2c.ReadExReq_misses::cpu0.inst 76639 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu1.inst 55158 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses 2442system.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses 2443system.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses 2444system.l2c.demand_misses::cpu0.inst 245732 # number of demand (read+write) misses 2445system.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses 2446system.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses 2447system.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses 2448system.l2c.demand_misses::cpu1.inst 217381 # number of demand (read+write) misses 2449system.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses 2450system.l2c.demand_misses::total 1002083 # number of demand (read+write) misses 2451system.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses 2452system.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses 2453system.l2c.overall_misses::cpu0.inst 245732 # number of overall misses 2454system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses 2455system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses 2456system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses 2457system.l2c.overall_misses::cpu1.inst 217381 # number of overall misses 2458system.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses 2459system.l2c.overall_misses::total 1002083 # number of overall misses 2460system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles 2461system.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles 2462system.l2c.ReadReq_miss_latency::cpu0.inst 13556032080 # number of ReadReq miss cycles 2463system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles 2464system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles 2465system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles 2466system.l2c.ReadReq_miss_latency::cpu1.inst 12762094450 # number of ReadReq miss cycles 2467system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles 2468system.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles 2469system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 36612963 # number of WriteInvalidateReq miss cycles 2470system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 35758482 # number of WriteInvalidateReq miss cycles 2471system.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles 2472system.l2c.UpgradeReq_miss_latency::cpu0.inst 213542030 # number of UpgradeReq miss cycles 2473system.l2c.UpgradeReq_miss_latency::cpu1.inst 216684315 # number of UpgradeReq miss cycles 2474system.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles 2475system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 36699987 # number of SCUpgradeReq miss cycles 2476system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 41305269 # number of SCUpgradeReq miss cycles 2477system.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles 2478system.l2c.ReadExReq_miss_latency::cpu0.inst 6278532917 # number of ReadExReq miss cycles 2479system.l2c.ReadExReq_miss_latency::cpu1.inst 4207751582 # number of ReadExReq miss cycles 2480system.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles 2481system.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles 2482system.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles 2483system.l2c.demand_miss_latency::cpu0.inst 19834564997 # number of demand (read+write) miss cycles 2484system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles 2485system.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::cpu1.inst 16969846032 # number of demand (read+write) miss cycles 2488system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles 2489system.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles 2490system.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles 2491system.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles 2492system.l2c.overall_miss_latency::cpu0.inst 19834564997 # number of overall miss cycles 2493system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles 2494system.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.inst 16969846032 # number of overall miss cycles 2497system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles 2498system.l2c.overall_miss_latency::total 106467817356 # number of overall miss cycles 2499system.l2c.ReadReq_accesses::cpu0.dtb.walker 8395 # number of ReadReq accesses(hits+misses) 2500system.l2c.ReadReq_accesses::cpu0.itb.walker 6043 # number of ReadReq accesses(hits+misses) 2501system.l2c.ReadReq_accesses::cpu0.inst 1220935 # number of ReadReq accesses(hits+misses) 2502system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 796553 # number of ReadReq accesses(hits+misses) 2503system.l2c.ReadReq_accesses::cpu1.dtb.walker 9295 # number of ReadReq accesses(hits+misses) 2504system.l2c.ReadReq_accesses::cpu1.itb.walker 6808 # number of ReadReq accesses(hits+misses) 2505system.l2c.ReadReq_accesses::cpu1.inst 1349794 # number of ReadReq accesses(hits+misses) 2506system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 786977 # number of ReadReq accesses(hits+misses) 2507system.l2c.ReadReq_accesses::total 4184800 # number of ReadReq accesses(hits+misses) 2508system.l2c.Writeback_accesses::writebacks 2491671 # number of Writeback accesses(hits+misses) 2509system.l2c.Writeback_accesses::total 2491671 # number of Writeback accesses(hits+misses) 2510system.l2c.WriteInvalidateReq_accesses::cpu0.inst 561349 # number of WriteInvalidateReq accesses(hits+misses) 2511system.l2c.WriteInvalidateReq_accesses::cpu1.inst 264022 # number of WriteInvalidateReq accesses(hits+misses) 2512system.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) 2513system.l2c.UpgradeReq_accesses::cpu0.inst 74724 # number of UpgradeReq accesses(hits+misses) 2514system.l2c.UpgradeReq_accesses::cpu1.inst 77877 # number of UpgradeReq accesses(hits+misses) 2515system.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) 2516system.l2c.SCUpgradeReq_accesses::cpu0.inst 14136 # number of SCUpgradeReq accesses(hits+misses) 2517system.l2c.SCUpgradeReq_accesses::cpu1.inst 15424 # number of SCUpgradeReq accesses(hits+misses) 2518system.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) 2519system.l2c.ReadExReq_accesses::cpu0.inst 133036 # number of ReadExReq accesses(hits+misses) 2520system.l2c.ReadExReq_accesses::cpu1.inst 108495 # number of ReadExReq accesses(hits+misses) 2521system.l2c.ReadExReq_accesses::total 241531 # number of ReadExReq accesses(hits+misses) 2522system.l2c.demand_accesses::cpu0.dtb.walker 8395 # number of demand (read+write) accesses 2523system.l2c.demand_accesses::cpu0.itb.walker 6043 # number of demand (read+write) accesses 2524system.l2c.demand_accesses::cpu0.inst 1353971 # number of demand (read+write) accesses 2525system.l2c.demand_accesses::cpu0.l2cache.prefetcher 796553 # number of demand (read+write) accesses 2526system.l2c.demand_accesses::cpu1.dtb.walker 9295 # number of demand (read+write) accesses 2527system.l2c.demand_accesses::cpu1.itb.walker 6808 # number of demand (read+write) accesses 2528system.l2c.demand_accesses::cpu1.inst 1458289 # number of demand (read+write) accesses 2529system.l2c.demand_accesses::cpu1.l2cache.prefetcher 786977 # number of demand (read+write) accesses 2530system.l2c.demand_accesses::total 4426331 # number of demand (read+write) accesses 2531system.l2c.overall_accesses::cpu0.dtb.walker 8395 # number of overall (read+write) accesses 2532system.l2c.overall_accesses::cpu0.itb.walker 6043 # number of overall (read+write) accesses 2533system.l2c.overall_accesses::cpu0.inst 1353971 # number of overall (read+write) accesses 2534system.l2c.overall_accesses::cpu0.l2cache.prefetcher 796553 # number of overall (read+write) accesses 2535system.l2c.overall_accesses::cpu1.dtb.walker 9295 # number of overall (read+write) accesses 2536system.l2c.overall_accesses::cpu1.itb.walker 6808 # number of overall (read+write) accesses 2537system.l2c.overall_accesses::cpu1.inst 1458289 # number of overall (read+write) accesses 2538system.l2c.overall_accesses::cpu1.l2cache.prefetcher 786977 # number of overall (read+write) accesses 2539system.l2c.overall_accesses::total 4426331 # number of overall (read+write) accesses 2540system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for ReadReq accesses 2541system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.215290 # miss rate for ReadReq accesses 2542system.l2c.ReadReq_miss_rate::cpu0.inst 0.138495 # miss rate for ReadReq accesses 2543system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for ReadReq accesses 2544system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for ReadReq accesses 2545system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.339160 # miss rate for ReadReq accesses 2546system.l2c.ReadReq_miss_rate::cpu1.inst 0.120184 # miss rate for ReadReq accesses 2547system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for ReadReq accesses 2548system.l2c.ReadReq_miss_rate::total 0.207964 # miss rate for ReadReq accesses 2549system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.775863 # miss rate for WriteInvalidateReq accesses 2550system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.467828 # miss rate for WriteInvalidateReq accesses 2551system.l2c.WriteInvalidateReq_miss_rate::total 0.677328 # miss rate for WriteInvalidateReq accesses 2552system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.601667 # miss rate for UpgradeReq accesses 2553system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.583921 # miss rate for UpgradeReq accesses 2554system.l2c.UpgradeReq_miss_rate::total 0.592611 # miss rate for UpgradeReq accesses 2555system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.584394 # miss rate for SCUpgradeReq accesses 2556system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.585970 # miss rate for SCUpgradeReq accesses 2557system.l2c.SCUpgradeReq_miss_rate::total 0.585217 # miss rate for SCUpgradeReq accesses 2558system.l2c.ReadExReq_miss_rate::cpu0.inst 0.576077 # miss rate for ReadExReq accesses 2559system.l2c.ReadExReq_miss_rate::cpu1.inst 0.508392 # miss rate for ReadExReq accesses 2560system.l2c.ReadExReq_miss_rate::total 0.545673 # miss rate for ReadExReq accesses 2561system.l2c.demand_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for demand accesses 2562system.l2c.demand_miss_rate::cpu0.itb.walker 0.215290 # miss rate for demand accesses 2563system.l2c.demand_miss_rate::cpu0.inst 0.181490 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for demand accesses 2565system.l2c.demand_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for demand accesses 2566system.l2c.demand_miss_rate::cpu1.itb.walker 0.339160 # miss rate for demand accesses 2567system.l2c.demand_miss_rate::cpu1.inst 0.149066 # miss rate for demand accesses 2568system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for demand accesses 2569system.l2c.demand_miss_rate::total 0.226391 # miss rate for demand accesses 2570system.l2c.overall_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for overall accesses 2571system.l2c.overall_miss_rate::cpu0.itb.walker 0.215290 # miss rate for overall accesses 2572system.l2c.overall_miss_rate::cpu0.inst 0.181490 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for overall accesses 2574system.l2c.overall_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for overall accesses 2575system.l2c.overall_miss_rate::cpu1.itb.walker 0.339160 # miss rate for overall accesses 2576system.l2c.overall_miss_rate::cpu1.inst 0.149066 # miss rate for overall accesses 2577system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for overall accesses 2578system.l2c.overall_miss_rate::total 0.226391 # miss rate for overall accesses 2579system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average ReadReq miss latency 2580system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191 # average ReadReq miss latency 2581system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80169.090855 # average ReadReq miss latency 2582system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average ReadReq miss latency 2583system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average ReadReq miss latency 2584system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722 # average ReadReq miss latency 2585system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78670.068054 # average ReadReq miss latency 2586system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average ReadReq miss latency 2587system.l2c.ReadReq_avg_miss_latency::total 110287.345605 # average ReadReq miss latency 2588system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 84.065307 # average WriteInvalidateReq miss latency 2589system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 289.502514 # average WriteInvalidateReq miss latency 2590system.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency 2591system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4749.705954 # average UpgradeReq miss latency 2592system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4765.015503 # average UpgradeReq miss latency 2593system.l2c.UpgradeReq_avg_miss_latency::total 4757.404321 # average UpgradeReq miss latency 2594system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 4442.559860 # average SCUpgradeReq miss latency 2595system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4570.178026 # average SCUpgradeReq miss latency 2596system.l2c.SCUpgradeReq_avg_miss_latency::total 4509.234985 # average SCUpgradeReq miss latency 2597system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301 # average ReadExReq miss latency 2598system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 76285.426992 # average ReadExReq miss latency 2599system.l2c.ReadExReq_avg_miss_latency::total 79563.908883 # average ReadExReq miss latency 2600system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency 2601system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency 2605system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency 2606system.l2c.demand_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency 2607system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency 2608system.l2c.demand_avg_miss_latency::total 106246.505884 # average overall miss latency 2609system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency 2610system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency 2614system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency 2615system.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency 2616system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency 2617system.l2c.overall_avg_miss_latency::total 106246.505884 # average overall miss latency 2618system.l2c.blocked_cycles::no_mshrs 5735 # number of cycles access was blocked 2619system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2620system.l2c.blocked::no_mshrs 156 # number of cycles access was blocked 2621system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2622system.l2c.avg_blocked_cycles::no_mshrs 36.762821 # average number of cycles each access was blocked 2623system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2624system.l2c.fast_writes 0 # number of fast writes performed 2625system.l2c.cache_copies 0 # number of cache copies performed 2626system.l2c.writebacks::writebacks 1116216 # number of writebacks 2627system.l2c.writebacks::total 1116216 # number of writebacks 2628system.l2c.ReadReq_mshr_hits::cpu0.inst 210 # number of ReadReq MSHR hits 2629system.l2c.ReadReq_mshr_hits::cpu1.inst 177 # number of ReadReq MSHR hits 2630system.l2c.ReadReq_mshr_hits::total 387 # number of ReadReq MSHR hits 2631system.l2c.demand_mshr_hits::cpu0.inst 210 # number of demand (read+write) MSHR hits 2632system.l2c.demand_mshr_hits::cpu1.inst 177 # number of demand (read+write) MSHR hits 2633system.l2c.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits 2634system.l2c.overall_mshr_hits::cpu0.inst 210 # number of overall MSHR hits 2635system.l2c.overall_mshr_hits::cpu1.inst 177 # number of overall MSHR hits 2636system.l2c.overall_mshr_hits::total 387 # number of overall MSHR hits 2637system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1664 # number of ReadReq MSHR misses 2638system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1301 # number of ReadReq MSHR misses 2639system.l2c.ReadReq_mshr_misses::cpu0.inst 168883 # number of ReadReq MSHR misses 2640system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq MSHR misses 2641system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2478 # number of ReadReq MSHR misses 2642system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2309 # number of ReadReq MSHR misses 2643system.l2c.ReadReq_mshr_misses::cpu1.inst 162046 # number of ReadReq MSHR misses 2644system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq MSHR misses 2645system.l2c.ReadReq_mshr_misses::total 869899 # number of ReadReq MSHR misses 2646system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 435530 # number of WriteInvalidateReq MSHR misses 2647system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 123517 # number of WriteInvalidateReq MSHR misses 2648system.l2c.WriteInvalidateReq_mshr_misses::total 559047 # number of WriteInvalidateReq MSHR misses 2649system.l2c.UpgradeReq_mshr_misses::cpu0.inst 44959 # number of UpgradeReq MSHR misses 2650system.l2c.UpgradeReq_mshr_misses::cpu1.inst 45474 # number of UpgradeReq MSHR misses 2651system.l2c.UpgradeReq_mshr_misses::total 90433 # number of UpgradeReq MSHR misses 2652system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 8261 # number of SCUpgradeReq MSHR misses 2653system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9038 # number of SCUpgradeReq MSHR misses 2654system.l2c.SCUpgradeReq_mshr_misses::total 17299 # number of SCUpgradeReq MSHR misses 2655system.l2c.ReadExReq_mshr_misses::cpu0.inst 76639 # number of ReadExReq MSHR misses 2656system.l2c.ReadExReq_mshr_misses::cpu1.inst 55158 # number of ReadExReq MSHR misses 2657system.l2c.ReadExReq_mshr_misses::total 131797 # number of ReadExReq MSHR misses 2658system.l2c.demand_mshr_misses::cpu0.dtb.walker 1664 # number of demand (read+write) MSHR misses 2659system.l2c.demand_mshr_misses::cpu0.itb.walker 1301 # number of demand (read+write) MSHR misses 2660system.l2c.demand_mshr_misses::cpu0.inst 245522 # number of demand (read+write) MSHR misses 2661system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) MSHR misses 2662system.l2c.demand_mshr_misses::cpu1.dtb.walker 2478 # number of demand (read+write) MSHR misses 2663system.l2c.demand_mshr_misses::cpu1.itb.walker 2309 # number of demand (read+write) MSHR misses 2664system.l2c.demand_mshr_misses::cpu1.inst 217204 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) MSHR misses 2666system.l2c.demand_mshr_misses::total 1001696 # number of demand (read+write) MSHR misses 2667system.l2c.overall_mshr_misses::cpu0.dtb.walker 1664 # number of overall MSHR misses 2668system.l2c.overall_mshr_misses::cpu0.itb.walker 1301 # number of overall MSHR misses 2669system.l2c.overall_mshr_misses::cpu0.inst 245522 # number of overall MSHR misses 2670system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of overall MSHR misses 2671system.l2c.overall_mshr_misses::cpu1.dtb.walker 2478 # number of overall MSHR misses 2672system.l2c.overall_mshr_misses::cpu1.itb.walker 2309 # number of overall MSHR misses 2673system.l2c.overall_mshr_misses::cpu1.inst 217204 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of overall MSHR misses 2675system.l2c.overall_mshr_misses::total 1001696 # number of overall MSHR misses 2676system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of ReadReq MSHR miss cycles 2677system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 94777748 # number of ReadReq MSHR miss cycles 2678system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11415126178 # number of ReadReq MSHR miss cycles 2679system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of ReadReq MSHR miss cycles 2680system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of ReadReq MSHR miss cycles 2681system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 156241500 # number of ReadReq MSHR miss cycles 2682system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 10713554460 # number of ReadReq MSHR miss cycles 2683system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of ReadReq MSHR miss cycles 2684system.l2c.ReadReq_mshr_miss_latency::total 85169385965 # number of ReadReq MSHR miss cycles 2685system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 9786055012 # number of WriteInvalidateReq MSHR miss cycles 2686system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 2515639470 # number of WriteInvalidateReq MSHR miss cycles 2687system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12301694482 # number of WriteInvalidateReq MSHR miss cycles 2688system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 455524094 # number of UpgradeReq MSHR miss cycles 2689system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 460871563 # number of UpgradeReq MSHR miss cycles 2690system.l2c.UpgradeReq_mshr_miss_latency::total 916395657 # number of UpgradeReq MSHR miss cycles 2691system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 84887682 # number of SCUpgradeReq MSHR miss cycles 2692system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92374949 # number of SCUpgradeReq MSHR miss cycles 2693system.l2c.SCUpgradeReq_mshr_miss_latency::total 177262631 # number of SCUpgradeReq MSHR miss cycles 2694system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5315349505 # number of ReadExReq MSHR miss cycles 2695system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3512186842 # number of ReadExReq MSHR miss cycles 2696system.l2c.ReadExReq_mshr_miss_latency::total 8827536347 # number of ReadExReq MSHR miss cycles 2697system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of demand (read+write) MSHR miss cycles 2698system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94777748 # number of demand (read+write) MSHR miss cycles 2699system.l2c.demand_mshr_miss_latency::cpu0.inst 16730475683 # number of demand (read+write) MSHR miss cycles 2700system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of demand (read+write) MSHR miss cycles 2701system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of demand (read+write) MSHR miss cycles 2702system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 156241500 # number of demand (read+write) MSHR miss cycles 2703system.l2c.demand_mshr_miss_latency::cpu1.inst 14225741302 # number of demand (read+write) MSHR miss cycles 2704system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of demand (read+write) MSHR miss cycles 2705system.l2c.demand_mshr_miss_latency::total 93996922312 # number of demand (read+write) MSHR miss cycles 2706system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of overall MSHR miss cycles 2707system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles 2708system.l2c.overall_mshr_miss_latency::cpu0.inst 16730475683 # number of overall MSHR miss cycles 2709system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles 2710system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles 2711system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles 2712system.l2c.overall_mshr_miss_latency::cpu1.inst 14225741302 # number of overall MSHR miss cycles 2713system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles 2714system.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles 2715system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7718194748 # number of ReadReq MSHR uncacheable cycles 2716system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 418305498 # number of ReadReq MSHR uncacheable cycles 2717system.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles 2718system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4773990997 # number of WriteReq MSHR uncacheable cycles 2719system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 484709502 # number of WriteReq MSHR uncacheable cycles 2720system.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles 2721system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles 2722system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles 2723system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles 2724system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses 2725system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses 2726system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses 2727system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses 2728system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses 2729system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses 2730system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses 2731system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses 2732system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses 2733system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses 2734system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses 2735system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses 2736system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses 2737system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses 2738system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses 2739system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses 2740system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses 2741system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses 2742system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses 2743system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses 2744system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses 2745system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses 2746system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses 2747system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses 2748system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses 2749system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses 2750system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses 2751system.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses 2752system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses 2753system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses 2754system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses 2755system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses 2756system.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses 2757system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses 2758system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses 2759system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses 2760system.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses 2761system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses 2762system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses 2763system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency 2764system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency 2765system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency 2766system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency 2767system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency 2768system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency 2769system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency 2770system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency 2771system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency 2772system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency 2773system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency 2774system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency 2775system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency 2776system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency 2777system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency 2778system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency 2779system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency 2780system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency 2781system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency 2782system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency 2783system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency 2784system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 2785system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 2786system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency 2787system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 2788system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 2789system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 2790system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency 2791system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 2792system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 2793system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency 2794system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency 2795system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency 2796system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency 2797system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency 2798system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency 2799system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency 2800system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency 2801system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency 2802system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2803system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2804system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2805system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2806system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2807system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2808system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2809system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2810system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2811system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2812system.membus.trans_dist::ReadReq 969598 # Transaction distribution 2813system.membus.trans_dist::ReadResp 969598 # Transaction distribution 2814system.membus.trans_dist::WriteReq 38347 # Transaction distribution 2815system.membus.trans_dist::WriteResp 38347 # Transaction distribution 2816system.membus.trans_dist::Writeback 1222910 # Transaction distribution 2817system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution 2818system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution 2819system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution 2820system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution 2821system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution 2822system.membus.trans_dist::ReadExReq 144468 # Transaction distribution 2823system.membus.trans_dist::ReadExResp 127604 # Transaction distribution 2824system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) 2825system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 2826system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) 2827system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) 2828system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) 2829system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) 2830system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) 2831system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) 2832system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) 2833system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 2834system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) 2835system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) 2836system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) 2837system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) 2838system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) 2839system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) 2840system.membus.snoops 617229 # Total snoops (count) 2841system.membus.snoop_fanout::samples 3621307 # Request fanout histogram 2842system.membus.snoop_fanout::mean 1 # Request fanout histogram 2843system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2844system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2845system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2846system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram 2847system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2848system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2849system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2850system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2851system.membus.snoop_fanout::total 3621307 # Request fanout histogram 2852system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) 2853system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2854system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) 2855system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2856system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) 2857system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2858system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) 2859system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2860system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) 2861system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2862system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) 2863system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2864system.realview.ethernet.txBytes 966 # Bytes Transmitted 2865system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 2866system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 2867system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 2868system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 2869system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2870system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2871system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2872system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2873system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 2874system.realview.ethernet.totPackets 3 # Total Packets 2875system.realview.ethernet.totBytes 966 # Total Bytes 2876system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 2877system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 2878system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 2879system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2880system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 2881system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2882system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2883system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 2884system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2885system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2886system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 2887system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2888system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2889system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 2890system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2891system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2892system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 2893system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2894system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2895system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 2896system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2897system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2898system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 2899system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2900system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2901system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 2902system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2903system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 2904system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 2905system.realview.ethernet.droppedPackets 0 # number of packets dropped 2906system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution 2907system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution 2908system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution 2909system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution 2910system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution 2911system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution 2912system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution 2913system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution 2914system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution 2915system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution 2916system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 2917system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 2918system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution 2919system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution 2920system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) 2921system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) 2922system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) 2923system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) 2924system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) 2925system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) 2926system.toL2Bus.snoops 1616950 # Total snoops (count) 2927system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram 2928system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram 2929system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram 2930system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2931system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2932system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram 2933system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram 2934system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2935system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2936system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2937system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram 2938system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) 2939system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2940system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) 2941system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2942system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) 2943system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2944system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) 2945system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2946 2947---------- End Simulation Statistics ---------- 2948