config.ini revision 9924
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain 17dtb_filename=False 18early_kernel_symbols=false 19enable_context_switch_stats_dump=false 20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727 28memories=system.physmem system.realview.nvmem 29multi_proc=true 30num_work_ids=16 31panic_on_oops=true 32panic_on_panic=true 33readfile=tests/halt.sh 34symbolfile= 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master 59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child 65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage 71image_file=/dist/m5/system/disks/linux-arm-ael.img 72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 77voltage_domain=system.voltage_domain 78 79[system.cpu0] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true 85LSQDepCheckShift=4 86SQEntries=32 87SSITSize=1024 88activity=0 89backComSize=5 90branchPred=system.cpu0.branchPred 91cachePorts=200 92checker=Null 93clk_domain=system.cpu_clk_domain 94commitToDecodeDelay=1 95commitToFetchDelay=1 96commitToIEWDelay=1 97commitToRenameDelay=1 98commitWidth=8 99cpu_id=0 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu0.dtb 108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu0.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119interrupts=system.cpu0.interrupts 120isa=system.cpu0.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124max_insts_all_threads=0 125max_insts_any_thread=0 126max_loads_all_threads=0 127max_loads_any_thread=0 128needsTSO=false 129numIQEntries=64 130numPhysCCRegs=0 131numPhysFloatRegs=256 132numPhysIntRegs=256 133numROBEntries=192 134numRobs=1 135numThreads=1 136profile=0 137progress_interval=0 138renameToDecodeDelay=1 139renameToFetchDelay=1 140renameToIEWDelay=2 141renameToROBDelay=1 142renameWidth=8 143simpoint_start_insts= 144smtCommitPolicy=RoundRobin 145smtFetchPolicy=SingleThread 146smtIQPolicy=Partitioned 147smtIQThreshold=100 148smtLSQPolicy=Partitioned 149smtLSQThreshold=100 150smtNumFetchingThreads=1 151smtROBPolicy=Partitioned 152smtROBThreshold=100 153squashWidth=8 154store_set_clear_period=250000 155switched_out=false 156system=system 157tracer=system.cpu0.tracer 158trapLatency=13 159wbDepth=1 160wbWidth=8 161workload= 162dcache_port=system.cpu0.dcache.cpu_side 163icache_port=system.cpu0.icache.cpu_side 164 165[system.cpu0.branchPred] 166type=BranchPredictor 167BTBEntries=4096 168BTBTagSize=16 169RASSize=16 170choiceCtrBits=2 171choicePredictorSize=8192 172globalCtrBits=2 173globalPredictorSize=8192 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179predType=tournament 180 181[system.cpu0.dcache] 182type=BaseCache 183children=tags 184addr_ranges=0:18446744073709551615 185assoc=4 186clk_domain=system.cpu_clk_domain 187forward_snoops=true 188hit_latency=2 189is_top_level=true 190max_miss_count=0 191mshrs=4 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195size=32768 196system=system 197tags=system.cpu0.dcache.tags 198tgts_per_mshr=20 199two_queue=false 200write_buffers=8 201cpu_side=system.cpu0.dcache_port 202mem_side=system.toL2Bus.slave[1] 203 204[system.cpu0.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain 209hit_latency=2 210size=32768 211 212[system.cpu0.dtb] 213type=ArmTLB 214children=walker 215size=64 216walker=system.cpu0.dtb.walker 217 218[system.cpu0.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221num_squash_per_cycle=2 222sys=system 223port=system.toL2Bus.slave[3] 224 225[system.cpu0.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 229 230[system.cpu0.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234opList=system.cpu0.fuPool.FUList0.opList 235 236[system.cpu0.fuPool.FUList0.opList] 237type=OpDesc 238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu0.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 246opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 247 248[system.cpu0.fuPool.FUList1.opList0] 249type=OpDesc 250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu0.fuPool.FUList1.opList1] 255type=OpDesc 256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu0.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 264opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 265 266[system.cpu0.fuPool.FUList2.opList0] 267type=OpDesc 268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu0.fuPool.FUList2.opList1] 273type=OpDesc 274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu0.fuPool.FUList2.opList2] 279type=OpDesc 280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu0.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 288opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 289 290[system.cpu0.fuPool.FUList3.opList0] 291type=OpDesc 292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu0.fuPool.FUList3.opList1] 297type=OpDesc 298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu0.fuPool.FUList3.opList2] 303type=OpDesc 304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu0.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312opList=system.cpu0.fuPool.FUList4.opList 313 314[system.cpu0.fuPool.FUList4.opList] 315type=OpDesc 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu0.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 325 326[system.cpu0.fuPool.FUList5.opList00] 327type=OpDesc 328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList01] 333type=OpDesc 334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList02] 339type=OpDesc 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList03] 345type=OpDesc 346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList04] 351type=OpDesc 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList05] 357type=OpDesc 358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList06] 363type=OpDesc 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList07] 369type=OpDesc 370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList08] 375type=OpDesc 376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList09] 381type=OpDesc 382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList10] 387type=OpDesc 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList11] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList12] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList13] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList14] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList15] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu0.fuPool.FUList5.opList17] 429type=OpDesc 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu0.fuPool.FUList5.opList18] 435type=OpDesc 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList19] 441type=OpDesc 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu0.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 450opList=system.cpu0.fuPool.FUList6.opList 451 452[system.cpu0.fuPool.FUList6.opList] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu0.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 462opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 463 464[system.cpu0.fuPool.FUList7.opList0] 465type=OpDesc 466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu0.fuPool.FUList7.opList1] 471type=OpDesc 472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu0.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 480opList=system.cpu0.fuPool.FUList8.opList 481 482[system.cpu0.fuPool.FUList8.opList] 483type=OpDesc 484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu0.icache] 489type=BaseCache 490children=tags 491addr_ranges=0:18446744073709551615 492assoc=1 493clk_domain=system.cpu_clk_domain 494forward_snoops=true 495hit_latency=2 496is_top_level=true 497max_miss_count=0 498mshrs=4 499prefetch_on_access=false 500prefetcher=Null 501response_latency=2 502size=32768 503system=system 504tags=system.cpu0.icache.tags 505tgts_per_mshr=20 506two_queue=false 507write_buffers=8 508cpu_side=system.cpu0.icache_port 509mem_side=system.toL2Bus.slave[0] 510 511[system.cpu0.icache.tags] 512type=LRU 513assoc=1 514block_size=64 515clk_domain=system.cpu_clk_domain 516hit_latency=2 517size=32768 518 519[system.cpu0.interrupts] 520type=ArmInterrupts 521 522[system.cpu0.isa] 523type=ArmISA 524fpsid=1090793632 525id_isar0=34607377 526id_isar1=34677009 527id_isar2=555950401 528id_isar3=17899825 529id_isar4=268501314 530id_isar5=0 531id_mmfr0=3 532id_mmfr1=0 533id_mmfr2=19070976 534id_mmfr3=4027589137 535id_pfr0=49 536id_pfr1=1 537midr=890224640 538 539[system.cpu0.itb] 540type=ArmTLB 541children=walker 542size=64 543walker=system.cpu0.itb.walker 544 545[system.cpu0.itb.walker] 546type=ArmTableWalker 547clk_domain=system.cpu_clk_domain 548num_squash_per_cycle=2 549sys=system 550port=system.toL2Bus.slave[2] 551 552[system.cpu0.tracer] 553type=ExeTracer 554 555[system.cpu1] 556type=DerivO3CPU 557children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 558LFSTSize=1024 559LQEntries=32 560LSQCheckLoads=true 561LSQDepCheckShift=4 562SQEntries=32 563SSITSize=1024 564activity=0 565backComSize=5 566branchPred=system.cpu1.branchPred 567cachePorts=200 568checker=Null 569clk_domain=system.cpu_clk_domain 570commitToDecodeDelay=1 571commitToFetchDelay=1 572commitToIEWDelay=1 573commitToRenameDelay=1 574commitWidth=8 575cpu_id=1 576decodeToFetchDelay=1 577decodeToRenameDelay=1 578decodeWidth=8 579dispatchWidth=8 580do_checkpoint_insts=true 581do_quiesce=true 582do_statistics_insts=true 583dtb=system.cpu1.dtb 584fetchToDecodeDelay=1 585fetchTrapLatency=1 586fetchWidth=8 587forwardComSize=5 588fuPool=system.cpu1.fuPool 589function_trace=false 590function_trace_start=0 591iewToCommitDelay=1 592iewToDecodeDelay=1 593iewToFetchDelay=1 594iewToRenameDelay=1 595interrupts=system.cpu1.interrupts 596isa=system.cpu1.isa 597issueToExecuteDelay=1 598issueWidth=8 599itb=system.cpu1.itb 600max_insts_all_threads=0 601max_insts_any_thread=0 602max_loads_all_threads=0 603max_loads_any_thread=0 604needsTSO=false 605numIQEntries=64 606numPhysCCRegs=0 607numPhysFloatRegs=256 608numPhysIntRegs=256 609numROBEntries=192 610numRobs=1 611numThreads=1 612profile=0 613progress_interval=0 614renameToDecodeDelay=1 615renameToFetchDelay=1 616renameToIEWDelay=2 617renameToROBDelay=1 618renameWidth=8 619simpoint_start_insts= 620smtCommitPolicy=RoundRobin 621smtFetchPolicy=SingleThread 622smtIQPolicy=Partitioned 623smtIQThreshold=100 624smtLSQPolicy=Partitioned 625smtLSQThreshold=100 626smtNumFetchingThreads=1 627smtROBPolicy=Partitioned 628smtROBThreshold=100 629squashWidth=8 630store_set_clear_period=250000 631switched_out=false 632system=system 633tracer=system.cpu1.tracer 634trapLatency=13 635wbDepth=1 636wbWidth=8 637workload= 638dcache_port=system.cpu1.dcache.cpu_side 639icache_port=system.cpu1.icache.cpu_side 640 641[system.cpu1.branchPred] 642type=BranchPredictor 643BTBEntries=4096 644BTBTagSize=16 645RASSize=16 646choiceCtrBits=2 647choicePredictorSize=8192 648globalCtrBits=2 649globalPredictorSize=8192 650instShiftAmt=2 651localCtrBits=2 652localHistoryTableSize=2048 653localPredictorSize=2048 654numThreads=1 655predType=tournament 656 657[system.cpu1.dcache] 658type=BaseCache 659children=tags 660addr_ranges=0:18446744073709551615 661assoc=4 662clk_domain=system.cpu_clk_domain 663forward_snoops=true 664hit_latency=2 665is_top_level=true 666max_miss_count=0 667mshrs=4 668prefetch_on_access=false 669prefetcher=Null 670response_latency=2 671size=32768 672system=system 673tags=system.cpu1.dcache.tags 674tgts_per_mshr=20 675two_queue=false 676write_buffers=8 677cpu_side=system.cpu1.dcache_port 678mem_side=system.toL2Bus.slave[5] 679 680[system.cpu1.dcache.tags] 681type=LRU 682assoc=4 683block_size=64 684clk_domain=system.cpu_clk_domain 685hit_latency=2 686size=32768 687 688[system.cpu1.dtb] 689type=ArmTLB 690children=walker 691size=64 692walker=system.cpu1.dtb.walker 693 694[system.cpu1.dtb.walker] 695type=ArmTableWalker 696clk_domain=system.cpu_clk_domain 697num_squash_per_cycle=2 698sys=system 699port=system.toL2Bus.slave[7] 700 701[system.cpu1.fuPool] 702type=FUPool 703children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 704FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 705 706[system.cpu1.fuPool.FUList0] 707type=FUDesc 708children=opList 709count=6 710opList=system.cpu1.fuPool.FUList0.opList 711 712[system.cpu1.fuPool.FUList0.opList] 713type=OpDesc 714issueLat=1 715opClass=IntAlu 716opLat=1 717 718[system.cpu1.fuPool.FUList1] 719type=FUDesc 720children=opList0 opList1 721count=2 722opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 723 724[system.cpu1.fuPool.FUList1.opList0] 725type=OpDesc 726issueLat=1 727opClass=IntMult 728opLat=3 729 730[system.cpu1.fuPool.FUList1.opList1] 731type=OpDesc 732issueLat=19 733opClass=IntDiv 734opLat=20 735 736[system.cpu1.fuPool.FUList2] 737type=FUDesc 738children=opList0 opList1 opList2 739count=4 740opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 741 742[system.cpu1.fuPool.FUList2.opList0] 743type=OpDesc 744issueLat=1 745opClass=FloatAdd 746opLat=2 747 748[system.cpu1.fuPool.FUList2.opList1] 749type=OpDesc 750issueLat=1 751opClass=FloatCmp 752opLat=2 753 754[system.cpu1.fuPool.FUList2.opList2] 755type=OpDesc 756issueLat=1 757opClass=FloatCvt 758opLat=2 759 760[system.cpu1.fuPool.FUList3] 761type=FUDesc 762children=opList0 opList1 opList2 763count=2 764opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 765 766[system.cpu1.fuPool.FUList3.opList0] 767type=OpDesc 768issueLat=1 769opClass=FloatMult 770opLat=4 771 772[system.cpu1.fuPool.FUList3.opList1] 773type=OpDesc 774issueLat=12 775opClass=FloatDiv 776opLat=12 777 778[system.cpu1.fuPool.FUList3.opList2] 779type=OpDesc 780issueLat=24 781opClass=FloatSqrt 782opLat=24 783 784[system.cpu1.fuPool.FUList4] 785type=FUDesc 786children=opList 787count=0 788opList=system.cpu1.fuPool.FUList4.opList 789 790[system.cpu1.fuPool.FUList4.opList] 791type=OpDesc 792issueLat=1 793opClass=MemRead 794opLat=1 795 796[system.cpu1.fuPool.FUList5] 797type=FUDesc 798children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 799count=4 800opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 801 802[system.cpu1.fuPool.FUList5.opList00] 803type=OpDesc 804issueLat=1 805opClass=SimdAdd 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList01] 809type=OpDesc 810issueLat=1 811opClass=SimdAddAcc 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList02] 815type=OpDesc 816issueLat=1 817opClass=SimdAlu 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList03] 821type=OpDesc 822issueLat=1 823opClass=SimdCmp 824opLat=1 825 826[system.cpu1.fuPool.FUList5.opList04] 827type=OpDesc 828issueLat=1 829opClass=SimdCvt 830opLat=1 831 832[system.cpu1.fuPool.FUList5.opList05] 833type=OpDesc 834issueLat=1 835opClass=SimdMisc 836opLat=1 837 838[system.cpu1.fuPool.FUList5.opList06] 839type=OpDesc 840issueLat=1 841opClass=SimdMult 842opLat=1 843 844[system.cpu1.fuPool.FUList5.opList07] 845type=OpDesc 846issueLat=1 847opClass=SimdMultAcc 848opLat=1 849 850[system.cpu1.fuPool.FUList5.opList08] 851type=OpDesc 852issueLat=1 853opClass=SimdShift 854opLat=1 855 856[system.cpu1.fuPool.FUList5.opList09] 857type=OpDesc 858issueLat=1 859opClass=SimdShiftAcc 860opLat=1 861 862[system.cpu1.fuPool.FUList5.opList10] 863type=OpDesc 864issueLat=1 865opClass=SimdSqrt 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList11] 869type=OpDesc 870issueLat=1 871opClass=SimdFloatAdd 872opLat=1 873 874[system.cpu1.fuPool.FUList5.opList12] 875type=OpDesc 876issueLat=1 877opClass=SimdFloatAlu 878opLat=1 879 880[system.cpu1.fuPool.FUList5.opList13] 881type=OpDesc 882issueLat=1 883opClass=SimdFloatCmp 884opLat=1 885 886[system.cpu1.fuPool.FUList5.opList14] 887type=OpDesc 888issueLat=1 889opClass=SimdFloatCvt 890opLat=1 891 892[system.cpu1.fuPool.FUList5.opList15] 893type=OpDesc 894issueLat=1 895opClass=SimdFloatDiv 896opLat=1 897 898[system.cpu1.fuPool.FUList5.opList16] 899type=OpDesc 900issueLat=1 901opClass=SimdFloatMisc 902opLat=1 903 904[system.cpu1.fuPool.FUList5.opList17] 905type=OpDesc 906issueLat=1 907opClass=SimdFloatMult 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList18] 911type=OpDesc 912issueLat=1 913opClass=SimdFloatMultAcc 914opLat=1 915 916[system.cpu1.fuPool.FUList5.opList19] 917type=OpDesc 918issueLat=1 919opClass=SimdFloatSqrt 920opLat=1 921 922[system.cpu1.fuPool.FUList6] 923type=FUDesc 924children=opList 925count=0 926opList=system.cpu1.fuPool.FUList6.opList 927 928[system.cpu1.fuPool.FUList6.opList] 929type=OpDesc 930issueLat=1 931opClass=MemWrite 932opLat=1 933 934[system.cpu1.fuPool.FUList7] 935type=FUDesc 936children=opList0 opList1 937count=4 938opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 939 940[system.cpu1.fuPool.FUList7.opList0] 941type=OpDesc 942issueLat=1 943opClass=MemRead 944opLat=1 945 946[system.cpu1.fuPool.FUList7.opList1] 947type=OpDesc 948issueLat=1 949opClass=MemWrite 950opLat=1 951 952[system.cpu1.fuPool.FUList8] 953type=FUDesc 954children=opList 955count=1 956opList=system.cpu1.fuPool.FUList8.opList 957 958[system.cpu1.fuPool.FUList8.opList] 959type=OpDesc 960issueLat=3 961opClass=IprAccess 962opLat=3 963 964[system.cpu1.icache] 965type=BaseCache 966children=tags 967addr_ranges=0:18446744073709551615 968assoc=1 969clk_domain=system.cpu_clk_domain 970forward_snoops=true 971hit_latency=2 972is_top_level=true 973max_miss_count=0 974mshrs=4 975prefetch_on_access=false 976prefetcher=Null 977response_latency=2 978size=32768 979system=system 980tags=system.cpu1.icache.tags 981tgts_per_mshr=20 982two_queue=false 983write_buffers=8 984cpu_side=system.cpu1.icache_port 985mem_side=system.toL2Bus.slave[4] 986 987[system.cpu1.icache.tags] 988type=LRU 989assoc=1 990block_size=64 991clk_domain=system.cpu_clk_domain 992hit_latency=2 993size=32768 994 995[system.cpu1.interrupts] 996type=ArmInterrupts 997 998[system.cpu1.isa] 999type=ArmISA 1000fpsid=1090793632 1001id_isar0=34607377 1002id_isar1=34677009 1003id_isar2=555950401 1004id_isar3=17899825 1005id_isar4=268501314 1006id_isar5=0 1007id_mmfr0=3 1008id_mmfr1=0 1009id_mmfr2=19070976 1010id_mmfr3=4027589137 1011id_pfr0=49 1012id_pfr1=1 1013midr=890224640 1014 1015[system.cpu1.itb] 1016type=ArmTLB 1017children=walker 1018size=64 1019walker=system.cpu1.itb.walker 1020 1021[system.cpu1.itb.walker] 1022type=ArmTableWalker 1023clk_domain=system.cpu_clk_domain 1024num_squash_per_cycle=2 1025sys=system 1026port=system.toL2Bus.slave[6] 1027 1028[system.cpu1.tracer] 1029type=ExeTracer 1030 1031[system.cpu_clk_domain] 1032type=SrcClockDomain 1033clock=500 1034voltage_domain=system.voltage_domain 1035 1036[system.intrctrl] 1037type=IntrControl 1038sys=system 1039 1040[system.iobus] 1041type=NoncoherentBus 1042clk_domain=system.clk_domain 1043header_cycles=1 1044use_default_range=false 1045width=8 1046master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1047slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1048 1049[system.iocache] 1050type=BaseCache 1051children=tags 1052addr_ranges=0:134217727 1053assoc=8 1054clk_domain=system.clk_domain 1055forward_snoops=false 1056hit_latency=50 1057is_top_level=true 1058max_miss_count=0 1059mshrs=20 1060prefetch_on_access=false 1061prefetcher=Null 1062response_latency=50 1063size=1024 1064system=system 1065tags=system.iocache.tags 1066tgts_per_mshr=12 1067two_queue=false 1068write_buffers=8 1069cpu_side=system.iobus.master[25] 1070mem_side=system.membus.slave[2] 1071 1072[system.iocache.tags] 1073type=LRU 1074assoc=8 1075block_size=64 1076clk_domain=system.clk_domain 1077hit_latency=50 1078size=1024 1079 1080[system.l2c] 1081type=BaseCache 1082children=tags 1083addr_ranges=0:18446744073709551615 1084assoc=8 1085clk_domain=system.cpu_clk_domain 1086forward_snoops=true 1087hit_latency=20 1088is_top_level=false 1089max_miss_count=0 1090mshrs=20 1091prefetch_on_access=false 1092prefetcher=Null 1093response_latency=20 1094size=4194304 1095system=system 1096tags=system.l2c.tags 1097tgts_per_mshr=12 1098two_queue=false 1099write_buffers=8 1100cpu_side=system.toL2Bus.master[0] 1101mem_side=system.membus.slave[1] 1102 1103[system.l2c.tags] 1104type=LRU 1105assoc=8 1106block_size=64 1107clk_domain=system.cpu_clk_domain 1108hit_latency=20 1109size=4194304 1110 1111[system.membus] 1112type=CoherentBus 1113children=badaddr_responder 1114clk_domain=system.clk_domain 1115header_cycles=1 1116system=system 1117use_default_range=false 1118width=8 1119default=system.membus.badaddr_responder.pio 1120master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1121slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1122 1123[system.membus.badaddr_responder] 1124type=IsaFake 1125clk_domain=system.clk_domain 1126fake_mem=false 1127pio_addr=0 1128pio_latency=100000 1129pio_size=8 1130ret_bad_addr=true 1131ret_data16=65535 1132ret_data32=4294967295 1133ret_data64=18446744073709551615 1134ret_data8=255 1135system=system 1136update_data=false 1137warn_access=warn 1138pio=system.membus.default 1139 1140[system.physmem] 1141type=SimpleDRAM 1142activation_limit=4 1143addr_mapping=RaBaChCo 1144banks_per_rank=8 1145burst_length=8 1146channels=1 1147clk_domain=system.clk_domain 1148conf_table_reported=true 1149device_bus_width=8 1150device_rowbuffer_size=1024 1151devices_per_rank=8 1152in_addr_map=true 1153mem_sched_policy=frfcfs 1154null=false 1155page_policy=open 1156range=0:134217727 1157ranks_per_channel=2 1158read_buffer_size=32 1159static_backend_latency=10000 1160static_frontend_latency=10000 1161tBURST=5000 1162tCL=13750 1163tRCD=13750 1164tREFI=7800000 1165tRFC=300000 1166tRP=13750 1167tWTR=7500 1168tXAW=40000 1169write_buffer_size=32 1170write_thresh_perc=70 1171port=system.membus.master[6] 1172 1173[system.realview] 1174type=RealView 1175children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1176intrctrl=system.intrctrl 1177max_mem_size=268435456 1178mem_start_addr=0 1179pci_cfg_base=0 1180system=system 1181 1182[system.realview.a9scu] 1183type=A9SCU 1184clk_domain=system.clk_domain 1185pio_addr=520093696 1186pio_latency=100000 1187system=system 1188pio=system.membus.master[4] 1189 1190[system.realview.aaci_fake] 1191type=AmbaFake 1192amba_id=0 1193clk_domain=system.clk_domain 1194ignore_access=false 1195pio_addr=268451840 1196pio_latency=100000 1197system=system 1198pio=system.iobus.master[21] 1199 1200[system.realview.cf_ctrl] 1201type=IdeController 1202BAR0=402653184 1203BAR0LegacyIO=true 1204BAR0Size=16 1205BAR1=402653440 1206BAR1LegacyIO=true 1207BAR1Size=1 1208BAR2=1 1209BAR2LegacyIO=false 1210BAR2Size=8 1211BAR3=1 1212BAR3LegacyIO=false 1213BAR3Size=4 1214BAR4=1 1215BAR4LegacyIO=false 1216BAR4Size=16 1217BAR5=1 1218BAR5LegacyIO=false 1219BAR5Size=0 1220BIST=0 1221CacheLineSize=0 1222CardbusCIS=0 1223ClassCode=1 1224Command=1 1225DeviceID=28945 1226ExpansionROM=0 1227HeaderType=0 1228InterruptLine=31 1229InterruptPin=1 1230LatencyTimer=0 1231MaximumLatency=0 1232MinimumGrant=0 1233ProgIF=133 1234Revision=0 1235Status=640 1236SubClassCode=1 1237SubsystemID=0 1238SubsystemVendorID=0 1239VendorID=32902 1240clk_domain=system.clk_domain 1241config_latency=20000 1242ctrl_offset=2 1243disks=system.cf0 1244io_shift=1 1245pci_bus=2 1246pci_dev=7 1247pci_func=0 1248pio_latency=30000 1249platform=system.realview 1250system=system 1251config=system.iobus.master[8] 1252dma=system.iobus.slave[2] 1253pio=system.iobus.master[7] 1254 1255[system.realview.clcd] 1256type=Pl111 1257amba_id=1315089 1258clk_domain=system.clk_domain 1259gic=system.realview.gic 1260int_num=55 1261pio_addr=268566528 1262pio_latency=10000 1263pixel_clock=41667 1264system=system 1265vnc=system.vncserver 1266dma=system.iobus.slave[1] 1267pio=system.iobus.master[4] 1268 1269[system.realview.dmac_fake] 1270type=AmbaFake 1271amba_id=0 1272clk_domain=system.clk_domain 1273ignore_access=false 1274pio_addr=268632064 1275pio_latency=100000 1276system=system 1277pio=system.iobus.master[9] 1278 1279[system.realview.flash_fake] 1280type=IsaFake 1281clk_domain=system.clk_domain 1282fake_mem=true 1283pio_addr=1073741824 1284pio_latency=100000 1285pio_size=536870912 1286ret_bad_addr=false 1287ret_data16=65535 1288ret_data32=4294967295 1289ret_data64=18446744073709551615 1290ret_data8=255 1291system=system 1292update_data=false 1293warn_access= 1294pio=system.iobus.master[24] 1295 1296[system.realview.gic] 1297type=Pl390 1298clk_domain=system.clk_domain 1299cpu_addr=520093952 1300cpu_pio_delay=10000 1301dist_addr=520097792 1302dist_pio_delay=10000 1303int_latency=10000 1304it_lines=128 1305platform=system.realview 1306system=system 1307pio=system.membus.master[2] 1308 1309[system.realview.gpio0_fake] 1310type=AmbaFake 1311amba_id=0 1312clk_domain=system.clk_domain 1313ignore_access=false 1314pio_addr=268513280 1315pio_latency=100000 1316system=system 1317pio=system.iobus.master[16] 1318 1319[system.realview.gpio1_fake] 1320type=AmbaFake 1321amba_id=0 1322clk_domain=system.clk_domain 1323ignore_access=false 1324pio_addr=268517376 1325pio_latency=100000 1326system=system 1327pio=system.iobus.master[17] 1328 1329[system.realview.gpio2_fake] 1330type=AmbaFake 1331amba_id=0 1332clk_domain=system.clk_domain 1333ignore_access=false 1334pio_addr=268521472 1335pio_latency=100000 1336system=system 1337pio=system.iobus.master[18] 1338 1339[system.realview.kmi0] 1340type=Pl050 1341amba_id=1314896 1342clk_domain=system.clk_domain 1343gic=system.realview.gic 1344int_delay=1000000 1345int_num=52 1346is_mouse=false 1347pio_addr=268460032 1348pio_latency=100000 1349system=system 1350vnc=system.vncserver 1351pio=system.iobus.master[5] 1352 1353[system.realview.kmi1] 1354type=Pl050 1355amba_id=1314896 1356clk_domain=system.clk_domain 1357gic=system.realview.gic 1358int_delay=1000000 1359int_num=53 1360is_mouse=true 1361pio_addr=268464128 1362pio_latency=100000 1363system=system 1364vnc=system.vncserver 1365pio=system.iobus.master[6] 1366 1367[system.realview.l2x0_fake] 1368type=IsaFake 1369clk_domain=system.clk_domain 1370fake_mem=false 1371pio_addr=520101888 1372pio_latency=100000 1373pio_size=4095 1374ret_bad_addr=false 1375ret_data16=65535 1376ret_data32=4294967295 1377ret_data64=18446744073709551615 1378ret_data8=255 1379system=system 1380update_data=false 1381warn_access= 1382pio=system.membus.master[3] 1383 1384[system.realview.local_cpu_timer] 1385type=CpuLocalTimer 1386clk_domain=system.clk_domain 1387gic=system.realview.gic 1388int_num_timer=29 1389int_num_watchdog=30 1390pio_addr=520095232 1391pio_latency=100000 1392system=system 1393pio=system.membus.master[5] 1394 1395[system.realview.mmc_fake] 1396type=AmbaFake 1397amba_id=0 1398clk_domain=system.clk_domain 1399ignore_access=false 1400pio_addr=268455936 1401pio_latency=100000 1402system=system 1403pio=system.iobus.master[22] 1404 1405[system.realview.nvmem] 1406type=SimpleMemory 1407bandwidth=73.000000 1408clk_domain=system.clk_domain 1409conf_table_reported=false 1410in_addr_map=true 1411latency=30000 1412latency_var=0 1413null=false 1414range=2147483648:2214592511 1415port=system.membus.master[1] 1416 1417[system.realview.realview_io] 1418type=RealViewCtrl 1419clk_domain=system.clk_domain 1420idreg=0 1421pio_addr=268435456 1422pio_latency=100000 1423proc_id0=201326592 1424proc_id1=201327138 1425system=system 1426pio=system.iobus.master[1] 1427 1428[system.realview.rtc] 1429type=PL031 1430amba_id=3412017 1431clk_domain=system.clk_domain 1432gic=system.realview.gic 1433int_delay=100000 1434int_num=42 1435pio_addr=268529664 1436pio_latency=100000 1437system=system 1438time=Thu Jan 1 00:00:00 2009 1439pio=system.iobus.master[23] 1440 1441[system.realview.sci_fake] 1442type=AmbaFake 1443amba_id=0 1444clk_domain=system.clk_domain 1445ignore_access=false 1446pio_addr=268492800 1447pio_latency=100000 1448system=system 1449pio=system.iobus.master[20] 1450 1451[system.realview.smc_fake] 1452type=AmbaFake 1453amba_id=0 1454clk_domain=system.clk_domain 1455ignore_access=false 1456pio_addr=269357056 1457pio_latency=100000 1458system=system 1459pio=system.iobus.master[13] 1460 1461[system.realview.sp810_fake] 1462type=AmbaFake 1463amba_id=0 1464clk_domain=system.clk_domain 1465ignore_access=true 1466pio_addr=268439552 1467pio_latency=100000 1468system=system 1469pio=system.iobus.master[14] 1470 1471[system.realview.ssp_fake] 1472type=AmbaFake 1473amba_id=0 1474clk_domain=system.clk_domain 1475ignore_access=false 1476pio_addr=268488704 1477pio_latency=100000 1478system=system 1479pio=system.iobus.master[19] 1480 1481[system.realview.timer0] 1482type=Sp804 1483amba_id=1316868 1484clk_domain=system.clk_domain 1485clock0=1000000 1486clock1=1000000 1487gic=system.realview.gic 1488int_num0=36 1489int_num1=36 1490pio_addr=268505088 1491pio_latency=100000 1492system=system 1493pio=system.iobus.master[2] 1494 1495[system.realview.timer1] 1496type=Sp804 1497amba_id=1316868 1498clk_domain=system.clk_domain 1499clock0=1000000 1500clock1=1000000 1501gic=system.realview.gic 1502int_num0=37 1503int_num1=37 1504pio_addr=268509184 1505pio_latency=100000 1506system=system 1507pio=system.iobus.master[3] 1508 1509[system.realview.uart] 1510type=Pl011 1511clk_domain=system.clk_domain 1512end_on_eot=false 1513gic=system.realview.gic 1514int_delay=100000 1515int_num=44 1516pio_addr=268472320 1517pio_latency=100000 1518platform=system.realview 1519system=system 1520terminal=system.terminal 1521pio=system.iobus.master[0] 1522 1523[system.realview.uart1_fake] 1524type=AmbaFake 1525amba_id=0 1526clk_domain=system.clk_domain 1527ignore_access=false 1528pio_addr=268476416 1529pio_latency=100000 1530system=system 1531pio=system.iobus.master[10] 1532 1533[system.realview.uart2_fake] 1534type=AmbaFake 1535amba_id=0 1536clk_domain=system.clk_domain 1537ignore_access=false 1538pio_addr=268480512 1539pio_latency=100000 1540system=system 1541pio=system.iobus.master[11] 1542 1543[system.realview.uart3_fake] 1544type=AmbaFake 1545amba_id=0 1546clk_domain=system.clk_domain 1547ignore_access=false 1548pio_addr=268484608 1549pio_latency=100000 1550system=system 1551pio=system.iobus.master[12] 1552 1553[system.realview.watchdog_fake] 1554type=AmbaFake 1555amba_id=0 1556clk_domain=system.clk_domain 1557ignore_access=false 1558pio_addr=268500992 1559pio_latency=100000 1560system=system 1561pio=system.iobus.master[15] 1562 1563[system.terminal] 1564type=Terminal 1565intr_control=system.intrctrl 1566number=0 1567output=true 1568port=3456 1569 1570[system.toL2Bus] 1571type=CoherentBus 1572clk_domain=system.cpu_clk_domain 1573header_cycles=1 1574system=system 1575use_default_range=false 1576width=8 1577master=system.l2c.cpu_side 1578slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1579 1580[system.vncserver] 1581type=VncServer 1582frame_capture=false 1583number=0 1584port=5900 1585 1586[system.voltage_domain] 1587type=VoltageDomain 1588voltage=1.000000 1589 1590