config.ini revision 8983:8800b05e1cb3
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15flags_addr=268435504 16gic_cpu_addr=520093952 17init_param=0 18kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 19load_addr_mask=268435455 20machine_type=RealView_PBX 21mem_mode=timing 22memories=system.physmem system.realview.nvmem 23midr_regval=890224640 24num_work_ids=16 25readfile=tests/halt.sh 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge 38delay=50000 39nack_delay=4000 40ranges=268435456:520093695 1073741824:1610612735 41req_size=16 42resp_size=16 43write_ack=false 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cf0] 48type=IdeDisk 49children=image 50delay=1000000 51driveID=master 52image=system.cf0.image 53 54[system.cf0.image] 55type=CowDiskImage 56children=child 57child=system.cf0.image.child 58image_file= 59read_only=false 60table_size=65536 61 62[system.cf0.image.child] 63type=RawDiskImage 64image_file=/dist/m5/system/disks/linux-arm-ael.img 65read_only=true 66 67[system.cpu0] 68type=DerivO3CPU 69children=dcache dtb fuPool icache interrupts itb tracer 70BTBEntries=4096 71BTBTagSize=16 72LFSTSize=1024 73LQEntries=32 74LSQCheckLoads=true 75LSQDepCheckShift=4 76RASSize=16 77SQEntries=32 78SSITSize=1024 79activity=0 80backComSize=5 81cachePorts=200 82checker=Null 83choiceCtrBits=2 84choicePredictorSize=8192 85clock=500 86commitToDecodeDelay=1 87commitToFetchDelay=1 88commitToIEWDelay=1 89commitToRenameDelay=1 90commitWidth=8 91cpu_id=0 92decodeToFetchDelay=1 93decodeToRenameDelay=1 94decodeWidth=8 95defer_registration=false 96dispatchWidth=8 97do_checkpoint_insts=true 98do_quiesce=true 99do_statistics_insts=true 100dtb=system.cpu0.dtb 101fetchToDecodeDelay=1 102fetchTrapLatency=1 103fetchWidth=8 104forwardComSize=5 105fuPool=system.cpu0.fuPool 106function_trace=false 107function_trace_start=0 108globalCtrBits=2 109globalHistoryBits=13 110globalPredictorSize=8192 111iewToCommitDelay=1 112iewToDecodeDelay=1 113iewToFetchDelay=1 114iewToRenameDelay=1 115instShiftAmt=2 116interrupts=system.cpu0.interrupts 117issueToExecuteDelay=1 118issueWidth=8 119itb=system.cpu0.itb 120localCtrBits=2 121localHistoryBits=11 122localHistoryTableSize=2048 123localPredictorSize=2048 124max_insts_all_threads=0 125max_insts_any_thread=0 126max_loads_all_threads=0 127max_loads_any_thread=0 128needsTSO=false 129numIQEntries=64 130numPhysFloatRegs=256 131numPhysIntRegs=256 132numROBEntries=192 133numRobs=1 134numThreads=1 135phase=0 136predType=tournament 137profile=0 138progress_interval=0 139renameToDecodeDelay=1 140renameToFetchDelay=1 141renameToIEWDelay=2 142renameToROBDelay=1 143renameWidth=8 144smtCommitPolicy=RoundRobin 145smtFetchPolicy=SingleThread 146smtIQPolicy=Partitioned 147smtIQThreshold=100 148smtLSQPolicy=Partitioned 149smtLSQThreshold=100 150smtNumFetchingThreads=1 151smtROBPolicy=Partitioned 152smtROBThreshold=100 153squashWidth=8 154store_set_clear_period=250000 155system=system 156tracer=system.cpu0.tracer 157trapLatency=13 158wbDepth=1 159wbWidth=8 160workload= 161dcache_port=system.cpu0.dcache.cpu_side 162icache_port=system.cpu0.icache.cpu_side 163 164[system.cpu0.dcache] 165type=BaseCache 166addr_ranges=0:18446744073709551615 167assoc=4 168block_size=64 169forward_snoops=true 170hash_delay=1 171is_top_level=true 172latency=1000 173max_miss_count=0 174mshrs=4 175prefetch_on_access=false 176prefetcher=Null 177prioritizeRequests=false 178repl=Null 179size=32768 180subblock_size=0 181system=system 182tgts_per_mshr=20 183trace_addr=0 184two_queue=false 185write_buffers=8 186cpu_side=system.cpu0.dcache_port 187mem_side=system.toL2Bus.slave[1] 188 189[system.cpu0.dtb] 190type=ArmTLB 191children=walker 192size=64 193walker=system.cpu0.dtb.walker 194 195[system.cpu0.dtb.walker] 196type=ArmTableWalker 197max_backoff=100000 198min_backoff=0 199sys=system 200port=system.toL2Bus.slave[3] 201 202[system.cpu0.fuPool] 203type=FUPool 204children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 205FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 206 207[system.cpu0.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6 211opList=system.cpu0.fuPool.FUList0.opList 212 213[system.cpu0.fuPool.FUList0.opList] 214type=OpDesc 215issueLat=1 216opClass=IntAlu 217opLat=1 218 219[system.cpu0.fuPool.FUList1] 220type=FUDesc 221children=opList0 opList1 222count=2 223opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 224 225[system.cpu0.fuPool.FUList1.opList0] 226type=OpDesc 227issueLat=1 228opClass=IntMult 229opLat=3 230 231[system.cpu0.fuPool.FUList1.opList1] 232type=OpDesc 233issueLat=19 234opClass=IntDiv 235opLat=20 236 237[system.cpu0.fuPool.FUList2] 238type=FUDesc 239children=opList0 opList1 opList2 240count=4 241opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 242 243[system.cpu0.fuPool.FUList2.opList0] 244type=OpDesc 245issueLat=1 246opClass=FloatAdd 247opLat=2 248 249[system.cpu0.fuPool.FUList2.opList1] 250type=OpDesc 251issueLat=1 252opClass=FloatCmp 253opLat=2 254 255[system.cpu0.fuPool.FUList2.opList2] 256type=OpDesc 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu0.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 266 267[system.cpu0.fuPool.FUList3.opList0] 268type=OpDesc 269issueLat=1 270opClass=FloatMult 271opLat=4 272 273[system.cpu0.fuPool.FUList3.opList1] 274type=OpDesc 275issueLat=12 276opClass=FloatDiv 277opLat=12 278 279[system.cpu0.fuPool.FUList3.opList2] 280type=OpDesc 281issueLat=24 282opClass=FloatSqrt 283opLat=24 284 285[system.cpu0.fuPool.FUList4] 286type=FUDesc 287children=opList 288count=0 289opList=system.cpu0.fuPool.FUList4.opList 290 291[system.cpu0.fuPool.FUList4.opList] 292type=OpDesc 293issueLat=1 294opClass=MemRead 295opLat=1 296 297[system.cpu0.fuPool.FUList5] 298type=FUDesc 299children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 300count=4 301opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 302 303[system.cpu0.fuPool.FUList5.opList00] 304type=OpDesc 305issueLat=1 306opClass=SimdAdd 307opLat=1 308 309[system.cpu0.fuPool.FUList5.opList01] 310type=OpDesc 311issueLat=1 312opClass=SimdAddAcc 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList02] 316type=OpDesc 317issueLat=1 318opClass=SimdAlu 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList03] 322type=OpDesc 323issueLat=1 324opClass=SimdCmp 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList04] 328type=OpDesc 329issueLat=1 330opClass=SimdCvt 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList05] 334type=OpDesc 335issueLat=1 336opClass=SimdMisc 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList06] 340type=OpDesc 341issueLat=1 342opClass=SimdMult 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList07] 346type=OpDesc 347issueLat=1 348opClass=SimdMultAcc 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList08] 352type=OpDesc 353issueLat=1 354opClass=SimdShift 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList09] 358type=OpDesc 359issueLat=1 360opClass=SimdShiftAcc 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList10] 364type=OpDesc 365issueLat=1 366opClass=SimdSqrt 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList11] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatAdd 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList12] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatAlu 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList13] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatCmp 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList14] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatCvt 391opLat=1 392 393[system.cpu0.fuPool.FUList5.opList15] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatDiv 397opLat=1 398 399[system.cpu0.fuPool.FUList5.opList16] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatMisc 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList17] 406type=OpDesc 407issueLat=1 408opClass=SimdFloatMult 409opLat=1 410 411[system.cpu0.fuPool.FUList5.opList18] 412type=OpDesc 413issueLat=1 414opClass=SimdFloatMultAcc 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList19] 418type=OpDesc 419issueLat=1 420opClass=SimdFloatSqrt 421opLat=1 422 423[system.cpu0.fuPool.FUList6] 424type=FUDesc 425children=opList 426count=0 427opList=system.cpu0.fuPool.FUList6.opList 428 429[system.cpu0.fuPool.FUList6.opList] 430type=OpDesc 431issueLat=1 432opClass=MemWrite 433opLat=1 434 435[system.cpu0.fuPool.FUList7] 436type=FUDesc 437children=opList0 opList1 438count=4 439opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 440 441[system.cpu0.fuPool.FUList7.opList0] 442type=OpDesc 443issueLat=1 444opClass=MemRead 445opLat=1 446 447[system.cpu0.fuPool.FUList7.opList1] 448type=OpDesc 449issueLat=1 450opClass=MemWrite 451opLat=1 452 453[system.cpu0.fuPool.FUList8] 454type=FUDesc 455children=opList 456count=1 457opList=system.cpu0.fuPool.FUList8.opList 458 459[system.cpu0.fuPool.FUList8.opList] 460type=OpDesc 461issueLat=3 462opClass=IprAccess 463opLat=3 464 465[system.cpu0.icache] 466type=BaseCache 467addr_ranges=0:18446744073709551615 468assoc=1 469block_size=64 470forward_snoops=true 471hash_delay=1 472is_top_level=true 473latency=1000 474max_miss_count=0 475mshrs=4 476prefetch_on_access=false 477prefetcher=Null 478prioritizeRequests=false 479repl=Null 480size=32768 481subblock_size=0 482system=system 483tgts_per_mshr=20 484trace_addr=0 485two_queue=false 486write_buffers=8 487cpu_side=system.cpu0.icache_port 488mem_side=system.toL2Bus.slave[0] 489 490[system.cpu0.interrupts] 491type=ArmInterrupts 492 493[system.cpu0.itb] 494type=ArmTLB 495children=walker 496size=64 497walker=system.cpu0.itb.walker 498 499[system.cpu0.itb.walker] 500type=ArmTableWalker 501max_backoff=100000 502min_backoff=0 503sys=system 504port=system.toL2Bus.slave[2] 505 506[system.cpu0.tracer] 507type=ExeTracer 508 509[system.cpu1] 510type=DerivO3CPU 511children=dcache dtb fuPool icache interrupts itb tracer 512BTBEntries=4096 513BTBTagSize=16 514LFSTSize=1024 515LQEntries=32 516LSQCheckLoads=true 517LSQDepCheckShift=4 518RASSize=16 519SQEntries=32 520SSITSize=1024 521activity=0 522backComSize=5 523cachePorts=200 524checker=Null 525choiceCtrBits=2 526choicePredictorSize=8192 527clock=500 528commitToDecodeDelay=1 529commitToFetchDelay=1 530commitToIEWDelay=1 531commitToRenameDelay=1 532commitWidth=8 533cpu_id=1 534decodeToFetchDelay=1 535decodeToRenameDelay=1 536decodeWidth=8 537defer_registration=false 538dispatchWidth=8 539do_checkpoint_insts=true 540do_quiesce=true 541do_statistics_insts=true 542dtb=system.cpu1.dtb 543fetchToDecodeDelay=1 544fetchTrapLatency=1 545fetchWidth=8 546forwardComSize=5 547fuPool=system.cpu1.fuPool 548function_trace=false 549function_trace_start=0 550globalCtrBits=2 551globalHistoryBits=13 552globalPredictorSize=8192 553iewToCommitDelay=1 554iewToDecodeDelay=1 555iewToFetchDelay=1 556iewToRenameDelay=1 557instShiftAmt=2 558interrupts=system.cpu1.interrupts 559issueToExecuteDelay=1 560issueWidth=8 561itb=system.cpu1.itb 562localCtrBits=2 563localHistoryBits=11 564localHistoryTableSize=2048 565localPredictorSize=2048 566max_insts_all_threads=0 567max_insts_any_thread=0 568max_loads_all_threads=0 569max_loads_any_thread=0 570needsTSO=false 571numIQEntries=64 572numPhysFloatRegs=256 573numPhysIntRegs=256 574numROBEntries=192 575numRobs=1 576numThreads=1 577phase=0 578predType=tournament 579profile=0 580progress_interval=0 581renameToDecodeDelay=1 582renameToFetchDelay=1 583renameToIEWDelay=2 584renameToROBDelay=1 585renameWidth=8 586smtCommitPolicy=RoundRobin 587smtFetchPolicy=SingleThread 588smtIQPolicy=Partitioned 589smtIQThreshold=100 590smtLSQPolicy=Partitioned 591smtLSQThreshold=100 592smtNumFetchingThreads=1 593smtROBPolicy=Partitioned 594smtROBThreshold=100 595squashWidth=8 596store_set_clear_period=250000 597system=system 598tracer=system.cpu1.tracer 599trapLatency=13 600wbDepth=1 601wbWidth=8 602workload= 603dcache_port=system.cpu1.dcache.cpu_side 604icache_port=system.cpu1.icache.cpu_side 605 606[system.cpu1.dcache] 607type=BaseCache 608addr_ranges=0:18446744073709551615 609assoc=4 610block_size=64 611forward_snoops=true 612hash_delay=1 613is_top_level=true 614latency=1000 615max_miss_count=0 616mshrs=4 617prefetch_on_access=false 618prefetcher=Null 619prioritizeRequests=false 620repl=Null 621size=32768 622subblock_size=0 623system=system 624tgts_per_mshr=20 625trace_addr=0 626two_queue=false 627write_buffers=8 628cpu_side=system.cpu1.dcache_port 629mem_side=system.toL2Bus.slave[5] 630 631[system.cpu1.dtb] 632type=ArmTLB 633children=walker 634size=64 635walker=system.cpu1.dtb.walker 636 637[system.cpu1.dtb.walker] 638type=ArmTableWalker 639max_backoff=100000 640min_backoff=0 641sys=system 642port=system.toL2Bus.slave[7] 643 644[system.cpu1.fuPool] 645type=FUPool 646children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 647FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 648 649[system.cpu1.fuPool.FUList0] 650type=FUDesc 651children=opList 652count=6 653opList=system.cpu1.fuPool.FUList0.opList 654 655[system.cpu1.fuPool.FUList0.opList] 656type=OpDesc 657issueLat=1 658opClass=IntAlu 659opLat=1 660 661[system.cpu1.fuPool.FUList1] 662type=FUDesc 663children=opList0 opList1 664count=2 665opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 666 667[system.cpu1.fuPool.FUList1.opList0] 668type=OpDesc 669issueLat=1 670opClass=IntMult 671opLat=3 672 673[system.cpu1.fuPool.FUList1.opList1] 674type=OpDesc 675issueLat=19 676opClass=IntDiv 677opLat=20 678 679[system.cpu1.fuPool.FUList2] 680type=FUDesc 681children=opList0 opList1 opList2 682count=4 683opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 684 685[system.cpu1.fuPool.FUList2.opList0] 686type=OpDesc 687issueLat=1 688opClass=FloatAdd 689opLat=2 690 691[system.cpu1.fuPool.FUList2.opList1] 692type=OpDesc 693issueLat=1 694opClass=FloatCmp 695opLat=2 696 697[system.cpu1.fuPool.FUList2.opList2] 698type=OpDesc 699issueLat=1 700opClass=FloatCvt 701opLat=2 702 703[system.cpu1.fuPool.FUList3] 704type=FUDesc 705children=opList0 opList1 opList2 706count=2 707opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 708 709[system.cpu1.fuPool.FUList3.opList0] 710type=OpDesc 711issueLat=1 712opClass=FloatMult 713opLat=4 714 715[system.cpu1.fuPool.FUList3.opList1] 716type=OpDesc 717issueLat=12 718opClass=FloatDiv 719opLat=12 720 721[system.cpu1.fuPool.FUList3.opList2] 722type=OpDesc 723issueLat=24 724opClass=FloatSqrt 725opLat=24 726 727[system.cpu1.fuPool.FUList4] 728type=FUDesc 729children=opList 730count=0 731opList=system.cpu1.fuPool.FUList4.opList 732 733[system.cpu1.fuPool.FUList4.opList] 734type=OpDesc 735issueLat=1 736opClass=MemRead 737opLat=1 738 739[system.cpu1.fuPool.FUList5] 740type=FUDesc 741children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 742count=4 743opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 744 745[system.cpu1.fuPool.FUList5.opList00] 746type=OpDesc 747issueLat=1 748opClass=SimdAdd 749opLat=1 750 751[system.cpu1.fuPool.FUList5.opList01] 752type=OpDesc 753issueLat=1 754opClass=SimdAddAcc 755opLat=1 756 757[system.cpu1.fuPool.FUList5.opList02] 758type=OpDesc 759issueLat=1 760opClass=SimdAlu 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList03] 764type=OpDesc 765issueLat=1 766opClass=SimdCmp 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList04] 770type=OpDesc 771issueLat=1 772opClass=SimdCvt 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList05] 776type=OpDesc 777issueLat=1 778opClass=SimdMisc 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList06] 782type=OpDesc 783issueLat=1 784opClass=SimdMult 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList07] 788type=OpDesc 789issueLat=1 790opClass=SimdMultAcc 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList08] 794type=OpDesc 795issueLat=1 796opClass=SimdShift 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList09] 800type=OpDesc 801issueLat=1 802opClass=SimdShiftAcc 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList10] 806type=OpDesc 807issueLat=1 808opClass=SimdSqrt 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList11] 812type=OpDesc 813issueLat=1 814opClass=SimdFloatAdd 815opLat=1 816 817[system.cpu1.fuPool.FUList5.opList12] 818type=OpDesc 819issueLat=1 820opClass=SimdFloatAlu 821opLat=1 822 823[system.cpu1.fuPool.FUList5.opList13] 824type=OpDesc 825issueLat=1 826opClass=SimdFloatCmp 827opLat=1 828 829[system.cpu1.fuPool.FUList5.opList14] 830type=OpDesc 831issueLat=1 832opClass=SimdFloatCvt 833opLat=1 834 835[system.cpu1.fuPool.FUList5.opList15] 836type=OpDesc 837issueLat=1 838opClass=SimdFloatDiv 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList16] 842type=OpDesc 843issueLat=1 844opClass=SimdFloatMisc 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList17] 848type=OpDesc 849issueLat=1 850opClass=SimdFloatMult 851opLat=1 852 853[system.cpu1.fuPool.FUList5.opList18] 854type=OpDesc 855issueLat=1 856opClass=SimdFloatMultAcc 857opLat=1 858 859[system.cpu1.fuPool.FUList5.opList19] 860type=OpDesc 861issueLat=1 862opClass=SimdFloatSqrt 863opLat=1 864 865[system.cpu1.fuPool.FUList6] 866type=FUDesc 867children=opList 868count=0 869opList=system.cpu1.fuPool.FUList6.opList 870 871[system.cpu1.fuPool.FUList6.opList] 872type=OpDesc 873issueLat=1 874opClass=MemWrite 875opLat=1 876 877[system.cpu1.fuPool.FUList7] 878type=FUDesc 879children=opList0 opList1 880count=4 881opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 882 883[system.cpu1.fuPool.FUList7.opList0] 884type=OpDesc 885issueLat=1 886opClass=MemRead 887opLat=1 888 889[system.cpu1.fuPool.FUList7.opList1] 890type=OpDesc 891issueLat=1 892opClass=MemWrite 893opLat=1 894 895[system.cpu1.fuPool.FUList8] 896type=FUDesc 897children=opList 898count=1 899opList=system.cpu1.fuPool.FUList8.opList 900 901[system.cpu1.fuPool.FUList8.opList] 902type=OpDesc 903issueLat=3 904opClass=IprAccess 905opLat=3 906 907[system.cpu1.icache] 908type=BaseCache 909addr_ranges=0:18446744073709551615 910assoc=1 911block_size=64 912forward_snoops=true 913hash_delay=1 914is_top_level=true 915latency=1000 916max_miss_count=0 917mshrs=4 918prefetch_on_access=false 919prefetcher=Null 920prioritizeRequests=false 921repl=Null 922size=32768 923subblock_size=0 924system=system 925tgts_per_mshr=20 926trace_addr=0 927two_queue=false 928write_buffers=8 929cpu_side=system.cpu1.icache_port 930mem_side=system.toL2Bus.slave[4] 931 932[system.cpu1.interrupts] 933type=ArmInterrupts 934 935[system.cpu1.itb] 936type=ArmTLB 937children=walker 938size=64 939walker=system.cpu1.itb.walker 940 941[system.cpu1.itb.walker] 942type=ArmTableWalker 943max_backoff=100000 944min_backoff=0 945sys=system 946port=system.toL2Bus.slave[6] 947 948[system.cpu1.tracer] 949type=ExeTracer 950 951[system.intrctrl] 952type=IntrControl 953sys=system 954 955[system.iobus] 956type=Bus 957block_size=64 958bus_id=0 959clock=1000 960header_cycles=1 961use_default_range=false 962width=64 963master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 964slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 965 966[system.iocache] 967type=BaseCache 968addr_ranges=0:268435455 969assoc=8 970block_size=64 971forward_snoops=false 972hash_delay=1 973is_top_level=false 974latency=50000 975max_miss_count=0 976mshrs=20 977prefetch_on_access=false 978prefetcher=Null 979prioritizeRequests=false 980repl=Null 981size=1024 982subblock_size=0 983system=system 984tgts_per_mshr=12 985trace_addr=0 986two_queue=false 987write_buffers=8 988cpu_side=system.iobus.master[25] 989mem_side=system.membus.slave[1] 990 991[system.l2c] 992type=BaseCache 993addr_ranges=0:18446744073709551615 994assoc=8 995block_size=64 996forward_snoops=true 997hash_delay=1 998is_top_level=false 999latency=10000 1000max_miss_count=0 1001mshrs=92 1002prefetch_on_access=false 1003prefetcher=Null 1004prioritizeRequests=false 1005repl=Null 1006size=4194304 1007subblock_size=0 1008system=system 1009tgts_per_mshr=16 1010trace_addr=0 1011two_queue=false 1012write_buffers=8 1013cpu_side=system.toL2Bus.master[0] 1014mem_side=system.membus.slave[2] 1015 1016[system.membus] 1017type=Bus 1018children=badaddr_responder 1019block_size=64 1020bus_id=1 1021clock=1000 1022header_cycles=1 1023use_default_range=false 1024width=64 1025default=system.membus.badaddr_responder.pio 1026master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1027slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1028 1029[system.membus.badaddr_responder] 1030type=IsaFake 1031fake_mem=false 1032pio_addr=0 1033pio_latency=1000 1034pio_size=8 1035ret_bad_addr=true 1036ret_data16=65535 1037ret_data32=4294967295 1038ret_data64=18446744073709551615 1039ret_data8=255 1040system=system 1041update_data=false 1042warn_access=warn 1043pio=system.membus.default 1044 1045[system.physmem] 1046type=SimpleMemory 1047conf_table_reported=true 1048file= 1049in_addr_map=true 1050latency=30000 1051latency_var=0 1052null=false 1053range=0:134217727 1054zero=false 1055port=system.membus.master[2] 1056 1057[system.realview] 1058type=RealView 1059children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1060intrctrl=system.intrctrl 1061max_mem_size=268435456 1062mem_start_addr=0 1063pci_cfg_base=0 1064system=system 1065 1066[system.realview.a9scu] 1067type=A9SCU 1068pio_addr=520093696 1069pio_latency=1000 1070system=system 1071pio=system.membus.master[5] 1072 1073[system.realview.aaci_fake] 1074type=AmbaFake 1075amba_id=0 1076ignore_access=false 1077pio_addr=268451840 1078pio_latency=1000 1079system=system 1080pio=system.iobus.master[21] 1081 1082[system.realview.cf_ctrl] 1083type=IdeController 1084BAR0=402653184 1085BAR0LegacyIO=true 1086BAR0Size=16 1087BAR1=402653440 1088BAR1LegacyIO=true 1089BAR1Size=1 1090BAR2=1 1091BAR2LegacyIO=false 1092BAR2Size=8 1093BAR3=1 1094BAR3LegacyIO=false 1095BAR3Size=4 1096BAR4=1 1097BAR4LegacyIO=false 1098BAR4Size=16 1099BAR5=1 1100BAR5LegacyIO=false 1101BAR5Size=0 1102BIST=0 1103CacheLineSize=0 1104CardbusCIS=0 1105ClassCode=1 1106Command=1 1107DeviceID=28945 1108ExpansionROM=0 1109HeaderType=0 1110InterruptLine=31 1111InterruptPin=1 1112LatencyTimer=0 1113MaximumLatency=0 1114MinimumGrant=0 1115ProgIF=133 1116Revision=0 1117Status=640 1118SubClassCode=1 1119SubsystemID=0 1120SubsystemVendorID=0 1121VendorID=32902 1122config_latency=20000 1123ctrl_offset=2 1124disks=system.cf0 1125io_shift=1 1126max_backoff_delay=10000000 1127min_backoff_delay=4000 1128pci_bus=2 1129pci_dev=7 1130pci_func=0 1131pio_latency=1000 1132platform=system.realview 1133system=system 1134config=system.iobus.master[8] 1135dma=system.iobus.slave[2] 1136pio=system.iobus.master[7] 1137 1138[system.realview.clcd] 1139type=Pl111 1140amba_id=1315089 1141clock=41667 1142gic=system.realview.gic 1143int_num=55 1144max_backoff_delay=10000000 1145min_backoff_delay=4000 1146pio_addr=268566528 1147pio_latency=10000 1148system=system 1149vnc=system.vncserver 1150dma=system.iobus.slave[1] 1151pio=system.iobus.master[4] 1152 1153[system.realview.dmac_fake] 1154type=AmbaFake 1155amba_id=0 1156ignore_access=false 1157pio_addr=268632064 1158pio_latency=1000 1159system=system 1160pio=system.iobus.master[9] 1161 1162[system.realview.flash_fake] 1163type=IsaFake 1164fake_mem=true 1165pio_addr=1073741824 1166pio_latency=1000 1167pio_size=536870912 1168ret_bad_addr=false 1169ret_data16=65535 1170ret_data32=4294967295 1171ret_data64=18446744073709551615 1172ret_data8=255 1173system=system 1174update_data=false 1175warn_access= 1176pio=system.iobus.master[24] 1177 1178[system.realview.gic] 1179type=Gic 1180cpu_addr=520093952 1181cpu_pio_delay=10000 1182dist_addr=520097792 1183dist_pio_delay=10000 1184int_latency=10000 1185it_lines=128 1186platform=system.realview 1187system=system 1188pio=system.membus.master[3] 1189 1190[system.realview.gpio0_fake] 1191type=AmbaFake 1192amba_id=0 1193ignore_access=false 1194pio_addr=268513280 1195pio_latency=1000 1196system=system 1197pio=system.iobus.master[16] 1198 1199[system.realview.gpio1_fake] 1200type=AmbaFake 1201amba_id=0 1202ignore_access=false 1203pio_addr=268517376 1204pio_latency=1000 1205system=system 1206pio=system.iobus.master[17] 1207 1208[system.realview.gpio2_fake] 1209type=AmbaFake 1210amba_id=0 1211ignore_access=false 1212pio_addr=268521472 1213pio_latency=1000 1214system=system 1215pio=system.iobus.master[18] 1216 1217[system.realview.kmi0] 1218type=Pl050 1219amba_id=1314896 1220gic=system.realview.gic 1221int_delay=1000000 1222int_num=52 1223is_mouse=false 1224pio_addr=268460032 1225pio_latency=1000 1226system=system 1227vnc=system.vncserver 1228pio=system.iobus.master[5] 1229 1230[system.realview.kmi1] 1231type=Pl050 1232amba_id=1314896 1233gic=system.realview.gic 1234int_delay=1000000 1235int_num=53 1236is_mouse=true 1237pio_addr=268464128 1238pio_latency=1000 1239system=system 1240vnc=system.vncserver 1241pio=system.iobus.master[6] 1242 1243[system.realview.l2x0_fake] 1244type=IsaFake 1245fake_mem=false 1246pio_addr=520101888 1247pio_latency=1000 1248pio_size=4095 1249ret_bad_addr=false 1250ret_data16=65535 1251ret_data32=4294967295 1252ret_data64=18446744073709551615 1253ret_data8=255 1254system=system 1255update_data=false 1256warn_access= 1257pio=system.membus.master[4] 1258 1259[system.realview.local_cpu_timer] 1260type=CpuLocalTimer 1261clock=1000 1262gic=system.realview.gic 1263int_num_timer=29 1264int_num_watchdog=30 1265pio_addr=520095232 1266pio_latency=1000 1267system=system 1268pio=system.membus.master[6] 1269 1270[system.realview.mmc_fake] 1271type=AmbaFake 1272amba_id=0 1273ignore_access=false 1274pio_addr=268455936 1275pio_latency=1000 1276system=system 1277pio=system.iobus.master[22] 1278 1279[system.realview.nvmem] 1280type=SimpleMemory 1281conf_table_reported=false 1282file= 1283in_addr_map=true 1284latency=30000 1285latency_var=0 1286null=false 1287range=2147483648:2214592511 1288zero=true 1289port=system.membus.master[1] 1290 1291[system.realview.realview_io] 1292type=RealViewCtrl 1293idreg=0 1294pio_addr=268435456 1295pio_latency=1000 1296proc_id0=201326592 1297proc_id1=201327138 1298system=system 1299pio=system.iobus.master[1] 1300 1301[system.realview.rtc] 1302type=PL031 1303amba_id=3412017 1304gic=system.realview.gic 1305int_delay=100000 1306int_num=42 1307pio_addr=268529664 1308pio_latency=1000 1309system=system 1310time=Thu Jan 1 00:00:00 2009 1311pio=system.iobus.master[23] 1312 1313[system.realview.sci_fake] 1314type=AmbaFake 1315amba_id=0 1316ignore_access=false 1317pio_addr=268492800 1318pio_latency=1000 1319system=system 1320pio=system.iobus.master[20] 1321 1322[system.realview.smc_fake] 1323type=AmbaFake 1324amba_id=0 1325ignore_access=false 1326pio_addr=269357056 1327pio_latency=1000 1328system=system 1329pio=system.iobus.master[13] 1330 1331[system.realview.sp810_fake] 1332type=AmbaFake 1333amba_id=0 1334ignore_access=true 1335pio_addr=268439552 1336pio_latency=1000 1337system=system 1338pio=system.iobus.master[14] 1339 1340[system.realview.ssp_fake] 1341type=AmbaFake 1342amba_id=0 1343ignore_access=false 1344pio_addr=268488704 1345pio_latency=1000 1346system=system 1347pio=system.iobus.master[19] 1348 1349[system.realview.timer0] 1350type=Sp804 1351amba_id=1316868 1352clock0=1000000 1353clock1=1000000 1354gic=system.realview.gic 1355int_num0=36 1356int_num1=36 1357pio_addr=268505088 1358pio_latency=1000 1359system=system 1360pio=system.iobus.master[2] 1361 1362[system.realview.timer1] 1363type=Sp804 1364amba_id=1316868 1365clock0=1000000 1366clock1=1000000 1367gic=system.realview.gic 1368int_num0=37 1369int_num1=37 1370pio_addr=268509184 1371pio_latency=1000 1372system=system 1373pio=system.iobus.master[3] 1374 1375[system.realview.uart] 1376type=Pl011 1377end_on_eot=false 1378gic=system.realview.gic 1379int_delay=100000 1380int_num=44 1381pio_addr=268472320 1382pio_latency=1000 1383platform=system.realview 1384system=system 1385terminal=system.terminal 1386pio=system.iobus.master[0] 1387 1388[system.realview.uart1_fake] 1389type=AmbaFake 1390amba_id=0 1391ignore_access=false 1392pio_addr=268476416 1393pio_latency=1000 1394system=system 1395pio=system.iobus.master[10] 1396 1397[system.realview.uart2_fake] 1398type=AmbaFake 1399amba_id=0 1400ignore_access=false 1401pio_addr=268480512 1402pio_latency=1000 1403system=system 1404pio=system.iobus.master[11] 1405 1406[system.realview.uart3_fake] 1407type=AmbaFake 1408amba_id=0 1409ignore_access=false 1410pio_addr=268484608 1411pio_latency=1000 1412system=system 1413pio=system.iobus.master[12] 1414 1415[system.realview.watchdog_fake] 1416type=AmbaFake 1417amba_id=0 1418ignore_access=false 1419pio_addr=268500992 1420pio_latency=1000 1421system=system 1422pio=system.iobus.master[15] 1423 1424[system.terminal] 1425type=Terminal 1426intr_control=system.intrctrl 1427number=0 1428output=true 1429port=3456 1430 1431[system.toL2Bus] 1432type=Bus 1433block_size=64 1434bus_id=0 1435clock=1000 1436header_cycles=1 1437use_default_range=false 1438width=64 1439master=system.l2c.cpu_side 1440slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1441 1442[system.vncserver] 1443type=VncServer 1444frame_capture=false 1445number=0 1446port=5900 1447 1448