stats.txt revision 9285
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 1.855236 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 1855236450500 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79285Sandreas.hansson@arm.comhost_inst_rate 87142 # Simulator instruction rate (inst/s) 89285Sandreas.hansson@arm.comhost_op_rate 87142 # Simulator op (including micro ops) rate (op/s) 99285Sandreas.hansson@arm.comhost_tick_rate 3050446700 # Simulator tick rate (ticks/s) 109285Sandreas.hansson@arm.comhost_mem_usage 299400 # Number of bytes of host memory used 119285Sandreas.hansson@arm.comhost_seconds 608.19 # Real time elapsed on the host 129285Sandreas.hansson@arm.comsim_insts 52998368 # Number of instructions simulated 139285Sandreas.hansson@arm.comsim_ops 52998368 # Number of ops (including micro ops) simulated 149285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory 159285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory 169199Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179285Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28503040 # Number of bytes read from this memory 189285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory 199285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory 209285Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory 219285Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7522688 # Number of bytes written to this memory 229285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory 239285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory 249199Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259285Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445360 # Number of read requests responded to by this memory 269285Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory 279285Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117542 # Number of write requests responded to by this memory 289285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) 309285Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) 319285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) 329285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) 339285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) 349285Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) 359285Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) 369285Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) 379285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) 389285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) 399285Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) 409285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) 418464SN/Asystem.iocache.replacements 41685 # number of replacements 429285Sandreas.hansson@arm.comsystem.iocache.tagsinuse 1.255779 # Cycle average of tags in use 438464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 448464SN/Asystem.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 458464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 469285Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. 479285Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor 489285Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy 499285Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy 508835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 518464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 528835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 538464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 548835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 558464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 568835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 578464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 589096Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 599096Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 609285Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles 619285Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles 629285Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles 639285Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles 649285Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles 659285Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles 668835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 678464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 688835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 698464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 708835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 718464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 728835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 738464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 748835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 759055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 768835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 779055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 788835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 799055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 808835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 819055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 829096Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 839096Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 849285Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency 859285Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency 869285Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 879285Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency 889285Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 899285Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency 909285Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked 918464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 929285Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked 938464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 949285Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked 958983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 968464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 978464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 988835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 998835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 1008835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1018835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1028835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 1038835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 1048835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1058835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1068835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1078835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1089096Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 1099096Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 1109285Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles 1119285Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles 1129285Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles 1139285Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles 1149285Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles 1159285Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles 1168835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1179055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1188835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 1199055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1208835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1219055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1228835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1239055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1249096Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 1259096Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 1269285Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency 1279285Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency 1289285Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 1299285Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency 1309285Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 1319285Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency 1328464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1338464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1348464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1358464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1368464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1378464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1388464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 1398464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1408464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1418464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1428464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1438464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1448464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 1458464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1468464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1478464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1488464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1499285Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9942716 # DTB read hits 1509285Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 44791 # DTB read misses 1519285Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 565 # DTB read access violations 1529285Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 947396 # DTB read accesses 1539285Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6623666 # DTB write hits 1549285Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10259 # DTB write misses 1559285Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 393 # DTB write access violations 1569285Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 338396 # DTB write accesses 1579285Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16566382 # DTB hits 1589285Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 55050 # DTB misses 1599285Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 958 # DTB access violations 1609285Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1285792 # DTB accesses 1619285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1328947 # ITB hits 1629285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 38142 # ITB misses 1639285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1080 # ITB acv 1649285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1367089 # ITB accesses 1658464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1668464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1678464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 1688464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1698464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1708464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1718464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 1728464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1738464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 1748464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 1758464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 1768464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 1779285Sandreas.hansson@arm.comsystem.cpu.numCycles 112948398 # number of cpu cycles simulated 1788464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1798464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1809285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 13966796 # Number of BP lookups 1819285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted 1829285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect 1839285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups 1849285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits 1856006SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1869285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. 1879285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. 1889285Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss 1899285Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed 1909285Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered 1919285Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken 1929285Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked 1939285Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing 1949285Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked 1959285Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1969285Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps 1979285Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions 1989285Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR 1999285Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched 2009285Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed 2019285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) 2029285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) 2039285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) 2048464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2059285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) 2069285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) 2079285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) 2089285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) 2099285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) 2109285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) 2119285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) 2129285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) 2139285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) 2148464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2158464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2168464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2179285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) 2189285Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle 2199285Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle 2209285Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle 2219285Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked 2229285Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12232048 # Number of cycles decode is running 2239285Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking 2249285Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing 2259285Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch 2269285Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction 2279285Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode 2289285Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode 2299285Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing 2309285Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle 2319285Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking 2329285Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst 2339285Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11473805 # Number of cycles rename is running 2349285Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking 2359285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename 2369285Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full 2379285Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full 2389285Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full 2399285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed 2409285Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made 2419285Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups 2429285Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups 2439285Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed 2449285Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing 2459285Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed 2469285Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed 2479285Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer 2489285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. 2499285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. 2509285Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. 2519285Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. 2529285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) 2539285Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ 2549285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued 2559285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued 2569285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling 2579285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph 2589285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed 2599285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle 2609285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle 2619285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle 2628464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2639285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle 2649285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle 2659285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle 2669285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle 2679285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle 2689285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle 2699285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle 2709285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle 2719285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle 2728464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2738464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2748464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2759285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle 2768464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2779285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available 2789285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available 2799285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available 2809285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available 2819285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available 2829285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available 2839285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available 2849285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available 2859285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 2869285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available 2879285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available 2889285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available 2899285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available 2909285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available 2919285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available 2929285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available 2939285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available 2949285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available 2959285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available 2969285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available 2979285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available 2989285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available 2999285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available 3009285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available 3019285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available 3029285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available 3039285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available 3049285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available 3059285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 3069285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available 3079285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available 3088464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3098464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3109285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 3119285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued 3129285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued 3139285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued 3149285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued 3159285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued 3169285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued 3179285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued 3189285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued 3199285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued 3209285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued 3219285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued 3229285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued 3239285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued 3249285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued 3259285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued 3269285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued 3279285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued 3289285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued 3299285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued 3309285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued 3319285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued 3329285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued 3339285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued 3349285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued 3359285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued 3369285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued 3379285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued 3389285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued 3399285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued 3409285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued 3419285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued 3429285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued 3438464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3449285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 57074473 # Type of FU issued 3459285Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.505315 # Inst issue rate 3469285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 789329 # FU busy when requested 3479285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) 3489285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads 3499285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes 3509285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses 3519285Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads 3529285Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes 3539285Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses 3549285Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses 3559285Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses 3569285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores 3578464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3589285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed 3599285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed 3609285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations 3619285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed 3628464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 3638464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 3649285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled 3659285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked 3668464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 3679285Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing 3689285Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking 3699285Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking 3709285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ 3719285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch 3729285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions 3739285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions 3749285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions 3759285Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall 3769285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall 3779285Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations 3789285Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly 3799285Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly 3809285Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute 3819285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions 3829285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed 3839285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute 3848464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 3859285Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3555305 # number of nop insts executed 3869285Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16665522 # number of memory reference insts executed 3879285Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8969939 # Number of branches executed 3889285Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6649129 # Number of stores executed 3899285Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.500679 # Inst execution rate 3909285Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit 3919285Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 56121532 # cumulative count of insts written-back 3929285Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27804186 # num instructions producing a value 3939285Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37617732 # num instructions consuming a value 3948464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 3959285Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.496878 # insts written-back per cycle 3969285Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back 3978464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 3989285Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit 3999285Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards 4009285Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted 4019285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle 4029285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle 4039285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle 4048241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4059285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle 4069285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle 4079285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle 4089285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle 4099285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle 4109285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle 4119285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle 4129285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle 4139285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle 4148241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4158241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4168241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4179285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle 4189285Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56188905 # Number of instructions committed 4199285Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed 4208464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4219285Sandreas.hansson@arm.comsystem.cpu.commit.refs 15476867 # Number of memory references committed 4229285Sandreas.hansson@arm.comsystem.cpu.commit.loads 9095415 # Number of loads committed 4239285Sandreas.hansson@arm.comsystem.cpu.commit.membars 226300 # Number of memory barriers committed 4249285Sandreas.hansson@arm.comsystem.cpu.commit.branches 8447820 # Number of branches committed 4258517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 4269285Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52034961 # Number of committed integer instructions. 4279285Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740468 # Number of function calls committed. 4289285Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached 4298464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4309285Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 141682968 # The number of ROB reads 4319285Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 129465441 # The number of ROB writes 4329285Sandreas.hansson@arm.comsystem.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself 4339285Sandreas.hansson@arm.comsystem.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling 4349285Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 4359285Sandreas.hansson@arm.comsystem.cpu.committedInsts 52998368 # Number of Instructions Simulated 4369285Sandreas.hansson@arm.comsystem.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated 4379285Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52998368 # Number of Instructions Simulated 4389285Sandreas.hansson@arm.comsystem.cpu.cpi 2.131167 # CPI: Cycles Per Instruction 4399285Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads 4409285Sandreas.hansson@arm.comsystem.cpu.ipc 0.469226 # IPC: Instructions Per Cycle 4419285Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads 4429285Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 74144483 # number of integer regfile reads 4439285Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40484328 # number of integer regfile writes 4449285Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 165992 # number of floating regfile reads 4459285Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167427 # number of floating regfile writes 4469285Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1993361 # number of misc regfile reads 4479285Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 946826 # number of misc regfile writes 4488464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 4498464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 4508464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 4518464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 4528464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 4538983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 4548464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 4558464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 4568983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 4578464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 4588464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 4598983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 4608464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 4618464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 4628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 4638464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 4648464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 4658983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4668464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4678464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4688983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4698464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4708464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4718983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4728464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4738464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4748983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4758464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4768983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4778464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4788464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 4799285Sandreas.hansson@arm.comsystem.cpu.icache.replacements 1020348 # number of replacements 4809285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use 4819285Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. 4829285Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. 4839285Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. 4849285Sandreas.hansson@arm.comsystem.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. 4859285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor 4869285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy 4879285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy 4889285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits 4899285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits 4909285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits 4919285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits 4929285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits 4939285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7661721 # number of overall hits 4949285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses 4959285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses 4969285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses 4979285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses 4989285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses 4999285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1079749 # number of overall misses 5009285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles 5019285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles 5029285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles 5039285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles 5049285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles 5059285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles 5069285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) 5079285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) 5089285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses 5099285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses 5109285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses 5119285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses 5129285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses 5139285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses 5149285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses 5159285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses 5169285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses 5179285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses 5189285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency 5199285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency 5209285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 5219285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency 5229285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 5239285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency 5249285Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked 5258464SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5269285Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked 5278464SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5289285Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked 5298983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5308464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5318464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5329285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits 5339285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits 5349285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits 5359285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits 5369285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits 5379285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits 5389285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses 5399285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses 5409285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses 5419285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses 5429285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses 5439285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses 5449285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles 5459285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles 5469285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles 5479285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles 5489285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles 5499285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles 5509285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses 5519285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses 5529285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses 5539285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses 5549285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses 5559285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses 5569285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency 5579285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency 5589285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 5599285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency 5609285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 5619285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency 5628464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5639285Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 1402622 # number of replacements 5649285Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use 5659285Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. 5669285Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. 5679285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. 5689285Sandreas.hansson@arm.comsystem.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. 5699285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor 5709199Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 5719199Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy 5729285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits 5739285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits 5749285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits 5759285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits 5769285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits 5779285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits 5789285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits 5799285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits 5809285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits 5819285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits 5829285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits 5839285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11479559 # number of overall hits 5849285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses 5859285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses 5869285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses 5879285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses 5889285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses 5899285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses 5909285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 5919285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 5929285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses 5939285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses 5949285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses 5959285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3739889 # number of overall misses 5969285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles 5979285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles 5989285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles 5999285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles 6009285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles 6019285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles 6029285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 6039285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 6049285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles 6059285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles 6069285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles 6079285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles 6089285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) 6099285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) 6109285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) 6119285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses) 6129285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses) 6139285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses) 6149285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses) 6159285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses) 6169285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses 6179285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses 6189285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses 6199285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses 6209285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses 6219285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses 6229285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses 6239285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses 6249285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses 6259285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses 6269285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 6279285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 6289285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses 6299285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses 6309285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses 6319285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses 6329285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency 6339285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency 6349285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency 6359285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency 6369285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency 6379285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency 6389285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 6399285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 6409285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 6419285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency 6429285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 6439285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency 6449285Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked 6459285Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked 6469285Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked 6479285Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 6489285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked 6499285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked 6508464SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 6518464SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 6529285Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 841878 # number of writebacks 6539285Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 841878 # number of writebacks 6549285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits 6559285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits 6569285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits 6579285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits 6589285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits 6599285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits 6609285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits 6619285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits 6629285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits 6639285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits 6649285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses 6659285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses 6669285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses 6679285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses 6689285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses 6699285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses 6709285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 6719285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 6729285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses 6739285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses 6749285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses 6759285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses 6769285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles 6779285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles 6789285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles 6799285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles 6809285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles 6819285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles 6829285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 6839285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 6849285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles 6859285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles 6869285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles 6879285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles 6889285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles 6899285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles 6909285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles 6919285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles 6929285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles 6939285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles 6949285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses 6959285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses 6969285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses 6979285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses 6989285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses 6999285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses 7009285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 7019285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 7029285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses 7039285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses 7049285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses 7059285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses 7069285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency 7079285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency 7089285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency 7099285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency 7109285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency 7119285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency 7129285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 7139285Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 7149285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 7159285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency 7169285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 7179285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency 7188835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 7199055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 7208835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 7219055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 7228835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 7239055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 7248464SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7259285Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 338417 # number of replacements 7269285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use 7279285Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. 7289285Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. 7299285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. 7309285Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. 7319285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor 7329285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor 7339285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor 7349285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy 7359285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy 7369285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy 7379285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy 7389285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits 7399285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits 7409285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits 7419285Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits 7429285Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits 7439285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 7449285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 7459285Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 7469285Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 7479285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits 7489285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits 7499285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1005811 # number of demand (read+write) hits 7509285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits 7519285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2019767 # number of demand (read+write) hits 7529285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1005811 # number of overall hits 7539285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits 7549285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2019767 # number of overall hits 7559285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15151 # number of ReadReq misses 7569285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses 7579285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses 7589285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses 7599285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses 7609285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses 7619285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses 7629285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses 7639285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses 7649285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses 7659285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses 7669285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses 7679285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404416 # number of overall misses 7689285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles 7699285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles 7709285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles 7719285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles 7729285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles 7739285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles 7749285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles 7759285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles 7769285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles 7779285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles 7789285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles 7799285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles 7809285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles 7819285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) 7829285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) 7839285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) 7849285Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses) 7859285Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses) 7869285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses) 7879285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses) 7889285Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 7899285Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 7909285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses) 7919285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses) 7929285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1020962 # number of demand (read+write) accesses 7939285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses 7949285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2424183 # number of demand (read+write) accesses 7959285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1020962 # number of overall (read+write) accesses 7969285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses 7979285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses 7989285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014840 # miss rate for ReadReq accesses 7999285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses 8009285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses 8019285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses 8029285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses 8039285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses 8049285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses 8059285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses 8069285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses 8079285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses 8089285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses 8099285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses 8109285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses 8119285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency 8129285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency 8139285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency 8149285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency 8159285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency 8169285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency 8179285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency 8189285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 8199285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 8209285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency 8219285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 8229285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 8239285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency 8249285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8259285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8269285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8279285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8289285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8299285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8309285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8319285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8329285Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks 8339285Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 76030 # number of writebacks 8349285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 8359285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 8369285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 8379285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 8389285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 8399285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 8409285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses 8419285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses 8429285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses 8439285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses 8449285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses 8459285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses 8469285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses 8479285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses 8489285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses 8499285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses 8509285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses 8519285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses 8529285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses 8539285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles 8549285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles 8559285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles 8569285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles 8579285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles 8589285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles 8599285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles 8609285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles 8619285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles 8629285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles 8639285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles 8649285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles 8659285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles 8669285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles 8679285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles 8689285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles 8699285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles 8709285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles 8719285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles 8729285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses 8739285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses 8749285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses 8759285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses 8769285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses 8779285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses 8789285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses 8799285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses 8809285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses 8819285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses 8829285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses 8839285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses 8849285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses 8859285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency 8869285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency 8879285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency 8889285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency 8899285Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency 8909285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency 8919285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency 8929285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 8939285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 8949285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 8959285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 8969285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 8979285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 8989285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 8999285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 9009285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 9019285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 9029285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 9039285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 9049285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9055703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 9069285Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 9079285Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed 9089285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl 9099285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 9109285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 9119285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl 9129285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl 9139285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl 9149285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 9159285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 9169285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl 9179285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl 9189285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl 9199285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl 9209285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl 9219285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl 9229285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl 9239285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl 9246127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 9256127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 9269285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl 9279285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl 9286291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 9296291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 9306291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 9316291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 9326291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 9336291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 9346291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 9356291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 9366291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 9376291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 9386291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 9396291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 9406291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 9416291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 9426291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 9436291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 9446291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 9456291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 9466291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 9476291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 9486291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 9496291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 9506291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 9516291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 9526291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 9536291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 9546291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 9556291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 9566291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 9576291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 9586127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 9598464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 9608464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 9618464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 9628464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 9639285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 9649285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 9659199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 9669285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed 9679285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 9689285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 9699199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 9709285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 9719285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 9729285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed 9738464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 9748464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 9759285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191902 # number of callpals executed 9769285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches 9779285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 9789285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 9799285Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 9809285Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1739 9818517SN/Asystem.cpu.kern.mode_good::idle 170 9829285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches 9838464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 9849285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 9859285Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 9869285Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode 9879285Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode 9889285Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode 9898517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 9905703SN/A 9915703SN/A---------- End Simulation Statistics ---------- 992