stats.txt revision 9285
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.855236 # Number of seconds simulated 4sim_ticks 1855236450500 # Number of ticks simulated 5final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 87142 # Simulator instruction rate (inst/s) 8host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3050446700 # Simulator tick rate (ticks/s) 10host_mem_usage 299400 # Number of bytes of host memory used 11host_seconds 608.19 # Real time elapsed on the host 12sim_insts 52998368 # Number of instructions simulated 13sim_ops 52998368 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) 41system.iocache.replacements 41685 # number of replacements 42system.iocache.tagsinuse 1.255779 # Cycle average of tags in use 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. 46system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy 50system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 57system.iocache.overall_misses::total 41725 # number of overall misses 58system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 59system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 60system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles 61system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles 62system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles 63system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles 64system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles 65system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles 66system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 68system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 70system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 72system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 74system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency 90system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked 94system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 141system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 142system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 143system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 144system.disk2.dma_write_txs 1 # Number of DMA write transactions. 145system.cpu.dtb.fetch_hits 0 # ITB hits 146system.cpu.dtb.fetch_misses 0 # ITB misses 147system.cpu.dtb.fetch_acv 0 # ITB acv 148system.cpu.dtb.fetch_accesses 0 # ITB accesses 149system.cpu.dtb.read_hits 9942716 # DTB read hits 150system.cpu.dtb.read_misses 44791 # DTB read misses 151system.cpu.dtb.read_acv 565 # DTB read access violations 152system.cpu.dtb.read_accesses 947396 # DTB read accesses 153system.cpu.dtb.write_hits 6623666 # DTB write hits 154system.cpu.dtb.write_misses 10259 # DTB write misses 155system.cpu.dtb.write_acv 393 # DTB write access violations 156system.cpu.dtb.write_accesses 338396 # DTB write accesses 157system.cpu.dtb.data_hits 16566382 # DTB hits 158system.cpu.dtb.data_misses 55050 # DTB misses 159system.cpu.dtb.data_acv 958 # DTB access violations 160system.cpu.dtb.data_accesses 1285792 # DTB accesses 161system.cpu.itb.fetch_hits 1328947 # ITB hits 162system.cpu.itb.fetch_misses 38142 # ITB misses 163system.cpu.itb.fetch_acv 1080 # ITB acv 164system.cpu.itb.fetch_accesses 1367089 # ITB accesses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.read_acv 0 # DTB read access violations 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.write_hits 0 # DTB write hits 170system.cpu.itb.write_misses 0 # DTB write misses 171system.cpu.itb.write_acv 0 # DTB write access violations 172system.cpu.itb.write_accesses 0 # DTB write accesses 173system.cpu.itb.data_hits 0 # DTB hits 174system.cpu.itb.data_misses 0 # DTB misses 175system.cpu.itb.data_acv 0 # DTB access violations 176system.cpu.itb.data_accesses 0 # DTB accesses 177system.cpu.numCycles 112948398 # number of cpu cycles simulated 178system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 179system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 180system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups 181system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted 182system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect 183system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups 184system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits 185system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 186system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. 187system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. 188system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss 189system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed 190system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered 191system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken 192system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked 193system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing 194system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked 195system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 196system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps 197system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions 198system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR 199system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched 200system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed 201system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) 204system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle 219system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle 220system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle 221system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked 222system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running 223system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking 224system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing 225system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch 226system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction 227system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode 228system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode 229system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed 240system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made 241system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups 242system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups 243system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed 244system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing 245system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed 246system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed 247system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer 248system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. 249system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. 250system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. 251system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. 252system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) 253system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ 254system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued 255system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued 256system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling 257system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph 258system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed 259system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle 276system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 277system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available 278system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available 279system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available 280system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 306system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available 307system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available 308system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 309system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 310system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 311system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued 312system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued 313system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued 314system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued 315system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued 316system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued 340system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued 341system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued 342system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued 343system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 344system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued 345system.cpu.iq.rate 0.505315 # Inst issue rate 346system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested 347system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) 348system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads 349system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes 350system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses 351system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads 352system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes 353system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses 354system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses 355system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses 356system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores 357system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 358system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed 359system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed 360system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations 361system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed 362system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 363system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 364system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled 365system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked 366system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 367system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing 368system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking 369system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking 370system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ 371system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch 372system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions 373system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions 374system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions 375system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall 376system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall 377system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations 378system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly 379system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly 380system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute 381system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions 382system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed 383system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute 384system.cpu.iew.exec_swp 0 # number of swp insts executed 385system.cpu.iew.exec_nop 3555305 # number of nop insts executed 386system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed 387system.cpu.iew.exec_branches 8969939 # Number of branches executed 388system.cpu.iew.exec_stores 6649129 # Number of stores executed 389system.cpu.iew.exec_rate 0.500679 # Inst execution rate 390system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit 391system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back 392system.cpu.iew.wb_producers 27804186 # num instructions producing a value 393system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value 394system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 395system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle 396system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back 397system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 398system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit 399system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards 400system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted 401system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle 418system.cpu.commit.committedInsts 56188905 # Number of instructions committed 419system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed 420system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 421system.cpu.commit.refs 15476867 # Number of memory references committed 422system.cpu.commit.loads 9095415 # Number of loads committed 423system.cpu.commit.membars 226300 # Number of memory barriers committed 424system.cpu.commit.branches 8447820 # Number of branches committed 425system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 426system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. 427system.cpu.commit.function_calls 740468 # Number of function calls committed. 428system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached 429system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 430system.cpu.rob.rob_reads 141682968 # The number of ROB reads 431system.cpu.rob.rob_writes 129465441 # The number of ROB writes 432system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself 433system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling 434system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 435system.cpu.committedInsts 52998368 # Number of Instructions Simulated 436system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated 438system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads 440system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 74144483 # number of integer regfile reads 443system.cpu.int_regfile_writes 40484328 # number of integer regfile writes 444system.cpu.fp_regfile_reads 165992 # number of floating regfile reads 445system.cpu.fp_regfile_writes 167427 # number of floating regfile writes 446system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads 447system.cpu.misc_regfile_writes 946826 # number of misc regfile writes 448system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 449system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 450system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 451system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 452system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 453system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 454system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 455system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 456system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 457system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 458system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 459system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 460system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 461system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 462system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 463system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 464system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 465system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 466system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 467system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 468system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 469system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 470system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 471system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 472system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 473system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 474system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 475system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 476system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 477system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 478system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 479system.cpu.icache.replacements 1020348 # number of replacements 480system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use 481system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. 482system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. 483system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. 484system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. 485system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor 486system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy 487system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy 488system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits 489system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits 490system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits 491system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits 492system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits 493system.cpu.icache.overall_hits::total 7661721 # number of overall hits 494system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses 495system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses 496system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses 497system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses 498system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses 499system.cpu.icache.overall_misses::total 1079749 # number of overall misses 500system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles 501system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles 502system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles 503system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles 504system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles 505system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles 506system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) 507system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) 508system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses 509system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses 510system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses 511system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses 512system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses 513system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses 514system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses 515system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses 516system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses 517system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses 518system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency 519system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency 520system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 521system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency 522system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 523system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency 524system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked 525system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 526system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked 527system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 528system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked 529system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 530system.cpu.icache.fast_writes 0 # number of fast writes performed 531system.cpu.icache.cache_copies 0 # number of cache copies performed 532system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits 533system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits 534system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits 535system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits 536system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits 537system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 563system.cpu.dcache.replacements 1402622 # number of replacements 564system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use 565system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits 583system.cpu.dcache.overall_hits::total 11479559 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses 590system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 591system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 592system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses 593system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses 594system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses 595system.cpu.dcache.overall_misses::total 3739889 # number of overall misses 596system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles 597system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles 608system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses) 612system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses) 613system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses) 614system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses) 615system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses) 616system.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses 617system.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses 618system.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses 619system.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses 620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses 624system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses 625system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses 626system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 627system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency 636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency 637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency 638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked 645system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked 649system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed 652system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks 653system.cpu.dcache.writebacks::total 841878 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits 658system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits 659system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits 662system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits 663system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits 664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses 665system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses 668system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses 669system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses 670system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 671system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 672system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses 673system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses 674system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses 675system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses 676system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles 681system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles 682system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 683system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles 689system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles 690system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles 691system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles 692system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles 693system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles 694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses 695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses 699system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses 700system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 701system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency 710system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency 711system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency 712system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 713system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency 718system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 719system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 720system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 721system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 722system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 723system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 724system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 725system.cpu.l2cache.replacements 338417 # number of replacements 726system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use 727system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. 728system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. 729system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. 730system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. 731system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor 732system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor 733system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor 734system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy 735system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy 736system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy 737system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy 738system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits 739system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits 741system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits 742system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits 743system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 744system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 745system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 746system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 747system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits 748system.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits 749system.cpu.l2cache.demand_hits::cpu.inst 1005811 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits 751system.cpu.l2cache.demand_hits::total 2019767 # number of demand (read+write) hits 752system.cpu.l2cache.overall_hits::cpu.inst 1005811 # number of overall hits 753system.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits 754system.cpu.l2cache.overall_hits::total 2019767 # number of overall hits 755system.cpu.l2cache.ReadReq_misses::cpu.inst 15151 # number of ReadReq misses 756system.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses 757system.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses 758system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses 759system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses 760system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses 761system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses 762system.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses 763system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses 764system.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses 765system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses 766system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses 767system.cpu.l2cache.overall_misses::total 404416 # number of overall misses 768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles 769system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles 770system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles 771system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles 772system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles 773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles 774system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles 775system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles 776system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles 777system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles 778system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles 779system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles 780system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles 781system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) 782system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) 783system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses) 785system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses) 786system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses) 787system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses) 788system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 789system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses) 792system.cpu.l2cache.demand_accesses::cpu.inst 1020962 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses 794system.cpu.l2cache.demand_accesses::total 2424183 # number of demand (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.inst 1020962 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses 797system.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014840 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency 813system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency 814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency 815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed 832system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks 833system.cpu.l2cache.writebacks::total 76030 # number of writebacks 834system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 835system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 836system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 837system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 838system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 839system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 840system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses 842system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses 843system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses 844system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses 853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles 857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles 865system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles 866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles 868system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles 869system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles 870system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles 871system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles 872system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses 873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses 875system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses 876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses 877system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses 879system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses 880system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses 881system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses 882system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses 883system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses 884system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses 885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency 887system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency 888system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency 889system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency 890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency 891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 898system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 899system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 900system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 901system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 902system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 903system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 904system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.cpu.kern.inst.arm 0 # number of arm instructions executed 906system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 907system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed 908system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl 909system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 910system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 911system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl 912system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl 913system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl 914system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 915system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 916system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl 917system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl 919system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl 920system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl 921system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl 922system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl 923system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl 924system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 925system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 926system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl 927system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl 928system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 929system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 930system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 931system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 932system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 933system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 934system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 935system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 936system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 937system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 938system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 939system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 940system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 941system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 942system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 943system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 944system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 945system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 946system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 947system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 948system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 949system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 950system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 951system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 952system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 953system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 954system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 955system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 956system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 957system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 958system.cpu.kern.syscall::total 326 # number of syscalls executed 959system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 960system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 961system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 962system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 963system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 964system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 965system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 966system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed 967system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 968system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 969system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 970system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 971system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 972system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed 973system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 974system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 975system.cpu.kern.callpal::total 191902 # number of callpals executed 976system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches 977system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 978system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 979system.cpu.kern.mode_good::kernel 1909 980system.cpu.kern.mode_good::user 1739 981system.cpu.kern.mode_good::idle 170 982system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches 983system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 984system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 985system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 986system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode 987system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode 988system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode 989system.cpu.kern.swap_context 4177 # number of times the context was actually changed 990 991---------- End Simulation Statistics ---------- 992