stats.txt revision 11336
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 1.875758 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 1875758115500 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 1875758115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711336Sandreas.hansson@arm.comhost_inst_rate 136821 # Simulator instruction rate (inst/s) 811336Sandreas.hansson@arm.comhost_op_rate 136821 # Simulator op (including micro ops) rate (op/s) 911336Sandreas.hansson@arm.comhost_tick_rate 4844017901 # Simulator tick rate (ticks/s) 1011336Sandreas.hansson@arm.comhost_mem_usage 335520 # Number of bytes of host memory used 1111336Sandreas.hansson@arm.comhost_seconds 387.23 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 52981544 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 52981544 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory 1711336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24881024 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1911336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25840192 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory 2211336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7524864 # Number of bytes written to this memory 2411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory 2511336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388766 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2711336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 403753 # Number of read requests responded to by this memory 2811336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory 2911336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117576 # Number of write requests responded to by this memory 3011336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 510838 # Total read bandwidth from this memory (bytes/s) 3111336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13264516 # Total read bandwidth from this memory (bytes/s) 3211138Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 3311336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13775866 # Total read bandwidth from this memory (bytes/s) 3411336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 510838 # Instruction read bandwidth from this memory (bytes/s) 3511336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 510838 # Instruction read bandwidth from this memory (bytes/s) 3611336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4011639 # Write bandwidth from this memory (bytes/s) 3711336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4011639 # Write bandwidth from this memory (bytes/s) 3811336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4011639 # Total bandwidth to/from this memory (bytes/s) 3911336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 510838 # Total bandwidth to/from this memory (bytes/s) 4011336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13264516 # Total bandwidth to/from this memory (bytes/s) 4111138Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 4211336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17787505 # Total bandwidth to/from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.readReqs 403753 # Number of read requests accepted 4411336Sandreas.hansson@arm.comsystem.physmem.writeReqs 117576 # Number of write requests accepted 4511336Sandreas.hansson@arm.comsystem.physmem.readBursts 403753 # Number of DRAM read bursts, including those serviced by the write queue 4611336Sandreas.hansson@arm.comsystem.physmem.writeBursts 117576 # Number of DRAM write bursts, including those merged in the write queue 4711336Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25832384 # Total number of bytes read from DRAM 4811336Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue 4911336Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7523392 # Total number of bytes written to DRAM 5011336Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25840192 # Total read bytes from the system interface side 5111336Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7524864 # Total written bytes from the system interface side 5211336Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue 5310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5511336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25611 # Per bank write bursts 5611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25424 # Per bank write bursts 5711336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25556 # Per bank write bursts 5811336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25503 # Per bank write bursts 5911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25379 # Per bank write bursts 6011336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 24725 # Per bank write bursts 6111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 24941 # Per bank write bursts 6211336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25083 # Per bank write bursts 6311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 24938 # Per bank write bursts 6411336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25019 # Per bank write bursts 6511336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25561 # Per bank write bursts 6611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24881 # Per bank write bursts 6711336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24458 # Per bank write bursts 6811336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25273 # Per bank write bursts 6911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25708 # Per bank write bursts 7011336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25571 # Per bank write bursts 7111336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7931 # Per bank write bursts 7211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7523 # Per bank write bursts 7311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7959 # Per bank write bursts 7411336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7526 # Per bank write bursts 7511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7322 # Per bank write bursts 7611336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6664 # Per bank write bursts 7711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6770 # Per bank write bursts 7811336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6720 # Per bank write bursts 7911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7147 # Per bank write bursts 8011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6703 # Per bank write bursts 8111336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7408 # Per bank write bursts 8211336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6973 # Per bank write bursts 8311336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7144 # Per bank write bursts 8411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7893 # Per bank write bursts 8511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8063 # Per bank write bursts 8611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7807 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811336Sandreas.hansson@arm.comsystem.physmem.numWrRetry 5 # Number of times write queue was full causing retry 8911336Sandreas.hansson@arm.comsystem.physmem.totGap 1875752798500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611336Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 403753 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311336Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117576 # Write request sizes (log2) 10411336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 315454 # What read queue length does an incoming req see 10511336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 35859 # What read queue length does an incoming req see 10611336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 28166 # What read queue length does an incoming req see 10711336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 24058 # What read queue length does an incoming req see 10811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see 10911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see 11010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1604 # What write queue length does an incoming req see 15211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see 15311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 4997 # What write queue length does an incoming req see 15411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4497 # What write queue length does an incoming req see 15511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see 15611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6077 # What write queue length does an incoming req see 15711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5895 # What write queue length does an incoming req see 15811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 6436 # What write queue length does an incoming req see 15911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 6919 # What write queue length does an incoming req see 16011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 6498 # What write queue length does an incoming req see 16111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8426 # What write queue length does an incoming req see 16211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 8816 # What write queue length does an incoming req see 16311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7437 # What write queue length does an incoming req see 16411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see 16511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 8393 # What write queue length does an incoming req see 16611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7415 # What write queue length does an incoming req see 16711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6659 # What write queue length does an incoming req see 16811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5777 # What write queue length does an incoming req see 16911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see 17011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see 17111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see 17211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see 17311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see 17411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 212 # What write queue length does an incoming req see 17511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see 17611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 217 # What write queue length does an incoming req see 17711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 170 # What write queue length does an incoming req see 17811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see 17911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 214 # What write queue length does an incoming req see 18011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 137 # What write queue length does an incoming req see 18111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see 18211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 247 # What write queue length does an incoming req see 18311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see 18411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 198 # What write queue length does an incoming req see 18511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 254 # What write queue length does an incoming req see 18611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 173 # What write queue length does an incoming req see 18711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see 18811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see 18911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see 19011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see 19111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see 19211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 19311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 19411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see 19511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see 19611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 19711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see 19811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 19911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see 20011336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62096 # Bytes accessed per row activation 20111336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 537.164648 # Bytes accessed per row activation 20211336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 331.293750 # Bytes accessed per row activation 20311336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 411.963299 # Bytes accessed per row activation 20411336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13665 22.01% 22.01% # Bytes accessed per row activation 20511336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10559 17.00% 39.01% # Bytes accessed per row activation 20611336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4854 7.82% 46.83% # Bytes accessed per row activation 20711336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2778 4.47% 51.30% # Bytes accessed per row activation 20811336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2418 3.89% 55.20% # Bytes accessed per row activation 20911336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1622 2.61% 57.81% # Bytes accessed per row activation 21011336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3711 5.98% 63.78% # Bytes accessed per row activation 21111336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1214 1.96% 65.74% # Bytes accessed per row activation 21211336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 21275 34.26% 100.00% # Bytes accessed per row activation 21311336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62096 # Bytes accessed per row activation 21411336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5200 # Reads before turning the bus around for writes 21511336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 77.619423 # Reads before turning the bus around for writes 21611336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2241.505208 # Reads before turning the bus around for writes 21711336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 5195 99.90% 99.90% # Reads before turning the bus around for writes 21811201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes 21911201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 22011201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes 22111201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 22211201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 22311336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5200 # Reads before turning the bus around for writes 22411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5200 # Writes before turning the bus around for reads 22511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.606346 # Writes before turning the bus around for reads 22611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 19.258970 # Writes before turning the bus around for reads 22711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 21.077519 # Writes before turning the bus around for reads 22811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4603 88.52% 88.52% # Writes before turning the bus around for reads 22911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 36 0.69% 89.21% # Writes before turning the bus around for reads 23011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 24 0.46% 89.67% # Writes before turning the bus around for reads 23111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 35 0.67% 90.35% # Writes before turning the bus around for reads 23211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 205 3.94% 94.29% # Writes before turning the bus around for reads 23311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 11 0.21% 94.50% # Writes before turning the bus around for reads 23411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 15 0.29% 94.79% # Writes before turning the bus around for reads 23511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 35 0.67% 95.46% # Writes before turning the bus around for reads 23611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 175 3.37% 98.83% # Writes before turning the bus around for reads 23711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 6 0.12% 98.94% # Writes before turning the bus around for reads 23811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 7 0.13% 99.08% # Writes before turning the bus around for reads 23911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 2 0.04% 99.12% # Writes before turning the bus around for reads 24011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 1 0.02% 99.13% # Writes before turning the bus around for reads 24111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 11 0.21% 99.35% # Writes before turning the bus around for reads 24211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 24311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 6 0.12% 99.48% # Writes before turning the bus around for reads 24411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 2 0.04% 99.52% # Writes before turning the bus around for reads 24511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 4 0.08% 99.60% # Writes before turning the bus around for reads 24611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 7 0.13% 99.73% # Writes before turning the bus around for reads 24711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 2 0.04% 99.77% # Writes before turning the bus around for reads 24811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 1 0.02% 99.79% # Writes before turning the bus around for reads 24911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 3 0.06% 99.85% # Writes before turning the bus around for reads 25011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 3 0.06% 99.90% # Writes before turning the bus around for reads 25111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads 25211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 25311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::344-351 1 0.02% 100.00% # Writes before turning the bus around for reads 25411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5200 # Writes before turning the bus around for reads 25511336Sandreas.hansson@arm.comsystem.physmem.totQLat 4180311250 # Total ticks spent queuing 25611336Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11748392500 # Total ticks spent from burst creation until serviced by the DRAM 25711336Sandreas.hansson@arm.comsystem.physmem.totBusLat 2018155000 # Total ticks spent in databus transfers 25811336Sandreas.hansson@arm.comsystem.physmem.avgQLat 10356.76 # Average queueing delay per DRAM burst 2599978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26011336Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 29106.76 # Average memory access latency per DRAM burst 26111138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 26211138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 26311138Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 26411138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 2659978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 26610726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 26710352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 26810892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 26911336Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 2.08 # Average read queue length when enqueuing 27011336Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing 27111336Sandreas.hansson@arm.comsystem.physmem.readRowHits 363824 # Number of row buffer hits during reads 27211336Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95264 # Number of row buffer hits during writes 27311336Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads 27411336Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes 27511336Sandreas.hansson@arm.comsystem.physmem.avgGap 3598021.21 # Average gap between requests 27611336Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.08 # Row buffer hit rate, read and write combined 27711336Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 232326360 # Energy for activate commands per rank (pJ) 27811336Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 126765375 # Energy for precharge commands per rank (pJ) 27911336Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1577331600 # Energy for read commands per rank (pJ) 28011336Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 378529200 # Energy for write commands per rank (pJ) 28111201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 28211336Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 61450630965 # Energy for active background per rank (pJ) 28311336Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1071548691000 # Energy for precharge background per rank (pJ) 28411336Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 1257829429860 # Total energy per rank (pJ) 28511336Sandreas.hansson@arm.comsystem.physmem_0.averagePower 670.572492 # Core power per rank (mW) 28611336Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 1782417296500 # Time in different power states 28711201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states 28810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28911336Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 30701746000 # Time in different power states 29010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 29111336Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 237119400 # Energy for activate commands per rank (pJ) 29211336Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 129380625 # Energy for precharge commands per rank (pJ) 29311336Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1570990200 # Energy for read commands per rank (pJ) 29411336Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 383214240 # Energy for write commands per rank (pJ) 29511201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 29611336Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 61460167635 # Energy for active background per rank (pJ) 29711336Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1071540333750 # Energy for precharge background per rank (pJ) 29811336Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 1257836361210 # Total energy per rank (pJ) 29911336Sandreas.hansson@arm.comsystem.physmem_1.averagePower 670.576183 # Core power per rank (mW) 30011336Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 1782399409250 # Time in different power states 30111201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states 30210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 30311336Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 30719647000 # Time in different power states 30410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 30511336Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17926200 # Number of BP lookups 30611336Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 15634549 # Number of conditional branches predicted 30711336Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 367641 # Number of conditional branches incorrect 30811336Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 11517888 # Number of BTB lookups 30911336Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5853508 # Number of BTB hits 3109481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 31111336Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 50.821019 # BTB Hit Percentage 31211336Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 912312 # Number of times the RAS was used to get a target. 31311336Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 21142 # Number of incorrect RAS predictions. 31410036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3158464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3168464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3178464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3188464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 31911336Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 10248777 # DTB read hits 32011336Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41124 # DTB read misses 32111336Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 537 # DTB read access violations 32211336Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 965282 # DTB read accesses 32311336Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6643148 # DTB write hits 32411336Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 9690 # DTB write misses 32511336Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 398 # DTB write access violations 32611336Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 341994 # DTB write accesses 32711336Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16891925 # DTB hits 32811336Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 50814 # DTB misses 32911336Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 935 # DTB access violations 33011336Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1307276 # DTB accesses 33111336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1767471 # ITB hits 33211336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 28221 # ITB misses 33311336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 656 # ITB acv 33411336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1795692 # ITB accesses 3358464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3368464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3378464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3388464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3398464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3408464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3418464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3428464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3438464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3448464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3458464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3468464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 34711336Sandreas.hansson@arm.comsystem.cpu.numCycles 154296938 # number of cpu cycles simulated 3488464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3498464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 35011336Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 29565992 # Number of cycles fetch is stalled on an Icache miss 35111336Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 77998562 # Number of instructions fetch has processed 35211336Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17926200 # Number of branches that fetch encountered 35311336Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6765820 # Number of branches that fetch has predicted taken 35411336Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 115499750 # Number of cycles fetch has run and was not squashing or blocked 35511336Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1227580 # Number of cycles fetch has spent squashing 35611336Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 1879 # Number of cycles fetch has spent waiting for tlb 35711336Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 29906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 35811336Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 1313604 # Number of stall cycles due to pending traps 35911336Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 470747 # Number of stall cycles due to pending quiesce instructions 36011336Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 522 # Number of stall cycles due to full MSHR 36111336Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8986717 # Number of cache lines fetched 36211336Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 269982 # Number of outstanding Icache misses that were squashed 36311336Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 36411336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 147496190 # Number of instructions fetched each cycle (Total) 36511336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.528817 # Number of instructions fetched each cycle (Total) 36611336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.784795 # Number of instructions fetched each cycle (Total) 3678464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 36811336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 132977860 90.16% 90.16% # Number of instructions fetched each cycle (Total) 36911336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 927689 0.63% 90.79% # Number of instructions fetched each cycle (Total) 37011336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1955483 1.33% 92.11% # Number of instructions fetched each cycle (Total) 37111336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 905427 0.61% 92.73% # Number of instructions fetched each cycle (Total) 37211336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2772003 1.88% 94.60% # Number of instructions fetched each cycle (Total) 37311336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 615447 0.42% 95.02% # Number of instructions fetched each cycle (Total) 37411336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 725348 0.49% 95.51% # Number of instructions fetched each cycle (Total) 37511336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1009173 0.68% 96.20% # Number of instructions fetched each cycle (Total) 37611336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 5607760 3.80% 100.00% # Number of instructions fetched each cycle (Total) 3778464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3788464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3798464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 38011336Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 147496190 # Number of instructions fetched each cycle (Total) 38111336Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.116180 # Number of branch fetches per cycle 38211336Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.505509 # Number of inst fetches per cycle 38311336Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 23986183 # Number of cycles decode is idle 38411336Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 111594322 # Number of cycles decode is blocked 38511336Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 9434858 # Number of cycles decode is running 38611336Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 1908489 # Number of cycles decode is unblocking 38711336Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 572337 # Number of cycles decode is squashing 38811336Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 581608 # Number of times decode resolved a branch 38911336Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 41807 # Number of times decode detected a branch misprediction 39011336Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 68042420 # Number of instructions handled by decode 39111336Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 132440 # Number of squashed instructions handled by decode 39211336Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 572337 # Number of cycles rename is squashing 39311336Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 24909467 # Number of cycles rename is idle 39411336Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 78381394 # Number of cycles rename is blocking 39511336Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 21682831 # count of cycles rename stalled for serializing inst 39611336Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 10333745 # Number of cycles rename is running 39711336Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 11616414 # Number of cycles rename is unblocking 39811336Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65623799 # Number of instructions processed by rename 39911336Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 205401 # Number of times rename has blocked due to ROB full 40011336Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2094519 # Number of times rename has blocked due to IQ full 40111336Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 225742 # Number of times rename has blocked due to LQ full 40211336Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 7349306 # Number of times rename has blocked due to SQ full 40311336Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43739456 # Number of destination operands rename has renamed 40411336Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79586592 # Number of register rename lookups that rename has made 40511336Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79405874 # Number of integer rename lookups 40611336Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 168265 # Number of floating rename lookups 40711336Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38181154 # Number of HB maps that are committed 40811336Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5558294 # Number of HB maps that are undone due to squashing 40911336Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1689229 # count of serializing insts renamed 41011336Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 239421 # count of temporary serializing insts renamed 41111336Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13564930 # count of insts added to the skid buffer 41211336Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10374266 # Number of loads inserted to the mem dependence unit. 41311336Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6952166 # Number of stores inserted to the mem dependence unit. 41411336Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1510457 # Number of conflicting loads. 41511336Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1094829 # Number of conflicting stores. 41611336Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58464384 # Number of instructions added to the IQ (excludes non-spec) 41711336Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2137218 # Number of non-speculative instructions added to the IQ 41811336Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 57492092 # Number of instructions issued 41911336Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 57307 # Number of squashed instructions issued 42011336Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7620053 # Number of squashed instructions iterated over during squash; mainly for profiling 42111336Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3404147 # Number of squashed operands that are examined and possibly removed from graph 42211336Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1476015 # Number of squashed non-spec instructions that were removed 42311336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 147496190 # Number of insts issued each cycle 42411336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.389787 # Number of insts issued each cycle 42511336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.113704 # Number of insts issued each cycle 4268464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 42711336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 123903149 84.00% 84.00% # Number of insts issued each cycle 42811336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10174594 6.90% 90.90% # Number of insts issued each cycle 42911336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4283554 2.90% 93.81% # Number of insts issued each cycle 43011336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3020095 2.05% 95.85% # Number of insts issued each cycle 43111336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3079434 2.09% 97.94% # Number of insts issued each cycle 43211336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1494296 1.01% 98.96% # Number of insts issued each cycle 43311336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1011464 0.69% 99.64% # Number of insts issued each cycle 43411336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 404727 0.27% 99.92% # Number of insts issued each cycle 43511336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 124877 0.08% 100.00% # Number of insts issued each cycle 4368464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4378464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4388464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 43911336Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 147496190 # Number of insts issued each cycle 4408464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 44111336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 210492 18.68% 18.68% # attempts to use FU when none available 44211336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available 44311336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available 44411336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available 44511336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available 44611336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available 44711336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available 44811336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available 44911336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 45011336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available 45111336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available 45211336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available 45311336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available 45411336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available 45511336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available 45611336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available 45711336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available 45811336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available 45911336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available 46011336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available 46111336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available 46211336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available 46311336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available 46411336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available 46511336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available 46611336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available 46711336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available 46811336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available 46911336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 47011336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 541350 48.03% 66.71% # attempts to use FU when none available 47111336Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 375218 33.29% 100.00% # attempts to use FU when none available 4728464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4738464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 47411336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued 47511336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 39049419 67.92% 67.93% # Type of FU issued 47611336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61870 0.11% 68.04% # Type of FU issued 47711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued 47811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued 47911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued 48011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued 48111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued 48211336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.12% # Type of FU issued 48311336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued 48411336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued 48511336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued 48611336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued 48711336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued 48811336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued 48911336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued 49011336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued 49111336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued 49211336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued 49311336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued 49411336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued 49511336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued 49611336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued 49711336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued 49811336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued 49911336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued 50011336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.12% # Type of FU issued 50111336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued 50211336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued 50311336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued 50411336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10658869 18.54% 86.65% # Type of FU issued 50511336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6723409 11.69% 98.35% # Type of FU issued 50611336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949053 1.65% 100.00% # Type of FU issued 5078464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 50811336Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 57492092 # Type of FU issued 50911336Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.372607 # Inst issue rate 51011336Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1127060 # FU busy when requested 51111336Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019604 # FU busy rate (busy events/executed inst) 51211336Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 262951820 # Number of integer instruction queue reads 51311336Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 67904206 # Number of integer instruction queue writes 51411336Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55848058 # Number of integer instruction queue wakeup accesses 51511336Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 712920 # Number of floating instruction queue reads 51611336Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336440 # Number of floating instruction queue writes 51711336Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 329015 # Number of floating instruction queue wakeup accesses 51811336Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 58229078 # Number of integer alu accesses 51911336Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 382791 # Number of floating point alu accesses 52011336Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 635540 # Number of loads that had data forwarded from stores 5218464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 52211336Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1281314 # Number of loads squashed 52311336Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3324 # Number of memory responses ignored because the instruction is squashed 52411201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations 52511336Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 573929 # Number of stores squashed 5268464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5278464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 52811201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled 52911336Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 459106 # Number of times an access to memory failed due to the cache being blocked 5308464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 53111336Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 572337 # Number of cycles IEW is squashing 53211336Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 74665457 # Number of cycles IEW is blocking 53311336Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 1160593 # Number of cycles IEW is unblocking 53411336Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 64290812 # Number of instructions dispatched to IQ 53511336Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 139650 # Number of squashed instructions skipped by dispatch 53611336Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10374266 # Number of dispatched load instructions 53711336Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6952166 # Number of dispatched store instructions 53811336Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1889682 # Number of dispatched non-speculative instructions 53911336Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 43932 # Number of times the IQ has become full, causing a stall 54011336Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 913665 # Number of times the LSQ has become full, causing a stall 54111201Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations 54211336Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 176905 # Number of branches that were predicted taken incorrectly 54311336Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 409384 # Number of branches that were predicted not taken incorrectly 54411336Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 586289 # Number of branch mispredicts detected at execute 54511336Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56905925 # Number of executed instructions 54611336Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 10317589 # Number of load instructions executed 54711336Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 586166 # Number of squashed instructions skipped in execute 5488464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 54911336Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3689210 # number of nop insts executed 55011336Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16985526 # number of memory reference insts executed 55111336Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8973539 # Number of branches executed 55211336Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6667937 # Number of stores executed 55311336Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.368808 # Inst execution rate 55411336Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56314090 # cumulative count of insts sent to commit 55511336Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 56177073 # cumulative count of insts written-back 55611336Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 28757350 # num instructions producing a value 55711336Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 39943859 # num instructions consuming a value 55811336Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.364084 # insts written-back per cycle 55911336Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.719944 # average fanout of values written-back 56011336Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 8001816 # The number of squashed insts skipped by commit 56111336Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661203 # The number of times commit has been forced to stall to communicate backwards 56211336Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 537200 # The number of times a branch was mispredicted 56311336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 146094021 # Number of insts commited each cycle 56411336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.384495 # Number of insts commited each cycle 56511336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.286335 # Number of insts commited each cycle 5668241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 56711336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 126314306 86.46% 86.46% # Number of insts commited each cycle 56811336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7853790 5.38% 91.84% # Number of insts commited each cycle 56911336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4274774 2.93% 94.76% # Number of insts commited each cycle 57011336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2236101 1.53% 96.29% # Number of insts commited each cycle 57111336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1744788 1.19% 97.49% # Number of insts commited each cycle 57211336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 615632 0.42% 97.91% # Number of insts commited each cycle 57311336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 478334 0.33% 98.24% # Number of insts commited each cycle 57411336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 476966 0.33% 98.56% # Number of insts commited each cycle 57511336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2099330 1.44% 100.00% # Number of insts commited each cycle 5768241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5778241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5788241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 57911336Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 146094021 # Number of insts commited each cycle 58011336Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56172359 # Number of instructions committed 58111336Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56172359 # Number of ops (including micro ops) committed 5828464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 58311336Sandreas.hansson@arm.comsystem.cpu.commit.refs 15471189 # Number of memory references committed 58411336Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092952 # Number of loads committed 58511336Sandreas.hansson@arm.comsystem.cpu.commit.membars 226351 # Number of memory barriers committed 58611336Sandreas.hansson@arm.comsystem.cpu.commit.branches 8440746 # Number of branches committed 58710892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 58811336Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52021709 # Number of committed integer instructions. 58911336Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740586 # Number of function calls committed. 59011336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3198088 5.69% 5.69% # Class of committed instruction 59111336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36219325 64.48% 70.17% # Class of committed instruction 59211201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction 59310892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 59410892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 59510892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 59610892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 59710892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 59811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 59911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 60011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 60111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 60211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 60311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 60411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 60511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 60611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 60711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 60811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 60911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 61011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 61111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 61211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 61311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 61411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 61511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 61611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 61711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 61811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 61911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 62011336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9319303 16.59% 86.95% # Class of committed instruction 62111336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6384192 11.37% 98.31% # Class of committed instruction 62211336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949053 1.69% 100.00% # Class of committed instruction 62310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 62411336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56172359 # Class of committed instruction 62511336Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2099330 # number cycles where commit BW limit reached 62611336Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 207919346 # The number of ROB reads 62711336Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 129746181 # The number of ROB writes 62811336Sandreas.hansson@arm.comsystem.cpu.timesIdled 581168 # Number of times that the entire CPU went into an idle state and unscheduled itself 62911336Sandreas.hansson@arm.comsystem.cpu.idleCycles 6800748 # Total number of cycles that the CPU has spent unscheduled due to idling 63011336Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3597219294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 63111336Sandreas.hansson@arm.comsystem.cpu.committedInsts 52981544 # Number of Instructions Simulated 63211336Sandreas.hansson@arm.comsystem.cpu.committedOps 52981544 # Number of Ops (including micro ops) Simulated 63311336Sandreas.hansson@arm.comsystem.cpu.cpi 2.912277 # CPI: Cycles Per Instruction 63411336Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.912277 # CPI: Total CPI of All Threads 63511336Sandreas.hansson@arm.comsystem.cpu.ipc 0.343374 # IPC: Instructions Per Cycle 63611336Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.343374 # IPC: Total IPC of All Threads 63711336Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 74565581 # number of integer regfile reads 63811336Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40526554 # number of integer regfile writes 63911336Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 167056 # number of floating regfile reads 64011336Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167536 # number of floating regfile writes 64111336Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1985625 # number of misc regfile reads 64211336Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939435 # number of misc regfile writes 64311336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1401792 # number of replacements 64411201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use 64511336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11831016 # Total number of references to valid blocks. 64611336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1402304 # Sample count of references to valid blocks. 64711336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.436841 # Average number of references to valid blocks. 64811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 64911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor 65011138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 65111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 65210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 65311138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 65411138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 65511138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 65610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 65711336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 63836509 # Number of tag accesses 65811336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 63836509 # Number of data accesses 65911336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7238578 # number of ReadReq hits 66011336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7238578 # number of ReadReq hits 66111336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4190111 # number of WriteReq hits 66211336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4190111 # number of WriteReq hits 66311336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186204 # number of LoadLockedReq hits 66411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186204 # number of LoadLockedReq hits 66511336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215724 # number of StoreCondReq hits 66611336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215724 # number of StoreCondReq hits 66711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11428689 # number of demand (read+write) hits 66811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11428689 # number of demand (read+write) hits 66911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11428689 # number of overall hits 67011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11428689 # number of overall hits 67111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1796989 # number of ReadReq misses 67211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1796989 # number of ReadReq misses 67311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1957670 # number of WriteReq misses 67411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1957670 # number of WriteReq misses 67511336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23246 # number of LoadLockedReq misses 67611336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23246 # number of LoadLockedReq misses 67711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses 67811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses 67911336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3754659 # number of demand (read+write) misses 68011336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3754659 # number of demand (read+write) misses 68111336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3754659 # number of overall misses 68211336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3754659 # number of overall misses 68311336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 57191537500 # number of ReadReq miss cycles 68411336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 57191537500 # number of ReadReq miss cycles 68511336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150 # number of WriteReq miss cycles 68611336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 116815247150 # number of WriteReq miss cycles 68711336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448333000 # number of LoadLockedReq miss cycles 68811336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 448333000 # number of LoadLockedReq miss cycles 68911336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 872000 # number of StoreCondReq miss cycles 69011336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 872000 # number of StoreCondReq miss cycles 69111336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 174006784650 # number of demand (read+write) miss cycles 69211336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 174006784650 # number of demand (read+write) miss cycles 69311336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 174006784650 # number of overall miss cycles 69411336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 174006784650 # number of overall miss cycles 69511336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9035567 # number of ReadReq accesses(hits+misses) 69611336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9035567 # number of ReadReq accesses(hits+misses) 69711336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147781 # number of WriteReq accesses(hits+misses) 69811336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147781 # number of WriteReq accesses(hits+misses) 69911336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209450 # number of LoadLockedReq accesses(hits+misses) 70011336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209450 # number of LoadLockedReq accesses(hits+misses) 70111336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215753 # number of StoreCondReq accesses(hits+misses) 70211336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215753 # number of StoreCondReq accesses(hits+misses) 70311336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15183348 # number of demand (read+write) accesses 70411336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15183348 # number of demand (read+write) accesses 70511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15183348 # number of overall (read+write) accesses 70611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15183348 # number of overall (read+write) accesses 70711336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198879 # miss rate for ReadReq accesses 70811336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.198879 # miss rate for ReadReq accesses 70911336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318435 # miss rate for WriteReq accesses 71011336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.318435 # miss rate for WriteReq accesses 71111336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110986 # miss rate for LoadLockedReq accesses 71211336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.110986 # miss rate for LoadLockedReq accesses 71311201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses 71411201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses 71511336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247288 # miss rate for demand accesses 71611336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247288 # miss rate for demand accesses 71711336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247288 # miss rate for overall accesses 71811336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247288 # miss rate for overall accesses 71911336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741 # average ReadReq miss latency 72011336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741 # average ReadReq miss latency 72111336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782 # average WriteReq miss latency 72211336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782 # average WriteReq miss latency 72311336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885 # average LoadLockedReq miss latency 72411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885 # average LoadLockedReq miss latency 72511336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517 # average StoreCondReq miss latency 72611336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517 # average StoreCondReq miss latency 72711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency 72811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 46344.231167 # average overall miss latency 72911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency 73011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 46344.231167 # average overall miss latency 73111336Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 7151643 # number of cycles access was blocked 73211336Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 5595 # number of cycles access was blocked 73311336Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 133832 # number of cycles access was blocked 73411201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked 73511336Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437466 # average number of cycles each access was blocked 73611336Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 199.821429 # average number of cycles each access was blocked 73710585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 73810585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 73911336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 841120 # number of writebacks 74011336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 841120 # number of writebacks 74111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 703166 # number of ReadReq MSHR hits 74211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 703166 # number of ReadReq MSHR hits 74311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666991 # number of WriteReq MSHR hits 74411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1666991 # number of WriteReq MSHR hits 74511336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5234 # number of LoadLockedReq MSHR hits 74611336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5234 # number of LoadLockedReq MSHR hits 74711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2370157 # number of demand (read+write) MSHR hits 74811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2370157 # number of demand (read+write) MSHR hits 74911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2370157 # number of overall MSHR hits 75011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2370157 # number of overall MSHR hits 75111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093823 # number of ReadReq MSHR misses 75211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1093823 # number of ReadReq MSHR misses 75311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 290679 # number of WriteReq MSHR misses 75411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 290679 # number of WriteReq MSHR misses 75511336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18012 # number of LoadLockedReq MSHR misses 75611336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 18012 # number of LoadLockedReq MSHR misses 75711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses 75811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses 75911336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1384502 # number of demand (read+write) MSHR misses 76011336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1384502 # number of demand (read+write) MSHR misses 76111336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1384502 # number of overall MSHR misses 76211336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1384502 # number of overall MSHR misses 76310827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 76410827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 76511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 76611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 76711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 76811138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 76911336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44561431000 # number of ReadReq MSHR miss cycles 77011336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 44561431000 # number of ReadReq MSHR miss cycles 77111336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18441083775 # number of WriteReq MSHR miss cycles 77211336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 18441083775 # number of WriteReq MSHR miss cycles 77311336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229476500 # number of LoadLockedReq MSHR miss cycles 77411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229476500 # number of LoadLockedReq MSHR miss cycles 77511336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 843000 # number of StoreCondReq MSHR miss cycles 77611336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 843000 # number of StoreCondReq MSHR miss cycles 77711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 63002514775 # number of demand (read+write) MSHR miss cycles 77811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 63002514775 # number of demand (read+write) MSHR miss cycles 77911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 63002514775 # number of overall MSHR miss cycles 78011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 63002514775 # number of overall MSHR miss cycles 78111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528979500 # number of ReadReq MSHR uncacheable cycles 78211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528979500 # number of ReadReq MSHR uncacheable cycles 78311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154218500 # number of WriteReq MSHR uncacheable cycles 78411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154218500 # number of WriteReq MSHR uncacheable cycles 78511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683198000 # number of overall MSHR uncacheable cycles 78611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3683198000 # number of overall MSHR uncacheable cycles 78711336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121057 # mshr miss rate for ReadReq accesses 78811336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121057 # mshr miss rate for ReadReq accesses 78911336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047282 # mshr miss rate for WriteReq accesses 79011336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047282 # mshr miss rate for WriteReq accesses 79111336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085997 # mshr miss rate for LoadLockedReq accesses 79211336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085997 # mshr miss rate for LoadLockedReq accesses 79311201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses 79411201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses 79511336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for demand accesses 79611336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091186 # mshr miss rate for demand accesses 79711336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for overall accesses 79811336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091186 # mshr miss rate for overall accesses 79911336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723 # average ReadReq mshr miss latency 80011336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723 # average ReadReq mshr miss latency 80111336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662 # average WriteReq mshr miss latency 80211336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662 # average WriteReq mshr miss latency 80311336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977 # average LoadLockedReq mshr miss latency 80411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977 # average LoadLockedReq mshr miss latency 80511336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517 # average StoreCondReq mshr miss latency 80611336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517 # average StoreCondReq mshr miss latency 80711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency 80811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency 80911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency 81011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency 81111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482 # average ReadReq mshr uncacheable latency 81211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482 # average ReadReq mshr uncacheable latency 81311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692 # average WriteReq mshr uncacheable latency 81411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692 # average WriteReq mshr uncacheable latency 81511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374 # average overall mshr uncacheable latency 81611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374 # average overall mshr uncacheable latency 81710585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 81811336Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1035081 # number of replacements 81911336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 507.835100 # Cycle average of tags in use 82011336Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7897485 # Total number of references to valid blocks. 82111336Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1035589 # Sample count of references to valid blocks. 82211336Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.626080 # Average number of references to valid blocks. 82311201Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. 82411336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 507.835100 # Average occupied blocks per requestor 82511201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy 82611201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy 82710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 82811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 82911336Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 83011336Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id 83110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 83211336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 10022677 # Number of tag accesses 83311336Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 10022677 # Number of data accesses 83411336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7897486 # number of ReadReq hits 83511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7897486 # number of ReadReq hits 83611336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7897486 # number of demand (read+write) hits 83711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7897486 # number of demand (read+write) hits 83811336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7897486 # number of overall hits 83911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7897486 # number of overall hits 84011336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1089229 # number of ReadReq misses 84111336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1089229 # number of ReadReq misses 84211336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1089229 # number of demand (read+write) misses 84311336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1089229 # number of demand (read+write) misses 84411336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1089229 # number of overall misses 84511336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1089229 # number of overall misses 84611336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16358882985 # number of ReadReq miss cycles 84711336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16358882985 # number of ReadReq miss cycles 84811336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16358882985 # number of demand (read+write) miss cycles 84911336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16358882985 # number of demand (read+write) miss cycles 85011336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16358882985 # number of overall miss cycles 85111336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16358882985 # number of overall miss cycles 85211336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8986715 # number of ReadReq accesses(hits+misses) 85311336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8986715 # number of ReadReq accesses(hits+misses) 85411336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8986715 # number of demand (read+write) accesses 85511336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8986715 # number of demand (read+write) accesses 85611336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8986715 # number of overall (read+write) accesses 85711336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8986715 # number of overall (read+write) accesses 85811336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121204 # miss rate for ReadReq accesses 85911336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.121204 # miss rate for ReadReq accesses 86011336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.121204 # miss rate for demand accesses 86111336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.121204 # miss rate for demand accesses 86211336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.121204 # miss rate for overall accesses 86311336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.121204 # miss rate for overall accesses 86411336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.772898 # average ReadReq miss latency 86511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 15018.772898 # average ReadReq miss latency 86611336Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency 86711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 15018.772898 # average overall miss latency 86811336Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency 86911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 15018.772898 # average overall miss latency 87011336Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 10400 # number of cycles access was blocked 87110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87211336Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked 87310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 87411336Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 33.766234 # average number of cycles each access was blocked 87510585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87610585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 87710585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 87811336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1035081 # number of writebacks 87911336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1035081 # number of writebacks 88011336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 53267 # number of ReadReq MSHR hits 88111336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 53267 # number of ReadReq MSHR hits 88211336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 53267 # number of demand (read+write) MSHR hits 88311336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 53267 # number of demand (read+write) MSHR hits 88411336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 53267 # number of overall MSHR hits 88511336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 53267 # number of overall MSHR hits 88611336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035962 # number of ReadReq MSHR misses 88711336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1035962 # number of ReadReq MSHR misses 88811336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1035962 # number of demand (read+write) MSHR misses 88911336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1035962 # number of demand (read+write) MSHR misses 89011336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1035962 # number of overall MSHR misses 89111336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1035962 # number of overall MSHR misses 89211336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14427899492 # number of ReadReq MSHR miss cycles 89311336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14427899492 # number of ReadReq MSHR miss cycles 89411336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14427899492 # number of demand (read+write) MSHR miss cycles 89511336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14427899492 # number of demand (read+write) MSHR miss cycles 89611336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14427899492 # number of overall MSHR miss cycles 89711336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14427899492 # number of overall MSHR miss cycles 89811336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for ReadReq accesses 89911336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.115277 # mshr miss rate for ReadReq accesses 90011336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for demand accesses 90111336Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.115277 # mshr miss rate for demand accesses 90211336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for overall accesses 90311336Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.115277 # mshr miss rate for overall accesses 90411336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13927.054749 # average ReadReq mshr miss latency 90511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13927.054749 # average ReadReq mshr miss latency 90611336Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency 90711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency 90811336Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency 90911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency 91010585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 91111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338544 # number of replacements 91211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65279.658287 # Cycle average of tags in use 91311336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4165713 # Total number of references to valid blocks. 91411336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403711 # Sample count of references to valid blocks. 91511336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 10.318552 # Average number of references to valid blocks. 91611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. 91711336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53291.619090 # Average occupied blocks per requestor 91811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5239.581641 # Average occupied blocks per requestor 91911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6748.457555 # Average occupied blocks per requestor 92011336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.813166 # Average percentage of cache occupancy 92111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.079950 # Average percentage of cache occupancy 92211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.102973 # Average percentage of cache occupancy 92311336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996089 # Average percentage of cache occupancy 92411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 92511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 92611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3482 # Occupied blocks per task id 92711336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3333 # Occupied blocks per task id 92811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2426 # Occupied blocks per task id 92911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id 93011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 93111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 39690670 # Number of tag accesses 93211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 39690670 # Number of data accesses 93311336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 841120 # number of WritebackDirty hits 93411336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 841120 # number of WritebackDirty hits 93511336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1034540 # number of WritebackClean hits 93611336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1034540 # number of WritebackClean hits 93711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 93811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 93911201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 94011201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 94111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185946 # number of ReadExReq hits 94211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185946 # number of ReadExReq hits 94311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1020673 # number of ReadCleanReq hits 94411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1020673 # number of ReadCleanReq hits 94511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 827071 # number of ReadSharedReq hits 94611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 827071 # number of ReadSharedReq hits 94711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1020673 # number of demand (read+write) hits 94811336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1013017 # number of demand (read+write) hits 94911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2033690 # number of demand (read+write) hits 95011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1020673 # number of overall hits 95111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1013017 # number of overall hits 95211336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2033690 # number of overall hits 95311201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses 95411201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses 95511138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses 95611138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses 95711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115508 # number of ReadExReq misses 95811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115508 # number of ReadExReq misses 95911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 14974 # number of ReadCleanReq misses 96011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 14974 # number of ReadCleanReq misses 96111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 273861 # number of ReadSharedReq misses 96211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 273861 # number of ReadSharedReq misses 96311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 14974 # number of demand (read+write) misses 96411336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389369 # number of demand (read+write) misses 96511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404343 # number of demand (read+write) misses 96611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 14974 # number of overall misses 96711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389369 # number of overall misses 96811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404343 # number of overall misses 96911336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 786000 # number of UpgradeReq miss cycles 97011336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 786000 # number of UpgradeReq miss cycles 97111336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 235500 # number of SCUpgradeReq miss cycles 97211336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 235500 # number of SCUpgradeReq miss cycles 97311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16104953000 # number of ReadExReq miss cycles 97411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 16104953000 # number of ReadExReq miss cycles 97511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2014947000 # number of ReadCleanReq miss cycles 97611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 2014947000 # number of ReadCleanReq miss cycles 97711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34006362500 # number of ReadSharedReq miss cycles 97811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 34006362500 # number of ReadSharedReq miss cycles 97911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 2014947000 # number of demand (read+write) miss cycles 98011336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 50111315500 # number of demand (read+write) miss cycles 98111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 52126262500 # number of demand (read+write) miss cycles 98211336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 2014947000 # number of overall miss cycles 98311336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 50111315500 # number of overall miss cycles 98411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 52126262500 # number of overall miss cycles 98511336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 841120 # number of WritebackDirty accesses(hits+misses) 98611336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 841120 # number of WritebackDirty accesses(hits+misses) 98711336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1034540 # number of WritebackClean accesses(hits+misses) 98811336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1034540 # number of WritebackClean accesses(hits+misses) 98911201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) 99011201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) 99111201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) 99211201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) 99311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301454 # number of ReadExReq accesses(hits+misses) 99411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 301454 # number of ReadExReq accesses(hits+misses) 99511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1035647 # number of ReadCleanReq accesses(hits+misses) 99611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1035647 # number of ReadCleanReq accesses(hits+misses) 99711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100932 # number of ReadSharedReq accesses(hits+misses) 99811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1100932 # number of ReadSharedReq accesses(hits+misses) 99911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1035647 # number of demand (read+write) accesses 100011336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1402386 # number of demand (read+write) accesses 100111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2438033 # number of demand (read+write) accesses 100211336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1035647 # number of overall (read+write) accesses 100311336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1402386 # number of overall (read+write) accesses 100411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2438033 # number of overall (read+write) accesses 100511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses 100611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses 100711201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses 100811201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.241379 # miss rate for SCUpgradeReq accesses 100911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383170 # miss rate for ReadExReq accesses 101011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383170 # miss rate for ReadExReq accesses 101111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014459 # miss rate for ReadCleanReq accesses 101211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014459 # miss rate for ReadCleanReq accesses 101311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248754 # miss rate for ReadSharedReq accesses 101411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248754 # miss rate for ReadSharedReq accesses 101511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014459 # miss rate for demand accesses 101611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277648 # miss rate for demand accesses 101711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.165848 # miss rate for demand accesses 101811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014459 # miss rate for overall accesses 101911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277648 # miss rate for overall accesses 102011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.165848 # miss rate for overall accesses 102111336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7782.178218 # average UpgradeReq miss latency 102211336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7782.178218 # average UpgradeReq miss latency 102311336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 33642.857143 # average SCUpgradeReq miss latency 102411336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 33642.857143 # average SCUpgradeReq miss latency 102511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139427.165218 # average ReadExReq miss latency 102611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 139427.165218 # average ReadExReq miss latency 102711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134563.042607 # average ReadCleanReq miss latency 102811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134563.042607 # average ReadCleanReq miss latency 102911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124173.805325 # average ReadSharedReq miss latency 103011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124173.805325 # average ReadSharedReq miss latency 103111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency 103211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency 103311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 128915.951309 # average overall miss latency 103411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency 103511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency 103611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 128915.951309 # average overall miss latency 103710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 103810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 104210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104310585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 104410585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 104511336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 76064 # number of writebacks 104611336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 76064 # number of writebacks 104710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 104810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 104910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 105010585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 105110585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 105210585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 105311201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 # number of UpgradeReq MSHR misses 105411201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses 105511138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses 105611138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses 105711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115508 # number of ReadExReq MSHR misses 105811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115508 # number of ReadExReq MSHR misses 105911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses 106011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses 106111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273861 # number of ReadSharedReq MSHR misses 106211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 273861 # number of ReadSharedReq MSHR misses 106311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses 106411336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389369 # number of demand (read+write) MSHR misses 106511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404342 # number of demand (read+write) MSHR misses 106611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses 106711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389369 # number of overall MSHR misses 106811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404342 # number of overall MSHR misses 106910827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 107010827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 107111138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 107211138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 107311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 107411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 107511336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6981000 # number of UpgradeReq MSHR miss cycles 107611336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6981000 # number of UpgradeReq MSHR miss cycles 107711336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 479500 # number of SCUpgradeReq MSHR miss cycles 107811336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 479500 # number of SCUpgradeReq MSHR miss cycles 107911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14949871007 # number of ReadExReq MSHR miss cycles 108011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14949871007 # number of ReadExReq MSHR miss cycles 108111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1865086000 # number of ReadCleanReq MSHR miss cycles 108211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1865086000 # number of ReadCleanReq MSHR miss cycles 108311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31278266000 # number of ReadSharedReq MSHR miss cycles 108411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31278266000 # number of ReadSharedReq MSHR miss cycles 108511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1865086000 # number of demand (read+write) MSHR miss cycles 108611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46228137007 # number of demand (read+write) MSHR miss cycles 108711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 48093223007 # number of demand (read+write) MSHR miss cycles 108811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1865086000 # number of overall MSHR miss cycles 108911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46228137007 # number of overall MSHR miss cycles 109011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 48093223007 # number of overall MSHR miss cycles 109111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442280000 # number of ReadReq MSHR uncacheable cycles 109211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442280000 # number of ReadReq MSHR uncacheable cycles 109311336Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043799500 # number of WriteReq MSHR uncacheable cycles 109411336Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043799500 # number of WriteReq MSHR uncacheable cycles 109511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486079500 # number of overall MSHR uncacheable cycles 109611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486079500 # number of overall MSHR uncacheable cycles 109711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses 109811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses 109911201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses 110011201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses 110111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383170 # mshr miss rate for ReadExReq accesses 110211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383170 # mshr miss rate for ReadExReq accesses 110311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for ReadCleanReq accesses 110411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014458 # mshr miss rate for ReadCleanReq accesses 110511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248754 # mshr miss rate for ReadSharedReq accesses 110611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248754 # mshr miss rate for ReadSharedReq accesses 110711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for demand accesses 110811336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for demand accesses 110911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.165848 # mshr miss rate for demand accesses 111011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for overall accesses 111111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for overall accesses 111211336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.165848 # mshr miss rate for overall accesses 111311336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881 # average UpgradeReq mshr miss latency 111411336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881 # average UpgradeReq mshr miss latency 111511336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency 111611336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency 111711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964 # average ReadExReq mshr miss latency 111811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964 # average ReadExReq mshr miss latency 111911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572 # average ReadCleanReq mshr miss latency 112011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572 # average ReadCleanReq mshr miss latency 112111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238 # average ReadSharedReq mshr miss latency 112211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238 # average ReadSharedReq mshr miss latency 112311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency 112411336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency 112511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency 112611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency 112711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency 112811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency 112911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121 # average ReadReq mshr uncacheable latency 113011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121 # average ReadReq mshr uncacheable latency 113111336Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780 # average WriteReq mshr uncacheable latency 113211336Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780 # average WriteReq mshr uncacheable latency 113311336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249 # average overall mshr uncacheable latency 113411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249 # average overall mshr uncacheable latency 113510585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 113611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4875380 # Total number of requests made to the snoop filter. 113711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2437337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 113811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2172 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 113911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 114011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 114111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 114210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 114311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2143899 # Transaction distribution 114411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 114511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 114611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 958701 # Transaction distribution 114711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1035081 # Transaction distribution 114811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 823325 # Transaction distribution 114911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution 115011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution 115111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution 115211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 301454 # Transaction distribution 115311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 301454 # Transaction distribution 115411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1035962 # Transaction distribution 115511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1101105 # Transaction distribution 115611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution 115710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 115811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106690 # Packet count per connected master and slave (bytes) 115911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240094 # Packet count per connected master and slave (bytes) 116011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 7346784 # Packet count per connected master and slave (bytes) 116111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132526592 # Cumulative packet size per connected master and slave (bytes) 116211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143633332 # Cumulative packet size per connected master and slave (bytes) 116311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 276159924 # Cumulative packet size per connected master and slave (bytes) 116411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 422430 # Total snoops (count) 116511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2876994 # Request fanout histogram 116611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001301 # Request fanout histogram 116711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.036051 # Request fanout histogram 116810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2873250 99.87% 99.87% # Request fanout histogram 117011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3744 0.13% 100.00% # Request fanout histogram 117111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 117210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 117411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 117511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2876994 # Request fanout histogram 117611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4326954000 # Layer occupancy (ticks) 117710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 117811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 117910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 118011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1555197985 # Layer occupancy (ticks) 118110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 118211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2115406799 # Layer occupancy (ticks) 118310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 118410585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 118510585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 118610585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 118710585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 118810585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 118910585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 119010585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119110585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 119210585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 119310585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 119410585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 119510585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 11969729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 11979729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 119811138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51150 # Transaction distribution 119911138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51150 # Transaction distribution 120011138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 120111245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 12029729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 12039729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 12049729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 12059729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 12069729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 12079729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12089729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 120911138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 12109729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12119729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 121211138Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 121311138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 121411245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 121510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 121610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 121710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 121810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 121910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 122010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 122110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 122211138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 122310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 122410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 122511138Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 122611336Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 5356500 # Layer occupancy (ticks) 12279729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 122811336Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 825500 # Layer occupancy (ticks) 12299729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 123011201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 12319729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 123211201Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 12339729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 123411336Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 12359729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 123611336Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14331000 # Layer occupancy (ticks) 12379729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 123811201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) 12399729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 124011336Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5952500 # Layer occupancy (ticks) 12419729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 124211336Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) 12439729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 124411336Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 215698160 # Layer occupancy (ticks) 12459729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 124611138Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 12479729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 124810892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12499729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 125010585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 125111336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.249420 # Cycle average of tags in use 125210585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 125310585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 125410585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 125511336Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1725995722000 # Cycle when the warmup percentage was hit. 125611336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.249420 # Average occupied blocks per requestor 125711201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy 125811201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy 125910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 126010585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 126110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 126210585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 126310585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 126410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 126510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 126610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 126710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 126810585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 126910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 127010585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 127110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 127211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles 127311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles 127411336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 5245293777 # number of WriteLineReq miss cycles 127511336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 5245293777 # number of WriteLineReq miss cycles 127611201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles 127711201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles 127811201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles 127911201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles 128010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 128110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 128210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 128310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 128410585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 128510585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 128610585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 128710585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 128810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 128910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 129010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 129110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 129210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 129310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 129410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 129510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 129611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency 129711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency 129811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848 # average WriteLineReq miss latency 129911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126234.447848 # average WriteLineReq miss latency 130011201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 130111201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency 130211201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 130311201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency 130411336Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 130510585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130611336Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 130710585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 130811336Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130910585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131010585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 131110585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 131210585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 131310585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 131410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 131510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 131610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 131710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 131810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 131910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 132010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 132110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 132211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles 132311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles 132411336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165897973 # number of WriteLineReq MSHR miss cycles 132511336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 3165897973 # number of WriteLineReq MSHR miss cycles 132611201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles 132711201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles 132811201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles 132911201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles 133010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 133110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 133210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 133310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 133410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 133510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 133610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 133710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 133811201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency 133911201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency 134011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616 # average WriteLineReq mshr miss latency 134111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616 # average WriteLineReq mshr miss latency 134211201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 134311201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 134411201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 134511201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 134610585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 134710892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 134811336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295856 # Transaction distribution 134911138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9598 # Transaction distribution 135011138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9598 # Transaction distribution 135111336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 117576 # Transaction distribution 135211336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 261861 # Transaction distribution 135311336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 350 # Transaction distribution 135411138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution 135511336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 135611336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 115259 # Transaction distribution 135711336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 115259 # Transaction distribution 135811336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 289007 # Transaction distribution 135911201Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 81 # Transaction distribution 136010892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 136111138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 136211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145859 # Packet count per connected master and slave (bytes) 136311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) 136411336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179077 # Packet count per connected master and slave (bytes) 136511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 136611336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 136711336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1262502 # Packet count per connected master and slave (bytes) 136811138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 136911336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707328 # Cumulative packet size per connected master and slave (bytes) 137011336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751476 # Cumulative packet size per connected master and slave (bytes) 137110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 137210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 137311336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33409204 # Cumulative packet size per connected master and slave (bytes) 137410585Sandreas.hansson@arm.comsystem.membus.snoops 435 # Total snoops (count) 137511336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 842145 # Request fanout histogram 137610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 137710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 137810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 138011336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 842145 100.00% 100.00% # Request fanout histogram 138110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 138210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 138410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 138511336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 842145 # Request fanout histogram 138611336Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 28932500 # Layer occupancy (ticks) 138710585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 138811336Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1314336715 # Layer occupancy (ticks) 138910585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 139011336Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 105000 # Layer occupancy (ticks) 139110585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 139211336Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2138304000 # Layer occupancy (ticks) 139310726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 139411336Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 911117 # Layer occupancy (ticks) 139510585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 139610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 139710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 139810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 139910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 140010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 140110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 140210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 140310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 140410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 140510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 140610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 140710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 140810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 140910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 141010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 141110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 141210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 141310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 141410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 141510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 141610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 141710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 141810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 141910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 142010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 142110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 142210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 142310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 142410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 142510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 142610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 14275703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 142811336Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 142911336Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211012 # number of hwrei instructions executed 143011201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl 14319285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 143211138Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 143311336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105568 57.93% 100.00% # number of times we switched to this ipl 143411336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl 143511201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14369285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 143711138Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 143811201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl 143911201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl 144011336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818034033000 96.92% 96.92% # number of cycles we spent at this ipl 144111336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64890000 0.00% 96.93% # number of cycles we spent at this ipl 144211336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 561380500 0.03% 96.96% # number of cycles we spent at this ipl 144311336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 57096986000 3.04% 100.00% # number of cycles we spent at this ipl 144411336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1875757289500 # number of cycles we spent at this ipl 144511201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 14466127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14476127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 144811336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694311 # fraction of swpipl calls that actually changed the ipl 144911336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815422 # fraction of swpipl calls that actually changed the ipl 14506291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14516291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14526291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14536291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14546291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14556291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14566291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14576291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14586291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14596291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14606291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14616291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14626291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14636291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14646291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14656291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14666291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14676291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14686291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14696291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14706291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14716291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14726291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14736291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14746291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14756291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14766291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14776291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14786291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14796291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14806127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14818464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14828464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14838464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14848464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 148510892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 14869285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 14879199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 148811336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175126 91.23% 93.43% # number of callpals executed 148911138Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 14909285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 14919199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 14929285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 14939285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 149411138Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 14958464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 14968464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 149711336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191971 # number of callpals executed 149811336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 149911336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 150011336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 150111336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 150211336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1739 15038517SN/Asystem.cpu.kern.mode_good::idle 170 150411336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches 15058464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 150611336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 150711336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 150811336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29989573500 1.60% 1.60% # number of ticks spent at the given mode 150911336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2896538000 0.15% 1.75% # number of ticks spent at the given mode 151011336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1842871170000 98.25% 100.00% # number of ticks spent at the given mode 151110892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15125703SN/A 15135703SN/A---------- End Simulation Statistics ---------- 1514