stats.txt revision 11336
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.875758 # Number of seconds simulated 4sim_ticks 1875758115500 # Number of ticks simulated 5final_tick 1875758115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 136821 # Simulator instruction rate (inst/s) 8host_op_rate 136821 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4844017901 # Simulator tick rate (ticks/s) 10host_mem_usage 335520 # Number of bytes of host memory used 11host_seconds 387.23 # Real time elapsed on the host 12sim_insts 52981544 # Number of instructions simulated 13sim_ops 52981544 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24881024 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25840192 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388766 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 403753 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 510838 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13264516 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13775866 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 510838 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 510838 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4011639 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4011639 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4011639 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 510838 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13264516 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17787505 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403753 # Number of read requests accepted 44system.physmem.writeReqs 117576 # Number of write requests accepted 45system.physmem.readBursts 403753 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117576 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25832384 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7523392 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25840192 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7524864 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25611 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25424 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25556 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25503 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25379 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24725 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24941 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25083 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24938 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25019 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25561 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24881 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24458 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25273 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25708 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25571 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7931 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7523 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7959 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7526 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7322 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6664 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6770 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6720 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7147 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6703 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7408 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6973 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7144 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7893 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8063 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7807 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 89system.physmem.totGap 1875752798500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 403753 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 117576 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 315454 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 35859 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 28166 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 24058 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1604 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 4997 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4497 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6077 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5895 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6436 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 6919 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6498 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 8426 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8816 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 7437 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8393 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7415 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6659 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5777 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 212 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 217 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 170 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 214 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 137 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 247 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 198 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 254 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 173 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 62096 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 537.164648 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 331.293750 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 411.963299 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13665 22.01% 22.01% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10559 17.00% 39.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4854 7.82% 46.83% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2778 4.47% 51.30% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2418 3.89% 55.20% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1622 2.61% 57.81% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 3711 5.98% 63.78% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1214 1.96% 65.74% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 21275 34.26% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 62096 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5200 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 77.619423 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2241.505208 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-4095 5195 99.90% 99.90% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 5200 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 5200 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 22.606346 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 19.258970 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 21.077519 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16-23 4603 88.52% 88.52% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24-31 36 0.69% 89.21% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-39 24 0.46% 89.67% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::40-47 35 0.67% 90.35% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::48-55 205 3.94% 94.29% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::56-63 11 0.21% 94.50% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::64-71 15 0.29% 94.79% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::72-79 35 0.67% 95.46% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::80-87 175 3.37% 98.83% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::88-95 6 0.12% 98.94% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::96-103 7 0.13% 99.08% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::104-111 2 0.04% 99.12% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::112-119 1 0.02% 99.13% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 11 0.21% 99.35% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 6 0.12% 99.48% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 2 0.04% 99.52% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 4 0.08% 99.60% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 7 0.13% 99.73% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 2 0.04% 99.77% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 1 0.02% 99.79% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 3 0.06% 99.85% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 3 0.06% 99.90% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::344-351 1 0.02% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5200 # Writes before turning the bus around for reads 255system.physmem.totQLat 4180311250 # Total ticks spent queuing 256system.physmem.totMemAccLat 11748392500 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 2018155000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 10356.76 # Average queueing delay per DRAM burst 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 260system.physmem.avgMemAccLat 29106.76 # Average memory access latency per DRAM burst 261system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.14 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 2.08 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing 271system.physmem.readRowHits 363824 # Number of row buffer hits during reads 272system.physmem.writeRowHits 95264 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes 275system.physmem.avgGap 3598021.21 # Average gap between requests 276system.physmem.pageHitRate 88.08 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 232326360 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 126765375 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1577331600 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 378529200 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 61450630965 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 1071548691000 # Energy for precharge background per rank (pJ) 284system.physmem_0.totalEnergy 1257829429860 # Total energy per rank (pJ) 285system.physmem_0.averagePower 670.572492 # Core power per rank (mW) 286system.physmem_0.memoryStateTime::IDLE 1782417296500 # Time in different power states 287system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states 288system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 289system.physmem_0.memoryStateTime::ACT 30701746000 # Time in different power states 290system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 291system.physmem_1.actEnergy 237119400 # Energy for activate commands per rank (pJ) 292system.physmem_1.preEnergy 129380625 # Energy for precharge commands per rank (pJ) 293system.physmem_1.readEnergy 1570990200 # Energy for read commands per rank (pJ) 294system.physmem_1.writeEnergy 383214240 # Energy for write commands per rank (pJ) 295system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 296system.physmem_1.actBackEnergy 61460167635 # Energy for active background per rank (pJ) 297system.physmem_1.preBackEnergy 1071540333750 # Energy for precharge background per rank (pJ) 298system.physmem_1.totalEnergy 1257836361210 # Total energy per rank (pJ) 299system.physmem_1.averagePower 670.576183 # Core power per rank (mW) 300system.physmem_1.memoryStateTime::IDLE 1782399409250 # Time in different power states 301system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states 302system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 303system.physmem_1.memoryStateTime::ACT 30719647000 # Time in different power states 304system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 305system.cpu.branchPred.lookups 17926200 # Number of BP lookups 306system.cpu.branchPred.condPredicted 15634549 # Number of conditional branches predicted 307system.cpu.branchPred.condIncorrect 367641 # Number of conditional branches incorrect 308system.cpu.branchPred.BTBLookups 11517888 # Number of BTB lookups 309system.cpu.branchPred.BTBHits 5853508 # Number of BTB hits 310system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 311system.cpu.branchPred.BTBHitPct 50.821019 # BTB Hit Percentage 312system.cpu.branchPred.usedRAS 912312 # Number of times the RAS was used to get a target. 313system.cpu.branchPred.RASInCorrect 21142 # Number of incorrect RAS predictions. 314system.cpu_clk_domain.clock 500 # Clock period in ticks 315system.cpu.dtb.fetch_hits 0 # ITB hits 316system.cpu.dtb.fetch_misses 0 # ITB misses 317system.cpu.dtb.fetch_acv 0 # ITB acv 318system.cpu.dtb.fetch_accesses 0 # ITB accesses 319system.cpu.dtb.read_hits 10248777 # DTB read hits 320system.cpu.dtb.read_misses 41124 # DTB read misses 321system.cpu.dtb.read_acv 537 # DTB read access violations 322system.cpu.dtb.read_accesses 965282 # DTB read accesses 323system.cpu.dtb.write_hits 6643148 # DTB write hits 324system.cpu.dtb.write_misses 9690 # DTB write misses 325system.cpu.dtb.write_acv 398 # DTB write access violations 326system.cpu.dtb.write_accesses 341994 # DTB write accesses 327system.cpu.dtb.data_hits 16891925 # DTB hits 328system.cpu.dtb.data_misses 50814 # DTB misses 329system.cpu.dtb.data_acv 935 # DTB access violations 330system.cpu.dtb.data_accesses 1307276 # DTB accesses 331system.cpu.itb.fetch_hits 1767471 # ITB hits 332system.cpu.itb.fetch_misses 28221 # ITB misses 333system.cpu.itb.fetch_acv 656 # ITB acv 334system.cpu.itb.fetch_accesses 1795692 # ITB accesses 335system.cpu.itb.read_hits 0 # DTB read hits 336system.cpu.itb.read_misses 0 # DTB read misses 337system.cpu.itb.read_acv 0 # DTB read access violations 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses 347system.cpu.numCycles 154296938 # number of cpu cycles simulated 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 350system.cpu.fetch.icacheStallCycles 29565992 # Number of cycles fetch is stalled on an Icache miss 351system.cpu.fetch.Insts 77998562 # Number of instructions fetch has processed 352system.cpu.fetch.Branches 17926200 # Number of branches that fetch encountered 353system.cpu.fetch.predictedBranches 6765820 # Number of branches that fetch has predicted taken 354system.cpu.fetch.Cycles 115499750 # Number of cycles fetch has run and was not squashing or blocked 355system.cpu.fetch.SquashCycles 1227580 # Number of cycles fetch has spent squashing 356system.cpu.fetch.TlbCycles 1879 # Number of cycles fetch has spent waiting for tlb 357system.cpu.fetch.MiscStallCycles 29906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 358system.cpu.fetch.PendingTrapStallCycles 1313604 # Number of stall cycles due to pending traps 359system.cpu.fetch.PendingQuiesceStallCycles 470747 # Number of stall cycles due to pending quiesce instructions 360system.cpu.fetch.IcacheWaitRetryStallCycles 522 # Number of stall cycles due to full MSHR 361system.cpu.fetch.CacheLines 8986717 # Number of cache lines fetched 362system.cpu.fetch.IcacheSquashes 269982 # Number of outstanding Icache misses that were squashed 363system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 364system.cpu.fetch.rateDist::samples 147496190 # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::mean 0.528817 # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::stdev 1.784795 # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::0 132977860 90.16% 90.16% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::1 927689 0.63% 90.79% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::2 1955483 1.33% 92.11% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::3 905427 0.61% 92.73% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::4 2772003 1.88% 94.60% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::5 615447 0.42% 95.02% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::6 725348 0.49% 95.51% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::7 1009173 0.68% 96.20% # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::8 5607760 3.80% 100.00% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::total 147496190 # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.branchRate 0.116180 # Number of branch fetches per cycle 382system.cpu.fetch.rate 0.505509 # Number of inst fetches per cycle 383system.cpu.decode.IdleCycles 23986183 # Number of cycles decode is idle 384system.cpu.decode.BlockedCycles 111594322 # Number of cycles decode is blocked 385system.cpu.decode.RunCycles 9434858 # Number of cycles decode is running 386system.cpu.decode.UnblockCycles 1908489 # Number of cycles decode is unblocking 387system.cpu.decode.SquashCycles 572337 # Number of cycles decode is squashing 388system.cpu.decode.BranchResolved 581608 # Number of times decode resolved a branch 389system.cpu.decode.BranchMispred 41807 # Number of times decode detected a branch misprediction 390system.cpu.decode.DecodedInsts 68042420 # Number of instructions handled by decode 391system.cpu.decode.SquashedInsts 132440 # Number of squashed instructions handled by decode 392system.cpu.rename.SquashCycles 572337 # Number of cycles rename is squashing 393system.cpu.rename.IdleCycles 24909467 # Number of cycles rename is idle 394system.cpu.rename.BlockCycles 78381394 # Number of cycles rename is blocking 395system.cpu.rename.serializeStallCycles 21682831 # count of cycles rename stalled for serializing inst 396system.cpu.rename.RunCycles 10333745 # Number of cycles rename is running 397system.cpu.rename.UnblockCycles 11616414 # Number of cycles rename is unblocking 398system.cpu.rename.RenamedInsts 65623799 # Number of instructions processed by rename 399system.cpu.rename.ROBFullEvents 205401 # Number of times rename has blocked due to ROB full 400system.cpu.rename.IQFullEvents 2094519 # Number of times rename has blocked due to IQ full 401system.cpu.rename.LQFullEvents 225742 # Number of times rename has blocked due to LQ full 402system.cpu.rename.SQFullEvents 7349306 # Number of times rename has blocked due to SQ full 403system.cpu.rename.RenamedOperands 43739456 # Number of destination operands rename has renamed 404system.cpu.rename.RenameLookups 79586592 # Number of register rename lookups that rename has made 405system.cpu.rename.int_rename_lookups 79405874 # Number of integer rename lookups 406system.cpu.rename.fp_rename_lookups 168265 # Number of floating rename lookups 407system.cpu.rename.CommittedMaps 38181154 # Number of HB maps that are committed 408system.cpu.rename.UndoneMaps 5558294 # Number of HB maps that are undone due to squashing 409system.cpu.rename.serializingInsts 1689229 # count of serializing insts renamed 410system.cpu.rename.tempSerializingInsts 239421 # count of temporary serializing insts renamed 411system.cpu.rename.skidInsts 13564930 # count of insts added to the skid buffer 412system.cpu.memDep0.insertedLoads 10374266 # Number of loads inserted to the mem dependence unit. 413system.cpu.memDep0.insertedStores 6952166 # Number of stores inserted to the mem dependence unit. 414system.cpu.memDep0.conflictingLoads 1510457 # Number of conflicting loads. 415system.cpu.memDep0.conflictingStores 1094829 # Number of conflicting stores. 416system.cpu.iq.iqInstsAdded 58464384 # Number of instructions added to the IQ (excludes non-spec) 417system.cpu.iq.iqNonSpecInstsAdded 2137218 # Number of non-speculative instructions added to the IQ 418system.cpu.iq.iqInstsIssued 57492092 # Number of instructions issued 419system.cpu.iq.iqSquashedInstsIssued 57307 # Number of squashed instructions issued 420system.cpu.iq.iqSquashedInstsExamined 7620053 # Number of squashed instructions iterated over during squash; mainly for profiling 421system.cpu.iq.iqSquashedOperandsExamined 3404147 # Number of squashed operands that are examined and possibly removed from graph 422system.cpu.iq.iqSquashedNonSpecRemoved 1476015 # Number of squashed non-spec instructions that were removed 423system.cpu.iq.issued_per_cycle::samples 147496190 # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::mean 0.389787 # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::stdev 1.113704 # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::0 123903149 84.00% 84.00% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::1 10174594 6.90% 90.90% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::2 4283554 2.90% 93.81% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::3 3020095 2.05% 95.85% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::4 3079434 2.09% 97.94% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::5 1494296 1.01% 98.96% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::6 1011464 0.69% 99.64% # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::7 404727 0.27% 99.92% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::8 124877 0.08% 100.00% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::total 147496190 # Number of insts issued each cycle 440system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 441system.cpu.iq.fu_full::IntAlu 210492 18.68% 18.68% # attempts to use FU when none available 442system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available 443system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available 446system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available 448system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available 449system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 470system.cpu.iq.fu_full::MemRead 541350 48.03% 66.71% # attempts to use FU when none available 471system.cpu.iq.fu_full::MemWrite 375218 33.29% 100.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 473system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 474system.cpu.iq.FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued 475system.cpu.iq.FU_type_0::IntAlu 39049419 67.92% 67.93% # Type of FU issued 476system.cpu.iq.FU_type_0::IntMult 61870 0.11% 68.04% # Type of FU issued 477system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued 480system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued 481system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued 482system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.12% # Type of FU issued 483system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.12% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued 504system.cpu.iq.FU_type_0::MemRead 10658869 18.54% 86.65% # Type of FU issued 505system.cpu.iq.FU_type_0::MemWrite 6723409 11.69% 98.35% # Type of FU issued 506system.cpu.iq.FU_type_0::IprAccess 949053 1.65% 100.00% # Type of FU issued 507system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 508system.cpu.iq.FU_type_0::total 57492092 # Type of FU issued 509system.cpu.iq.rate 0.372607 # Inst issue rate 510system.cpu.iq.fu_busy_cnt 1127060 # FU busy when requested 511system.cpu.iq.fu_busy_rate 0.019604 # FU busy rate (busy events/executed inst) 512system.cpu.iq.int_inst_queue_reads 262951820 # Number of integer instruction queue reads 513system.cpu.iq.int_inst_queue_writes 67904206 # Number of integer instruction queue writes 514system.cpu.iq.int_inst_queue_wakeup_accesses 55848058 # Number of integer instruction queue wakeup accesses 515system.cpu.iq.fp_inst_queue_reads 712920 # Number of floating instruction queue reads 516system.cpu.iq.fp_inst_queue_writes 336440 # Number of floating instruction queue writes 517system.cpu.iq.fp_inst_queue_wakeup_accesses 329015 # Number of floating instruction queue wakeup accesses 518system.cpu.iq.int_alu_accesses 58229078 # Number of integer alu accesses 519system.cpu.iq.fp_alu_accesses 382791 # Number of floating point alu accesses 520system.cpu.iew.lsq.thread0.forwLoads 635540 # Number of loads that had data forwarded from stores 521system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 522system.cpu.iew.lsq.thread0.squashedLoads 1281314 # Number of loads squashed 523system.cpu.iew.lsq.thread0.ignoredResponses 3324 # Number of memory responses ignored because the instruction is squashed 524system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations 525system.cpu.iew.lsq.thread0.squashedStores 573929 # Number of stores squashed 526system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 527system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 528system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled 529system.cpu.iew.lsq.thread0.cacheBlocked 459106 # Number of times an access to memory failed due to the cache being blocked 530system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 531system.cpu.iew.iewSquashCycles 572337 # Number of cycles IEW is squashing 532system.cpu.iew.iewBlockCycles 74665457 # Number of cycles IEW is blocking 533system.cpu.iew.iewUnblockCycles 1160593 # Number of cycles IEW is unblocking 534system.cpu.iew.iewDispatchedInsts 64290812 # Number of instructions dispatched to IQ 535system.cpu.iew.iewDispSquashedInsts 139650 # Number of squashed instructions skipped by dispatch 536system.cpu.iew.iewDispLoadInsts 10374266 # Number of dispatched load instructions 537system.cpu.iew.iewDispStoreInsts 6952166 # Number of dispatched store instructions 538system.cpu.iew.iewDispNonSpecInsts 1889682 # Number of dispatched non-speculative instructions 539system.cpu.iew.iewIQFullEvents 43932 # Number of times the IQ has become full, causing a stall 540system.cpu.iew.iewLSQFullEvents 913665 # Number of times the LSQ has become full, causing a stall 541system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations 542system.cpu.iew.predictedTakenIncorrect 176905 # Number of branches that were predicted taken incorrectly 543system.cpu.iew.predictedNotTakenIncorrect 409384 # Number of branches that were predicted not taken incorrectly 544system.cpu.iew.branchMispredicts 586289 # Number of branch mispredicts detected at execute 545system.cpu.iew.iewExecutedInsts 56905925 # Number of executed instructions 546system.cpu.iew.iewExecLoadInsts 10317589 # Number of load instructions executed 547system.cpu.iew.iewExecSquashedInsts 586166 # Number of squashed instructions skipped in execute 548system.cpu.iew.exec_swp 0 # number of swp insts executed 549system.cpu.iew.exec_nop 3689210 # number of nop insts executed 550system.cpu.iew.exec_refs 16985526 # number of memory reference insts executed 551system.cpu.iew.exec_branches 8973539 # Number of branches executed 552system.cpu.iew.exec_stores 6667937 # Number of stores executed 553system.cpu.iew.exec_rate 0.368808 # Inst execution rate 554system.cpu.iew.wb_sent 56314090 # cumulative count of insts sent to commit 555system.cpu.iew.wb_count 56177073 # cumulative count of insts written-back 556system.cpu.iew.wb_producers 28757350 # num instructions producing a value 557system.cpu.iew.wb_consumers 39943859 # num instructions consuming a value 558system.cpu.iew.wb_rate 0.364084 # insts written-back per cycle 559system.cpu.iew.wb_fanout 0.719944 # average fanout of values written-back 560system.cpu.commit.commitSquashedInsts 8001816 # The number of squashed insts skipped by commit 561system.cpu.commit.commitNonSpecStalls 661203 # The number of times commit has been forced to stall to communicate backwards 562system.cpu.commit.branchMispredicts 537200 # The number of times a branch was mispredicted 563system.cpu.commit.committed_per_cycle::samples 146094021 # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::mean 0.384495 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::stdev 1.286335 # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::0 126314306 86.46% 86.46% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::1 7853790 5.38% 91.84% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::2 4274774 2.93% 94.76% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::3 2236101 1.53% 96.29% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::4 1744788 1.19% 97.49% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::5 615632 0.42% 97.91% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::6 478334 0.33% 98.24% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::7 476966 0.33% 98.56% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::8 2099330 1.44% 100.00% # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::total 146094021 # Number of insts commited each cycle 580system.cpu.commit.committedInsts 56172359 # Number of instructions committed 581system.cpu.commit.committedOps 56172359 # Number of ops (including micro ops) committed 582system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 583system.cpu.commit.refs 15471189 # Number of memory references committed 584system.cpu.commit.loads 9092952 # Number of loads committed 585system.cpu.commit.membars 226351 # Number of memory barriers committed 586system.cpu.commit.branches 8440746 # Number of branches committed 587system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 588system.cpu.commit.int_insts 52021709 # Number of committed integer instructions. 589system.cpu.commit.function_calls 740586 # Number of function calls committed. 590system.cpu.commit.op_class_0::No_OpClass 3198088 5.69% 5.69% # Class of committed instruction 591system.cpu.commit.op_class_0::IntAlu 36219325 64.48% 70.17% # Class of committed instruction 592system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction 593system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 596system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 597system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 598system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 599system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 620system.cpu.commit.op_class_0::MemRead 9319303 16.59% 86.95% # Class of committed instruction 621system.cpu.commit.op_class_0::MemWrite 6384192 11.37% 98.31% # Class of committed instruction 622system.cpu.commit.op_class_0::IprAccess 949053 1.69% 100.00% # Class of committed instruction 623system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 624system.cpu.commit.op_class_0::total 56172359 # Class of committed instruction 625system.cpu.commit.bw_lim_events 2099330 # number cycles where commit BW limit reached 626system.cpu.rob.rob_reads 207919346 # The number of ROB reads 627system.cpu.rob.rob_writes 129746181 # The number of ROB writes 628system.cpu.timesIdled 581168 # Number of times that the entire CPU went into an idle state and unscheduled itself 629system.cpu.idleCycles 6800748 # Total number of cycles that the CPU has spent unscheduled due to idling 630system.cpu.quiesceCycles 3597219294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 631system.cpu.committedInsts 52981544 # Number of Instructions Simulated 632system.cpu.committedOps 52981544 # Number of Ops (including micro ops) Simulated 633system.cpu.cpi 2.912277 # CPI: Cycles Per Instruction 634system.cpu.cpi_total 2.912277 # CPI: Total CPI of All Threads 635system.cpu.ipc 0.343374 # IPC: Instructions Per Cycle 636system.cpu.ipc_total 0.343374 # IPC: Total IPC of All Threads 637system.cpu.int_regfile_reads 74565581 # number of integer regfile reads 638system.cpu.int_regfile_writes 40526554 # number of integer regfile writes 639system.cpu.fp_regfile_reads 167056 # number of floating regfile reads 640system.cpu.fp_regfile_writes 167536 # number of floating regfile writes 641system.cpu.misc_regfile_reads 1985625 # number of misc regfile reads 642system.cpu.misc_regfile_writes 939435 # number of misc regfile writes 643system.cpu.dcache.tags.replacements 1401792 # number of replacements 644system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use 645system.cpu.dcache.tags.total_refs 11831016 # Total number of references to valid blocks. 646system.cpu.dcache.tags.sampled_refs 1402304 # Sample count of references to valid blocks. 647system.cpu.dcache.tags.avg_refs 8.436841 # Average number of references to valid blocks. 648system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 649system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor 650system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 651system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 652system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 653system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 654system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 655system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 656system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 657system.cpu.dcache.tags.tag_accesses 63836509 # Number of tag accesses 658system.cpu.dcache.tags.data_accesses 63836509 # Number of data accesses 659system.cpu.dcache.ReadReq_hits::cpu.data 7238578 # number of ReadReq hits 660system.cpu.dcache.ReadReq_hits::total 7238578 # number of ReadReq hits 661system.cpu.dcache.WriteReq_hits::cpu.data 4190111 # number of WriteReq hits 662system.cpu.dcache.WriteReq_hits::total 4190111 # number of WriteReq hits 663system.cpu.dcache.LoadLockedReq_hits::cpu.data 186204 # number of LoadLockedReq hits 664system.cpu.dcache.LoadLockedReq_hits::total 186204 # number of LoadLockedReq hits 665system.cpu.dcache.StoreCondReq_hits::cpu.data 215724 # number of StoreCondReq hits 666system.cpu.dcache.StoreCondReq_hits::total 215724 # number of StoreCondReq hits 667system.cpu.dcache.demand_hits::cpu.data 11428689 # number of demand (read+write) hits 668system.cpu.dcache.demand_hits::total 11428689 # number of demand (read+write) hits 669system.cpu.dcache.overall_hits::cpu.data 11428689 # number of overall hits 670system.cpu.dcache.overall_hits::total 11428689 # number of overall hits 671system.cpu.dcache.ReadReq_misses::cpu.data 1796989 # number of ReadReq misses 672system.cpu.dcache.ReadReq_misses::total 1796989 # number of ReadReq misses 673system.cpu.dcache.WriteReq_misses::cpu.data 1957670 # number of WriteReq misses 674system.cpu.dcache.WriteReq_misses::total 1957670 # number of WriteReq misses 675system.cpu.dcache.LoadLockedReq_misses::cpu.data 23246 # number of LoadLockedReq misses 676system.cpu.dcache.LoadLockedReq_misses::total 23246 # number of LoadLockedReq misses 677system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses 678system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses 679system.cpu.dcache.demand_misses::cpu.data 3754659 # number of demand (read+write) misses 680system.cpu.dcache.demand_misses::total 3754659 # number of demand (read+write) misses 681system.cpu.dcache.overall_misses::cpu.data 3754659 # number of overall misses 682system.cpu.dcache.overall_misses::total 3754659 # number of overall misses 683system.cpu.dcache.ReadReq_miss_latency::cpu.data 57191537500 # number of ReadReq miss cycles 684system.cpu.dcache.ReadReq_miss_latency::total 57191537500 # number of ReadReq miss cycles 685system.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150 # number of WriteReq miss cycles 686system.cpu.dcache.WriteReq_miss_latency::total 116815247150 # number of WriteReq miss cycles 687system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448333000 # number of LoadLockedReq miss cycles 688system.cpu.dcache.LoadLockedReq_miss_latency::total 448333000 # number of LoadLockedReq miss cycles 689system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 872000 # number of StoreCondReq miss cycles 690system.cpu.dcache.StoreCondReq_miss_latency::total 872000 # number of StoreCondReq miss cycles 691system.cpu.dcache.demand_miss_latency::cpu.data 174006784650 # number of demand (read+write) miss cycles 692system.cpu.dcache.demand_miss_latency::total 174006784650 # number of demand (read+write) miss cycles 693system.cpu.dcache.overall_miss_latency::cpu.data 174006784650 # number of overall miss cycles 694system.cpu.dcache.overall_miss_latency::total 174006784650 # number of overall miss cycles 695system.cpu.dcache.ReadReq_accesses::cpu.data 9035567 # number of ReadReq accesses(hits+misses) 696system.cpu.dcache.ReadReq_accesses::total 9035567 # number of ReadReq accesses(hits+misses) 697system.cpu.dcache.WriteReq_accesses::cpu.data 6147781 # number of WriteReq accesses(hits+misses) 698system.cpu.dcache.WriteReq_accesses::total 6147781 # number of WriteReq accesses(hits+misses) 699system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209450 # number of LoadLockedReq accesses(hits+misses) 700system.cpu.dcache.LoadLockedReq_accesses::total 209450 # number of LoadLockedReq accesses(hits+misses) 701system.cpu.dcache.StoreCondReq_accesses::cpu.data 215753 # number of StoreCondReq accesses(hits+misses) 702system.cpu.dcache.StoreCondReq_accesses::total 215753 # number of StoreCondReq accesses(hits+misses) 703system.cpu.dcache.demand_accesses::cpu.data 15183348 # number of demand (read+write) accesses 704system.cpu.dcache.demand_accesses::total 15183348 # number of demand (read+write) accesses 705system.cpu.dcache.overall_accesses::cpu.data 15183348 # number of overall (read+write) accesses 706system.cpu.dcache.overall_accesses::total 15183348 # number of overall (read+write) accesses 707system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198879 # miss rate for ReadReq accesses 708system.cpu.dcache.ReadReq_miss_rate::total 0.198879 # miss rate for ReadReq accesses 709system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318435 # miss rate for WriteReq accesses 710system.cpu.dcache.WriteReq_miss_rate::total 0.318435 # miss rate for WriteReq accesses 711system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110986 # miss rate for LoadLockedReq accesses 712system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110986 # miss rate for LoadLockedReq accesses 713system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses 714system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses 715system.cpu.dcache.demand_miss_rate::cpu.data 0.247288 # miss rate for demand accesses 716system.cpu.dcache.demand_miss_rate::total 0.247288 # miss rate for demand accesses 717system.cpu.dcache.overall_miss_rate::cpu.data 0.247288 # miss rate for overall accesses 718system.cpu.dcache.overall_miss_rate::total 0.247288 # miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741 # average ReadReq miss latency 720system.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741 # average ReadReq miss latency 721system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782 # average WriteReq miss latency 722system.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782 # average WriteReq miss latency 723system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885 # average LoadLockedReq miss latency 724system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885 # average LoadLockedReq miss latency 725system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517 # average StoreCondReq miss latency 726system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517 # average StoreCondReq miss latency 727system.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency 728system.cpu.dcache.demand_avg_miss_latency::total 46344.231167 # average overall miss latency 729system.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency 730system.cpu.dcache.overall_avg_miss_latency::total 46344.231167 # average overall miss latency 731system.cpu.dcache.blocked_cycles::no_mshrs 7151643 # number of cycles access was blocked 732system.cpu.dcache.blocked_cycles::no_targets 5595 # number of cycles access was blocked 733system.cpu.dcache.blocked::no_mshrs 133832 # number of cycles access was blocked 734system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked 735system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437466 # average number of cycles each access was blocked 736system.cpu.dcache.avg_blocked_cycles::no_targets 199.821429 # average number of cycles each access was blocked 737system.cpu.dcache.fast_writes 0 # number of fast writes performed 738system.cpu.dcache.cache_copies 0 # number of cache copies performed 739system.cpu.dcache.writebacks::writebacks 841120 # number of writebacks 740system.cpu.dcache.writebacks::total 841120 # number of writebacks 741system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703166 # number of ReadReq MSHR hits 742system.cpu.dcache.ReadReq_mshr_hits::total 703166 # number of ReadReq MSHR hits 743system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666991 # number of WriteReq MSHR hits 744system.cpu.dcache.WriteReq_mshr_hits::total 1666991 # number of WriteReq MSHR hits 745system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5234 # number of LoadLockedReq MSHR hits 746system.cpu.dcache.LoadLockedReq_mshr_hits::total 5234 # number of LoadLockedReq MSHR hits 747system.cpu.dcache.demand_mshr_hits::cpu.data 2370157 # number of demand (read+write) MSHR hits 748system.cpu.dcache.demand_mshr_hits::total 2370157 # number of demand (read+write) MSHR hits 749system.cpu.dcache.overall_mshr_hits::cpu.data 2370157 # number of overall MSHR hits 750system.cpu.dcache.overall_mshr_hits::total 2370157 # number of overall MSHR hits 751system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093823 # number of ReadReq MSHR misses 752system.cpu.dcache.ReadReq_mshr_misses::total 1093823 # number of ReadReq MSHR misses 753system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290679 # number of WriteReq MSHR misses 754system.cpu.dcache.WriteReq_mshr_misses::total 290679 # number of WriteReq MSHR misses 755system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18012 # number of LoadLockedReq MSHR misses 756system.cpu.dcache.LoadLockedReq_mshr_misses::total 18012 # number of LoadLockedReq MSHR misses 757system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses 758system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses 759system.cpu.dcache.demand_mshr_misses::cpu.data 1384502 # number of demand (read+write) MSHR misses 760system.cpu.dcache.demand_mshr_misses::total 1384502 # number of demand (read+write) MSHR misses 761system.cpu.dcache.overall_mshr_misses::cpu.data 1384502 # number of overall MSHR misses 762system.cpu.dcache.overall_mshr_misses::total 1384502 # number of overall MSHR misses 763system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 764system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 765system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 766system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 767system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 768system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 769system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44561431000 # number of ReadReq MSHR miss cycles 770system.cpu.dcache.ReadReq_mshr_miss_latency::total 44561431000 # number of ReadReq MSHR miss cycles 771system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18441083775 # number of WriteReq MSHR miss cycles 772system.cpu.dcache.WriteReq_mshr_miss_latency::total 18441083775 # number of WriteReq MSHR miss cycles 773system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229476500 # number of LoadLockedReq MSHR miss cycles 774system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229476500 # number of LoadLockedReq MSHR miss cycles 775system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 843000 # number of StoreCondReq MSHR miss cycles 776system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 843000 # number of StoreCondReq MSHR miss cycles 777system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63002514775 # number of demand (read+write) MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::total 63002514775 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63002514775 # number of overall MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::total 63002514775 # number of overall MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528979500 # number of ReadReq MSHR uncacheable cycles 782system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528979500 # number of ReadReq MSHR uncacheable cycles 783system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154218500 # number of WriteReq MSHR uncacheable cycles 784system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154218500 # number of WriteReq MSHR uncacheable cycles 785system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683198000 # number of overall MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683198000 # number of overall MSHR uncacheable cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121057 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121057 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047282 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047282 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085997 # mshr miss rate for LoadLockedReq accesses 792system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085997 # mshr miss rate for LoadLockedReq accesses 793system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses 794system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses 795system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for demand accesses 796system.cpu.dcache.demand_mshr_miss_rate::total 0.091186 # mshr miss rate for demand accesses 797system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for overall accesses 798system.cpu.dcache.overall_mshr_miss_rate::total 0.091186 # mshr miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723 # average ReadReq mshr miss latency 800system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723 # average ReadReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662 # average WriteReq mshr miss latency 802system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662 # average WriteReq mshr miss latency 803system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977 # average LoadLockedReq mshr miss latency 804system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977 # average LoadLockedReq mshr miss latency 805system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517 # average StoreCondReq mshr miss latency 806system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517 # average StoreCondReq mshr miss latency 807system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency 809system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency 811system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482 # average ReadReq mshr uncacheable latency 812system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482 # average ReadReq mshr uncacheable latency 813system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692 # average WriteReq mshr uncacheable latency 814system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692 # average WriteReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374 # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374 # average overall mshr uncacheable latency 817system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.cpu.icache.tags.replacements 1035081 # number of replacements 819system.cpu.icache.tags.tagsinuse 507.835100 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 7897485 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 1035589 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 7.626080 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 507.835100 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy 826system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy 827system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 828system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 829system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 830system.cpu.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id 831system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 832system.cpu.icache.tags.tag_accesses 10022677 # Number of tag accesses 833system.cpu.icache.tags.data_accesses 10022677 # Number of data accesses 834system.cpu.icache.ReadReq_hits::cpu.inst 7897486 # number of ReadReq hits 835system.cpu.icache.ReadReq_hits::total 7897486 # number of ReadReq hits 836system.cpu.icache.demand_hits::cpu.inst 7897486 # number of demand (read+write) hits 837system.cpu.icache.demand_hits::total 7897486 # number of demand (read+write) hits 838system.cpu.icache.overall_hits::cpu.inst 7897486 # number of overall hits 839system.cpu.icache.overall_hits::total 7897486 # number of overall hits 840system.cpu.icache.ReadReq_misses::cpu.inst 1089229 # number of ReadReq misses 841system.cpu.icache.ReadReq_misses::total 1089229 # number of ReadReq misses 842system.cpu.icache.demand_misses::cpu.inst 1089229 # number of demand (read+write) misses 843system.cpu.icache.demand_misses::total 1089229 # number of demand (read+write) misses 844system.cpu.icache.overall_misses::cpu.inst 1089229 # number of overall misses 845system.cpu.icache.overall_misses::total 1089229 # number of overall misses 846system.cpu.icache.ReadReq_miss_latency::cpu.inst 16358882985 # number of ReadReq miss cycles 847system.cpu.icache.ReadReq_miss_latency::total 16358882985 # number of ReadReq miss cycles 848system.cpu.icache.demand_miss_latency::cpu.inst 16358882985 # number of demand (read+write) miss cycles 849system.cpu.icache.demand_miss_latency::total 16358882985 # number of demand (read+write) miss cycles 850system.cpu.icache.overall_miss_latency::cpu.inst 16358882985 # number of overall miss cycles 851system.cpu.icache.overall_miss_latency::total 16358882985 # number of overall miss cycles 852system.cpu.icache.ReadReq_accesses::cpu.inst 8986715 # number of ReadReq accesses(hits+misses) 853system.cpu.icache.ReadReq_accesses::total 8986715 # number of ReadReq accesses(hits+misses) 854system.cpu.icache.demand_accesses::cpu.inst 8986715 # number of demand (read+write) accesses 855system.cpu.icache.demand_accesses::total 8986715 # number of demand (read+write) accesses 856system.cpu.icache.overall_accesses::cpu.inst 8986715 # number of overall (read+write) accesses 857system.cpu.icache.overall_accesses::total 8986715 # number of overall (read+write) accesses 858system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121204 # miss rate for ReadReq accesses 859system.cpu.icache.ReadReq_miss_rate::total 0.121204 # miss rate for ReadReq accesses 860system.cpu.icache.demand_miss_rate::cpu.inst 0.121204 # miss rate for demand accesses 861system.cpu.icache.demand_miss_rate::total 0.121204 # miss rate for demand accesses 862system.cpu.icache.overall_miss_rate::cpu.inst 0.121204 # miss rate for overall accesses 863system.cpu.icache.overall_miss_rate::total 0.121204 # miss rate for overall accesses 864system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.772898 # average ReadReq miss latency 865system.cpu.icache.ReadReq_avg_miss_latency::total 15018.772898 # average ReadReq miss latency 866system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency 867system.cpu.icache.demand_avg_miss_latency::total 15018.772898 # average overall miss latency 868system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency 869system.cpu.icache.overall_avg_miss_latency::total 15018.772898 # average overall miss latency 870system.cpu.icache.blocked_cycles::no_mshrs 10400 # number of cycles access was blocked 871system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 872system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked 873system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 874system.cpu.icache.avg_blocked_cycles::no_mshrs 33.766234 # average number of cycles each access was blocked 875system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 876system.cpu.icache.fast_writes 0 # number of fast writes performed 877system.cpu.icache.cache_copies 0 # number of cache copies performed 878system.cpu.icache.writebacks::writebacks 1035081 # number of writebacks 879system.cpu.icache.writebacks::total 1035081 # number of writebacks 880system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53267 # number of ReadReq MSHR hits 881system.cpu.icache.ReadReq_mshr_hits::total 53267 # number of ReadReq MSHR hits 882system.cpu.icache.demand_mshr_hits::cpu.inst 53267 # number of demand (read+write) MSHR hits 883system.cpu.icache.demand_mshr_hits::total 53267 # number of demand (read+write) MSHR hits 884system.cpu.icache.overall_mshr_hits::cpu.inst 53267 # number of overall MSHR hits 885system.cpu.icache.overall_mshr_hits::total 53267 # number of overall MSHR hits 886system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035962 # number of ReadReq MSHR misses 887system.cpu.icache.ReadReq_mshr_misses::total 1035962 # number of ReadReq MSHR misses 888system.cpu.icache.demand_mshr_misses::cpu.inst 1035962 # number of demand (read+write) MSHR misses 889system.cpu.icache.demand_mshr_misses::total 1035962 # number of demand (read+write) MSHR misses 890system.cpu.icache.overall_mshr_misses::cpu.inst 1035962 # number of overall MSHR misses 891system.cpu.icache.overall_mshr_misses::total 1035962 # number of overall MSHR misses 892system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14427899492 # number of ReadReq MSHR miss cycles 893system.cpu.icache.ReadReq_mshr_miss_latency::total 14427899492 # number of ReadReq MSHR miss cycles 894system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14427899492 # number of demand (read+write) MSHR miss cycles 895system.cpu.icache.demand_mshr_miss_latency::total 14427899492 # number of demand (read+write) MSHR miss cycles 896system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14427899492 # number of overall MSHR miss cycles 897system.cpu.icache.overall_mshr_miss_latency::total 14427899492 # number of overall MSHR miss cycles 898system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for ReadReq accesses 899system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115277 # mshr miss rate for ReadReq accesses 900system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for demand accesses 901system.cpu.icache.demand_mshr_miss_rate::total 0.115277 # mshr miss rate for demand accesses 902system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for overall accesses 903system.cpu.icache.overall_mshr_miss_rate::total 0.115277 # mshr miss rate for overall accesses 904system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13927.054749 # average ReadReq mshr miss latency 905system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13927.054749 # average ReadReq mshr miss latency 906system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency 907system.cpu.icache.demand_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency 908system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency 909system.cpu.icache.overall_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency 910system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 911system.cpu.l2cache.tags.replacements 338544 # number of replacements 912system.cpu.l2cache.tags.tagsinuse 65279.658287 # Cycle average of tags in use 913system.cpu.l2cache.tags.total_refs 4165713 # Total number of references to valid blocks. 914system.cpu.l2cache.tags.sampled_refs 403711 # Sample count of references to valid blocks. 915system.cpu.l2cache.tags.avg_refs 10.318552 # Average number of references to valid blocks. 916system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. 917system.cpu.l2cache.tags.occ_blocks::writebacks 53291.619090 # Average occupied blocks per requestor 918system.cpu.l2cache.tags.occ_blocks::cpu.inst 5239.581641 # Average occupied blocks per requestor 919system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.457555 # Average occupied blocks per requestor 920system.cpu.l2cache.tags.occ_percent::writebacks 0.813166 # Average percentage of cache occupancy 921system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079950 # Average percentage of cache occupancy 922system.cpu.l2cache.tags.occ_percent::cpu.data 0.102973 # Average percentage of cache occupancy 923system.cpu.l2cache.tags.occ_percent::total 0.996089 # Average percentage of cache occupancy 924system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 925system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 926system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3482 # Occupied blocks per task id 927system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3333 # Occupied blocks per task id 928system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2426 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id 930system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 931system.cpu.l2cache.tags.tag_accesses 39690670 # Number of tag accesses 932system.cpu.l2cache.tags.data_accesses 39690670 # Number of data accesses 933system.cpu.l2cache.WritebackDirty_hits::writebacks 841120 # number of WritebackDirty hits 934system.cpu.l2cache.WritebackDirty_hits::total 841120 # number of WritebackDirty hits 935system.cpu.l2cache.WritebackClean_hits::writebacks 1034540 # number of WritebackClean hits 936system.cpu.l2cache.WritebackClean_hits::total 1034540 # number of WritebackClean hits 937system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 938system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 939system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 940system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 941system.cpu.l2cache.ReadExReq_hits::cpu.data 185946 # number of ReadExReq hits 942system.cpu.l2cache.ReadExReq_hits::total 185946 # number of ReadExReq hits 943system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1020673 # number of ReadCleanReq hits 944system.cpu.l2cache.ReadCleanReq_hits::total 1020673 # number of ReadCleanReq hits 945system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827071 # number of ReadSharedReq hits 946system.cpu.l2cache.ReadSharedReq_hits::total 827071 # number of ReadSharedReq hits 947system.cpu.l2cache.demand_hits::cpu.inst 1020673 # number of demand (read+write) hits 948system.cpu.l2cache.demand_hits::cpu.data 1013017 # number of demand (read+write) hits 949system.cpu.l2cache.demand_hits::total 2033690 # number of demand (read+write) hits 950system.cpu.l2cache.overall_hits::cpu.inst 1020673 # number of overall hits 951system.cpu.l2cache.overall_hits::cpu.data 1013017 # number of overall hits 952system.cpu.l2cache.overall_hits::total 2033690 # number of overall hits 953system.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses 954system.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses 955system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses 956system.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses 957system.cpu.l2cache.ReadExReq_misses::cpu.data 115508 # number of ReadExReq misses 958system.cpu.l2cache.ReadExReq_misses::total 115508 # number of ReadExReq misses 959system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 14974 # number of ReadCleanReq misses 960system.cpu.l2cache.ReadCleanReq_misses::total 14974 # number of ReadCleanReq misses 961system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273861 # number of ReadSharedReq misses 962system.cpu.l2cache.ReadSharedReq_misses::total 273861 # number of ReadSharedReq misses 963system.cpu.l2cache.demand_misses::cpu.inst 14974 # number of demand (read+write) misses 964system.cpu.l2cache.demand_misses::cpu.data 389369 # number of demand (read+write) misses 965system.cpu.l2cache.demand_misses::total 404343 # number of demand (read+write) misses 966system.cpu.l2cache.overall_misses::cpu.inst 14974 # number of overall misses 967system.cpu.l2cache.overall_misses::cpu.data 389369 # number of overall misses 968system.cpu.l2cache.overall_misses::total 404343 # number of overall misses 969system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 786000 # number of UpgradeReq miss cycles 970system.cpu.l2cache.UpgradeReq_miss_latency::total 786000 # number of UpgradeReq miss cycles 971system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 235500 # number of SCUpgradeReq miss cycles 972system.cpu.l2cache.SCUpgradeReq_miss_latency::total 235500 # number of SCUpgradeReq miss cycles 973system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16104953000 # number of ReadExReq miss cycles 974system.cpu.l2cache.ReadExReq_miss_latency::total 16104953000 # number of ReadExReq miss cycles 975system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2014947000 # number of ReadCleanReq miss cycles 976system.cpu.l2cache.ReadCleanReq_miss_latency::total 2014947000 # number of ReadCleanReq miss cycles 977system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34006362500 # number of ReadSharedReq miss cycles 978system.cpu.l2cache.ReadSharedReq_miss_latency::total 34006362500 # number of ReadSharedReq miss cycles 979system.cpu.l2cache.demand_miss_latency::cpu.inst 2014947000 # number of demand (read+write) miss cycles 980system.cpu.l2cache.demand_miss_latency::cpu.data 50111315500 # number of demand (read+write) miss cycles 981system.cpu.l2cache.demand_miss_latency::total 52126262500 # number of demand (read+write) miss cycles 982system.cpu.l2cache.overall_miss_latency::cpu.inst 2014947000 # number of overall miss cycles 983system.cpu.l2cache.overall_miss_latency::cpu.data 50111315500 # number of overall miss cycles 984system.cpu.l2cache.overall_miss_latency::total 52126262500 # number of overall miss cycles 985system.cpu.l2cache.WritebackDirty_accesses::writebacks 841120 # number of WritebackDirty accesses(hits+misses) 986system.cpu.l2cache.WritebackDirty_accesses::total 841120 # number of WritebackDirty accesses(hits+misses) 987system.cpu.l2cache.WritebackClean_accesses::writebacks 1034540 # number of WritebackClean accesses(hits+misses) 988system.cpu.l2cache.WritebackClean_accesses::total 1034540 # number of WritebackClean accesses(hits+misses) 989system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) 990system.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) 991system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) 992system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) 993system.cpu.l2cache.ReadExReq_accesses::cpu.data 301454 # number of ReadExReq accesses(hits+misses) 994system.cpu.l2cache.ReadExReq_accesses::total 301454 # number of ReadExReq accesses(hits+misses) 995system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1035647 # number of ReadCleanReq accesses(hits+misses) 996system.cpu.l2cache.ReadCleanReq_accesses::total 1035647 # number of ReadCleanReq accesses(hits+misses) 997system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100932 # number of ReadSharedReq accesses(hits+misses) 998system.cpu.l2cache.ReadSharedReq_accesses::total 1100932 # number of ReadSharedReq accesses(hits+misses) 999system.cpu.l2cache.demand_accesses::cpu.inst 1035647 # number of demand (read+write) accesses 1000system.cpu.l2cache.demand_accesses::cpu.data 1402386 # number of demand (read+write) accesses 1001system.cpu.l2cache.demand_accesses::total 2438033 # number of demand (read+write) accesses 1002system.cpu.l2cache.overall_accesses::cpu.inst 1035647 # number of overall (read+write) accesses 1003system.cpu.l2cache.overall_accesses::cpu.data 1402386 # number of overall (read+write) accesses 1004system.cpu.l2cache.overall_accesses::total 2438033 # number of overall (read+write) accesses 1005system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses 1006system.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses 1007system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses 1008system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.241379 # miss rate for SCUpgradeReq accesses 1009system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383170 # miss rate for ReadExReq accesses 1010system.cpu.l2cache.ReadExReq_miss_rate::total 0.383170 # miss rate for ReadExReq accesses 1011system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014459 # miss rate for ReadCleanReq accesses 1012system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014459 # miss rate for ReadCleanReq accesses 1013system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248754 # miss rate for ReadSharedReq accesses 1014system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248754 # miss rate for ReadSharedReq accesses 1015system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014459 # miss rate for demand accesses 1016system.cpu.l2cache.demand_miss_rate::cpu.data 0.277648 # miss rate for demand accesses 1017system.cpu.l2cache.demand_miss_rate::total 0.165848 # miss rate for demand accesses 1018system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014459 # miss rate for overall accesses 1019system.cpu.l2cache.overall_miss_rate::cpu.data 0.277648 # miss rate for overall accesses 1020system.cpu.l2cache.overall_miss_rate::total 0.165848 # miss rate for overall accesses 1021system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7782.178218 # average UpgradeReq miss latency 1022system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7782.178218 # average UpgradeReq miss latency 1023system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 33642.857143 # average SCUpgradeReq miss latency 1024system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 33642.857143 # average SCUpgradeReq miss latency 1025system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139427.165218 # average ReadExReq miss latency 1026system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139427.165218 # average ReadExReq miss latency 1027system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134563.042607 # average ReadCleanReq miss latency 1028system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134563.042607 # average ReadCleanReq miss latency 1029system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124173.805325 # average ReadSharedReq miss latency 1030system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124173.805325 # average ReadSharedReq miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency 1033system.cpu.l2cache.demand_avg_miss_latency::total 128915.951309 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::total 128915.951309 # average overall miss latency 1037system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1043system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1044system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1045system.cpu.l2cache.writebacks::writebacks 76064 # number of writebacks 1046system.cpu.l2cache.writebacks::total 76064 # number of writebacks 1047system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1048system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1049system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1050system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1051system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1052system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1053system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 # number of UpgradeReq MSHR misses 1054system.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses 1055system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses 1056system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses 1057system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115508 # number of ReadExReq MSHR misses 1058system.cpu.l2cache.ReadExReq_mshr_misses::total 115508 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses 1060system.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses 1061system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273861 # number of ReadSharedReq MSHR misses 1062system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273861 # number of ReadSharedReq MSHR misses 1063system.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses 1064system.cpu.l2cache.demand_mshr_misses::cpu.data 389369 # number of demand (read+write) MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::total 404342 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses 1067system.cpu.l2cache.overall_mshr_misses::cpu.data 389369 # number of overall MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::total 404342 # number of overall MSHR misses 1069system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1070system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 1071system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 1072system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 1073system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 1074system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 1075system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6981000 # number of UpgradeReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6981000 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 479500 # number of SCUpgradeReq MSHR miss cycles 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 479500 # number of SCUpgradeReq MSHR miss cycles 1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14949871007 # number of ReadExReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14949871007 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1865086000 # number of ReadCleanReq MSHR miss cycles 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1865086000 # number of ReadCleanReq MSHR miss cycles 1083system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31278266000 # number of ReadSharedReq MSHR miss cycles 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31278266000 # number of ReadSharedReq MSHR miss cycles 1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1865086000 # number of demand (read+write) MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46228137007 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.demand_mshr_miss_latency::total 48093223007 # number of demand (read+write) MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1865086000 # number of overall MSHR miss cycles 1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46228137007 # number of overall MSHR miss cycles 1090system.cpu.l2cache.overall_mshr_miss_latency::total 48093223007 # number of overall MSHR miss cycles 1091system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442280000 # number of ReadReq MSHR uncacheable cycles 1092system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442280000 # number of ReadReq MSHR uncacheable cycles 1093system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043799500 # number of WriteReq MSHR uncacheable cycles 1094system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043799500 # number of WriteReq MSHR uncacheable cycles 1095system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486079500 # number of overall MSHR uncacheable cycles 1096system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486079500 # number of overall MSHR uncacheable cycles 1097system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses 1098system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses 1099system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses 1100system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses 1101system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383170 # mshr miss rate for ReadExReq accesses 1102system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383170 # mshr miss rate for ReadExReq accesses 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for ReadCleanReq accesses 1104system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014458 # mshr miss rate for ReadCleanReq accesses 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248754 # mshr miss rate for ReadSharedReq accesses 1106system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248754 # mshr miss rate for ReadSharedReq accesses 1107system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for demand accesses 1108system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for demand accesses 1109system.cpu.l2cache.demand_mshr_miss_rate::total 0.165848 # mshr miss rate for demand accesses 1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for overall accesses 1111system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for overall accesses 1112system.cpu.l2cache.overall_mshr_miss_rate::total 0.165848 # mshr miss rate for overall accesses 1113system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881 # average UpgradeReq mshr miss latency 1114system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881 # average UpgradeReq mshr miss latency 1115system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency 1116system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency 1117system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964 # average ReadExReq mshr miss latency 1118system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964 # average ReadExReq mshr miss latency 1119system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572 # average ReadCleanReq mshr miss latency 1120system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572 # average ReadCleanReq mshr miss latency 1121system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238 # average ReadSharedReq mshr miss latency 1122system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238 # average ReadSharedReq mshr miss latency 1123system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency 1125system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency 1129system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121 # average ReadReq mshr uncacheable latency 1130system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121 # average ReadReq mshr uncacheable latency 1131system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780 # average WriteReq mshr uncacheable latency 1132system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780 # average WriteReq mshr uncacheable latency 1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249 # average overall mshr uncacheable latency 1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249 # average overall mshr uncacheable latency 1135system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1136system.cpu.toL2Bus.snoop_filter.tot_requests 4875380 # Total number of requests made to the snoop filter. 1137system.cpu.toL2Bus.snoop_filter.hit_single_requests 2437337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1138system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2172 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1139system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1140system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1141system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1142system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadResp 2143899 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::WritebackDirty 958701 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::WritebackClean 1035081 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::CleanEvict 823325 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::ReadExReq 301454 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::ReadExResp 301454 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035962 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101105 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 1158system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106690 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240094 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_count::total 7346784 # Packet count per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132526592 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143633332 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.pkt_size::total 276159924 # Cumulative packet size per connected master and slave (bytes) 1164system.cpu.toL2Bus.snoops 422430 # Total snoops (count) 1165system.cpu.toL2Bus.snoop_fanout::samples 2876994 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::mean 0.001301 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::stdev 0.036051 # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::0 2873250 99.87% 99.87% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::1 3744 0.13% 100.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::total 2876994 # Request fanout histogram 1176system.cpu.toL2Bus.reqLayer0.occupancy 4326954000 # Layer occupancy (ticks) 1177system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1178system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 1179system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1180system.cpu.toL2Bus.respLayer0.occupancy 1555197985 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1182system.cpu.toL2Bus.respLayer1.occupancy 2115406799 # Layer occupancy (ticks) 1183system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1184system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1185system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1186system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1187system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1188system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1189system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1190system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1191system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1192system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1193system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1194system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1195system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1196system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1197system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1198system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 1199system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 1200system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1204system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1222system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.reqLayer0.occupancy 5356500 # Layer occupancy (ticks) 1227system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1228system.iobus.reqLayer1.occupancy 825500 # Layer occupancy (ticks) 1229system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1230system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1231system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1232system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1233system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1234system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 1235system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1236system.iobus.reqLayer23.occupancy 14331000 # Layer occupancy (ticks) 1237system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1238system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) 1239system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1240system.iobus.reqLayer25.occupancy 5952500 # Layer occupancy (ticks) 1241system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1242system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) 1243system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1244system.iobus.reqLayer27.occupancy 215698160 # Layer occupancy (ticks) 1245system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1246system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 1247system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1248system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1249system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1250system.iocache.tags.replacements 41685 # number of replacements 1251system.iocache.tags.tagsinuse 1.249420 # Cycle average of tags in use 1252system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1253system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1254system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1255system.iocache.tags.warmup_cycle 1725995722000 # Cycle when the warmup percentage was hit. 1256system.iocache.tags.occ_blocks::tsunami.ide 1.249420 # Average occupied blocks per requestor 1257system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy 1258system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy 1259system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1260system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1261system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1262system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1263system.iocache.tags.data_accesses 375525 # Number of data accesses 1264system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1265system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1266system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1267system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1268system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1269system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1270system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1271system.iocache.overall_misses::total 173 # number of overall misses 1272system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles 1273system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles 1274system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245293777 # number of WriteLineReq miss cycles 1275system.iocache.WriteLineReq_miss_latency::total 5245293777 # number of WriteLineReq miss cycles 1276system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles 1277system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles 1278system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles 1279system.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles 1280system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1281system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1282system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1283system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1284system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1285system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1286system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1287system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1288system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1289system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1290system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1291system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1292system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1293system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1294system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1295system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1296system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency 1297system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency 1298system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848 # average WriteLineReq miss latency 1299system.iocache.WriteLineReq_avg_miss_latency::total 126234.447848 # average WriteLineReq miss latency 1300system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 1301system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency 1302system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 1303system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency 1304system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1305system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1306system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1307system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1308system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1309system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1310system.iocache.fast_writes 0 # number of fast writes performed 1311system.iocache.cache_copies 0 # number of cache copies performed 1312system.iocache.writebacks::writebacks 41512 # number of writebacks 1313system.iocache.writebacks::total 41512 # number of writebacks 1314system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1315system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1316system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1317system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1318system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1319system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1320system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1321system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1322system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles 1323system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles 1324system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165897973 # number of WriteLineReq MSHR miss cycles 1325system.iocache.WriteLineReq_mshr_miss_latency::total 3165897973 # number of WriteLineReq MSHR miss cycles 1326system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles 1327system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles 1328system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles 1329system.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles 1330system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1331system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1332system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1333system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1334system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1335system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1336system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1337system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1338system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency 1339system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency 1340system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616 # average WriteLineReq mshr miss latency 1341system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616 # average WriteLineReq mshr miss latency 1342system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 1343system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 1344system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 1345system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 1346system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1347system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1348system.membus.trans_dist::ReadResp 295856 # Transaction distribution 1349system.membus.trans_dist::WriteReq 9598 # Transaction distribution 1350system.membus.trans_dist::WriteResp 9598 # Transaction distribution 1351system.membus.trans_dist::WritebackDirty 117576 # Transaction distribution 1352system.membus.trans_dist::CleanEvict 261861 # Transaction distribution 1353system.membus.trans_dist::UpgradeReq 350 # Transaction distribution 1354system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution 1355system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1356system.membus.trans_dist::ReadExReq 115259 # Transaction distribution 1357system.membus.trans_dist::ReadExResp 115259 # Transaction distribution 1358system.membus.trans_dist::ReadSharedReq 289007 # Transaction distribution 1359system.membus.trans_dist::BadAddressError 81 # Transaction distribution 1360system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1361system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 1362system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145859 # Packet count per connected master and slave (bytes) 1363system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) 1364system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179077 # Packet count per connected master and slave (bytes) 1365system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1366system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 1367system.membus.pkt_count::total 1262502 # Packet count per connected master and slave (bytes) 1368system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 1369system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707328 # Cumulative packet size per connected master and slave (bytes) 1370system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751476 # Cumulative packet size per connected master and slave (bytes) 1371system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1372system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1373system.membus.pkt_size::total 33409204 # Cumulative packet size per connected master and slave (bytes) 1374system.membus.snoops 435 # Total snoops (count) 1375system.membus.snoop_fanout::samples 842145 # Request fanout histogram 1376system.membus.snoop_fanout::mean 1 # Request fanout histogram 1377system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1378system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1379system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1380system.membus.snoop_fanout::1 842145 100.00% 100.00% # Request fanout histogram 1381system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1382system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1383system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1384system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1385system.membus.snoop_fanout::total 842145 # Request fanout histogram 1386system.membus.reqLayer0.occupancy 28932500 # Layer occupancy (ticks) 1387system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1388system.membus.reqLayer1.occupancy 1314336715 # Layer occupancy (ticks) 1389system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1390system.membus.reqLayer2.occupancy 105000 # Layer occupancy (ticks) 1391system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1392system.membus.respLayer1.occupancy 2138304000 # Layer occupancy (ticks) 1393system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1394system.membus.respLayer2.occupancy 911117 # Layer occupancy (ticks) 1395system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1396system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1397system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1398system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1399system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1400system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1401system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1402system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1403system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1404system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1405system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1406system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1407system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1408system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1409system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1410system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1411system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1412system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1413system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1414system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1415system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1416system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1417system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1418system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1419system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1420system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1421system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1422system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1423system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1424system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1425system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1426system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1427system.cpu.kern.inst.arm 0 # number of arm instructions executed 1428system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 1429system.cpu.kern.inst.hwrei 211012 # number of hwrei instructions executed 1430system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl 1431system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1432system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1433system.cpu.kern.ipl_count::31 105568 57.93% 100.00% # number of times we switched to this ipl 1434system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl 1435system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1436system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1437system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1438system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1439system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl 1440system.cpu.kern.ipl_ticks::0 1818034033000 96.92% 96.92% # number of cycles we spent at this ipl 1441system.cpu.kern.ipl_ticks::21 64890000 0.00% 96.93% # number of cycles we spent at this ipl 1442system.cpu.kern.ipl_ticks::22 561380500 0.03% 96.96% # number of cycles we spent at this ipl 1443system.cpu.kern.ipl_ticks::31 57096986000 3.04% 100.00% # number of cycles we spent at this ipl 1444system.cpu.kern.ipl_ticks::total 1875757289500 # number of cycles we spent at this ipl 1445system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 1446system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1447system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1448system.cpu.kern.ipl_used::31 0.694311 # fraction of swpipl calls that actually changed the ipl 1449system.cpu.kern.ipl_used::total 0.815422 # fraction of swpipl calls that actually changed the ipl 1450system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1451system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1452system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1453system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1454system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1455system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1456system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1457system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1458system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1459system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1460system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1461system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1462system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1463system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1464system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1465system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1466system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1467system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1468system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1469system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1470system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1471system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1472system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1473system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1474system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1475system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1476system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1477system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1478system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1479system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1480system.cpu.kern.syscall::total 326 # number of syscalls executed 1481system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1482system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1483system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1484system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1485system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1486system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1487system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 1488system.cpu.kern.callpal::swpipl 175126 91.23% 93.43% # number of callpals executed 1489system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 1490system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1491system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1492system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1493system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1494system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 1495system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1496system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1497system.cpu.kern.callpal::total 191971 # number of callpals executed 1498system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 1499system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 1500system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 1501system.cpu.kern.mode_good::kernel 1909 1502system.cpu.kern.mode_good::user 1739 1503system.cpu.kern.mode_good::idle 170 1504system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches 1505system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1506system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 1507system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 1508system.cpu.kern.mode_ticks::kernel 29989573500 1.60% 1.60% # number of ticks spent at the given mode 1509system.cpu.kern.mode_ticks::user 2896538000 0.15% 1.75% # number of ticks spent at the given mode 1510system.cpu.kern.mode_ticks::idle 1842871170000 98.25% 100.00% # number of ticks spent at the given mode 1511system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1512 1513---------- End Simulation Statistics ---------- 1514