config.ini revision 9481
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/scratch/nilay/GEM5/system/binaries/console 16init_param=0 17kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20mem_ranges=0:134217727 21memories=system.physmem 22num_work_ids=16 23pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clock=500 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76fetchToDecodeDelay=1 77fetchTrapLatency=1 78fetchWidth=8 79forwardComSize=5 80fuPool=system.cpu.fuPool 81function_trace=false 82function_trace_start=0 83iewToCommitDelay=1 84iewToDecodeDelay=1 85iewToFetchDelay=1 86iewToRenameDelay=1 87interrupts=system.cpu.interrupts 88isa=system.cpu.isa 89issueToExecuteDelay=1 90issueWidth=8 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119squashWidth=8 120store_set_clear_period=250000 121switched_out=false 122system=system 123tracer=system.cpu.tracer 124trapLatency=13 125wbDepth=1 126wbWidth=8 127workload= 128dcache_port=system.cpu.dcache.cpu_side 129icache_port=system.cpu.icache.cpu_side 130 131[system.cpu.branchPred] 132type=BranchPredictor 133BTBEntries=4096 134BTBTagSize=16 135RASSize=16 136choiceCtrBits=2 137choicePredictorSize=8192 138globalCtrBits=2 139globalHistoryBits=13 140globalPredictorSize=8192 141instShiftAmt=2 142localCtrBits=2 143localHistoryBits=11 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu.dcache] 150type=BaseCache 151addr_ranges=0:18446744073709551615 152assoc=4 153block_size=64 154clock=500 155forward_snoops=true 156hit_latency=2 157is_top_level=true 158max_miss_count=0 159mshrs=4 160prefetch_on_access=false 161prefetcher=Null 162response_latency=2 163size=32768 164system=system 165tgts_per_mshr=20 166two_queue=false 167write_buffers=8 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dtb] 172type=AlphaTLB 173size=64 174 175[system.cpu.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 179 180[system.cpu.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 184opList=system.cpu.fuPool.FUList0.opList 185 186[system.cpu.fuPool.FUList0.opList] 187type=OpDesc 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 196opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 197 198[system.cpu.fuPool.FUList1.opList0] 199type=OpDesc 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu.fuPool.FUList1.opList1] 205type=OpDesc 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 214opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 215 216[system.cpu.fuPool.FUList2.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu.fuPool.FUList2.opList1] 223type=OpDesc 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu.fuPool.FUList2.opList2] 229type=OpDesc 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 238opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 239 240[system.cpu.fuPool.FUList3.opList0] 241type=OpDesc 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu.fuPool.FUList3.opList1] 247type=OpDesc 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu.fuPool.FUList3.opList2] 253type=OpDesc 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 262opList=system.cpu.fuPool.FUList4.opList 263 264[system.cpu.fuPool.FUList4.opList] 265type=OpDesc 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 274opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 275 276[system.cpu.fuPool.FUList5.opList00] 277type=OpDesc 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList01] 283type=OpDesc 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList02] 289type=OpDesc 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList03] 295type=OpDesc 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList04] 301type=OpDesc 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList05] 307type=OpDesc 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList06] 313type=OpDesc 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList07] 319type=OpDesc 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList08] 325type=OpDesc 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList09] 331type=OpDesc 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList10] 337type=OpDesc 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList11] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList12] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList13] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList14] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList15] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList16] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList17] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList18] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList19] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 400opList=system.cpu.fuPool.FUList6.opList 401 402[system.cpu.fuPool.FUList6.opList] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 412opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 413 414[system.cpu.fuPool.FUList7.opList0] 415type=OpDesc 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu.fuPool.FUList7.opList1] 421type=OpDesc 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 430opList=system.cpu.fuPool.FUList8.opList 431 432[system.cpu.fuPool.FUList8.opList] 433type=OpDesc 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu.icache] 439type=BaseCache 440addr_ranges=0:18446744073709551615 441assoc=1 442block_size=64 443clock=500 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 452size=32768 453system=system 454tgts_per_mshr=20 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu.icache_port 458mem_side=system.cpu.toL2Bus.slave[0] 459 460[system.cpu.interrupts] 461type=AlphaInterrupts 462 463[system.cpu.isa] 464type=AlphaISA 465 466[system.cpu.itb] 467type=AlphaTLB 468size=48 469 470[system.cpu.l2cache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=8 474block_size=64 475clock=500 476forward_snoops=true 477hit_latency=20 478is_top_level=false 479max_miss_count=0 480mshrs=20 481prefetch_on_access=false 482prefetcher=Null 483response_latency=20 484size=4194304 485system=system 486tgts_per_mshr=12 487two_queue=false 488write_buffers=8 489cpu_side=system.cpu.toL2Bus.master[0] 490mem_side=system.membus.slave[1] 491 492[system.cpu.toL2Bus] 493type=CoherentBus 494block_size=64 495clock=500 496header_cycles=1 497use_default_range=false 498width=32 499master=system.cpu.l2cache.cpu_side 500slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 501 502[system.cpu.tracer] 503type=ExeTracer 504 505[system.disk0] 506type=IdeDisk 507children=image 508delay=1000000 509driveID=master 510image=system.disk0.image 511 512[system.disk0.image] 513type=CowDiskImage 514children=child 515child=system.disk0.image.child 516image_file= 517read_only=false 518table_size=65536 519 520[system.disk0.image.child] 521type=RawDiskImage 522image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 523read_only=true 524 525[system.disk2] 526type=IdeDisk 527children=image 528delay=1000000 529driveID=master 530image=system.disk2.image 531 532[system.disk2.image] 533type=CowDiskImage 534children=child 535child=system.disk2.image.child 536image_file= 537read_only=false 538table_size=65536 539 540[system.disk2.image.child] 541type=RawDiskImage 542image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img 543read_only=true 544 545[system.intrctrl] 546type=IntrControl 547sys=system 548 549[system.iobus] 550type=NoncoherentBus 551block_size=64 552clock=1000 553header_cycles=1 554use_default_range=true 555width=8 556default=system.tsunami.pciconfig.pio 557master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 558slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 559 560[system.iocache] 561type=BaseCache 562addr_ranges=0:134217727 563assoc=8 564block_size=64 565clock=1000 566forward_snoops=false 567hit_latency=50 568is_top_level=true 569max_miss_count=0 570mshrs=20 571prefetch_on_access=false 572prefetcher=Null 573response_latency=50 574size=1024 575system=system 576tgts_per_mshr=12 577two_queue=false 578write_buffers=8 579cpu_side=system.iobus.master[29] 580mem_side=system.membus.slave[2] 581 582[system.membus] 583type=CoherentBus 584children=badaddr_responder 585block_size=64 586clock=1000 587header_cycles=1 588use_default_range=false 589width=8 590default=system.membus.badaddr_responder.pio 591master=system.bridge.slave system.physmem.port 592slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 593 594[system.membus.badaddr_responder] 595type=IsaFake 596clock=1000 597fake_mem=false 598pio_addr=0 599pio_latency=100000 600pio_size=8 601ret_bad_addr=true 602ret_data16=65535 603ret_data32=4294967295 604ret_data64=18446744073709551615 605ret_data8=255 606system=system 607update_data=false 608warn_access= 609pio=system.membus.default 610 611[system.physmem] 612type=SimpleDRAM 613addr_mapping=openmap 614banks_per_rank=8 615clock=1000 616conf_table_reported=false 617in_addr_map=true 618lines_per_rowbuffer=64 619mem_sched_policy=fcfs 620null=false 621page_policy=open 622range=0:134217727 623ranks_per_channel=2 624read_buffer_size=32 625tBURST=4000 626tCL=14000 627tRCD=14000 628tREFI=7800000 629tRFC=300000 630tRP=14000 631tWTR=1000 632write_buffer_size=32 633write_thresh_perc=70 634zero=false 635port=system.membus.master[1] 636 637[system.simple_disk] 638type=SimpleDisk 639children=disk 640disk=system.simple_disk.disk 641system=system 642 643[system.simple_disk.disk] 644type=RawDiskImage 645image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 646read_only=true 647 648[system.terminal] 649type=Terminal 650intr_control=system.intrctrl 651number=0 652output=true 653port=3456 654 655[system.tsunami] 656type=Tsunami 657children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 658intrctrl=system.intrctrl 659system=system 660 661[system.tsunami.backdoor] 662type=AlphaBackdoor 663clock=1000 664cpu=system.cpu 665disk=system.simple_disk 666pio_addr=8804682956800 667pio_latency=100000 668platform=system.tsunami 669system=system 670terminal=system.terminal 671pio=system.iobus.master[24] 672 673[system.tsunami.cchip] 674type=TsunamiCChip 675clock=1000 676pio_addr=8803072344064 677pio_latency=100000 678system=system 679tsunami=system.tsunami 680pio=system.iobus.master[0] 681 682[system.tsunami.ethernet] 683type=NSGigE 684BAR0=1 685BAR0LegacyIO=false 686BAR0Size=256 687BAR1=0 688BAR1LegacyIO=false 689BAR1Size=4096 690BAR2=0 691BAR2LegacyIO=false 692BAR2Size=0 693BAR3=0 694BAR3LegacyIO=false 695BAR3Size=0 696BAR4=0 697BAR4LegacyIO=false 698BAR4Size=0 699BAR5=0 700BAR5LegacyIO=false 701BAR5Size=0 702BIST=0 703CacheLineSize=0 704CardbusCIS=0 705ClassCode=2 706Command=0 707DeviceID=34 708ExpansionROM=0 709HeaderType=0 710InterruptLine=30 711InterruptPin=1 712LatencyTimer=0 713MaximumLatency=52 714MinimumGrant=176 715ProgIF=0 716Revision=0 717Status=656 718SubClassCode=0 719SubsystemID=0 720SubsystemVendorID=0 721VendorID=4107 722clock=2000 723config_latency=20000 724dma_data_free=false 725dma_desc_free=false 726dma_no_allocate=true 727dma_read_delay=0 728dma_read_factor=0 729dma_write_delay=0 730dma_write_factor=0 731hardware_address=00:90:00:00:00:01 732intr_delay=10000000 733pci_bus=0 734pci_dev=1 735pci_func=0 736pio_latency=30000 737platform=system.tsunami 738rss=false 739rx_delay=1000000 740rx_fifo_size=524288 741rx_filter=true 742rx_thread=false 743system=system 744tx_delay=1000000 745tx_fifo_size=524288 746tx_thread=false 747config=system.iobus.master[28] 748dma=system.iobus.slave[2] 749pio=system.iobus.master[27] 750 751[system.tsunami.fake_OROM] 752type=IsaFake 753clock=1000 754fake_mem=false 755pio_addr=8796093677568 756pio_latency=100000 757pio_size=393216 758ret_bad_addr=false 759ret_data16=65535 760ret_data32=4294967295 761ret_data64=18446744073709551615 762ret_data8=255 763system=system 764update_data=false 765warn_access= 766pio=system.iobus.master[8] 767 768[system.tsunami.fake_ata0] 769type=IsaFake 770clock=1000 771fake_mem=false 772pio_addr=8804615848432 773pio_latency=100000 774pio_size=8 775ret_bad_addr=false 776ret_data16=65535 777ret_data32=4294967295 778ret_data64=18446744073709551615 779ret_data8=255 780system=system 781update_data=false 782warn_access= 783pio=system.iobus.master[19] 784 785[system.tsunami.fake_ata1] 786type=IsaFake 787clock=1000 788fake_mem=false 789pio_addr=8804615848304 790pio_latency=100000 791pio_size=8 792ret_bad_addr=false 793ret_data16=65535 794ret_data32=4294967295 795ret_data64=18446744073709551615 796ret_data8=255 797system=system 798update_data=false 799warn_access= 800pio=system.iobus.master[20] 801 802[system.tsunami.fake_pnp_addr] 803type=IsaFake 804clock=1000 805fake_mem=false 806pio_addr=8804615848569 807pio_latency=100000 808pio_size=8 809ret_bad_addr=false 810ret_data16=65535 811ret_data32=4294967295 812ret_data64=18446744073709551615 813ret_data8=255 814system=system 815update_data=false 816warn_access= 817pio=system.iobus.master[9] 818 819[system.tsunami.fake_pnp_read0] 820type=IsaFake 821clock=1000 822fake_mem=false 823pio_addr=8804615848451 824pio_latency=100000 825pio_size=8 826ret_bad_addr=false 827ret_data16=65535 828ret_data32=4294967295 829ret_data64=18446744073709551615 830ret_data8=255 831system=system 832update_data=false 833warn_access= 834pio=system.iobus.master[11] 835 836[system.tsunami.fake_pnp_read1] 837type=IsaFake 838clock=1000 839fake_mem=false 840pio_addr=8804615848515 841pio_latency=100000 842pio_size=8 843ret_bad_addr=false 844ret_data16=65535 845ret_data32=4294967295 846ret_data64=18446744073709551615 847ret_data8=255 848system=system 849update_data=false 850warn_access= 851pio=system.iobus.master[12] 852 853[system.tsunami.fake_pnp_read2] 854type=IsaFake 855clock=1000 856fake_mem=false 857pio_addr=8804615848579 858pio_latency=100000 859pio_size=8 860ret_bad_addr=false 861ret_data16=65535 862ret_data32=4294967295 863ret_data64=18446744073709551615 864ret_data8=255 865system=system 866update_data=false 867warn_access= 868pio=system.iobus.master[13] 869 870[system.tsunami.fake_pnp_read3] 871type=IsaFake 872clock=1000 873fake_mem=false 874pio_addr=8804615848643 875pio_latency=100000 876pio_size=8 877ret_bad_addr=false 878ret_data16=65535 879ret_data32=4294967295 880ret_data64=18446744073709551615 881ret_data8=255 882system=system 883update_data=false 884warn_access= 885pio=system.iobus.master[14] 886 887[system.tsunami.fake_pnp_read4] 888type=IsaFake 889clock=1000 890fake_mem=false 891pio_addr=8804615848707 892pio_latency=100000 893pio_size=8 894ret_bad_addr=false 895ret_data16=65535 896ret_data32=4294967295 897ret_data64=18446744073709551615 898ret_data8=255 899system=system 900update_data=false 901warn_access= 902pio=system.iobus.master[15] 903 904[system.tsunami.fake_pnp_read5] 905type=IsaFake 906clock=1000 907fake_mem=false 908pio_addr=8804615848771 909pio_latency=100000 910pio_size=8 911ret_bad_addr=false 912ret_data16=65535 913ret_data32=4294967295 914ret_data64=18446744073709551615 915ret_data8=255 916system=system 917update_data=false 918warn_access= 919pio=system.iobus.master[16] 920 921[system.tsunami.fake_pnp_read6] 922type=IsaFake 923clock=1000 924fake_mem=false 925pio_addr=8804615848835 926pio_latency=100000 927pio_size=8 928ret_bad_addr=false 929ret_data16=65535 930ret_data32=4294967295 931ret_data64=18446744073709551615 932ret_data8=255 933system=system 934update_data=false 935warn_access= 936pio=system.iobus.master[17] 937 938[system.tsunami.fake_pnp_read7] 939type=IsaFake 940clock=1000 941fake_mem=false 942pio_addr=8804615848899 943pio_latency=100000 944pio_size=8 945ret_bad_addr=false 946ret_data16=65535 947ret_data32=4294967295 948ret_data64=18446744073709551615 949ret_data8=255 950system=system 951update_data=false 952warn_access= 953pio=system.iobus.master[18] 954 955[system.tsunami.fake_pnp_write] 956type=IsaFake 957clock=1000 958fake_mem=false 959pio_addr=8804615850617 960pio_latency=100000 961pio_size=8 962ret_bad_addr=false 963ret_data16=65535 964ret_data32=4294967295 965ret_data64=18446744073709551615 966ret_data8=255 967system=system 968update_data=false 969warn_access= 970pio=system.iobus.master[10] 971 972[system.tsunami.fake_ppc] 973type=IsaFake 974clock=1000 975fake_mem=false 976pio_addr=8804615848891 977pio_latency=100000 978pio_size=8 979ret_bad_addr=false 980ret_data16=65535 981ret_data32=4294967295 982ret_data64=18446744073709551615 983ret_data8=255 984system=system 985update_data=false 986warn_access= 987pio=system.iobus.master[7] 988 989[system.tsunami.fake_sm_chip] 990type=IsaFake 991clock=1000 992fake_mem=false 993pio_addr=8804615848816 994pio_latency=100000 995pio_size=8 996ret_bad_addr=false 997ret_data16=65535 998ret_data32=4294967295 999ret_data64=18446744073709551615 1000ret_data8=255 1001system=system 1002update_data=false 1003warn_access= 1004pio=system.iobus.master[2] 1005 1006[system.tsunami.fake_uart1] 1007type=IsaFake 1008clock=1000 1009fake_mem=false 1010pio_addr=8804615848696 1011pio_latency=100000 1012pio_size=8 1013ret_bad_addr=false 1014ret_data16=65535 1015ret_data32=4294967295 1016ret_data64=18446744073709551615 1017ret_data8=255 1018system=system 1019update_data=false 1020warn_access= 1021pio=system.iobus.master[3] 1022 1023[system.tsunami.fake_uart2] 1024type=IsaFake 1025clock=1000 1026fake_mem=false 1027pio_addr=8804615848936 1028pio_latency=100000 1029pio_size=8 1030ret_bad_addr=false 1031ret_data16=65535 1032ret_data32=4294967295 1033ret_data64=18446744073709551615 1034ret_data8=255 1035system=system 1036update_data=false 1037warn_access= 1038pio=system.iobus.master[4] 1039 1040[system.tsunami.fake_uart3] 1041type=IsaFake 1042clock=1000 1043fake_mem=false 1044pio_addr=8804615848680 1045pio_latency=100000 1046pio_size=8 1047ret_bad_addr=false 1048ret_data16=65535 1049ret_data32=4294967295 1050ret_data64=18446744073709551615 1051ret_data8=255 1052system=system 1053update_data=false 1054warn_access= 1055pio=system.iobus.master[5] 1056 1057[system.tsunami.fake_uart4] 1058type=IsaFake 1059clock=1000 1060fake_mem=false 1061pio_addr=8804615848944 1062pio_latency=100000 1063pio_size=8 1064ret_bad_addr=false 1065ret_data16=65535 1066ret_data32=4294967295 1067ret_data64=18446744073709551615 1068ret_data8=255 1069system=system 1070update_data=false 1071warn_access= 1072pio=system.iobus.master[6] 1073 1074[system.tsunami.fb] 1075type=BadDevice 1076clock=1000 1077devicename=FrameBuffer 1078pio_addr=8804615848912 1079pio_latency=100000 1080system=system 1081pio=system.iobus.master[21] 1082 1083[system.tsunami.ide] 1084type=IdeController 1085BAR0=1 1086BAR0LegacyIO=false 1087BAR0Size=8 1088BAR1=1 1089BAR1LegacyIO=false 1090BAR1Size=4 1091BAR2=1 1092BAR2LegacyIO=false 1093BAR2Size=8 1094BAR3=1 1095BAR3LegacyIO=false 1096BAR3Size=4 1097BAR4=1 1098BAR4LegacyIO=false 1099BAR4Size=16 1100BAR5=1 1101BAR5LegacyIO=false 1102BAR5Size=0 1103BIST=0 1104CacheLineSize=0 1105CardbusCIS=0 1106ClassCode=1 1107Command=0 1108DeviceID=28945 1109ExpansionROM=0 1110HeaderType=0 1111InterruptLine=31 1112InterruptPin=1 1113LatencyTimer=0 1114MaximumLatency=0 1115MinimumGrant=0 1116ProgIF=133 1117Revision=0 1118Status=640 1119SubClassCode=1 1120SubsystemID=0 1121SubsystemVendorID=0 1122VendorID=32902 1123clock=1000 1124config_latency=20000 1125ctrl_offset=0 1126disks=system.disk0 system.disk2 1127io_shift=0 1128pci_bus=0 1129pci_dev=0 1130pci_func=0 1131pio_latency=30000 1132platform=system.tsunami 1133system=system 1134config=system.iobus.master[26] 1135dma=system.iobus.slave[1] 1136pio=system.iobus.master[25] 1137 1138[system.tsunami.io] 1139type=TsunamiIO 1140clock=1000 1141frequency=976562500 1142pio_addr=8804615847936 1143pio_latency=100000 1144system=system 1145time=Thu Jan 1 00:00:00 2009 1146tsunami=system.tsunami 1147year_is_bcd=false 1148pio=system.iobus.master[22] 1149 1150[system.tsunami.pchip] 1151type=TsunamiPChip 1152clock=1000 1153pio_addr=8802535473152 1154pio_latency=100000 1155system=system 1156tsunami=system.tsunami 1157pio=system.iobus.master[1] 1158 1159[system.tsunami.pciconfig] 1160type=PciConfigAll 1161bus=0 1162clock=1000 1163pio_latency=30000 1164platform=system.tsunami 1165size=16777216 1166system=system 1167pio=system.iobus.default 1168 1169[system.tsunami.uart] 1170type=Uart8250 1171clock=1000 1172pio_addr=8804615848952 1173pio_latency=100000 1174platform=system.tsunami 1175system=system 1176terminal=system.terminal 1177pio=system.iobus.master[23] 1178 1179