config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh 39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null 63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 72domain_id=-1 73eventq_index=0 74init_perf_level=0 75voltage_domain=system.voltage_domain 76 77[system.cpu] 78type=DerivO3CPU 79children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 80LFSTSize=1024 81LQEntries=32 82LSQCheckLoads=true 83LSQDepCheckShift=4 84SQEntries=32 85SSITSize=1024 86activity=0 87backComSize=5 88branchPred=system.cpu.branchPred 89cachePorts=200 90checker=Null 91clk_domain=system.cpu_clk_domain 92commitToDecodeDelay=1 93commitToFetchDelay=1 94commitToIEWDelay=1 95commitToRenameDelay=1 96commitWidth=8 97cpu_id=0 98decodeToFetchDelay=1 99decodeToRenameDelay=1 100decodeWidth=8 101default_p_state=UNDEFINED 102dispatchWidth=8 103do_checkpoint_insts=true 104do_quiesce=true 105do_statistics_insts=true 106dtb=system.cpu.dtb 107eventq_index=0 108fetchBufferSize=64 109fetchQueueSize=32 110fetchToDecodeDelay=1 111fetchTrapLatency=1 112fetchWidth=8 113forwardComSize=5 114fuPool=system.cpu.fuPool 115function_trace=false 116function_trace_start=0 117iewToCommitDelay=1 118iewToDecodeDelay=1 119iewToFetchDelay=1 120iewToRenameDelay=1 121interrupts=system.cpu.interrupts 122isa=system.cpu.isa 123issueToExecuteDelay=1 124issueWidth=8 125itb=system.cpu.itb 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130needsTSO=false 131numIQEntries=64 132numPhysCCRegs=0 133numPhysFloatRegs=256 134numPhysIntRegs=256 135numROBEntries=192 136numRobs=1 137numThreads=1 138p_state_clk_gate_bins=20 139p_state_clk_gate_max=1000000000000 140p_state_clk_gate_min=1000 141power_model=Null 142profile=0 143progress_interval=0 144renameToDecodeDelay=1 145renameToFetchDelay=1 146renameToIEWDelay=2 147renameToROBDelay=1 148renameWidth=8 149simpoint_start_insts= 150smtCommitPolicy=RoundRobin 151smtFetchPolicy=SingleThread 152smtIQPolicy=Partitioned 153smtIQThreshold=100 154smtLSQPolicy=Partitioned 155smtLSQThreshold=100 156smtNumFetchingThreads=1 157smtROBPolicy=Partitioned 158smtROBThreshold=100 159socket_id=0 160squashWidth=8 161store_set_clear_period=250000 162switched_out=false 163system=system 164tracer=system.cpu.tracer 165trapLatency=13 166wbWidth=8 167workload= 168dcache_port=system.cpu.dcache.cpu_side 169icache_port=system.cpu.icache.cpu_side 170 171[system.cpu.branchPred] 172type=TournamentBP 173BTBEntries=4096 174BTBTagSize=16 175RASSize=16 176choiceCtrBits=2 177choicePredictorSize=8192 178eventq_index=0 179globalCtrBits=2 180globalPredictorSize=8192 181indirectHashGHR=true 182indirectHashTargets=true 183indirectPathLength=3 184indirectSets=256 185indirectTagSize=16 186indirectWays=2 187instShiftAmt=2 188localCtrBits=2 189localHistoryTableSize=2048 190localPredictorSize=2048 191numThreads=1 192useIndirect=true 193 194[system.cpu.dcache] 195type=Cache 196children=tags 197addr_ranges=0:18446744073709551615 198assoc=4 199clk_domain=system.cpu_clk_domain 200clusivity=mostly_incl 201default_p_state=UNDEFINED 202demand_mshr_reserve=1 203eventq_index=0 204hit_latency=2 205is_read_only=false 206max_miss_count=0 207mshrs=4 208p_state_clk_gate_bins=20 209p_state_clk_gate_max=1000000000000 210p_state_clk_gate_min=1000 211power_model=Null 212prefetch_on_access=false 213prefetcher=Null 214response_latency=2 215sequential_access=false 216size=32768 217system=system 218tags=system.cpu.dcache.tags 219tgts_per_mshr=20 220write_buffers=8 221writeback_clean=false 222cpu_side=system.cpu.dcache_port 223mem_side=system.cpu.toL2Bus.slave[1] 224 225[system.cpu.dcache.tags] 226type=LRU 227assoc=4 228block_size=64 229clk_domain=system.cpu_clk_domain 230default_p_state=UNDEFINED 231eventq_index=0 232hit_latency=2 233p_state_clk_gate_bins=20 234p_state_clk_gate_max=1000000000000 235p_state_clk_gate_min=1000 236power_model=Null 237sequential_access=false 238size=32768 239 240[system.cpu.dtb] 241type=AlphaTLB 242eventq_index=0 243size=64 244 245[system.cpu.fuPool] 246type=FUPool 247children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 248FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 249eventq_index=0 250 251[system.cpu.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255eventq_index=0 256opList=system.cpu.fuPool.FUList0.opList 257 258[system.cpu.fuPool.FUList0.opList] 259type=OpDesc 260eventq_index=0 261opClass=IntAlu 262opLat=1 263pipelined=true 264 265[system.cpu.fuPool.FUList1] 266type=FUDesc 267children=opList0 opList1 268count=2 269eventq_index=0 270opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 271 272[system.cpu.fuPool.FUList1.opList0] 273type=OpDesc 274eventq_index=0 275opClass=IntMult 276opLat=3 277pipelined=true 278 279[system.cpu.fuPool.FUList1.opList1] 280type=OpDesc 281eventq_index=0 282opClass=IntDiv 283opLat=20 284pipelined=false 285 286[system.cpu.fuPool.FUList2] 287type=FUDesc 288children=opList0 opList1 opList2 289count=4 290eventq_index=0 291opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 292 293[system.cpu.fuPool.FUList2.opList0] 294type=OpDesc 295eventq_index=0 296opClass=FloatAdd 297opLat=2 298pipelined=true 299 300[system.cpu.fuPool.FUList2.opList1] 301type=OpDesc 302eventq_index=0 303opClass=FloatCmp 304opLat=2 305pipelined=true 306 307[system.cpu.fuPool.FUList2.opList2] 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc 316children=opList0 opList1 opList2 317count=2 318eventq_index=0 319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 335[system.cpu.fuPool.FUList3.opList2] 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc 344children=opList 345count=0 346eventq_index=0 347opList=system.cpu.fuPool.FUList4.opList 348 349[system.cpu.fuPool.FUList4.opList] 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] 364type=OpDesc 365eventq_index=0 366opClass=SimdAdd 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList01] 371type=OpDesc 372eventq_index=0 373opClass=SimdAddAcc 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList02] 378type=OpDesc 379eventq_index=0 380opClass=SimdAlu 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList03] 385type=OpDesc 386eventq_index=0 387opClass=SimdCmp 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList04] 392type=OpDesc 393eventq_index=0 394opClass=SimdCvt 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList05] 399type=OpDesc 400eventq_index=0 401opClass=SimdMisc 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList06] 406type=OpDesc 407eventq_index=0 408opClass=SimdMult 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList07] 413type=OpDesc 414eventq_index=0 415opClass=SimdMultAcc 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList08] 420type=OpDesc 421eventq_index=0 422opClass=SimdShift 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList09] 427type=OpDesc 428eventq_index=0 429opClass=SimdShiftAcc 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList10] 434type=OpDesc 435eventq_index=0 436opClass=SimdSqrt 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList11] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatAdd 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList12] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatAlu 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList13] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatCmp 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList14] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatCvt 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList15] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatDiv 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList16] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatMisc 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList5.opList17] 483type=OpDesc 484eventq_index=0 485opClass=SimdFloatMult 486opLat=1 487pipelined=true 488 489[system.cpu.fuPool.FUList5.opList18] 490type=OpDesc 491eventq_index=0 492opClass=SimdFloatMultAcc 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5.opList19] 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc 505children=opList 506count=0 507eventq_index=0 508opList=system.cpu.fuPool.FUList6.opList 509 510[system.cpu.fuPool.FUList6.opList] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList7] 518type=FUDesc 519children=opList0 opList1 520count=4 521eventq_index=0 522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] 546type=OpDesc 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615 556assoc=1 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=32768 575system=system 576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=1 586block_size=64 587clk_domain=system.cpu_clk_domain 588default_p_state=UNDEFINED 589eventq_index=0 590hit_latency=2 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=32768 597 598[system.cpu.interrupts] 599type=AlphaInterrupts 600eventq_index=0 601 602[system.cpu.isa] 603type=AlphaISA 604eventq_index=0 605system=system 606 607[system.cpu.itb] 608type=AlphaTLB 609eventq_index=0 610size=48 611 612[system.cpu.l2cache] 613type=Cache 614children=tags 615addr_ranges=0:18446744073709551615 616assoc=8 617clk_domain=system.cpu_clk_domain 618clusivity=mostly_incl 619default_p_state=UNDEFINED 620demand_mshr_reserve=1 621eventq_index=0 622hit_latency=20 623is_read_only=false 624max_miss_count=0 625mshrs=20 626p_state_clk_gate_bins=20 627p_state_clk_gate_max=1000000000000 628p_state_clk_gate_min=1000 629power_model=Null 630prefetch_on_access=false 631prefetcher=Null 632response_latency=20 633sequential_access=false 634size=4194304 635system=system 636tags=system.cpu.l2cache.tags 637tgts_per_mshr=12 638write_buffers=8 639writeback_clean=false 640cpu_side=system.cpu.toL2Bus.master[0] 641mem_side=system.membus.slave[1] 642 643[system.cpu.l2cache.tags] 644type=LRU 645assoc=8 646block_size=64 647clk_domain=system.cpu_clk_domain 648default_p_state=UNDEFINED 649eventq_index=0 650hit_latency=20 651p_state_clk_gate_bins=20 652p_state_clk_gate_max=1000000000000 653p_state_clk_gate_min=1000 654power_model=Null 655sequential_access=false 656size=4194304 657 658[system.cpu.toL2Bus] 659type=CoherentXBar 660children=snoop_filter 661clk_domain=system.cpu_clk_domain 662default_p_state=UNDEFINED 663eventq_index=0 664forward_latency=0 665frontend_latency=1 666p_state_clk_gate_bins=20 667p_state_clk_gate_max=1000000000000 668p_state_clk_gate_min=1000 669point_of_coherency=false 670power_model=Null 671response_latency=1 672snoop_filter=system.cpu.toL2Bus.snoop_filter 673snoop_response_latency=1 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 679 680[system.cpu.toL2Bus.snoop_filter] 681type=SnoopFilter 682eventq_index=0 683lookup_latency=0 684max_capacity=8388608 685system=system 686 687[system.cpu.tracer] 688type=ExeTracer 689eventq_index=0 690 691[system.cpu_clk_domain] 692type=SrcClockDomain 693clock=500 694domain_id=-1 695eventq_index=0 696init_perf_level=0 697voltage_domain=system.voltage_domain 698 699[system.disk0] 700type=IdeDisk 701children=image 702delay=1000000 703driveID=master 704eventq_index=0 705image=system.disk0.image 706 707[system.disk0.image] 708type=CowDiskImage 709children=child 710child=system.disk0.image.child 711eventq_index=0 712image_file= 713read_only=false 714table_size=65536 715 716[system.disk0.image.child] 717type=RawDiskImage 718eventq_index=0 719image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 720read_only=true 721 722[system.disk2] 723type=IdeDisk 724children=image 725delay=1000000 726driveID=master 727eventq_index=0 728image=system.disk2.image 729 730[system.disk2.image] 731type=CowDiskImage 732children=child 733child=system.disk2.image.child 734eventq_index=0 735image_file= 736read_only=false 737table_size=65536 738 739[system.disk2.image.child] 740type=RawDiskImage 741eventq_index=0 742image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img 743read_only=true 744 745[system.dvfs_handler] 746type=DVFSHandler 747domains= 748enable=false 749eventq_index=0 750sys_clk_domain=system.clk_domain 751transition_latency=100000000 752 753[system.intrctrl] 754type=IntrControl 755eventq_index=0 756sys=system 757 758[system.iobus] 759type=NoncoherentXBar 760clk_domain=system.clk_domain 761default_p_state=UNDEFINED 762eventq_index=0 763forward_latency=1 764frontend_latency=2 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768power_model=Null 769response_latency=2 770use_default_range=false 771width=16 772master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 773slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 774 775[system.iocache] 776type=Cache 777children=tags 778addr_ranges=0:134217727 779assoc=8 780clk_domain=system.clk_domain 781clusivity=mostly_incl 782default_p_state=UNDEFINED 783demand_mshr_reserve=1 784eventq_index=0 785hit_latency=50 786is_read_only=false 787max_miss_count=0 788mshrs=20 789p_state_clk_gate_bins=20 790p_state_clk_gate_max=1000000000000 791p_state_clk_gate_min=1000 792power_model=Null 793prefetch_on_access=false 794prefetcher=Null 795response_latency=50 796sequential_access=false 797size=1024 798system=system 799tags=system.iocache.tags 800tgts_per_mshr=12 801write_buffers=8 802writeback_clean=false 803cpu_side=system.iobus.master[27] 804mem_side=system.membus.slave[2] 805 806[system.iocache.tags] 807type=LRU 808assoc=8 809block_size=64 810clk_domain=system.clk_domain 811default_p_state=UNDEFINED 812eventq_index=0 813hit_latency=50 814p_state_clk_gate_bins=20 815p_state_clk_gate_max=1000000000000 816p_state_clk_gate_min=1000 817power_model=Null 818sequential_access=false 819size=1024 820 821[system.membus] 822type=CoherentXBar 823children=badaddr_responder 824clk_domain=system.clk_domain 825default_p_state=UNDEFINED 826eventq_index=0 827forward_latency=4 828frontend_latency=3 829p_state_clk_gate_bins=20 830p_state_clk_gate_max=1000000000000 831p_state_clk_gate_min=1000 832point_of_coherency=true 833power_model=Null 834response_latency=2 835snoop_filter=Null 836snoop_response_latency=4 837system=system 838use_default_range=false 839width=16 840default=system.membus.badaddr_responder.pio 841master=system.bridge.slave system.physmem.port 842slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 843 844[system.membus.badaddr_responder] 845type=IsaFake 846clk_domain=system.clk_domain 847default_p_state=UNDEFINED 848eventq_index=0 849fake_mem=false 850p_state_clk_gate_bins=20 851p_state_clk_gate_max=1000000000000 852p_state_clk_gate_min=1000 853pio_addr=0 854pio_latency=100000 855pio_size=8 856power_model=Null 857ret_bad_addr=true 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.membus.default 866 867[system.physmem] 868type=DRAMCtrl 869IDD0=0.075000 870IDD02=0.000000 871IDD2N=0.050000 872IDD2N2=0.000000 873IDD2P0=0.000000 874IDD2P02=0.000000 875IDD2P1=0.000000 876IDD2P12=0.000000 877IDD3N=0.057000 878IDD3N2=0.000000 879IDD3P0=0.000000 880IDD3P02=0.000000 881IDD3P1=0.000000 882IDD3P12=0.000000 883IDD4R=0.187000 884IDD4R2=0.000000 885IDD4W=0.165000 886IDD4W2=0.000000 887IDD5=0.220000 888IDD52=0.000000 889IDD6=0.000000 890IDD62=0.000000 891VDD=1.500000 892VDD2=0.000000 893activation_limit=4 894addr_mapping=RoRaBaCoCh 895bank_groups_per_rank=0 896banks_per_rank=8 897burst_length=8 898channels=1 899clk_domain=system.clk_domain 900conf_table_reported=true 901default_p_state=UNDEFINED 902device_bus_width=8 903device_rowbuffer_size=1024 904device_size=536870912 905devices_per_rank=8 906dll=true 907eventq_index=0 908in_addr_map=true 909max_accesses_per_row=16 910mem_sched_policy=frfcfs 911min_writes_per_switch=16 912null=false 913p_state_clk_gate_bins=20 914p_state_clk_gate_max=1000000000000 915p_state_clk_gate_min=1000 916page_policy=open_adaptive 917power_model=Null 918range=0:134217727 919ranks_per_channel=2 920read_buffer_size=32 921static_backend_latency=10000 922static_frontend_latency=10000 923tBURST=5000 924tCCD_L=0 925tCK=1250 926tCL=13750 927tCS=2500 928tRAS=35000 929tRCD=13750 930tREFI=7800000 931tRFC=260000 932tRP=13750 933tRRD=6000 934tRRD_L=0 935tRTP=7500 936tRTW=2500 937tWR=15000 938tWTR=7500 939tXAW=30000 940tXP=0 941tXPDLL=0 942tXS=0 943tXSDLL=0 944write_buffer_size=64 945write_high_thresh_perc=85 946write_low_thresh_perc=50 947port=system.membus.master[1] 948 949[system.simple_disk] 950type=SimpleDisk 951children=disk 952disk=system.simple_disk.disk 953eventq_index=0 954system=system 955 956[system.simple_disk.disk] 957type=RawDiskImage 958eventq_index=0 959image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 960read_only=true 961 962[system.terminal] 963type=Terminal 964eventq_index=0 965intr_control=system.intrctrl 966number=0 967output=true 968port=3456 969 970[system.tsunami] 971type=Tsunami 972children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart 973eventq_index=0 974intrctrl=system.intrctrl 975system=system 976 977[system.tsunami.backdoor] 978type=AlphaBackdoor 979clk_domain=system.clk_domain 980cpu=system.cpu 981default_p_state=UNDEFINED 982disk=system.simple_disk 983eventq_index=0 984p_state_clk_gate_bins=20 985p_state_clk_gate_max=1000000000000 986p_state_clk_gate_min=1000 987pio_addr=8804682956800 988pio_latency=100000 989platform=system.tsunami 990power_model=Null 991system=system 992terminal=system.terminal 993pio=system.iobus.master[24] 994 995[system.tsunami.cchip] 996type=TsunamiCChip 997clk_domain=system.clk_domain 998default_p_state=UNDEFINED 999eventq_index=0 1000p_state_clk_gate_bins=20 1001p_state_clk_gate_max=1000000000000 1002p_state_clk_gate_min=1000 1003pio_addr=8803072344064 1004pio_latency=100000 1005power_model=Null 1006system=system 1007tsunami=system.tsunami 1008pio=system.iobus.master[0] 1009 1010[system.tsunami.ethernet] 1011type=NSGigE 1012BAR0=1 1013BAR0LegacyIO=false 1014BAR0Size=256 1015BAR1=0 1016BAR1LegacyIO=false 1017BAR1Size=4096 1018BAR2=0 1019BAR2LegacyIO=false 1020BAR2Size=0 1021BAR3=0 1022BAR3LegacyIO=false 1023BAR3Size=0 1024BAR4=0 1025BAR4LegacyIO=false 1026BAR4Size=0 1027BAR5=0 1028BAR5LegacyIO=false 1029BAR5Size=0 1030BIST=0 1031CacheLineSize=0 1032CapabilityPtr=0 1033CardbusCIS=0 1034ClassCode=2 1035Command=0 1036DeviceID=34 1037ExpansionROM=0 1038HeaderType=0 1039InterruptLine=30 1040InterruptPin=1 1041LatencyTimer=0 1042LegacyIOBase=0 1043MSICAPBaseOffset=0 1044MSICAPCapId=0 1045MSICAPMaskBits=0 1046MSICAPMsgAddr=0 1047MSICAPMsgCtrl=0 1048MSICAPMsgData=0 1049MSICAPMsgUpperAddr=0 1050MSICAPNextCapability=0 1051MSICAPPendingBits=0 1052MSIXCAPBaseOffset=0 1053MSIXCAPCapId=0 1054MSIXCAPNextCapability=0 1055MSIXMsgCtrl=0 1056MSIXPbaOffset=0 1057MSIXTableOffset=0 1058MaximumLatency=52 1059MinimumGrant=176 1060PMCAPBaseOffset=0 1061PMCAPCapId=0 1062PMCAPCapabilities=0 1063PMCAPCtrlStatus=0 1064PMCAPNextCapability=0 1065PXCAPBaseOffset=0 1066PXCAPCapId=0 1067PXCAPCapabilities=0 1068PXCAPDevCap2=0 1069PXCAPDevCapabilities=0 1070PXCAPDevCtrl=0 1071PXCAPDevCtrl2=0 1072PXCAPDevStatus=0 1073PXCAPLinkCap=0 1074PXCAPLinkCtrl=0 1075PXCAPLinkStatus=0 1076PXCAPNextCapability=0 1077ProgIF=0 1078Revision=0 1079Status=656 1080SubClassCode=0 1081SubsystemID=0 1082SubsystemVendorID=0 1083VendorID=4107 1084clk_domain=system.clk_domain 1085config_latency=20000 1086default_p_state=UNDEFINED 1087dma_data_free=false 1088dma_desc_free=false 1089dma_no_allocate=true 1090dma_read_delay=0 1091dma_read_factor=0 1092dma_write_delay=0 1093dma_write_factor=0 1094eventq_index=0 1095hardware_address=00:90:00:00:00:01 1096host=system.tsunami.pchip 1097intr_delay=10000000 1098p_state_clk_gate_bins=20 1099p_state_clk_gate_max=1000000000000 1100p_state_clk_gate_min=1000 1101pci_bus=0 1102pci_dev=1 1103pci_func=0 1104pio_latency=30000 1105power_model=Null 1106rss=false 1107rx_delay=1000000 1108rx_fifo_size=524288 1109rx_filter=true 1110rx_thread=false 1111system=system 1112tx_delay=1000000 1113tx_fifo_size=524288 1114tx_thread=false 1115dma=system.iobus.slave[2] 1116pio=system.iobus.master[26] 1117 1118[system.tsunami.fake_OROM] 1119type=IsaFake 1120clk_domain=system.clk_domain 1121default_p_state=UNDEFINED 1122eventq_index=0 1123fake_mem=false 1124p_state_clk_gate_bins=20 1125p_state_clk_gate_max=1000000000000 1126p_state_clk_gate_min=1000 1127pio_addr=8796093677568 1128pio_latency=100000 1129pio_size=393216 1130power_model=Null 1131ret_bad_addr=false 1132ret_data16=65535 1133ret_data32=4294967295 1134ret_data64=18446744073709551615 1135ret_data8=255 1136system=system 1137update_data=false 1138warn_access= 1139pio=system.iobus.master[8] 1140 1141[system.tsunami.fake_ata0] 1142type=IsaFake 1143clk_domain=system.clk_domain 1144default_p_state=UNDEFINED 1145eventq_index=0 1146fake_mem=false 1147p_state_clk_gate_bins=20 1148p_state_clk_gate_max=1000000000000 1149p_state_clk_gate_min=1000 1150pio_addr=8804615848432 1151pio_latency=100000 1152pio_size=8 1153power_model=Null 1154ret_bad_addr=false 1155ret_data16=65535 1156ret_data32=4294967295 1157ret_data64=18446744073709551615 1158ret_data8=255 1159system=system 1160update_data=false 1161warn_access= 1162pio=system.iobus.master[19] 1163 1164[system.tsunami.fake_ata1] 1165type=IsaFake 1166clk_domain=system.clk_domain 1167default_p_state=UNDEFINED 1168eventq_index=0 1169fake_mem=false 1170p_state_clk_gate_bins=20 1171p_state_clk_gate_max=1000000000000 1172p_state_clk_gate_min=1000 1173pio_addr=8804615848304 1174pio_latency=100000 1175pio_size=8 1176power_model=Null 1177ret_bad_addr=false 1178ret_data16=65535 1179ret_data32=4294967295 1180ret_data64=18446744073709551615 1181ret_data8=255 1182system=system 1183update_data=false 1184warn_access= 1185pio=system.iobus.master[20] 1186 1187[system.tsunami.fake_pnp_addr] 1188type=IsaFake 1189clk_domain=system.clk_domain 1190default_p_state=UNDEFINED 1191eventq_index=0 1192fake_mem=false 1193p_state_clk_gate_bins=20 1194p_state_clk_gate_max=1000000000000 1195p_state_clk_gate_min=1000 1196pio_addr=8804615848569 1197pio_latency=100000 1198pio_size=8 1199power_model=Null 1200ret_bad_addr=false 1201ret_data16=65535 1202ret_data32=4294967295 1203ret_data64=18446744073709551615 1204ret_data8=255 1205system=system 1206update_data=false 1207warn_access= 1208pio=system.iobus.master[9] 1209 1210[system.tsunami.fake_pnp_read0] 1211type=IsaFake 1212clk_domain=system.clk_domain 1213default_p_state=UNDEFINED 1214eventq_index=0 1215fake_mem=false 1216p_state_clk_gate_bins=20 1217p_state_clk_gate_max=1000000000000 1218p_state_clk_gate_min=1000 1219pio_addr=8804615848451 1220pio_latency=100000 1221pio_size=8 1222power_model=Null 1223ret_bad_addr=false 1224ret_data16=65535 1225ret_data32=4294967295 1226ret_data64=18446744073709551615 1227ret_data8=255 1228system=system 1229update_data=false 1230warn_access= 1231pio=system.iobus.master[11] 1232 1233[system.tsunami.fake_pnp_read1] 1234type=IsaFake 1235clk_domain=system.clk_domain 1236default_p_state=UNDEFINED 1237eventq_index=0 1238fake_mem=false 1239p_state_clk_gate_bins=20 1240p_state_clk_gate_max=1000000000000 1241p_state_clk_gate_min=1000 1242pio_addr=8804615848515 1243pio_latency=100000 1244pio_size=8 1245power_model=Null 1246ret_bad_addr=false 1247ret_data16=65535 1248ret_data32=4294967295 1249ret_data64=18446744073709551615 1250ret_data8=255 1251system=system 1252update_data=false 1253warn_access= 1254pio=system.iobus.master[12] 1255 1256[system.tsunami.fake_pnp_read2] 1257type=IsaFake 1258clk_domain=system.clk_domain 1259default_p_state=UNDEFINED 1260eventq_index=0 1261fake_mem=false 1262p_state_clk_gate_bins=20 1263p_state_clk_gate_max=1000000000000 1264p_state_clk_gate_min=1000 1265pio_addr=8804615848579 1266pio_latency=100000 1267pio_size=8 1268power_model=Null 1269ret_bad_addr=false 1270ret_data16=65535 1271ret_data32=4294967295 1272ret_data64=18446744073709551615 1273ret_data8=255 1274system=system 1275update_data=false 1276warn_access= 1277pio=system.iobus.master[13] 1278 1279[system.tsunami.fake_pnp_read3] 1280type=IsaFake 1281clk_domain=system.clk_domain 1282default_p_state=UNDEFINED 1283eventq_index=0 1284fake_mem=false 1285p_state_clk_gate_bins=20 1286p_state_clk_gate_max=1000000000000 1287p_state_clk_gate_min=1000 1288pio_addr=8804615848643 1289pio_latency=100000 1290pio_size=8 1291power_model=Null 1292ret_bad_addr=false 1293ret_data16=65535 1294ret_data32=4294967295 1295ret_data64=18446744073709551615 1296ret_data8=255 1297system=system 1298update_data=false 1299warn_access= 1300pio=system.iobus.master[14] 1301 1302[system.tsunami.fake_pnp_read4] 1303type=IsaFake 1304clk_domain=system.clk_domain 1305default_p_state=UNDEFINED 1306eventq_index=0 1307fake_mem=false 1308p_state_clk_gate_bins=20 1309p_state_clk_gate_max=1000000000000 1310p_state_clk_gate_min=1000 1311pio_addr=8804615848707 1312pio_latency=100000 1313pio_size=8 1314power_model=Null 1315ret_bad_addr=false 1316ret_data16=65535 1317ret_data32=4294967295 1318ret_data64=18446744073709551615 1319ret_data8=255 1320system=system 1321update_data=false 1322warn_access= 1323pio=system.iobus.master[15] 1324 1325[system.tsunami.fake_pnp_read5] 1326type=IsaFake 1327clk_domain=system.clk_domain 1328default_p_state=UNDEFINED 1329eventq_index=0 1330fake_mem=false 1331p_state_clk_gate_bins=20 1332p_state_clk_gate_max=1000000000000 1333p_state_clk_gate_min=1000 1334pio_addr=8804615848771 1335pio_latency=100000 1336pio_size=8 1337power_model=Null 1338ret_bad_addr=false 1339ret_data16=65535 1340ret_data32=4294967295 1341ret_data64=18446744073709551615 1342ret_data8=255 1343system=system 1344update_data=false 1345warn_access= 1346pio=system.iobus.master[16] 1347 1348[system.tsunami.fake_pnp_read6] 1349type=IsaFake 1350clk_domain=system.clk_domain 1351default_p_state=UNDEFINED 1352eventq_index=0 1353fake_mem=false 1354p_state_clk_gate_bins=20 1355p_state_clk_gate_max=1000000000000 1356p_state_clk_gate_min=1000 1357pio_addr=8804615848835 1358pio_latency=100000 1359pio_size=8 1360power_model=Null 1361ret_bad_addr=false 1362ret_data16=65535 1363ret_data32=4294967295 1364ret_data64=18446744073709551615 1365ret_data8=255 1366system=system 1367update_data=false 1368warn_access= 1369pio=system.iobus.master[17] 1370 1371[system.tsunami.fake_pnp_read7] 1372type=IsaFake 1373clk_domain=system.clk_domain 1374default_p_state=UNDEFINED 1375eventq_index=0 1376fake_mem=false 1377p_state_clk_gate_bins=20 1378p_state_clk_gate_max=1000000000000 1379p_state_clk_gate_min=1000 1380pio_addr=8804615848899 1381pio_latency=100000 1382pio_size=8 1383power_model=Null 1384ret_bad_addr=false 1385ret_data16=65535 1386ret_data32=4294967295 1387ret_data64=18446744073709551615 1388ret_data8=255 1389system=system 1390update_data=false 1391warn_access= 1392pio=system.iobus.master[18] 1393 1394[system.tsunami.fake_pnp_write] 1395type=IsaFake 1396clk_domain=system.clk_domain 1397default_p_state=UNDEFINED 1398eventq_index=0 1399fake_mem=false 1400p_state_clk_gate_bins=20 1401p_state_clk_gate_max=1000000000000 1402p_state_clk_gate_min=1000 1403pio_addr=8804615850617 1404pio_latency=100000 1405pio_size=8 1406power_model=Null 1407ret_bad_addr=false 1408ret_data16=65535 1409ret_data32=4294967295 1410ret_data64=18446744073709551615 1411ret_data8=255 1412system=system 1413update_data=false 1414warn_access= 1415pio=system.iobus.master[10] 1416 1417[system.tsunami.fake_ppc] 1418type=IsaFake 1419clk_domain=system.clk_domain 1420default_p_state=UNDEFINED 1421eventq_index=0 1422fake_mem=false 1423p_state_clk_gate_bins=20 1424p_state_clk_gate_max=1000000000000 1425p_state_clk_gate_min=1000 1426pio_addr=8804615848891 1427pio_latency=100000 1428pio_size=8 1429power_model=Null 1430ret_bad_addr=false 1431ret_data16=65535 1432ret_data32=4294967295 1433ret_data64=18446744073709551615 1434ret_data8=255 1435system=system 1436update_data=false 1437warn_access= 1438pio=system.iobus.master[7] 1439 1440[system.tsunami.fake_sm_chip] 1441type=IsaFake 1442clk_domain=system.clk_domain 1443default_p_state=UNDEFINED 1444eventq_index=0 1445fake_mem=false 1446p_state_clk_gate_bins=20 1447p_state_clk_gate_max=1000000000000 1448p_state_clk_gate_min=1000 1449pio_addr=8804615848816 1450pio_latency=100000 1451pio_size=8 1452power_model=Null 1453ret_bad_addr=false 1454ret_data16=65535 1455ret_data32=4294967295 1456ret_data64=18446744073709551615 1457ret_data8=255 1458system=system 1459update_data=false 1460warn_access= 1461pio=system.iobus.master[2] 1462 1463[system.tsunami.fake_uart1] 1464type=IsaFake 1465clk_domain=system.clk_domain 1466default_p_state=UNDEFINED 1467eventq_index=0 1468fake_mem=false 1469p_state_clk_gate_bins=20 1470p_state_clk_gate_max=1000000000000 1471p_state_clk_gate_min=1000 1472pio_addr=8804615848696 1473pio_latency=100000 1474pio_size=8 1475power_model=Null 1476ret_bad_addr=false 1477ret_data16=65535 1478ret_data32=4294967295 1479ret_data64=18446744073709551615 1480ret_data8=255 1481system=system 1482update_data=false 1483warn_access= 1484pio=system.iobus.master[3] 1485 1486[system.tsunami.fake_uart2] 1487type=IsaFake 1488clk_domain=system.clk_domain 1489default_p_state=UNDEFINED 1490eventq_index=0 1491fake_mem=false 1492p_state_clk_gate_bins=20 1493p_state_clk_gate_max=1000000000000 1494p_state_clk_gate_min=1000 1495pio_addr=8804615848936 1496pio_latency=100000 1497pio_size=8 1498power_model=Null 1499ret_bad_addr=false 1500ret_data16=65535 1501ret_data32=4294967295 1502ret_data64=18446744073709551615 1503ret_data8=255 1504system=system 1505update_data=false 1506warn_access= 1507pio=system.iobus.master[4] 1508 1509[system.tsunami.fake_uart3] 1510type=IsaFake 1511clk_domain=system.clk_domain 1512default_p_state=UNDEFINED 1513eventq_index=0 1514fake_mem=false 1515p_state_clk_gate_bins=20 1516p_state_clk_gate_max=1000000000000 1517p_state_clk_gate_min=1000 1518pio_addr=8804615848680 1519pio_latency=100000 1520pio_size=8 1521power_model=Null 1522ret_bad_addr=false 1523ret_data16=65535 1524ret_data32=4294967295 1525ret_data64=18446744073709551615 1526ret_data8=255 1527system=system 1528update_data=false 1529warn_access= 1530pio=system.iobus.master[5] 1531 1532[system.tsunami.fake_uart4] 1533type=IsaFake 1534clk_domain=system.clk_domain 1535default_p_state=UNDEFINED 1536eventq_index=0 1537fake_mem=false 1538p_state_clk_gate_bins=20 1539p_state_clk_gate_max=1000000000000 1540p_state_clk_gate_min=1000 1541pio_addr=8804615848944 1542pio_latency=100000 1543pio_size=8 1544power_model=Null 1545ret_bad_addr=false 1546ret_data16=65535 1547ret_data32=4294967295 1548ret_data64=18446744073709551615 1549ret_data8=255 1550system=system 1551update_data=false 1552warn_access= 1553pio=system.iobus.master[6] 1554 1555[system.tsunami.fb] 1556type=BadDevice 1557clk_domain=system.clk_domain 1558default_p_state=UNDEFINED 1559devicename=FrameBuffer 1560eventq_index=0 1561p_state_clk_gate_bins=20 1562p_state_clk_gate_max=1000000000000 1563p_state_clk_gate_min=1000 1564pio_addr=8804615848912 1565pio_latency=100000 1566power_model=Null 1567system=system 1568pio=system.iobus.master[21] 1569 1570[system.tsunami.ide] 1571type=IdeController 1572BAR0=1 1573BAR0LegacyIO=false 1574BAR0Size=8 1575BAR1=1 1576BAR1LegacyIO=false 1577BAR1Size=4 1578BAR2=1 1579BAR2LegacyIO=false 1580BAR2Size=8 1581BAR3=1 1582BAR3LegacyIO=false 1583BAR3Size=4 1584BAR4=1 1585BAR4LegacyIO=false 1586BAR4Size=16 1587BAR5=1 1588BAR5LegacyIO=false 1589BAR5Size=0 1590BIST=0 1591CacheLineSize=0 1592CapabilityPtr=0 1593CardbusCIS=0 1594ClassCode=1 1595Command=0 1596DeviceID=28945 1597ExpansionROM=0 1598HeaderType=0 1599InterruptLine=31 1600InterruptPin=1 1601LatencyTimer=0 1602LegacyIOBase=0 1603MSICAPBaseOffset=0 1604MSICAPCapId=0 1605MSICAPMaskBits=0 1606MSICAPMsgAddr=0 1607MSICAPMsgCtrl=0 1608MSICAPMsgData=0 1609MSICAPMsgUpperAddr=0 1610MSICAPNextCapability=0 1611MSICAPPendingBits=0 1612MSIXCAPBaseOffset=0 1613MSIXCAPCapId=0 1614MSIXCAPNextCapability=0 1615MSIXMsgCtrl=0 1616MSIXPbaOffset=0 1617MSIXTableOffset=0 1618MaximumLatency=0 1619MinimumGrant=0 1620PMCAPBaseOffset=0 1621PMCAPCapId=0 1622PMCAPCapabilities=0 1623PMCAPCtrlStatus=0 1624PMCAPNextCapability=0 1625PXCAPBaseOffset=0 1626PXCAPCapId=0 1627PXCAPCapabilities=0 1628PXCAPDevCap2=0 1629PXCAPDevCapabilities=0 1630PXCAPDevCtrl=0 1631PXCAPDevCtrl2=0 1632PXCAPDevStatus=0 1633PXCAPLinkCap=0 1634PXCAPLinkCtrl=0 1635PXCAPLinkStatus=0 1636PXCAPNextCapability=0 1637ProgIF=133 1638Revision=0 1639Status=640 1640SubClassCode=1 1641SubsystemID=0 1642SubsystemVendorID=0 1643VendorID=32902 1644clk_domain=system.clk_domain 1645config_latency=20000 1646ctrl_offset=0 1647default_p_state=UNDEFINED 1648disks=system.disk0 system.disk2 1649eventq_index=0 1650host=system.tsunami.pchip 1651io_shift=0 1652p_state_clk_gate_bins=20 1653p_state_clk_gate_max=1000000000000 1654p_state_clk_gate_min=1000 1655pci_bus=0 1656pci_dev=0 1657pci_func=0 1658pio_latency=30000 1659power_model=Null 1660system=system 1661dma=system.iobus.slave[1] 1662pio=system.iobus.master[25] 1663 1664[system.tsunami.io] 1665type=TsunamiIO 1666clk_domain=system.clk_domain 1667default_p_state=UNDEFINED 1668eventq_index=0 1669frequency=976562500 1670p_state_clk_gate_bins=20 1671p_state_clk_gate_max=1000000000000 1672p_state_clk_gate_min=1000 1673pio_addr=8804615847936 1674pio_latency=100000 1675power_model=Null 1676system=system 1677time=Thu Jan 1 00:00:00 2009 1678tsunami=system.tsunami 1679year_is_bcd=false 1680pio=system.iobus.master[22] 1681 1682[system.tsunami.pchip] 1683type=TsunamiPChip 1684clk_domain=system.clk_domain 1685conf_base=8804649402368 1686conf_device_bits=8 1687conf_size=16777216 1688default_p_state=UNDEFINED 1689eventq_index=0 1690p_state_clk_gate_bins=20 1691p_state_clk_gate_max=1000000000000 1692p_state_clk_gate_min=1000 1693pci_dma_base=0 1694pci_mem_base=8796093022208 1695pci_pio_base=8804615847936 1696pio_addr=8802535473152 1697pio_latency=100000 1698platform=system.tsunami 1699power_model=Null 1700system=system 1701tsunami=system.tsunami 1702pio=system.iobus.master[1] 1703 1704[system.tsunami.uart] 1705type=Uart8250 1706clk_domain=system.clk_domain 1707default_p_state=UNDEFINED 1708eventq_index=0 1709p_state_clk_gate_bins=20 1710p_state_clk_gate_max=1000000000000 1711p_state_clk_gate_min=1000 1712pio_addr=8804615848952 1713pio_latency=100000 1714platform=system.tsunami 1715power_model=Null 1716system=system 1717terminal=system.terminal 1718pio=system.iobus.master[23] 1719 1720[system.voltage_domain] 1721type=VoltageDomain 1722eventq_index=0 1723voltage=1.000000 1724 1725