stats.txt revision 9289
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39289Sandreas.hansson@arm.comsim_seconds 1.902683 # Number of seconds simulated 49289Sandreas.hansson@arm.comsim_ticks 1902682770000 # Number of ticks simulated 59289Sandreas.hansson@arm.comfinal_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79289Sandreas.hansson@arm.comhost_inst_rate 192931 # Simulator instruction rate (inst/s) 89289Sandreas.hansson@arm.comhost_op_rate 192931 # Simulator op (including micro ops) rate (op/s) 99289Sandreas.hansson@arm.comhost_tick_rate 6436506827 # Simulator tick rate (ticks/s) 109289Sandreas.hansson@arm.comhost_mem_usage 296908 # Number of bytes of host memory used 119289Sandreas.hansson@arm.comhost_seconds 295.61 # Real time elapsed on the host 129289Sandreas.hansson@arm.comsim_insts 57032045 # Number of instructions simulated 139289Sandreas.hansson@arm.comsim_ops 57032045 # Number of ops (including micro ops) simulated 149289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory 159289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory 169289Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 179289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory 189289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory 199289Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28940032 # Number of bytes read from this memory 209289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory 219289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory 229289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory 239289Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory 249289Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7895360 # Number of bytes written to this memory 259289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory 269289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory 279289Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 289289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory 299289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory 309289Sandreas.hansson@arm.comsystem.physmem.num_reads::total 452188 # Number of read requests responded to by this memory 319289Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory 329289Sandreas.hansson@arm.comsystem.physmem.num_writes::total 123365 # Number of write requests responded to by this memory 339289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s) 349289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s) 359289Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s) 369289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s) 379289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s) 389289Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s) 399289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s) 409289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s) 419289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s) 429289Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s) 439289Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s) 449289Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s) 459289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s) 469289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s) 479289Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s) 489289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s) 499289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s) 509289Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s) 519289Sandreas.hansson@arm.comsystem.l2c.replacements 345291 # number of replacements 529289Sandreas.hansson@arm.comsystem.l2c.tagsinuse 65280.360301 # Cycle average of tags in use 539289Sandreas.hansson@arm.comsystem.l2c.total_refs 2575351 # Total number of references to valid blocks. 549289Sandreas.hansson@arm.comsystem.l2c.sampled_refs 410382 # Sample count of references to valid blocks. 559289Sandreas.hansson@arm.comsystem.l2c.avg_refs 6.275497 # Average number of references to valid blocks. 569289Sandreas.hansson@arm.comsystem.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit. 579289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor 589289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor 599289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor 609289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor 619289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor 629289Sandreas.hansson@arm.comsystem.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy 639289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy 649289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy 659289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy 669289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy 679289Sandreas.hansson@arm.comsystem.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy 689289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits 699289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits 709289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits 719289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits 729289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits 739289Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits 749289Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 812223 # number of Writeback hits 759289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits 769289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits 779289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits 789289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits 799229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits 809289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits 819289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 135544 # number of ReadExReq hits 829289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 39704 # number of ReadExReq hits 839289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 175248 # number of ReadExReq hits 849289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 798441 # number of demand (read+write) hits 859289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 832478 # number of demand (read+write) hits 869289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 292090 # number of demand (read+write) hits 879289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 139299 # number of demand (read+write) hits 889289Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2062308 # number of demand (read+write) hits 899289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 798441 # number of overall hits 909289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 832478 # number of overall hits 919289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 292090 # number of overall hits 929289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 139299 # number of overall hits 939289Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2062308 # number of overall hits 949289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 14171 # number of ReadReq misses 959289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 272326 # number of ReadReq misses 969289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses 979289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1502 # number of ReadReq misses 989289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 289172 # number of ReadReq misses 999289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2767 # number of UpgradeReq misses 1009289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 1411 # number of UpgradeReq misses 1019289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 4178 # number of UpgradeReq misses 1029289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses 1039289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 630 # number of SCUpgradeReq misses 1049289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1236 # number of SCUpgradeReq misses 1059289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 111402 # number of ReadExReq misses 1069289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 10975 # number of ReadExReq misses 1079289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 122377 # number of ReadExReq misses 1089289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 14171 # number of demand (read+write) misses 1099289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 383728 # number of demand (read+write) misses 1109289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses 1119289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 12477 # number of demand (read+write) misses 1129289Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 411549 # number of demand (read+write) misses 1139289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 14171 # number of overall misses 1149289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 383728 # number of overall misses 1159289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1173 # number of overall misses 1169289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 12477 # number of overall misses 1179289Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 411549 # number of overall misses 1189289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 755985500 # number of ReadReq miss cycles 1199289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.data 14184372500 # number of ReadReq miss cycles 1209289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 62331000 # number of ReadReq miss cycles 1219289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.data 81509998 # number of ReadReq miss cycles 1229289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 15084198998 # number of ReadReq miss cycles 1239289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 1749500 # number of UpgradeReq miss cycles 1249289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 16214497 # number of UpgradeReq miss cycles 1259289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 17963997 # number of UpgradeReq miss cycles 1269289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 2002500 # number of SCUpgradeReq miss cycles 1279289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 367000 # number of SCUpgradeReq miss cycles 1289289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 2369500 # number of SCUpgradeReq miss cycles 1299289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 6034072500 # number of ReadExReq miss cycles 1309289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 609639000 # number of ReadExReq miss cycles 1319289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 6643711500 # number of ReadExReq miss cycles 1329289Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 755985500 # number of demand (read+write) miss cycles 1339289Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 20218445000 # number of demand (read+write) miss cycles 1349289Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 62331000 # number of demand (read+write) miss cycles 1359289Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 691148998 # number of demand (read+write) miss cycles 1369289Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 21727910498 # number of demand (read+write) miss cycles 1379289Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 755985500 # number of overall miss cycles 1389289Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 20218445000 # number of overall miss cycles 1399289Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 62331000 # number of overall miss cycles 1409289Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 691148998 # number of overall miss cycles 1419289Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 21727910498 # number of overall miss cycles 1429289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 812612 # number of ReadReq accesses(hits+misses) 1439289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 969260 # number of ReadReq accesses(hits+misses) 1449289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 293263 # number of ReadReq accesses(hits+misses) 1459289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 101097 # number of ReadReq accesses(hits+misses) 1469289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2176232 # number of ReadReq accesses(hits+misses) 1479289Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 812223 # number of Writeback accesses(hits+misses) 1489289Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 812223 # number of Writeback accesses(hits+misses) 1499289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2936 # number of UpgradeReq accesses(hits+misses) 1509289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1808 # number of UpgradeReq accesses(hits+misses) 1519289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 4744 # number of UpgradeReq accesses(hits+misses) 1529289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) 1539289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 659 # number of SCUpgradeReq accesses(hits+misses) 1549289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 1311 # number of SCUpgradeReq accesses(hits+misses) 1559289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 246946 # number of ReadExReq accesses(hits+misses) 1569289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 50679 # number of ReadExReq accesses(hits+misses) 1579289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 297625 # number of ReadExReq accesses(hits+misses) 1589289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 812612 # number of demand (read+write) accesses 1599289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1216206 # number of demand (read+write) accesses 1609289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 293263 # number of demand (read+write) accesses 1619289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 151776 # number of demand (read+write) accesses 1629289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2473857 # number of demand (read+write) accesses 1639289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 812612 # number of overall (read+write) accesses 1649289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1216206 # number of overall (read+write) accesses 1659289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 293263 # number of overall (read+write) accesses 1669289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 151776 # number of overall (read+write) accesses 1679289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2473857 # number of overall (read+write) accesses 1689289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.017439 # miss rate for ReadReq accesses 1699289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.280963 # miss rate for ReadReq accesses 1709289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.004000 # miss rate for ReadReq accesses 1719289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.014857 # miss rate for ReadReq accesses 1729289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.132877 # miss rate for ReadReq accesses 1739289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.942439 # miss rate for UpgradeReq accesses 1749289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.780420 # miss rate for UpgradeReq accesses 1759289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.880691 # miss rate for UpgradeReq accesses 1769289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.929448 # miss rate for SCUpgradeReq accesses 1779289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.955994 # miss rate for SCUpgradeReq accesses 1789289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.942792 # miss rate for SCUpgradeReq accesses 1799289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.451119 # miss rate for ReadExReq accesses 1809289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.216559 # miss rate for ReadExReq accesses 1819289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.411178 # miss rate for ReadExReq accesses 1829289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.017439 # miss rate for demand accesses 1839289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.315512 # miss rate for demand accesses 1849289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.004000 # miss rate for demand accesses 1859289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.082207 # miss rate for demand accesses 1869289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.166359 # miss rate for demand accesses 1879289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.017439 # miss rate for overall accesses 1889289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.315512 # miss rate for overall accesses 1899289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.004000 # miss rate for overall accesses 1909289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.082207 # miss rate for overall accesses 1919289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.166359 # miss rate for overall accesses 1929289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 53347.364336 # average ReadReq miss latency 1939289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.data 52086.001704 # average ReadReq miss latency 1949289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 53138.107417 # average ReadReq miss latency 1959289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.data 54267.641811 # average ReadReq miss latency 1969289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 52163.414847 # average ReadReq miss latency 1979289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 632.273220 # average UpgradeReq miss latency 1989289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11491.493267 # average UpgradeReq miss latency 1999289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 4299.664193 # average UpgradeReq miss latency 2009289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3304.455446 # average SCUpgradeReq miss latency 2019289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.539683 # average SCUpgradeReq miss latency 2029289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 1917.071197 # average SCUpgradeReq miss latency 2039289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 54164.848926 # average ReadExReq miss latency 2049289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 55547.972665 # average ReadExReq miss latency 2059289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 54288.890069 # average ReadExReq miss latency 2069289Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency 2079289Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency 2089289Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency 2099289Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency 2109289Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 52795.439906 # average overall miss latency 2119289Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency 2129289Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency 2139289Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency 2149289Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency 2159289Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 52795.439906 # average overall miss latency 2168464SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2178464SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2188464SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2198464SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2208983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2218983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2228464SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 2238464SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 2249289Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 81845 # number of writebacks 2259289Sandreas.hansson@arm.comsystem.l2c.writebacks::total 81845 # number of writebacks 2268844SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 2278844SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 2288835SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 2298844SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2308844SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 2318835SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 2328844SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2338844SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 2348835SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 2359289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 14170 # number of ReadReq MSHR misses 2369289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.data 272326 # number of ReadReq MSHR misses 2379289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 1156 # number of ReadReq MSHR misses 2389289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.data 1502 # number of ReadReq MSHR misses 2399289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 289154 # number of ReadReq MSHR misses 2409289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 2767 # number of UpgradeReq MSHR misses 2419289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 1411 # number of UpgradeReq MSHR misses 2429289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 4178 # number of UpgradeReq MSHR misses 2439289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 606 # number of SCUpgradeReq MSHR misses 2449289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 630 # number of SCUpgradeReq MSHR misses 2459289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1236 # number of SCUpgradeReq MSHR misses 2469289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 111402 # number of ReadExReq MSHR misses 2479289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 10975 # number of ReadExReq MSHR misses 2489289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 122377 # number of ReadExReq MSHR misses 2499289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 14170 # number of demand (read+write) MSHR misses 2509289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 383728 # number of demand (read+write) MSHR misses 2519289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 1156 # number of demand (read+write) MSHR misses 2529289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 12477 # number of demand (read+write) MSHR misses 2539289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 411531 # number of demand (read+write) MSHR misses 2549289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 14170 # number of overall MSHR misses 2559289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 383728 # number of overall MSHR misses 2569289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 1156 # number of overall MSHR misses 2579289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 12477 # number of overall MSHR misses 2589289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 411531 # number of overall MSHR misses 2599289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 582633500 # number of ReadReq MSHR miss cycles 2609289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.data 10923275000 # number of ReadReq MSHR miss cycles 2619289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 47336500 # number of ReadReq MSHR miss cycles 2629289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.data 63194498 # number of ReadReq MSHR miss cycles 2639289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::total 11616439498 # number of ReadReq MSHR miss cycles 2649289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 110819971 # number of UpgradeReq MSHR miss cycles 2659289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56511497 # number of UpgradeReq MSHR miss cycles 2669289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 167331468 # number of UpgradeReq MSHR miss cycles 2679289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24296484 # number of SCUpgradeReq MSHR miss cycles 2689289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25202500 # number of SCUpgradeReq MSHR miss cycles 2699289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 49498984 # number of SCUpgradeReq MSHR miss cycles 2709289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4677812000 # number of ReadExReq MSHR miss cycles 2719289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 476518500 # number of ReadExReq MSHR miss cycles 2729289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 5154330500 # number of ReadExReq MSHR miss cycles 2739289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 582633500 # number of demand (read+write) MSHR miss cycles 2749289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 15601087000 # number of demand (read+write) MSHR miss cycles 2759289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 47336500 # number of demand (read+write) MSHR miss cycles 2769289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 539712998 # number of demand (read+write) MSHR miss cycles 2779289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 16770769998 # number of demand (read+write) MSHR miss cycles 2789289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 582633500 # number of overall MSHR miss cycles 2799289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 15601087000 # number of overall MSHR miss cycles 2809289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 47336500 # number of overall MSHR miss cycles 2819289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 539712998 # number of overall MSHR miss cycles 2829289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 16770769998 # number of overall MSHR miss cycles 2839289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1358127000 # number of ReadReq MSHR uncacheable cycles 2849289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28700000 # number of ReadReq MSHR uncacheable cycles 2859289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1386827000 # number of ReadReq MSHR uncacheable cycles 2869289Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2042144000 # number of WriteReq MSHR uncacheable cycles 2879289Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647379000 # number of WriteReq MSHR uncacheable cycles 2889289Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 2689523000 # number of WriteReq MSHR uncacheable cycles 2899289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3400271000 # number of overall MSHR uncacheable cycles 2909289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 676079000 # number of overall MSHR uncacheable cycles 2919289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 4076350000 # number of overall MSHR uncacheable cycles 2929289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for ReadReq accesses 2939289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.280963 # mshr miss rate for ReadReq accesses 2949289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for ReadReq accesses 2959289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.014857 # mshr miss rate for ReadReq accesses 2969289Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.132869 # mshr miss rate for ReadReq accesses 2979289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942439 # mshr miss rate for UpgradeReq accesses 2989289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780420 # mshr miss rate for UpgradeReq accesses 2999289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.880691 # mshr miss rate for UpgradeReq accesses 3009289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.929448 # mshr miss rate for SCUpgradeReq accesses 3019289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955994 # mshr miss rate for SCUpgradeReq accesses 3029289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.942792 # mshr miss rate for SCUpgradeReq accesses 3039289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.451119 # mshr miss rate for ReadExReq accesses 3049289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.216559 # mshr miss rate for ReadExReq accesses 3059289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.411178 # mshr miss rate for ReadExReq accesses 3069289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for demand accesses 3079289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for demand accesses 3089289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for demand accesses 3099289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for demand accesses 3109289Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.166352 # mshr miss rate for demand accesses 3119289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for overall accesses 3129289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for overall accesses 3139289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for overall accesses 3149289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for overall accesses 3159289Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.166352 # mshr miss rate for overall accesses 3169289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average ReadReq mshr miss latency 3179289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40111.025021 # average ReadReq mshr miss latency 3189289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average ReadReq mshr miss latency 3199289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42073.567244 # average ReadReq mshr miss latency 3209289Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 40173.884843 # average ReadReq mshr miss latency 3219289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40050.585833 # average UpgradeReq mshr miss latency 3229289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.671155 # average UpgradeReq mshr miss latency 3239289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.614648 # average UpgradeReq mshr miss latency 3249289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40093.207921 # average SCUpgradeReq mshr miss latency 3259289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.968254 # average SCUpgradeReq mshr miss latency 3269289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.721683 # average SCUpgradeReq mshr miss latency 3279289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41990.377193 # average ReadExReq mshr miss latency 3289289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43418.542141 # average ReadExReq mshr miss latency 3299289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 42118.457717 # average ReadExReq mshr miss latency 3309289Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency 3319289Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency 3329289Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency 3339289Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency 3349289Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency 3359289Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency 3369289Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency 3379289Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency 3389289Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency 3399289Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency 3408835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3418835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3429055Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3438835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3448835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3459055Ssaidi@eecs.umich.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3468835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3478835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3489055Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3498464SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3509289Sandreas.hansson@arm.comsystem.iocache.replacements 41697 # number of replacements 3519289Sandreas.hansson@arm.comsystem.iocache.tagsinuse 0.492574 # Cycle average of tags in use 3528464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 3539289Sandreas.hansson@arm.comsystem.iocache.sampled_refs 41713 # Sample count of references to valid blocks. 3548464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 3559289Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1709348959000 # Cycle when the warmup percentage was hit. 3569289Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 0.492574 # Average occupied blocks per requestor 3579289Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.030786 # Average percentage of cache occupancy 3589289Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.030786 # Average percentage of cache occupancy 3599289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses 3609289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 177 # number of ReadReq misses 3618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3628464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3639289Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses 3649289Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41729 # number of demand (read+write) misses 3659289Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41729 # number of overall misses 3669289Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41729 # number of overall misses 3679289Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21127998 # number of ReadReq miss cycles 3689289Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21127998 # number of ReadReq miss cycles 3699289Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 11486516806 # number of WriteReq miss cycles 3709289Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 11486516806 # number of WriteReq miss cycles 3719289Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 11507644804 # number of demand (read+write) miss cycles 3729289Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 11507644804 # number of demand (read+write) miss cycles 3739289Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 11507644804 # number of overall miss cycles 3749289Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 11507644804 # number of overall miss cycles 3759289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) 3769289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) 3778835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3788464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3799289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses 3809289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses 3819289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses 3829289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses 3838835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3849055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3858835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3869055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3878835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3889055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3898835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3909055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3919289Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency 3929289Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency 3939289Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency 3949289Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency 3959289Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency 3969289Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency 3979289Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency 3989289Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency 3999289Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked 4008464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4019289Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked 4028464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 4039289Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked 4048983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4058464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 4068464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 4078835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 4088835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41520 # number of writebacks 4099289Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 4109289Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses 4118835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 4128835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 4139289Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses 4149289Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses 4159289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses 4169289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses 4179289Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles 4189289Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles 4199289Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles 4209289Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles 4219289Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles 4229289Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles 4239289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles 4249289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles 4258835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4269055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 4278835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 4289055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 4298835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4309055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4318835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4329055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 4339289Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency 4349289Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency 4359289Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency 4369289Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency 4379289Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency 4389289Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency 4399289Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency 4409289Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency 4418464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4428464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4438464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4448464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4458464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4468464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4478464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4488464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4498464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4508464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4518464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4528464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4538464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 4548464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 4558464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 4568464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 4578464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 4589289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 8304100 # DTB read hits 4599289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 28307 # DTB read misses 4609289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 549 # DTB read access violations 4619289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 542239 # DTB read accesses 4629289Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5411904 # DTB write hits 4639289Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 5987 # DTB write misses 4649289Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 347 # DTB write access violations 4659289Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 182798 # DTB write accesses 4669289Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 13716004 # DTB hits 4679289Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 34294 # DTB misses 4689289Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 896 # DTB access violations 4699289Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 725037 # DTB accesses 4709289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 908718 # ITB hits 4719289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 19910 # ITB misses 4729289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 927 # ITB acv 4739289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 928628 # ITB accesses 4748464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 4758464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 4768464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 4778464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 4788464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 4798464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 4808464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 4818464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 4828464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 4838464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 4848464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 4858464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 4869289Sandreas.hansson@arm.comsystem.cpu0.numCycles 102599658 # number of cpu cycles simulated 4878464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 4888464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 4899289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups 4909289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted 4919289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect 4929289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups 4939289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits 4946006SN/Asystem.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4959289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target. 4969289Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions. 4979289Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss 4989289Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed 4999289Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered 5009289Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken 5019289Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked 5029289Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing 5039289Sandreas.hansson@arm.comsystem.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked 5049289Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 5059289Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps 5069289Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions 5079289Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR 5089289Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched 5099289Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed 5109289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total) 5119289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total) 5129289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total) 5138464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 5149289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total) 5159289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total) 5169289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total) 5179289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total) 5189289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total) 5199289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total) 5209289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total) 5219289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total) 5229289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total) 5238464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5248464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5258464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 5269289Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total) 5279289Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle 5289289Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle 5299289Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle 5309289Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked 5319289Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running 5329289Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking 5339289Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing 5349289Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch 5359289Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction 5369289Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode 5379289Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode 5389289Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing 5399289Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle 5409289Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking 5419289Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst 5429289Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running 5439289Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking 5449289Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename 5459289Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full 5469289Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full 5479289Sandreas.hansson@arm.comsystem.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full 5489289Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed 5499289Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made 5509289Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups 5519289Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups 5529289Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed 5539289Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing 5549289Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed 5559289Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed 5569289Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer 5579289Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit. 5589289Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit. 5599289Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads. 5609289Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores. 5619289Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec) 5629289Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ 5639289Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued 5649289Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued 5659289Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling 5669289Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph 5679289Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed 5689289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle 5699289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle 5709289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle 5718464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 5729289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle 5739289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle 5749289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle 5759289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle 5769289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle 5779289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle 5789289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle 5799289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle 5809289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle 5818464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5828464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5838464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 5849289Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle 5858464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5869289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available 5879289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available 5889289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available 5899289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available 5909289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available 5919289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available 5929289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available 5939289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available 5949289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available 5959289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available 5969289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available 5979289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available 5989289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available 5999289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available 6009289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available 6019289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available 6029289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available 6039289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available 6049289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available 6059289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available 6069289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available 6079289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available 6089289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available 6099289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available 6109289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available 6119289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available 6129289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available 6139289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available 6149289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available 6159289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available 6169289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available 6178464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6188464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6199289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued 6209289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued 6219289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued 6229289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued 6239289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued 6249289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued 6259289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued 6269289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued 6279289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued 6289289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued 6299289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued 6309289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued 6319289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued 6329289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued 6339289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued 6349289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued 6359289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued 6369289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued 6379289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued 6389289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued 6399289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued 6409289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued 6419289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued 6429289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued 6439289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued 6449289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued 6459289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued 6469289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued 6479289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued 6489289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued 6499289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued 6509289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued 6519289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued 6528464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 6539289Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued 6549289Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.476270 # Inst issue rate 6559289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested 6569289Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst) 6579289Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads 6589289Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes 6599289Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses 6609289Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads 6619289Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes 6629289Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses 6639289Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses 6649289Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses 6659289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores 6668464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 6679289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed 6689289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed 6699289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations 6709289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed 6718464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6728464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 6739289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled 6749289Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked 6758464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 6769289Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing 6779289Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking 6789289Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking 6799289Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ 6809289Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch 6819289Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions 6829289Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions 6839289Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions 6849289Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall 6859289Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall 6869289Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations 6879289Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly 6889289Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly 6899289Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute 6909289Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions 6919289Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed 6929289Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute 6938464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 6949289Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3090325 # number of nop insts executed 6959289Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed 6969289Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 7754310 # Number of branches executed 6979289Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 5430719 # Number of stores executed 6989289Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.472236 # Inst execution rate 6999289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit 7009289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back 7019289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 24107105 # num instructions producing a value 7029289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value 7038464SN/Asystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 7049289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle 7059289Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back 7068464SN/Asystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 7079289Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit 7089289Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards 7099289Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted 7109289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle 7119289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle 7129289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle 7138241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 7149289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle 7159289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle 7169289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle 7179289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle 7189289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle 7199289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle 7209289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle 7219289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle 7229289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle 7238241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7248241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7258241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 7269289Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle 7279289Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 48486178 # Number of instructions committed 7289289Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed 7298241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 7309289Sandreas.hansson@arm.comsystem.cpu0.commit.refs 12881900 # Number of memory references committed 7319289Sandreas.hansson@arm.comsystem.cpu0.commit.loads 7658821 # Number of loads committed 7329289Sandreas.hansson@arm.comsystem.cpu0.commit.membars 183715 # Number of memory barriers committed 7339289Sandreas.hansson@arm.comsystem.cpu0.commit.branches 7346956 # Number of branches committed 7349289Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions. 7359289Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 44900899 # Number of committed integer instructions. 7369289Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 613493 # Number of function calls committed. 7379289Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached 7388464SN/Asystem.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 7399289Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 123809295 # The number of ROB reads 7409289Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 110434143 # The number of ROB writes 7419289Sandreas.hansson@arm.comsystem.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself 7429289Sandreas.hansson@arm.comsystem.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling 7439289Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 7449289Sandreas.hansson@arm.comsystem.cpu0.committedInsts 45684021 # Number of Instructions Simulated 7459289Sandreas.hansson@arm.comsystem.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated 7469289Sandreas.hansson@arm.comsystem.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated 7479289Sandreas.hansson@arm.comsystem.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction 7489289Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads 7499289Sandreas.hansson@arm.comsystem.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle 7509289Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads 7519289Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 63838240 # number of integer regfile reads 7529289Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 34928793 # number of integer regfile writes 7539289Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 112215 # number of floating regfile reads 7549289Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 113746 # number of floating regfile writes 7559289Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads 7569289Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 757779 # number of misc regfile writes 7575703SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7585703SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7595703SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7605703SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7618464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7638464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7648464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7658983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7668464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7678464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7688983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7698464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7708464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7718983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7728464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7738464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7748983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7758464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7768464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7778983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 7788464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 7798464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 7808983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 7818464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 7828464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 7838983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 7848464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 7858983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 7868464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 7875703SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 7889289Sandreas.hansson@arm.comsystem.cpu0.icache.replacements 812060 # number of replacements 7899289Sandreas.hansson@arm.comsystem.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use 7909289Sandreas.hansson@arm.comsystem.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks. 7919289Sandreas.hansson@arm.comsystem.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks. 7929289Sandreas.hansson@arm.comsystem.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks. 7939289Sandreas.hansson@arm.comsystem.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit. 7949289Sandreas.hansson@arm.comsystem.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor 7959289Sandreas.hansson@arm.comsystem.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy 7969289Sandreas.hansson@arm.comsystem.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy 7979289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits 7989289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits 7999289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits 8009289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits 8019289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits 8029289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 6590229 # number of overall hits 8039289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 853981 # number of ReadReq misses 8049289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 853981 # number of ReadReq misses 8059289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 853981 # number of demand (read+write) misses 8069289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 853981 # number of demand (read+write) misses 8079289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 853981 # number of overall misses 8089289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 853981 # number of overall misses 8099289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11857055495 # number of ReadReq miss cycles 8109289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 11857055495 # number of ReadReq miss cycles 8119289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 11857055495 # number of demand (read+write) miss cycles 8129289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 11857055495 # number of demand (read+write) miss cycles 8139289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 11857055495 # number of overall miss cycles 8149289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 11857055495 # number of overall miss cycles 8159289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses) 8169289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses) 8179289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses 8189289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses 8199289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses 8209289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses 8219289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses 8229289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses 8239289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses 8249289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses 8259289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses 8269289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses 8279289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency 8289289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency 8299289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency 8309289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency 8319289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency 8329289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency 8339289Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked 8348464SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8359289Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked 8368464SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 8379289Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked 8388983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8398464SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 8408464SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 8419289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41272 # number of ReadReq MSHR hits 8429289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 41272 # number of ReadReq MSHR hits 8439289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 41272 # number of demand (read+write) MSHR hits 8449289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 41272 # number of demand (read+write) MSHR hits 8459289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 41272 # number of overall MSHR hits 8469289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 41272 # number of overall MSHR hits 8479289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 812709 # number of ReadReq MSHR misses 8489289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 812709 # number of ReadReq MSHR misses 8499289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 812709 # number of demand (read+write) MSHR misses 8509289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 812709 # number of demand (read+write) MSHR misses 8519289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 812709 # number of overall MSHR misses 8529289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 812709 # number of overall MSHR misses 8539289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9799988995 # number of ReadReq MSHR miss cycles 8549289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 9799988995 # number of ReadReq MSHR miss cycles 8559289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9799988995 # number of demand (read+write) MSHR miss cycles 8569289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 9799988995 # number of demand (read+write) MSHR miss cycles 8579289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9799988995 # number of overall MSHR miss cycles 8589289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 9799988995 # number of overall MSHR miss cycles 8599289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for ReadReq accesses 8609289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109173 # mshr miss rate for ReadReq accesses 8619289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for demand accesses 8629289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.109173 # mshr miss rate for demand accesses 8639289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for overall accesses 8649289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.109173 # mshr miss rate for overall accesses 8659289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average ReadReq mshr miss latency 8669289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12058.423119 # average ReadReq mshr miss latency 8679289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency 8689289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency 8699289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency 8709289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency 8718464SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 8729289Sandreas.hansson@arm.comsystem.cpu0.dcache.replacements 1218511 # number of replacements 8739289Sandreas.hansson@arm.comsystem.cpu0.dcache.tagsinuse 505.616339 # Cycle average of tags in use 8749289Sandreas.hansson@arm.comsystem.cpu0.dcache.total_refs 9815926 # Total number of references to valid blocks. 8759289Sandreas.hansson@arm.comsystem.cpu0.dcache.sampled_refs 1218945 # Sample count of references to valid blocks. 8769289Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_refs 8.052805 # Average number of references to valid blocks. 8779289Sandreas.hansson@arm.comsystem.cpu0.dcache.warmup_cycle 23286000 # Cycle when the warmup percentage was hit. 8789289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_blocks::cpu0.data 505.616339 # Average occupied blocks per requestor 8799289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::cpu0.data 0.987532 # Average percentage of cache occupancy 8809289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::total 0.987532 # Average percentage of cache occupancy 8819289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6063177 # number of ReadReq hits 8829289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6063177 # number of ReadReq hits 8839289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3417347 # number of WriteReq hits 8849289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3417347 # number of WriteReq hits 8859289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151987 # number of LoadLockedReq hits 8869289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 151987 # number of LoadLockedReq hits 8879289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 174443 # number of StoreCondReq hits 8889289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 174443 # number of StoreCondReq hits 8899289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 9480524 # number of demand (read+write) hits 8909289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 9480524 # number of demand (read+write) hits 8919289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 9480524 # number of overall hits 8929289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 9480524 # number of overall hits 8939289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1492446 # number of ReadReq misses 8949289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1492446 # number of ReadReq misses 8959289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1612731 # number of WriteReq misses 8969289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1612731 # number of WriteReq misses 8979289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19429 # number of LoadLockedReq misses 8989289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 19429 # number of LoadLockedReq misses 8999289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 4062 # number of StoreCondReq misses 9009289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 4062 # number of StoreCondReq misses 9019289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3105177 # number of demand (read+write) misses 9029289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3105177 # number of demand (read+write) misses 9039289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3105177 # number of overall misses 9049289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3105177 # number of overall misses 9059289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34499425000 # number of ReadReq miss cycles 9069289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 34499425000 # number of ReadReq miss cycles 9079289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55944257946 # number of WriteReq miss cycles 9089289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 55944257946 # number of WriteReq miss cycles 9099289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 264930500 # number of LoadLockedReq miss cycles 9109289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 264930500 # number of LoadLockedReq miss cycles 9119289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47614500 # number of StoreCondReq miss cycles 9129289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 47614500 # number of StoreCondReq miss cycles 9139289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 90443682946 # number of demand (read+write) miss cycles 9149289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 90443682946 # number of demand (read+write) miss cycles 9159289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 90443682946 # number of overall miss cycles 9169289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 90443682946 # number of overall miss cycles 9179289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7555623 # number of ReadReq accesses(hits+misses) 9189289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7555623 # number of ReadReq accesses(hits+misses) 9199289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5030078 # number of WriteReq accesses(hits+misses) 9209289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5030078 # number of WriteReq accesses(hits+misses) 9219289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 171416 # number of LoadLockedReq accesses(hits+misses) 9229289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 171416 # number of LoadLockedReq accesses(hits+misses) 9239289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178505 # number of StoreCondReq accesses(hits+misses) 9249289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 178505 # number of StoreCondReq accesses(hits+misses) 9259289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12585701 # number of demand (read+write) accesses 9269289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12585701 # number of demand (read+write) accesses 9279289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12585701 # number of overall (read+write) accesses 9289289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12585701 # number of overall (read+write) accesses 9299289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197528 # miss rate for ReadReq accesses 9309289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.197528 # miss rate for ReadReq accesses 9319289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses 9329289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses 9339289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113344 # miss rate for LoadLockedReq accesses 9349289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113344 # miss rate for LoadLockedReq accesses 9359289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.022756 # miss rate for StoreCondReq accesses 9369289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.022756 # miss rate for StoreCondReq accesses 9379289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.246723 # miss rate for demand accesses 9389289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.246723 # miss rate for demand accesses 9399289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.246723 # miss rate for overall accesses 9409289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.246723 # miss rate for overall accesses 9419289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23116.028989 # average ReadReq miss latency 9429289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 23116.028989 # average ReadReq miss latency 9439289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34689.144033 # average WriteReq miss latency 9449289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 34689.144033 # average WriteReq miss latency 9459289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13635.827886 # average LoadLockedReq miss latency 9469289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13635.827886 # average LoadLockedReq miss latency 9479289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11721.935007 # average StoreCondReq miss latency 9489289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11721.935007 # average StoreCondReq miss latency 9499289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency 9509289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 29126.739940 # average overall miss latency 9519289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency 9529289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 29126.739940 # average overall miss latency 9539289Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 1403245 # number of cycles access was blocked 9549289Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 435 # number of cycles access was blocked 9559289Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 52795 # number of cycles access was blocked 9569289Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 9579289Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked 9589289Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked 9598464SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 9608464SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 9619289Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks 9629289Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 710192 # number of writebacks 9639289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits 9649289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits 9659289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits 9669289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits 9679289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits 9689289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits 9699289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits 9709289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits 9719289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits 9729289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits 9739289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses 9749289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses 9759289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses 9769289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses 9779289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses 9789289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses 9799289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses 9809289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses 9819289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses 9829289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses 9839289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses 9849289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses 9859289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles 9869289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles 9879289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles 9889289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles 9899289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles 9909289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles 9919289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles 9929289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles 9939289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles 9949289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles 9959289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles 9969289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles 9979289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles 9989289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles 9999289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles 10009289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles 10019289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles 10029289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles 10039289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses 10049289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses 10059289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses 10069289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses 10079289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses 10089289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses 10099289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses 10109289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses 10119289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses 10129289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses 10139289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses 10149289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses 10159289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency 10169289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency 10179289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency 10189289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency 10199289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency 10209289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency 10219289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency 10229289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency 10239289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency 10249289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency 10259289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency 10269289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency 10278835SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 10289055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 10298835SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 10309055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 10318835SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 10329055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 10338464SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10348464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 10358464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 10368464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 10378464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 10389289Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2472786 # DTB read hits 10399289Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 14686 # DTB read misses 10409289Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 33 # DTB read access violations 10419289Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 413814 # DTB read accesses 10429289Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1645990 # DTB write hits 10439289Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 3399 # DTB write misses 10449289Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 61 # DTB write access violations 10459289Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 158815 # DTB write accesses 10469289Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4118776 # DTB hits 10479289Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 18085 # DTB misses 10489289Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 94 # DTB access violations 10499289Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 572629 # DTB accesses 10509289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 546471 # ITB hits 10519289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 10636 # ITB misses 10529289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 251 # ITB acv 10539289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 557107 # ITB accesses 10548464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 10558464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 10568464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 10578464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 10588464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 10598464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 10608464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 10618464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 10628464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 10638464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 10648464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 10658464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 10669289Sandreas.hansson@arm.comsystem.cpu1.numCycles 20144234 # number of cpu cycles simulated 10678464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 10688464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 10699289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups 10709289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted 10719289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect 10729289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups 10739289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits 10748464SN/Asystem.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 10759289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target. 10769289Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions. 10779289Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss 10789289Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed 10799289Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered 10809289Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken 10819289Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked 10829289Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing 10839289Sandreas.hansson@arm.comsystem.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked 10849289Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 10859289Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps 10869289Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions 10879289Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR 10889289Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched 10899289Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed 10909289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total) 10919289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total) 10929289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total) 10938464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 10949289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total) 10959289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total) 10969289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total) 10979289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total) 10989289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total) 10999289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total) 11009289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total) 11019289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total) 11029289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total) 11038464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 11048464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 11058464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 11069289Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total) 11079289Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle 11089289Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle 11099289Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle 11109289Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked 11119289Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running 11129289Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking 11139289Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing 11149289Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch 11159289Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction 11169289Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode 11179289Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode 11189289Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing 11199289Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle 11209289Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking 11219289Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst 11229289Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running 11239289Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking 11249289Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename 11259289Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full 11269289Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full 11279289Sandreas.hansson@arm.comsystem.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full 11289289Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed 11299289Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made 11309289Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups 11319289Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups 11329289Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed 11339289Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing 11349289Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed 11359289Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed 11369289Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer 11379289Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit. 11389289Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit. 11399289Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads. 11409289Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores. 11419289Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec) 11429289Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ 11439289Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued 11449289Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued 11459289Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling 11469289Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph 11479289Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed 11489289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle 11499289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle 11509289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle 11518464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 11529289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle 11539289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle 11549289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle 11559289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle 11569289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle 11579289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle 11589289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle 11599289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle 11609289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle 11618464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 11628464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 11638464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 11649289Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle 11658464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 11669289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available 11679289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available 11689289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available 11699289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available 11709289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available 11719289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available 11729289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available 11739289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available 11749289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available 11759289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available 11769289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available 11779289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available 11789289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available 11799289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available 11809289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available 11819289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available 11829289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available 11839289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available 11849289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available 11859289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available 11869289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available 11879289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available 11889289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available 11899289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available 11909289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available 11919289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available 11929289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available 11939289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available 11949289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available 11959289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available 11969289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available 11978464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 11988464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 11999289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued 12009289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued 12019289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued 12029289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued 12039289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued 12049289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued 12059289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued 12069289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued 12079289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued 12089289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued 12099289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued 12109289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued 12119289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued 12129289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued 12139289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued 12149289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued 12159289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued 12169289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued 12179289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued 12189289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued 12199289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued 12209289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued 12219289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued 12229289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued 12239289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued 12249289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued 12259289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued 12269289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued 12279289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued 12289289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued 12299289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued 12309289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued 12319289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued 12328464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 12339289Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued 12349289Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.611028 # Inst issue rate 12359289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested 12369289Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst) 12379289Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads 12389289Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes 12399289Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses 12409289Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads 12419289Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes 12429289Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses 12439289Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses 12449289Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses 12459289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores 12468464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 12479289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed 12489289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed 12499289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations 12509289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed 12518464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 12528464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 12539289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled 12549289Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked 12558464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 12569289Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing 12579289Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking 12589289Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking 12599289Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ 12609289Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch 12619289Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions 12629289Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions 12639289Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions 12649289Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall 12659289Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall 12669289Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations 12679289Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly 12689289Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly 12699289Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute 12709289Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions 12719289Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed 12729289Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute 12738464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 12749289Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 665828 # number of nop insts executed 12759289Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed 12769289Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 1827055 # Number of branches executed 12779289Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 1656959 # Number of stores executed 12789289Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.604802 # Inst execution rate 12799289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit 12809289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back 12819289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 5640555 # num instructions producing a value 12829289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value 12838464SN/Asystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 12849289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle 12859289Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back 12868464SN/Asystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 12879289Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit 12889289Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards 12899289Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted 12909289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle 12919289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle 12929289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle 12938464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 12949289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle 12959289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle 12969289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle 12979289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle 12989289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle 12999289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle 13009289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle 13019289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle 13029289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle 13038464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 13048464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 13058464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 13069289Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle 13079289Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 11936636 # Number of instructions committed 13089289Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed 13098464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 13109289Sandreas.hansson@arm.comsystem.cpu1.commit.refs 3824800 # Number of memory references committed 13119289Sandreas.hansson@arm.comsystem.cpu1.commit.loads 2242306 # Number of loads committed 13129289Sandreas.hansson@arm.comsystem.cpu1.commit.membars 59908 # Number of memory barriers committed 13139289Sandreas.hansson@arm.comsystem.cpu1.commit.branches 1711003 # Number of branches committed 13149289Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions. 13159289Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 11053668 # Number of committed integer instructions. 13169289Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 186526 # Number of function calls committed. 13179289Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached 13188464SN/Asystem.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 13199289Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 32234171 # The number of ROB reads 13209289Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 28090700 # The number of ROB writes 13219289Sandreas.hansson@arm.comsystem.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself 13229289Sandreas.hansson@arm.comsystem.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling 13239289Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 13249289Sandreas.hansson@arm.comsystem.cpu1.committedInsts 11348024 # Number of Instructions Simulated 13259289Sandreas.hansson@arm.comsystem.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated 13269289Sandreas.hansson@arm.comsystem.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated 13279289Sandreas.hansson@arm.comsystem.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction 13289289Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads 13299289Sandreas.hansson@arm.comsystem.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle 13309289Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads 13319289Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 15713233 # number of integer regfile reads 13329289Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 8535659 # number of integer regfile writes 13339289Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 74431 # number of floating regfile reads 13349289Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 74222 # number of floating regfile writes 13359289Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 667576 # number of misc regfile reads 13369289Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 284444 # number of misc regfile writes 13379289Sandreas.hansson@arm.comsystem.cpu1.icache.replacements 292722 # number of replacements 13389289Sandreas.hansson@arm.comsystem.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use 13399289Sandreas.hansson@arm.comsystem.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks. 13409289Sandreas.hansson@arm.comsystem.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks. 13419289Sandreas.hansson@arm.comsystem.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks. 13429289Sandreas.hansson@arm.comsystem.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit. 13439289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor 13449289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy 13459289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy 13469289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits 13479289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits 13489289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits 13499289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits 13509289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits 13519289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 1621349 # number of overall hits 13529289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses 13539289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses 13549289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses 13559289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses 13569289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses 13579289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 304491 # number of overall misses 13589289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles 13599289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles 13609289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles 13619289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles 13629289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles 13639289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles 13649289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses) 13659289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses) 13669289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses 13679289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses 13689289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses 13699289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses 13709289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses 13719289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses 13729289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses 13739289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses 13749289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses 13759289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses 13769289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency 13779289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency 13789289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency 13799289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency 13809289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency 13819289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency 13829289Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked 13838464SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 13849289Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked 13858464SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 13869289Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 8.826087 # average number of cycles each access was blocked 13878983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 13888464SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 13898464SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 13909289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11170 # number of ReadReq MSHR hits 13919289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 11170 # number of ReadReq MSHR hits 13929289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 11170 # number of demand (read+write) MSHR hits 13939289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 11170 # number of demand (read+write) MSHR hits 13949289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 11170 # number of overall MSHR hits 13959289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 11170 # number of overall MSHR hits 13969289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 293321 # number of ReadReq MSHR misses 13979289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses 13989289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 293321 # number of demand (read+write) MSHR misses 13999289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 293321 # number of demand (read+write) MSHR misses 14009289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 293321 # number of overall MSHR misses 14019289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses 14029289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3385018500 # number of ReadReq MSHR miss cycles 14039289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 3385018500 # number of ReadReq MSHR miss cycles 14049289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3385018500 # number of demand (read+write) MSHR miss cycles 14059289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 3385018500 # number of demand (read+write) MSHR miss cycles 14069289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3385018500 # number of overall MSHR miss cycles 14079289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 3385018500 # number of overall MSHR miss cycles 14089289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for ReadReq accesses 14099289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152308 # mshr miss rate for ReadReq accesses 14109289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for demand accesses 14119289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.152308 # mshr miss rate for demand accesses 14129289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for overall accesses 14139289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.152308 # mshr miss rate for overall accesses 14149289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average ReadReq mshr miss latency 14159289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency 14169289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency 14179289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency 14189289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency 14199289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency 14208464SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 14219289Sandreas.hansson@arm.comsystem.cpu1.dcache.replacements 154238 # number of replacements 14229289Sandreas.hansson@arm.comsystem.cpu1.dcache.tagsinuse 492.768701 # Cycle average of tags in use 14239289Sandreas.hansson@arm.comsystem.cpu1.dcache.total_refs 3312022 # Total number of references to valid blocks. 14249289Sandreas.hansson@arm.comsystem.cpu1.dcache.sampled_refs 154750 # Sample count of references to valid blocks. 14259289Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_refs 21.402404 # Average number of references to valid blocks. 14269289Sandreas.hansson@arm.comsystem.cpu1.dcache.warmup_cycle 38606824000 # Cycle when the warmup percentage was hit. 14279289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_blocks::cpu1.data 492.768701 # Average occupied blocks per requestor 14289289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::cpu1.data 0.962439 # Average percentage of cache occupancy 14299289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::total 0.962439 # Average percentage of cache occupancy 14309289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2009764 # number of ReadReq hits 14319289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2009764 # number of ReadReq hits 14329289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1195197 # number of WriteReq hits 14339289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1195197 # number of WriteReq hits 14349289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47136 # number of LoadLockedReq hits 14359289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 47136 # number of LoadLockedReq hits 14369289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 45762 # number of StoreCondReq hits 14379289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 45762 # number of StoreCondReq hits 14389289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 3204961 # number of demand (read+write) hits 14399289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 3204961 # number of demand (read+write) hits 14409289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 3204961 # number of overall hits 14419289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 3204961 # number of overall hits 14429289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 288765 # number of ReadReq misses 14439289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 288765 # number of ReadReq misses 14449289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 330549 # number of WriteReq misses 14459289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 330549 # number of WriteReq misses 14469289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7490 # number of LoadLockedReq misses 14479289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 7490 # number of LoadLockedReq misses 14489289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 4284 # number of StoreCondReq misses 14499289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 4284 # number of StoreCondReq misses 14509289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 619314 # number of demand (read+write) misses 14519289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 619314 # number of demand (read+write) misses 14529289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 619314 # number of overall misses 14539289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 619314 # number of overall misses 14549289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4275169500 # number of ReadReq miss cycles 14559289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 4275169500 # number of ReadReq miss cycles 14569289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8473061608 # number of WriteReq miss cycles 14579289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 8473061608 # number of WriteReq miss cycles 14589289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77853000 # number of LoadLockedReq miss cycles 14599289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 77853000 # number of LoadLockedReq miss cycles 14609289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49370500 # number of StoreCondReq miss cycles 14619289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 49370500 # number of StoreCondReq miss cycles 14629289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 12748231108 # number of demand (read+write) miss cycles 14639289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 12748231108 # number of demand (read+write) miss cycles 14649289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 12748231108 # number of overall miss cycles 14659289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 12748231108 # number of overall miss cycles 14669289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2298529 # number of ReadReq accesses(hits+misses) 14679289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2298529 # number of ReadReq accesses(hits+misses) 14689289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1525746 # number of WriteReq accesses(hits+misses) 14699289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1525746 # number of WriteReq accesses(hits+misses) 14709289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54626 # number of LoadLockedReq accesses(hits+misses) 14719289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 54626 # number of LoadLockedReq accesses(hits+misses) 14729289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 50046 # number of StoreCondReq accesses(hits+misses) 14739289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 50046 # number of StoreCondReq accesses(hits+misses) 14749289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 3824275 # number of demand (read+write) accesses 14759289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 3824275 # number of demand (read+write) accesses 14769289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 3824275 # number of overall (read+write) accesses 14779289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 3824275 # number of overall (read+write) accesses 14789289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125630 # miss rate for ReadReq accesses 14799289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.125630 # miss rate for ReadReq accesses 14809289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.216647 # miss rate for WriteReq accesses 14819289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.216647 # miss rate for WriteReq accesses 14829289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137114 # miss rate for LoadLockedReq accesses 14839289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137114 # miss rate for LoadLockedReq accesses 14849289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085601 # miss rate for StoreCondReq accesses 14859289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.085601 # miss rate for StoreCondReq accesses 14869289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.161943 # miss rate for demand accesses 14879289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.161943 # miss rate for demand accesses 14889289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.161943 # miss rate for overall accesses 14899289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.161943 # miss rate for overall accesses 14909289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14805.012727 # average ReadReq miss latency 14919289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14805.012727 # average ReadReq miss latency 14929289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25633.299777 # average WriteReq miss latency 14939289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 25633.299777 # average WriteReq miss latency 14949289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10394.259012 # average LoadLockedReq miss latency 14959289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10394.259012 # average LoadLockedReq miss latency 14969289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11524.393091 # average StoreCondReq miss latency 14979289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11524.393091 # average StoreCondReq miss latency 14989289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency 14999289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 20584.438763 # average overall miss latency 15009289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency 15019289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 20584.438763 # average overall miss latency 15029289Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 148655 # number of cycles access was blocked 15038521SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 15049289Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked 15058521SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 15069289Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked 15078983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 15088464SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 15098464SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 15109289Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks 15119289Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 102031 # number of writebacks 15129289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits 15139289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits 15149289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits 15159289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits 15169289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits 15179289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits 15189289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits 15199289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits 15209289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits 15219289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits 15229289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses 15239289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses 15249289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses 15259289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses 15269289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses 15279289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses 15289289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses 15299289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses 15309289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses 15319289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses 15329289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses 15339289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses 15349289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles 15359289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles 15369289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles 15379289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles 15389289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles 15399289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles 15409289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles 15419289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles 15429289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles 15439289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles 15449289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles 15459289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles 15469289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles 15479289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles 15489289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles 15499289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles 15509289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles 15519289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles 15529289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses 15539289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses 15549289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses 15559289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses 15569289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses 15579289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses 15589289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses 15599289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses 15609289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses 15619289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses 15629289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses 15639289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses 15649289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency 15659289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency 15669289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency 15679289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency 15689289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency 15699289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency 15709289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency 15719289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency 15729289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency 15739289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency 15749289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency 15759289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency 15768835SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 15779055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 15788835SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 15799055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 15808835SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 15819055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 15828464SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 15838464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 15849289Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed 15859289Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed 15869289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl 15879289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl 15889289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl 15899289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl 15909289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl 15919289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl 15929289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl 15939289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl 15949289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl 15959289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl 15969289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl 15979289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl 15989289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl 15999289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl 16009289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl 16019289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl 16029289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl 16039289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl 16049289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl 16058464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 16068464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 16078464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 16089289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl 16099289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl 16109289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed 16119289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed 16129289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed 16139289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed 16149289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed 16159289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed 16169289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed 16179289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed 16189289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed 16199289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed 16209289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed 16219289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed 16229289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed 16239289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed 16249289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed 16259289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed 16269289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed 16279289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed 16289289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed 16299289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed 16309289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed 16319289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed 16329289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed 16339289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed 16349289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed 16359289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed 16369289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed 16379289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed 16389289Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 178 # number of syscalls executed 16398464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 16409289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed 16419289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed 16429289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed 16439289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed 16449289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed 16459289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed 16469289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed 16479289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed 16489289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed 16499289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed 16509289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed 16519289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed 16529289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed 16539289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed 16549289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed 16559289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 16569289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 156308 # number of callpals executed 16579289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches 16589289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1098 # number of protection mode switches 16598464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 16609289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1098 16619289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1098 16628464SN/Asystem.cpu0.kern.mode_good::idle 0 16639289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches 16648464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 16658983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 16669289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches 16679289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode 16689289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode 16698464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 16709289Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3189 # number of times the context was actually changed 16718464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 16729289Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed 16739289Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed 16749289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl 16759289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl 16769289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl 16779289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl 16789289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl 16799289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl 16809289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl 16819289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl 16829289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl 16839289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl 16849289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl 16859289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl 16869289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl 16879289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl 16889289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl 16899289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl 16908464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 16918464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 16929289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl 16939289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl 16949289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed 16959289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed 16969289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed 16979289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed 16989289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed 16999289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed 17009289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed 17019289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed 17029289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed 17039289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed 17049289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed 17059289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed 17069289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed 17079289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed 17089289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed 17099289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed 17109289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed 17119289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed 17129289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed 17139289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed 17149289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed 17159289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed 17169289Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 148 # number of syscalls executed 17178464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 17189289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed 17199289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed 17209289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed 17219289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed 17229289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed 17239289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed 17249289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed 17259289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed 17269289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed 17279289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed 17289289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed 17299289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed 17309289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed 17319289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed 17329289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed 17338464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 17349289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 62728 # number of callpals executed 17359289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches 17369289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 639 # number of protection mode switches 17379289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches 17389289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 948 17399289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 639 17409289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 309 17419289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches 17428464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 17439289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches 17449289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches 17459289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode 17469289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode 17479289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode 17489289Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 1594 # number of times the context was actually changed 17495703SN/A 17505703SN/A---------- End Simulation Statistics ---------- 1751