stats.txt revision 9229
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39229Sandreas.hansson@arm.comsim_seconds 1.903548 # Number of seconds simulated 49229Sandreas.hansson@arm.comsim_ticks 1903548166500 # Number of ticks simulated 59229Sandreas.hansson@arm.comfinal_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79229Sandreas.hansson@arm.comhost_inst_rate 123505 # Simulator instruction rate (inst/s) 89229Sandreas.hansson@arm.comhost_op_rate 123505 # Simulator op (including micro ops) rate (op/s) 99229Sandreas.hansson@arm.comhost_tick_rate 4187441182 # Simulator tick rate (ticks/s) 109229Sandreas.hansson@arm.comhost_mem_usage 303204 # Number of bytes of host memory used 119229Sandreas.hansson@arm.comhost_seconds 454.59 # Real time elapsed on the host 129229Sandreas.hansson@arm.comsim_insts 56143492 # Number of instructions simulated 139229Sandreas.hansson@arm.comsim_ops 56143492 # Number of ops (including micro ops) simulated 149229Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory 159229Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory 169199Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory 179229Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory 189229Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory 199229Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28986880 # Number of bytes read from this memory 209229Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory 219229Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory 229229Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory 239229Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory 249229Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7925376 # Number of bytes written to this memory 259229Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory 269229Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory 279199Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory 289229Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory 299229Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory 309229Sandreas.hansson@arm.comsystem.physmem.num_reads::total 452920 # Number of read requests responded to by this memory 319229Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory 329229Sandreas.hansson@arm.comsystem.physmem.num_writes::total 123834 # Number of write requests responded to by this memory 339229Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) 349229Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) 359229Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) 369229Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) 379229Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) 389229Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) 399229Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) 409229Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) 419229Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) 429229Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) 439229Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) 449229Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) 459229Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) 469229Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) 479229Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) 489229Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) 499229Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) 509229Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) 519229Sandreas.hansson@arm.comsystem.l2c.replacements 346033 # number of replacements 529229Sandreas.hansson@arm.comsystem.l2c.tagsinuse 65330.743124 # Cycle average of tags in use 539229Sandreas.hansson@arm.comsystem.l2c.total_refs 2608063 # Total number of references to valid blocks. 549229Sandreas.hansson@arm.comsystem.l2c.sampled_refs 411178 # Sample count of references to valid blocks. 559229Sandreas.hansson@arm.comsystem.l2c.avg_refs 6.342905 # Average number of references to valid blocks. 569229Sandreas.hansson@arm.comsystem.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. 579229Sandreas.hansson@arm.comsystem.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor 589229Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor 599229Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor 609229Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor 619229Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor 629229Sandreas.hansson@arm.comsystem.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy 639229Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy 649229Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy 659229Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy 669229Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy 679229Sandreas.hansson@arm.comsystem.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy 689229Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits 699229Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits 709229Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits 719229Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits 729229Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits 739229Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits 749229Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 832636 # number of Writeback hits 759229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits 769229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits 779229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits 789229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits 799229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits 809199Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits 819229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 168538 # number of ReadExReq hits 829229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 13567 # number of ReadExReq hits 839229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits 849229Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits 859229Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits 869229Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 107670 # number of demand (read+write) hits 879229Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits 889229Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2080503 # number of demand (read+write) hits 899229Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 970913 # number of overall hits 909229Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 949286 # number of overall hits 919229Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 107670 # number of overall hits 929229Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 52634 # number of overall hits 939229Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2080503 # number of overall hits 949229Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 13744 # number of ReadReq misses 959229Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 272909 # number of ReadReq misses 969229Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1606 # number of ReadReq misses 979229Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses 989229Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 289146 # number of ReadReq misses 999199Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2478 # number of UpgradeReq misses 1009229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 531 # number of UpgradeReq misses 1019229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses 1029229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 43 # number of SCUpgradeReq misses 1039229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 77 # number of SCUpgradeReq misses 1049229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 120 # number of SCUpgradeReq misses 1059229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 114968 # number of ReadExReq misses 1069229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 7955 # number of ReadExReq misses 1079229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 122923 # number of ReadExReq misses 1089229Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 13744 # number of demand (read+write) misses 1099229Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 387877 # number of demand (read+write) misses 1109229Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1606 # number of demand (read+write) misses 1119229Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 8842 # number of demand (read+write) misses 1129229Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 412069 # number of demand (read+write) misses 1139229Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 13744 # number of overall misses 1149229Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 387877 # number of overall misses 1159229Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1606 # number of overall misses 1169229Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 8842 # number of overall misses 1179229Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 412069 # number of overall misses 1189229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 731783998 # number of ReadReq miss cycles 1199229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.data 14210594000 # number of ReadReq miss cycles 1209229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 85626000 # number of ReadReq miss cycles 1219229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles 1229229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 15076443995 # number of ReadReq miss cycles 1239229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 2486000 # number of UpgradeReq miss cycles 1249229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1250500 # number of UpgradeReq miss cycles 1259229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 3736500 # number of UpgradeReq miss cycles 1269229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000 # number of SCUpgradeReq miss cycles 1279229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500 # number of SCUpgradeReq miss cycles 1289229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 678500 # number of SCUpgradeReq miss cycles 1299229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 6190320497 # number of ReadExReq miss cycles 1309229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 441967499 # number of ReadExReq miss cycles 1319229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 6632287996 # number of ReadExReq miss cycles 1329229Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 731783998 # number of demand (read+write) miss cycles 1339229Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 20400914497 # number of demand (read+write) miss cycles 1349229Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 85626000 # number of demand (read+write) miss cycles 1359229Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 490407496 # number of demand (read+write) miss cycles 1369229Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 21708731991 # number of demand (read+write) miss cycles 1379229Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 731783998 # number of overall miss cycles 1389229Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 20400914497 # number of overall miss cycles 1399229Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 85626000 # number of overall miss cycles 1409229Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 490407496 # number of overall miss cycles 1419229Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 21708731991 # number of overall miss cycles 1429229Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 984657 # number of ReadReq accesses(hits+misses) 1439229Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1053657 # number of ReadReq accesses(hits+misses) 1449229Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 109276 # number of ReadReq accesses(hits+misses) 1459229Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 39954 # number of ReadReq accesses(hits+misses) 1469229Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses) 1479229Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses) 1489229Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses) 1499229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2662 # number of UpgradeReq accesses(hits+misses) 1509229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 585 # number of UpgradeReq accesses(hits+misses) 1519229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 3247 # number of UpgradeReq accesses(hits+misses) 1529229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 70 # number of SCUpgradeReq accesses(hits+misses) 1539199Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 106 # number of SCUpgradeReq accesses(hits+misses) 1549229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 176 # number of SCUpgradeReq accesses(hits+misses) 1559229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 283506 # number of ReadExReq accesses(hits+misses) 1569229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 21522 # number of ReadExReq accesses(hits+misses) 1579229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 305028 # number of ReadExReq accesses(hits+misses) 1589229Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 984657 # number of demand (read+write) accesses 1599229Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1337163 # number of demand (read+write) accesses 1609229Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 109276 # number of demand (read+write) accesses 1619229Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 61476 # number of demand (read+write) accesses 1629229Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2492572 # number of demand (read+write) accesses 1639229Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 984657 # number of overall (read+write) accesses 1649229Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1337163 # number of overall (read+write) accesses 1659229Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 109276 # number of overall (read+write) accesses 1669229Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 61476 # number of overall (read+write) accesses 1679229Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2492572 # number of overall (read+write) accesses 1689229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 # miss rate for ReadReq accesses 1699229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.259011 # miss rate for ReadReq accesses 1709229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 # miss rate for ReadReq accesses 1719229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.022201 # miss rate for ReadReq accesses 1729229Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.132178 # miss rate for ReadReq accesses 1739229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879 # miss rate for UpgradeReq accesses 1749229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692 # miss rate for UpgradeReq accesses 1759229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.926702 # miss rate for UpgradeReq accesses 1769229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286 # miss rate for SCUpgradeReq accesses 1779229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415 # miss rate for SCUpgradeReq accesses 1789229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.681818 # miss rate for SCUpgradeReq accesses 1799229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 # miss rate for ReadExReq accesses 1809229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 # miss rate for ReadExReq accesses 1819229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.402989 # miss rate for ReadExReq accesses 1829229Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.013958 # miss rate for demand accesses 1839229Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.290075 # miss rate for demand accesses 1849229Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.014697 # miss rate for demand accesses 1859229Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.143828 # miss rate for demand accesses 1869229Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.165319 # miss rate for demand accesses 1879229Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.013958 # miss rate for overall accesses 1889229Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.290075 # miss rate for overall accesses 1899229Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.014697 # miss rate for overall accesses 1909229Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.143828 # miss rate for overall accesses 1919229Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.165319 # miss rate for overall accesses 1929229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097 # average ReadReq miss latency 1939229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814 # average ReadReq miss latency 1949229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823 # average ReadReq miss latency 1959229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096 # average ReadReq miss latency 1969229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 52141.285008 # average ReadReq miss latency 1979229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.228410 # average UpgradeReq miss latency 1989229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584 # average UpgradeReq miss latency 1999229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 1241.774676 # average UpgradeReq miss latency 2009229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884 # average SCUpgradeReq miss latency 2019229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532 # average SCUpgradeReq miss latency 2029229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 5654.166667 # average SCUpgradeReq miss latency 2039229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525 # average ReadExReq miss latency 2049229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677 # average ReadExReq miss latency 2059229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 53954.817211 # average ReadExReq miss latency 2069229Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency 2079229Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency 2089229Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency 2099229Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency 2109229Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 52682.274063 # average overall miss latency 2119229Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency 2129229Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency 2139229Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency 2149229Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency 2159229Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 52682.274063 # average overall miss latency 2168464SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2178464SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2188464SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2198464SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2208983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2218983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2228464SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 2238464SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 2249229Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 82314 # number of writebacks 2259229Sandreas.hansson@arm.comsystem.l2c.writebacks::total 82314 # number of writebacks 2268844SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 2278844SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 2288835SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 2298844SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2308844SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 2318835SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 2328844SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2338844SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 2348835SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 2359229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 13743 # number of ReadReq MSHR misses 2369229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.data 272909 # number of ReadReq MSHR misses 2379229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 1589 # number of ReadReq MSHR misses 2389229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.data 887 # number of ReadReq MSHR misses 2399229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 289128 # number of ReadReq MSHR misses 2409199Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 2478 # number of UpgradeReq MSHR misses 2419229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 531 # number of UpgradeReq MSHR misses 2429229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses 2439229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 43 # number of SCUpgradeReq MSHR misses 2449229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 77 # number of SCUpgradeReq MSHR misses 2459229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 120 # number of SCUpgradeReq MSHR misses 2469229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 114968 # number of ReadExReq MSHR misses 2479229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 7955 # number of ReadExReq MSHR misses 2489229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 122923 # number of ReadExReq MSHR misses 2499229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 13743 # number of demand (read+write) MSHR misses 2509229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 387877 # number of demand (read+write) MSHR misses 2519229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 1589 # number of demand (read+write) MSHR misses 2529229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 8842 # number of demand (read+write) MSHR misses 2539229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 412051 # number of demand (read+write) MSHR misses 2549229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 13743 # number of overall MSHR misses 2559229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 387877 # number of overall MSHR misses 2569229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 1589 # number of overall MSHR misses 2579229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 8842 # number of overall MSHR misses 2589229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 412051 # number of overall MSHR misses 2599229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 563800998 # number of ReadReq MSHR miss cycles 2609229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.data 10943970500 # number of ReadReq MSHR miss cycles 2619229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 65437000 # number of ReadReq MSHR miss cycles 2629229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.data 37722500 # number of ReadReq MSHR miss cycles 2639229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::total 11610930998 # number of ReadReq MSHR miss cycles 2649229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 99235500 # number of UpgradeReq MSHR miss cycles 2659229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 21259000 # number of UpgradeReq MSHR miss cycles 2669229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 120494500 # number of UpgradeReq MSHR miss cycles 2679229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1720000 # number of SCUpgradeReq MSHR miss cycles 2689229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3080000 # number of SCUpgradeReq MSHR miss cycles 2699229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 4800000 # number of SCUpgradeReq MSHR miss cycles 2709229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4801585997 # number of ReadExReq MSHR miss cycles 2719229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 345787499 # number of ReadExReq MSHR miss cycles 2729229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 5147373496 # number of ReadExReq MSHR miss cycles 2739229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 563800998 # number of demand (read+write) MSHR miss cycles 2749229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 15745556497 # number of demand (read+write) MSHR miss cycles 2759229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 65437000 # number of demand (read+write) MSHR miss cycles 2769229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 383509999 # number of demand (read+write) MSHR miss cycles 2779229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 16758304494 # number of demand (read+write) MSHR miss cycles 2789229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 563800998 # number of overall MSHR miss cycles 2799229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 15745556497 # number of overall MSHR miss cycles 2809229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 65437000 # number of overall MSHR miss cycles 2819229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 383509999 # number of overall MSHR miss cycles 2829229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 16758304494 # number of overall MSHR miss cycles 2839229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363601000 # number of ReadReq MSHR uncacheable cycles 2849229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23660000 # number of ReadReq MSHR uncacheable cycles 2859229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles 2869229Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles 2879229Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles 2889229Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles 2899229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles 2909229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles 2919229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles 2929229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses 2939229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses 2949229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for ReadReq accesses 2959229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022201 # mshr miss rate for ReadReq accesses 2969229Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.132170 # mshr miss rate for ReadReq accesses 2979229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.930879 # mshr miss rate for UpgradeReq accesses 2989229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.907692 # mshr miss rate for UpgradeReq accesses 2999229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.926702 # mshr miss rate for UpgradeReq accesses 3009229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.614286 # mshr miss rate for SCUpgradeReq accesses 3019229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.726415 # mshr miss rate for SCUpgradeReq accesses 3029229Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.681818 # mshr miss rate for SCUpgradeReq accesses 3039229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.405522 # mshr miss rate for ReadExReq accesses 3049229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.369622 # mshr miss rate for ReadExReq accesses 3059229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.402989 # mshr miss rate for ReadExReq accesses 3069229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses 3079229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses 3089229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses 3099229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses 3109229Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses 3119229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses 3129229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses 3139229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses 3149229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses 3159229Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses 3169229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average ReadReq mshr miss latency 3179229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40101.171086 # average ReadReq mshr miss latency 3189229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average ReadReq mshr miss latency 3199229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42528.184893 # average ReadReq mshr miss latency 3209229Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 40158.445388 # average ReadReq mshr miss latency 3219229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40046.610169 # average UpgradeReq mshr miss latency 3229229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40035.781544 # average UpgradeReq mshr miss latency 3239229Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 40044.699236 # average UpgradeReq mshr miss latency 3249199Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency 3259079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency 3269199Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 3279229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency 3289229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency 3299229Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency 3309229Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency 3319229Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency 3329229Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency 3339229Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency 3349229Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency 3359229Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency 3369229Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency 3379229Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency 3389229Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency 3399229Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency 3408835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3418835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3429055Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3438835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3448835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3459055Ssaidi@eecs.umich.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3468835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3478835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3489055Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3498464SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3509199Sandreas.hansson@arm.comsystem.iocache.replacements 41696 # number of replacements 3519229Sandreas.hansson@arm.comsystem.iocache.tagsinuse 0.468369 # Cycle average of tags in use 3528464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 3539199Sandreas.hansson@arm.comsystem.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 3548464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 3559229Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. 3569229Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor 3579229Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy 3589229Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy 3599199Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 3609199Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 176 # number of ReadReq misses 3618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3628464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3639199Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 3649199Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41728 # number of demand (read+write) misses 3659199Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 3669199Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41728 # number of overall misses 3679199Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles 3689199Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles 3699229Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 11487114806 # number of WriteReq miss cycles 3709229Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 11487114806 # number of WriteReq miss cycles 3719229Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 11508127804 # number of demand (read+write) miss cycles 3729229Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 11508127804 # number of demand (read+write) miss cycles 3739229Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 11508127804 # number of overall miss cycles 3749229Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 11508127804 # number of overall miss cycles 3759199Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 3769199Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 3778835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3788464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3799199Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 3809199Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 3819199Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 3829199Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 3838835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3849055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3858835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3869055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3878835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3889055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3898835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3909055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3919199Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency 3929199Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency 3939229Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency 3949229Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency 3959229Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency 3969229Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency 3979229Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency 3989229Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency 3999229Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked 4008464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4019229Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked 4028464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 4039229Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked 4048983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4058464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 4068464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 4078835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 4088835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41520 # number of writebacks 4099199Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 4109199Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 4118835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 4128835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 4139199Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 4149199Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 4159199Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 4169199Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 4179199Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles 4189199Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles 4199229Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles 4209229Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles 4219229Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles 4229229Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles 4239229Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles 4249229Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles 4258835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4269055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 4278835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 4289055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 4298835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4309055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4318835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4329055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 4339199Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency 4349199Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency 4359229Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency 4369229Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency 4379229Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency 4389229Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency 4399229Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency 4409229Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency 4418464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4428464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4438464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4448464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4458464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4468464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4478464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4488464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4498464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4508464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4518464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4528464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4538464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 4548464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 4558464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 4568464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 4578464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 4589229Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9377828 # DTB read hits 4599229Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 33360 # DTB read misses 4609229Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 521 # DTB read access violations 4619229Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 633373 # DTB read accesses 4629229Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 6221809 # DTB write hits 4639229Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 7167 # DTB write misses 4649229Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 341 # DTB write access violations 4659229Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 216042 # DTB write accesses 4669229Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15599637 # DTB hits 4679229Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 40527 # DTB misses 4689229Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 862 # DTB access violations 4699229Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 849415 # DTB accesses 4709229Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 1073423 # ITB hits 4719229Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 26403 # ITB misses 4729229Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 1051 # ITB acv 4739229Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 1099826 # ITB accesses 4748464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 4758464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 4768464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 4778464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 4788464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 4798464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 4808464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 4818464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 4828464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 4838464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 4848464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 4858464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 4869229Sandreas.hansson@arm.comsystem.cpu0.numCycles 120667689 # number of cpu cycles simulated 4878464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 4888464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 4899229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups 4909229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted 4919229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect 4929229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups 4939229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits 4946006SN/Asystem.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4959229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. 4969229Sandreas.hansson@arm.comsystem.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. 4979229Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss 4989229Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed 4999229Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered 5009229Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken 5019229Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked 5029229Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing 5039229Sandreas.hansson@arm.comsystem.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked 5049229Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 5059229Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps 5069229Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions 5079229Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR 5089229Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched 5099229Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed 5109229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) 5119229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) 5129229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) 5138464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 5149229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) 5159229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) 5169229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) 5179229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) 5189229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) 5199229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) 5209229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) 5219229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) 5229229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) 5238464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5248464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5258464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 5269229Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) 5279229Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle 5289229Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle 5299229Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle 5309229Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked 5319229Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running 5329229Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking 5339229Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing 5349229Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch 5359229Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction 5369229Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode 5379229Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode 5389229Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing 5399229Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle 5409229Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking 5419229Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst 5429229Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running 5439229Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking 5449229Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename 5459229Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full 5469229Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full 5479229Sandreas.hansson@arm.comsystem.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full 5489229Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed 5499229Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made 5509229Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups 5519229Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups 5529229Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed 5539229Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing 5549229Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed 5559229Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed 5569229Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer 5579229Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. 5589229Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. 5599229Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. 5609229Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. 5619229Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) 5629229Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ 5639229Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued 5649229Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued 5659229Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling 5669229Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph 5679229Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed 5689229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle 5699229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle 5709229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle 5718464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 5729229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle 5739229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle 5749229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle 5759229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle 5769229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle 5779229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle 5789229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle 5799229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle 5809229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle 5818464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5828464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5838464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 5849229Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle 5858464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5869229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available 5879229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available 5889229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available 5899229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available 5909229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available 5919229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available 5929229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available 5939229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available 5949229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available 5959229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available 5969229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available 5979229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available 5989229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available 5999229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available 6009229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available 6019229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available 6029229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available 6039229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available 6049229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available 6059229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available 6069229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available 6079229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available 6089229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available 6099229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available 6109229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available 6119229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available 6129229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available 6139229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available 6149229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available 6159229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available 6169229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available 6178464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6188464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6199229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued 6209229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued 6219229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued 6229229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued 6239229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued 6249229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued 6259229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued 6269229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued 6279229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued 6289229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued 6299229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued 6309229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued 6319229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued 6329229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued 6339229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued 6349229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued 6359229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued 6369229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued 6379229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued 6389229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued 6399229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued 6409229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued 6419229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued 6429229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued 6439229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued 6449229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued 6459229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued 6469229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued 6479229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued 6489229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued 6499229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued 6509229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued 6519229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued 6528464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 6539229Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued 6549229Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.450141 # Inst issue rate 6559229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested 6569229Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) 6579229Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads 6589229Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes 6599229Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses 6609229Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads 6619229Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes 6629229Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses 6639229Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses 6649229Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses 6659229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores 6668464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 6679229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed 6689229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed 6699229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations 6709229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed 6718464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6728464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 6739229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled 6749229Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked 6758464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 6769229Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing 6779229Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking 6789229Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking 6799229Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ 6809229Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch 6819229Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions 6829229Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions 6839229Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions 6849229Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall 6859229Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall 6869229Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations 6879229Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly 6889229Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly 6899229Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute 6909229Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions 6919229Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed 6929229Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute 6938464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 6949229Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3451283 # number of nop insts executed 6959229Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed 6969229Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 8587439 # Number of branches executed 6979229Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 6243263 # Number of stores executed 6989229Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.446138 # Inst execution rate 6999229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit 7009229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back 7019229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 26356174 # num instructions producing a value 7029229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value 7038464SN/Asystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 7049229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle 7059229Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back 7068464SN/Asystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 7079229Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit 7089229Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards 7099229Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted 7109229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle 7119229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle 7129229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle 7138241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 7149229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle 7159229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle 7169229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle 7179229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle 7189229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle 7199229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle 7209229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle 7219229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle 7229229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle 7238241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7248241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7258241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 7269229Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle 7279229Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 53723778 # Number of instructions committed 7289229Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed 7298241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 7309229Sandreas.hansson@arm.comsystem.cpu0.commit.refs 14622104 # Number of memory references committed 7319229Sandreas.hansson@arm.comsystem.cpu0.commit.loads 8616233 # Number of loads committed 7329229Sandreas.hansson@arm.comsystem.cpu0.commit.membars 216543 # Number of memory barriers committed 7339229Sandreas.hansson@arm.comsystem.cpu0.commit.branches 8113778 # Number of branches committed 7349229Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. 7359229Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. 7369229Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 703203 # Number of function calls committed. 7379229Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached 7388464SN/Asystem.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 7399229Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 143945633 # The number of ROB reads 7409229Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 123274808 # The number of ROB writes 7419229Sandreas.hansson@arm.comsystem.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself 7429229Sandreas.hansson@arm.comsystem.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling 7439229Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 7449229Sandreas.hansson@arm.comsystem.cpu0.committedInsts 50608732 # Number of Instructions Simulated 7459229Sandreas.hansson@arm.comsystem.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated 7469229Sandreas.hansson@arm.comsystem.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated 7479229Sandreas.hansson@arm.comsystem.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction 7489229Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads 7499229Sandreas.hansson@arm.comsystem.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle 7509229Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads 7519229Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 70600527 # number of integer regfile reads 7529229Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 38607300 # number of integer regfile writes 7539229Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 144193 # number of floating regfile reads 7549229Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 146198 # number of floating regfile writes 7559229Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads 7569229Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 886886 # number of misc regfile writes 7575703SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7585703SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7595703SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7605703SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7618464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7638464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7648464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7658983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7668464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7678464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7688983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7698464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7708464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7718983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7728464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7738464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7748983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7758464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7768464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7778983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 7788464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 7798464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 7808983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 7818464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 7828464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 7838983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 7848464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 7858983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 7868464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 7875703SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 7889229Sandreas.hansson@arm.comsystem.cpu0.icache.replacements 984085 # number of replacements 7899229Sandreas.hansson@arm.comsystem.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use 7909229Sandreas.hansson@arm.comsystem.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. 7919229Sandreas.hansson@arm.comsystem.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. 7929229Sandreas.hansson@arm.comsystem.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. 7939229Sandreas.hansson@arm.comsystem.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. 7949229Sandreas.hansson@arm.comsystem.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor 7959229Sandreas.hansson@arm.comsystem.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy 7969229Sandreas.hansson@arm.comsystem.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy 7979229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits 7989229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits 7999229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits 8009229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits 8019229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits 8029229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 7264923 # number of overall hits 8039229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses 8049229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses 8059229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses 8069229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses 8079229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses 8089229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1039697 # number of overall misses 8099229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles 8109229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles 8119229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles 8129229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles 8139229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles 8149229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles 8159229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) 8169229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) 8179229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses 8189229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses 8199229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses 8209229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses 8219229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses 8229229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses 8239229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses 8249229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses 8259229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses 8269229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses 8279229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency 8289229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency 8299229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency 8309229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency 8319229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency 8329229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency 8339229Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked 8348464SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8359229Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked 8368464SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 8379229Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked 8388983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8398464SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 8408464SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 8419229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits 8429229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits 8439229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits 8449229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits 8459229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits 8469229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits 8479229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses 8489229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses 8499229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses 8509229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses 8519229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses 8529229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses 8539229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles 8549229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles 8559229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles 8569229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles 8579229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles 8589229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles 8599229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses 8609229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses 8619229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses 8629229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses 8639229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses 8649229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses 8659229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency 8669229Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency 8679229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency 8689229Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency 8699229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency 8709229Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency 8718464SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 8729229Sandreas.hansson@arm.comsystem.cpu0.dcache.replacements 1341345 # number of replacements 8739229Sandreas.hansson@arm.comsystem.cpu0.dcache.tagsinuse 506.494858 # Cycle average of tags in use 8749229Sandreas.hansson@arm.comsystem.cpu0.dcache.total_refs 11161433 # Total number of references to valid blocks. 8759229Sandreas.hansson@arm.comsystem.cpu0.dcache.sampled_refs 1341857 # Sample count of references to valid blocks. 8769229Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_refs 8.317900 # Average number of references to valid blocks. 8779229Sandreas.hansson@arm.comsystem.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit. 8789229Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_blocks::cpu0.data 506.494858 # Average occupied blocks per requestor 8799229Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::cpu0.data 0.989248 # Average percentage of cache occupancy 8809229Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::total 0.989248 # Average percentage of cache occupancy 8819229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6822568 # number of ReadReq hits 8829229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6822568 # number of ReadReq hits 8839229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3942957 # number of WriteReq hits 8849229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits 8859229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits 8869229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits 8879229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits 8889229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits 8899229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits 8909229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits 8919229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits 8929229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10765525 # number of overall hits 8939229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses 8949229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses 8959229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses 8969229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses 8979229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses 8989229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses 8999229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses 9009229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses 9019229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses 9029229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses 9039229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses 9049229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3558406 # number of overall misses 9059229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles 9069229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles 9079229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles 9089229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles 9099229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles 9109229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles 9119229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles 9129229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles 9139229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles 9149229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles 9159229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles 9169229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles 9179229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) 9189229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) 9199229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) 9209229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) 9219229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) 9229229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) 9239229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) 9249229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) 9259229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses 9269229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses 9279229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses 9289229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses 9299229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses 9309229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses 9319229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses 9329229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses 9339229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses 9349229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses 9359229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses 9369229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses 9379229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses 9389229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses 9399229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses 9409229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses 9419229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency 9429229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency 9439229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency 9449229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency 9459229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency 9469229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency 9479229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency 9489229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency 9499229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency 9509229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency 9519229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency 9529229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency 9539229Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked 9549229Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked 9559229Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked 9569229Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked 9579229Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked 9589229Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked 9598464SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 9608464SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 9619229Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks 9629229Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 796119 # number of writebacks 9639229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits 9649229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits 9659229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits 9669229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits 9679229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits 9689229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits 9699229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits 9709229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits 9719229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits 9729229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits 9739229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses 9749229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses 9759229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses 9769229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses 9779229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses 9789229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses 9799229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses 9809229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses 9819229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses 9829229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses 9839229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses 9849229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses 9859229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles 9869229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles 9879229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles 9889229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles 9899229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles 9909229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles 9919229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles 9929229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles 9939229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles 9949229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles 9959229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles 9969229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles 9979229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles 9989229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles 9999229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles 10009229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles 10019229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles 10029229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles 10039229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses 10049229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses 10059229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses 10069229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses 10079229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses 10089229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses 10099229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses 10109229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses 10119229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses 10129229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses 10139229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses 10149229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses 10159229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency 10169229Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency 10179229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency 10189229Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency 10199229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency 10209229Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency 10219229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency 10229229Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency 10239229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency 10249229Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency 10259229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency 10269229Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency 10278835SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 10289055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 10298835SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 10309055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 10318835SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 10329055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 10338464SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10348464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 10358464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 10368464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 10378464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 10389229Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1298594 # DTB read hits 10399229Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 11503 # DTB read misses 10409229Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 6 # DTB read access violations 10419229Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 332098 # DTB read accesses 10429229Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 765153 # DTB write hits 10439229Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 2957 # DTB write misses 10449229Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 47 # DTB write access violations 10459229Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 125840 # DTB write accesses 10469229Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 2063747 # DTB hits 10479229Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 14460 # DTB misses 10489229Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 53 # DTB access violations 10499229Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 457938 # DTB accesses 10509229Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 372513 # ITB hits 10519229Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 8563 # ITB misses 10529229Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 155 # ITB acv 10539229Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 381076 # ITB accesses 10548464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 10558464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 10568464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 10578464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 10588464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 10598464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 10608464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 10618464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 10628464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 10638464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 10648464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 10658464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 10669229Sandreas.hansson@arm.comsystem.cpu1.numCycles 10640951 # number of cpu cycles simulated 10678464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 10688464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 10699229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups 10709229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted 10719229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect 10729229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups 10739229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits 10748464SN/Asystem.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 10759229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. 10769229Sandreas.hansson@arm.comsystem.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. 10779229Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss 10789229Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed 10799229Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered 10809229Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken 10819229Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked 10829229Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing 10839229Sandreas.hansson@arm.comsystem.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked 10849229Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 10859229Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps 10869229Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions 10879229Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 10889229Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched 10899229Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed 10909229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) 10919229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) 10929229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) 10938464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 10949229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) 10959229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) 10969229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) 10979229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) 10989229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) 10999229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) 11009229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) 11019229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) 11029229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) 11038464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 11048464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 11058464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 11069229Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) 11079229Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle 11089229Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle 11099229Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle 11109229Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked 11119229Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running 11129229Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking 11139229Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing 11149229Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch 11159229Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction 11169229Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode 11179229Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode 11189229Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing 11199229Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle 11209229Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking 11219229Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst 11229229Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running 11239229Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking 11249229Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename 11259229Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full 11269229Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full 11279229Sandreas.hansson@arm.comsystem.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full 11289229Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed 11299229Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made 11309229Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups 11319229Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups 11329229Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed 11339229Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing 11349229Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed 11359229Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed 11369229Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer 11379229Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. 11389229Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. 11399229Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. 11409229Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. 11419229Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) 11429229Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ 11439229Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued 11449229Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued 11459229Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling 11469229Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph 11479229Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed 11489229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle 11499229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle 11509229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle 11518464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 11529229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle 11539229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle 11549229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle 11559229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle 11569229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle 11579229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle 11589229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle 11599229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle 11609229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle 11618464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 11628464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 11638464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 11649229Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle 11658464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 11669229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available 11679229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available 11689229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available 11699229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available 11709229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available 11719229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available 11729229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available 11739229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available 11749229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available 11759229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available 11769229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available 11779229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available 11789229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available 11799229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available 11809229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available 11819229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available 11829229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available 11839229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available 11849229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available 11859229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available 11869229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available 11879229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available 11889229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available 11899229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available 11909229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available 11919229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available 11929229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available 11939229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available 11949229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available 11959229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available 11969229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available 11978464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 11988464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 11999229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued 12009229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued 12019229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued 12029229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued 12039229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued 12049229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued 12059229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued 12069229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued 12079229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued 12089229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued 12099229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued 12109229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued 12119229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued 12129229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued 12139229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued 12149229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued 12159229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued 12169229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued 12179229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued 12189229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued 12199229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued 12209229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued 12219229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued 12229229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued 12239229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued 12249229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued 12259229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued 12269229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued 12279229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued 12289229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued 12299229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued 12309229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued 12319229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued 12328464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 12339229Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued 12349229Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.580207 # Inst issue rate 12359229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested 12369229Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) 12379229Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads 12389229Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes 12399229Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses 12409229Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads 12419229Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes 12429229Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses 12439229Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses 12449229Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses 12459229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores 12468464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 12479229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed 12489229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed 12499229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations 12509229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed 12518464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 12528464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 12539229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled 12549229Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked 12558464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 12569229Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing 12579229Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking 12589229Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking 12599229Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ 12609229Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch 12619229Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions 12629229Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions 12639229Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions 12649229Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall 12659229Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall 12669229Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations 12679229Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly 12689229Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly 12699229Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute 12709229Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions 12719229Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed 12729229Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute 12738464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 12749229Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 261760 # number of nop insts executed 12759229Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed 12769229Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 894247 # Number of branches executed 12779229Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 771430 # Number of stores executed 12789229Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.573587 # Inst execution rate 12799229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit 12809229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back 12819229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 2917806 # num instructions producing a value 12829229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value 12838464SN/Asystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 12849229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle 12859229Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back 12868464SN/Asystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 12879229Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit 12889229Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards 12899229Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted 12909229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle 12919229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle 12929229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle 12938464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 12949229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle 12959229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle 12969229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle 12979229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle 12989229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle 12999229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle 13009229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle 13019229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle 13029229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle 13038464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 13048464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 13058464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 13069229Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle 13079229Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 5754744 # Number of instructions committed 13089229Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed 13098464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 13109229Sandreas.hansson@arm.comsystem.cpu1.commit.refs 1860459 # Number of memory references committed 13119229Sandreas.hansson@arm.comsystem.cpu1.commit.loads 1142005 # Number of loads committed 13129229Sandreas.hansson@arm.comsystem.cpu1.commit.membars 20259 # Number of memory barriers committed 13139229Sandreas.hansson@arm.comsystem.cpu1.commit.branches 814036 # Number of branches committed 13149229Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. 13159229Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. 13169229Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 87726 # Number of function calls committed. 13179229Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached 13188464SN/Asystem.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 13199229Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 16310969 # The number of ROB reads 13209229Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 14184459 # The number of ROB writes 13219229Sandreas.hansson@arm.comsystem.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself 13229229Sandreas.hansson@arm.comsystem.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling 13239229Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 13249229Sandreas.hansson@arm.comsystem.cpu1.committedInsts 5534760 # Number of Instructions Simulated 13259229Sandreas.hansson@arm.comsystem.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated 13269229Sandreas.hansson@arm.comsystem.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated 13279229Sandreas.hansson@arm.comsystem.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction 13289229Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads 13299229Sandreas.hansson@arm.comsystem.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle 13309229Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads 13319229Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 7951221 # number of integer regfile reads 13329229Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 4345022 # number of integer regfile writes 13339229Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 24272 # number of floating regfile reads 13349229Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 22982 # number of floating regfile writes 13359229Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 283160 # number of misc regfile reads 13369229Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 134137 # number of misc regfile writes 13379229Sandreas.hansson@arm.comsystem.cpu1.icache.replacements 108736 # number of replacements 13389229Sandreas.hansson@arm.comsystem.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use 13399229Sandreas.hansson@arm.comsystem.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. 13409229Sandreas.hansson@arm.comsystem.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. 13419229Sandreas.hansson@arm.comsystem.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. 13429229Sandreas.hansson@arm.comsystem.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. 13439229Sandreas.hansson@arm.comsystem.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor 13449229Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy 13459229Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy 13469229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits 13479229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits 13489229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits 13499229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits 13509229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits 13519229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 924017 # number of overall hits 13529229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses 13539229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses 13549229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses 13559229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses 13569229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses 13579229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 115346 # number of overall misses 13589229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles 13599229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles 13609229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles 13619229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles 13629229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles 13639229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles 13649229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) 13659229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) 13669229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses 13679229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses 13689229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses 13699229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses 13709229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses 13719229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses 13729229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses 13739229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses 13749229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses 13759229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses 13769229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency 13779229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency 13789229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency 13799229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency 13809229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency 13819229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency 13829229Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked 13838464SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 13849229Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked 13858464SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 13869229Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked 13878983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 13888464SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 13898464SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 13909229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits 13919229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits 13929229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits 13939229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits 13949229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits 13959229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits 13969229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses 13979229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses 13989229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses 13999229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses 14009229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses 14019229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses 14029229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles 14039229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles 14049229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles 14059229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles 14069229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles 14079229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles 14089229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses 14099229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses 14109229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses 14119229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses 14129229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses 14139229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses 14149229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency 14159229Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency 14169229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency 14179229Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency 14189229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency 14199229Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency 14208464SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 14219229Sandreas.hansson@arm.comsystem.cpu1.dcache.replacements 61811 # number of replacements 14229229Sandreas.hansson@arm.comsystem.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use 14239229Sandreas.hansson@arm.comsystem.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. 14249229Sandreas.hansson@arm.comsystem.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. 14259229Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. 14269229Sandreas.hansson@arm.comsystem.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. 14279229Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor 14289229Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy 14299229Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy 14309229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits 14319229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits 14329229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits 14339229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits 14349229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits 14359229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits 14369229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits 14379229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits 14389229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits 14399229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits 14409229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits 14419229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 1641949 # number of overall hits 14429229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses 14439229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses 14449229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses 14459229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses 14469229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses 14479229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses 14489229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses 14499229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses 14509229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses 14519229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses 14529229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses 14539229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 266705 # number of overall misses 14549229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles 14559229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles 14569229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles 14579229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles 14589229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles 14599229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles 14609229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles 14619229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles 14629229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles 14639229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles 14649229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles 14659229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles 14669229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) 14679229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) 14689229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) 14699229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) 14709229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) 14719229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) 14729229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) 14739229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) 14749229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses 14759229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses 14769229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses 14779229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses 14789229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses 14799229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses 14809229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses 14819229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses 14829229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses 14839229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses 14849229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses 14859229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses 14869229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses 14879229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses 14889229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses 14899229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses 14909229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency 14919229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency 14929229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency 14939229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency 14949229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency 14959229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency 14969229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency 14979229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency 14989229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency 14999229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency 15009229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency 15019229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency 15029229Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked 15038521SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 15049229Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked 15058521SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 15069229Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked 15078983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 15088464SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 15098464SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 15109229Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks 15119229Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 36517 # number of writebacks 15129229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits 15139229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits 15149229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits 15159229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits 15169229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits 15179229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits 15189229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits 15199229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits 15209229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits 15219229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits 15229229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses 15239229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses 15249229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses 15259229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses 15269229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses 15279229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses 15289229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses 15299229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses 15309229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses 15319229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses 15329229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses 15339229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses 15349229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles 15359229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles 15369229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles 15379229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles 15389229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles 15399229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles 15409229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles 15419229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles 15429229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles 15439229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles 15449229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles 15459229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles 15469229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles 15479229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles 15489229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles 15499229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles 15509229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles 15519229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles 15529229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses 15539229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses 15549229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses 15559229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses 15569229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses 15579229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses 15589229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses 15599229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses 15609229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses 15619229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses 15629229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses 15639229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses 15649229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency 15659229Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency 15669229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency 15679229Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency 15689229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency 15699229Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency 15709229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency 15719229Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency 15729229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency 15739229Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency 15749229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency 15759229Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency 15768835SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 15779055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 15788835SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 15799055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 15808835SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 15819055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 15828464SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 15838464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 15849229Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 15859229Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed 15869229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl 15879229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl 15889229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl 15899229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl 15909229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl 15919229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl 15929229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl 15939229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl 15949229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl 15959229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl 15969229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl 15979229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl 15989229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl 15999229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl 16009229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl 16019229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl 16029229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl 16039229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl 16049229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl 16058464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 16068464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 16078464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 16089229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl 16099229Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl 16109229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed 16119229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed 16129229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed 16139229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed 16149229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed 16159229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed 16169229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed 16179229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed 16189229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed 16199229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed 16209229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed 16219229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed 16229229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed 16239229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed 16249229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed 16259229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed 16269229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed 16279229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed 16289229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed 16299229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed 16309229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed 16319229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed 16329229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed 16339229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed 16349229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed 16359229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed 16369229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed 16379229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed 16389229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed 16399229Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 219 # number of syscalls executed 16408464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 16419229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed 16429199Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 16439199Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 16449199Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 16459229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed 16469229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed 16479229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed 16489229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed 16499229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed 16509229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed 16519229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed 16529229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed 16539229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed 16549229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed 16559229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed 16569229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed 16579229Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 184824 # number of callpals executed 16589229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches 16599229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1251 # number of protection mode switches 16608464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 16619229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1250 16629229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1251 16638464SN/Asystem.cpu0.kern.mode_good::idle 0 16649229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches 16658464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 16668983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 16679229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches 16689229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode 16699229Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode 16708464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 16719229Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3851 # number of times the context was actually changed 16728464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 16739229Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed 16749229Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed 16759229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl 16769229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl 16779229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl 16789229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl 16799229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl 16809229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl 16819229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl 16829229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl 16839229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl 16849229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl 16859229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl 16869229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl 16879229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl 16889229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl 16899229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl 16909229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl 16918464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 16928464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 16939229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl 16949229Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl 16959229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed 16969229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed 16979229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed 16989229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed 16999229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed 17009229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed 17019229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed 17029229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed 17039229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed 17049229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed 17059229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed 17069229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed 17079229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed 17089229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed 17099229Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 107 # number of syscalls executed 17108464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 17119229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed 17129199Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 17139229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed 17149229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed 17159229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed 17169229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed 17179229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed 17189229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed 17199229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed 17209229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed 17219229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed 17229229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed 17239229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed 17249229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed 17258464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 17269229Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 31584 # number of callpals executed 17279229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches 17289229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 488 # number of protection mode switches 17299199Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches 17309229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 514 17319229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 488 17329199Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 26 17339229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches 17348464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 17359199Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches 17369229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches 17379229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode 17389229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode 17399229Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode 17409229Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 386 # number of times the context was actually changed 17415703SN/A 17425703SN/A---------- End Simulation Statistics ---------- 1743