stats.txt revision 9229
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.903548 # Number of seconds simulated 4sim_ticks 1903548166500 # Number of ticks simulated 5final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123505 # Simulator instruction rate (inst/s) 8host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4187441182 # Simulator tick rate (ticks/s) 10host_mem_usage 303204 # Number of bytes of host memory used 11host_seconds 454.59 # Real time elapsed on the host 12sim_insts 56143492 # Number of instructions simulated 13sim_ops 56143492 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 346033 # number of replacements 52system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use 53system.l2c.total_refs 2608063 # Total number of references to valid blocks. 54system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits 74system.l2c.Writeback_hits::total 832636 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 168538 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 13567 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 107670 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2080503 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 970913 # number of overall hits 90system.l2c.overall_hits::cpu0.data 949286 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 107670 # number of overall hits 92system.l2c.overall_hits::cpu1.data 52634 # number of overall hits 93system.l2c.overall_hits::total 2080503 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13744 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 272909 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1606 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 289146 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2478 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 531 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 43 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 77 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 120 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 114968 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 7955 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 122923 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13744 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 387877 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1606 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 8842 # number of demand (read+write) misses 112system.l2c.demand_misses::total 412069 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13744 # number of overall misses 114system.l2c.overall_misses::cpu0.data 387877 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1606 # number of overall misses 116system.l2c.overall_misses::cpu1.data 8842 # number of overall misses 117system.l2c.overall_misses::total 412069 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 731783998 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14210594000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 85626000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 15076443995 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 3736500 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 678500 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 441967499 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6632287996 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 731783998 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20400914497 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 85626000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 490407496 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21708731991 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 731783998 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20400914497 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 85626000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 490407496 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21708731991 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 984657 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 1053657 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 109276 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 39954 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 2662 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 585 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3247 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 70 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 106 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 176 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 283506 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 21522 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 305028 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 984657 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1337163 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 109276 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 61476 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2492572 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 984657 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1337163 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 109276 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 61476 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2492572 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.259011 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.022201 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.132178 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.926702 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.681818 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.402989 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.013958 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.290075 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.014697 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.143828 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.165319 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.013958 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.290075 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.014697 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.143828 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.165319 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52141.285008 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.228410 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 1241.774676 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 5654.166667 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 53954.817211 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52682.274063 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52682.274063 # average overall miss latency 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed 224system.l2c.writebacks::writebacks 82314 # number of writebacks 225system.l2c.writebacks::total 82314 # number of writebacks 226system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 228system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 229system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 230system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 231system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 232system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 233system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 234system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13743 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 272909 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 1589 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 887 # number of ReadReq MSHR misses 239system.l2c.ReadReq_mshr_misses::total 289128 # number of ReadReq MSHR misses 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2478 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 531 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 43 # number of SCUpgradeReq MSHR misses 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 77 # number of SCUpgradeReq MSHR misses 245system.l2c.SCUpgradeReq_mshr_misses::total 120 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 114968 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 7955 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 122923 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13743 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 387877 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 1589 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 8842 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 412051 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13743 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 387877 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 1589 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 8842 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 412051 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 563800998 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10943970500 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 65437000 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 37722500 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 11610930998 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 99235500 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 21259000 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 120494500 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1720000 # number of SCUpgradeReq MSHR miss cycles 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3080000 # number of SCUpgradeReq MSHR miss cycles 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 4800000 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4801585997 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 345787499 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 5147373496 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 563800998 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15745556497 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 65437000 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 383509999 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 16758304494 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 563800998 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15745556497 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 65437000 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 383509999 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 16758304494 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363601000 # number of ReadReq MSHR uncacheable cycles 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23660000 # number of ReadReq MSHR uncacheable cycles 285system.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles 288system.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles 291system.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022201 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.132170 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.930879 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.907692 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.926702 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.614286 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.726415 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.681818 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.405522 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.369622 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.402989 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40101.171086 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42528.184893 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40158.445388 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40046.610169 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40035.781544 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40044.699236 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 350system.iocache.replacements 41696 # number of replacements 351system.iocache.tagsinuse 0.468369 # Cycle average of tags in use 352system.iocache.total_refs 0 # Total number of references to valid blocks. 353system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 354system.iocache.avg_refs 0 # Average number of references to valid blocks. 355system.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. 356system.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor 357system.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 363system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 366system.iocache.overall_misses::total 41728 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles 369system.iocache.WriteReq_miss_latency::tsunami.ide 11487114806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 11487114806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 11508127804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 11508127804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 11508127804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 11508127804 # number of overall miss cycles 375system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 379system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked 403system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks 409system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 413system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses 458system.cpu0.dtb.read_hits 9377828 # DTB read hits 459system.cpu0.dtb.read_misses 33360 # DTB read misses 460system.cpu0.dtb.read_acv 521 # DTB read access violations 461system.cpu0.dtb.read_accesses 633373 # DTB read accesses 462system.cpu0.dtb.write_hits 6221809 # DTB write hits 463system.cpu0.dtb.write_misses 7167 # DTB write misses 464system.cpu0.dtb.write_acv 341 # DTB write access violations 465system.cpu0.dtb.write_accesses 216042 # DTB write accesses 466system.cpu0.dtb.data_hits 15599637 # DTB hits 467system.cpu0.dtb.data_misses 40527 # DTB misses 468system.cpu0.dtb.data_acv 862 # DTB access violations 469system.cpu0.dtb.data_accesses 849415 # DTB accesses 470system.cpu0.itb.fetch_hits 1073423 # ITB hits 471system.cpu0.itb.fetch_misses 26403 # ITB misses 472system.cpu0.itb.fetch_acv 1051 # ITB acv 473system.cpu0.itb.fetch_accesses 1099826 # ITB accesses 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses 486system.cpu0.numCycles 120667689 # number of cpu cycles simulated 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 489system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 495system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 514system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 526system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 572system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 584system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 586system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 619system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued 620system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued 623system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued 631system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued 632system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued 633system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued 634system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued 635system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued 636system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued 637system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued 638system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued 639system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued 640system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued 649system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 653system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued 654system.cpu0.iq.rate 0.450141 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 667system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 673system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 676system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute 693system.cpu0.iew.exec_swp 0 # number of swp insts executed 694system.cpu0.iew.exec_nop 3451283 # number of nop insts executed 695system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 8587439 # Number of branches executed 697system.cpu0.iew.exec_stores 6243263 # Number of stores executed 698system.cpu0.iew.exec_rate 0.446138 # Inst execution rate 699system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 26356174 # num instructions producing a value 702system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 704system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 707system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit 708system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards 709system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted 710system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle 711system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle 712system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle 715system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle 716system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 725system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle 727system.cpu0.commit.committedInsts 53723778 # Number of instructions committed 728system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed 729system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 730system.cpu0.commit.refs 14622104 # Number of memory references committed 731system.cpu0.commit.loads 8616233 # Number of loads committed 732system.cpu0.commit.membars 216543 # Number of memory barriers committed 733system.cpu0.commit.branches 8113778 # Number of branches committed 734system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. 735system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. 736system.cpu0.commit.function_calls 703203 # Number of function calls committed. 737system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached 738system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 739system.cpu0.rob.rob_reads 143945633 # The number of ROB reads 740system.cpu0.rob.rob_writes 123274808 # The number of ROB writes 741system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself 742system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling 743system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 744system.cpu0.committedInsts 50608732 # Number of Instructions Simulated 745system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated 746system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated 747system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction 748system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads 749system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle 750system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads 751system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads 752system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes 753system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads 754system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes 755system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads 756system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes 757system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 758system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 759system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 760system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 761system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 762system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 763system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 764system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 765system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 766system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 767system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 768system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 769system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 770system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 771system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 772system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 773system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 774system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 775system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 776system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 777system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 778system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 779system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 780system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 781system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 782system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 783system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 784system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 785system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 786system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 787system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 788system.cpu0.icache.replacements 984085 # number of replacements 789system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use 790system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. 791system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. 792system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. 793system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. 794system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor 795system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy 796system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy 797system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits 798system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits 799system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits 800system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits 801system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits 802system.cpu0.icache.overall_hits::total 7264923 # number of overall hits 803system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses 804system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses 805system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses 806system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses 807system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses 808system.cpu0.icache.overall_misses::total 1039697 # number of overall misses 809system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles 810system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles 811system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles 812system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles 813system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles 814system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles 815system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) 816system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) 817system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses 818system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses 819system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses 820system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses 821system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses 822system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses 823system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses 824system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses 825system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses 826system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses 827system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency 828system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency 829system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency 830system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency 831system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency 832system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency 833system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked 834system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 835system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked 836system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 837system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked 838system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 839system.cpu0.icache.fast_writes 0 # number of fast writes performed 840system.cpu0.icache.cache_copies 0 # number of cache copies performed 841system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits 842system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits 843system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits 844system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits 845system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits 846system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits 847system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses 848system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses 849system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses 850system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses 851system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses 852system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses 853system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles 854system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles 855system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles 856system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles 857system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles 858system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles 859system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses 860system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses 861system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses 862system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses 863system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses 864system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses 865system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency 866system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency 867system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency 868system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency 869system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency 870system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency 871system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 872system.cpu0.dcache.replacements 1341345 # number of replacements 873system.cpu0.dcache.tagsinuse 506.494858 # Cycle average of tags in use 874system.cpu0.dcache.total_refs 11161433 # Total number of references to valid blocks. 875system.cpu0.dcache.sampled_refs 1341857 # Sample count of references to valid blocks. 876system.cpu0.dcache.avg_refs 8.317900 # Average number of references to valid blocks. 877system.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit. 878system.cpu0.dcache.occ_blocks::cpu0.data 506.494858 # Average occupied blocks per requestor 879system.cpu0.dcache.occ_percent::cpu0.data 0.989248 # Average percentage of cache occupancy 880system.cpu0.dcache.occ_percent::total 0.989248 # Average percentage of cache occupancy 881system.cpu0.dcache.ReadReq_hits::cpu0.data 6822568 # number of ReadReq hits 882system.cpu0.dcache.ReadReq_hits::total 6822568 # number of ReadReq hits 883system.cpu0.dcache.WriteReq_hits::cpu0.data 3942957 # number of WriteReq hits 884system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits 885system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits 886system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits 887system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits 888system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits 889system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits 890system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits 891system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits 892system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits 893system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses 894system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses 895system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses 896system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses 897system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses 898system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses 899system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses 900system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses 901system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses 902system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses 903system.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses 904system.cpu0.dcache.overall_misses::total 3558406 # number of overall misses 905system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles 906system.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles 907system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles 908system.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles 909system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles 910system.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles 911system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles 912system.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles 913system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles 914system.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles 915system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles 916system.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles 917system.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) 918system.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) 919system.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) 920system.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) 921system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) 922system.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) 923system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) 924system.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) 925system.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses 926system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses 927system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses 928system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses 929system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses 930system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses 931system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses 932system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses 933system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses 934system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses 935system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses 936system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses 937system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses 938system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses 939system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses 940system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses 941system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency 942system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency 943system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency 944system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency 945system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency 946system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency 947system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency 948system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency 949system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency 950system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency 951system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency 952system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency 953system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked 954system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked 955system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked 956system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked 957system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked 958system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked 959system.cpu0.dcache.fast_writes 0 # number of fast writes performed 960system.cpu0.dcache.cache_copies 0 # number of cache copies performed 961system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks 962system.cpu0.dcache.writebacks::total 796119 # number of writebacks 963system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits 964system.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits 965system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits 966system.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits 967system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits 968system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits 969system.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits 970system.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits 971system.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits 972system.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits 973system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses 974system.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses 975system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses 976system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses 977system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses 978system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses 979system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses 980system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses 981system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses 982system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses 983system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses 984system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses 985system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles 986system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles 987system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles 988system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles 989system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles 990system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles 991system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles 992system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles 993system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles 994system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles 995system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles 996system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles 997system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles 998system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles 999system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles 1000system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles 1001system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles 1002system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles 1003system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses 1004system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses 1005system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses 1006system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses 1007system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses 1008system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses 1009system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses 1010system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses 1011system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses 1012system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses 1013system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses 1014system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses 1015system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency 1016system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency 1017system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency 1018system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency 1019system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency 1020system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency 1021system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency 1022system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency 1023system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency 1024system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency 1025system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency 1026system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency 1027system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1028system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1029system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1030system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1031system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1032system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1033system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1034system.cpu1.dtb.fetch_hits 0 # ITB hits 1035system.cpu1.dtb.fetch_misses 0 # ITB misses 1036system.cpu1.dtb.fetch_acv 0 # ITB acv 1037system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1038system.cpu1.dtb.read_hits 1298594 # DTB read hits 1039system.cpu1.dtb.read_misses 11503 # DTB read misses 1040system.cpu1.dtb.read_acv 6 # DTB read access violations 1041system.cpu1.dtb.read_accesses 332098 # DTB read accesses 1042system.cpu1.dtb.write_hits 765153 # DTB write hits 1043system.cpu1.dtb.write_misses 2957 # DTB write misses 1044system.cpu1.dtb.write_acv 47 # DTB write access violations 1045system.cpu1.dtb.write_accesses 125840 # DTB write accesses 1046system.cpu1.dtb.data_hits 2063747 # DTB hits 1047system.cpu1.dtb.data_misses 14460 # DTB misses 1048system.cpu1.dtb.data_acv 53 # DTB access violations 1049system.cpu1.dtb.data_accesses 457938 # DTB accesses 1050system.cpu1.itb.fetch_hits 372513 # ITB hits 1051system.cpu1.itb.fetch_misses 8563 # ITB misses 1052system.cpu1.itb.fetch_acv 155 # ITB acv 1053system.cpu1.itb.fetch_accesses 381076 # ITB accesses 1054system.cpu1.itb.read_hits 0 # DTB read hits 1055system.cpu1.itb.read_misses 0 # DTB read misses 1056system.cpu1.itb.read_acv 0 # DTB read access violations 1057system.cpu1.itb.read_accesses 0 # DTB read accesses 1058system.cpu1.itb.write_hits 0 # DTB write hits 1059system.cpu1.itb.write_misses 0 # DTB write misses 1060system.cpu1.itb.write_acv 0 # DTB write access violations 1061system.cpu1.itb.write_accesses 0 # DTB write accesses 1062system.cpu1.itb.data_hits 0 # DTB hits 1063system.cpu1.itb.data_misses 0 # DTB misses 1064system.cpu1.itb.data_acv 0 # DTB access violations 1065system.cpu1.itb.data_accesses 0 # DTB accesses 1066system.cpu1.numCycles 10640951 # number of cpu cycles simulated 1067system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1068system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1069system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups 1070system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted 1071system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect 1072system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups 1073system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits 1074system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1075system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. 1076system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. 1077system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss 1078system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed 1079system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered 1080system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken 1081system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked 1082system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing 1083system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked 1084system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1085system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps 1086system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions 1087system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 1088system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched 1089system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed 1090system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) 1091system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) 1092system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) 1093system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1094system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) 1095system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) 1096system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) 1097system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) 1098system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1105system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) 1107system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle 1108system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle 1109system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle 1110system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked 1111system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running 1112system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking 1113system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing 1114system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch 1115system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction 1116system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode 1117system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode 1118system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing 1119system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle 1120system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking 1121system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst 1122system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running 1123system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking 1124system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename 1125system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full 1126system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full 1127system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full 1128system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed 1129system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made 1130system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups 1131system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups 1132system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed 1133system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing 1134system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed 1135system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed 1136system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer 1137system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. 1138system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. 1139system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. 1140system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. 1141system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) 1142system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ 1143system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued 1144system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued 1145system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling 1146system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph 1147system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed 1148system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle 1149system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle 1150system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle 1151system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1152system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle 1153system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle 1154system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle 1155system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle 1156system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1163system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle 1165system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1166system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available 1167system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available 1168system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available 1169system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available 1170system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1199system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued 1200system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued 1201system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued 1202system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued 1203system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued 1204system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued 1205system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued 1206system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued 1208system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued 1209system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued 1210system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued 1211system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued 1212system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued 1214system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued 1215system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued 1216system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued 1217system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued 1218system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued 1219system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued 1220system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued 1221system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued 1222system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued 1223system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued 1224system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued 1225system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued 1229system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued 1230system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued 1231system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued 1232system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1233system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued 1234system.cpu1.iq.rate 0.580207 # Inst issue rate 1235system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested 1236system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) 1237system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads 1238system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes 1239system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses 1240system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads 1241system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes 1242system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses 1243system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses 1244system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses 1245system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores 1246system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1247system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed 1248system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed 1249system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations 1250system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed 1251system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1252system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1253system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled 1254system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked 1255system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1256system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing 1257system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking 1258system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking 1259system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ 1260system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch 1261system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions 1262system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions 1263system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions 1264system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall 1265system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall 1266system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations 1267system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly 1268system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly 1269system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute 1270system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions 1271system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed 1272system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute 1273system.cpu1.iew.exec_swp 0 # number of swp insts executed 1274system.cpu1.iew.exec_nop 261760 # number of nop insts executed 1275system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed 1276system.cpu1.iew.exec_branches 894247 # Number of branches executed 1277system.cpu1.iew.exec_stores 771430 # Number of stores executed 1278system.cpu1.iew.exec_rate 0.573587 # Inst execution rate 1279system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit 1280system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back 1281system.cpu1.iew.wb_producers 2917806 # num instructions producing a value 1282system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value 1283system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1284system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle 1285system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back 1286system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1287system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit 1288system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards 1289system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted 1290system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle 1291system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle 1292system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle 1293system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1294system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle 1295system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle 1296system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle 1297system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle 1298system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle 1299system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle 1300system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle 1307system.cpu1.commit.committedInsts 5754744 # Number of instructions committed 1308system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed 1309system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1310system.cpu1.commit.refs 1860459 # Number of memory references committed 1311system.cpu1.commit.loads 1142005 # Number of loads committed 1312system.cpu1.commit.membars 20259 # Number of memory barriers committed 1313system.cpu1.commit.branches 814036 # Number of branches committed 1314system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. 1315system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. 1316system.cpu1.commit.function_calls 87726 # Number of function calls committed. 1317system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached 1318system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1319system.cpu1.rob.rob_reads 16310969 # The number of ROB reads 1320system.cpu1.rob.rob_writes 14184459 # The number of ROB writes 1321system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself 1322system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling 1323system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1324system.cpu1.committedInsts 5534760 # Number of Instructions Simulated 1325system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated 1326system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated 1327system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction 1328system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads 1329system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle 1330system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads 1331system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads 1332system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes 1333system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads 1334system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes 1335system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads 1336system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes 1337system.cpu1.icache.replacements 108736 # number of replacements 1338system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use 1339system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. 1340system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. 1341system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. 1342system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. 1343system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor 1344system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy 1345system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy 1346system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits 1347system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits 1348system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits 1349system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits 1350system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits 1351system.cpu1.icache.overall_hits::total 924017 # number of overall hits 1352system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses 1353system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses 1354system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses 1355system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses 1356system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses 1357system.cpu1.icache.overall_misses::total 115346 # number of overall misses 1358system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles 1359system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles 1360system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles 1361system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles 1362system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles 1363system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles 1364system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) 1365system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) 1366system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses 1367system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses 1368system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses 1369system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses 1370system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses 1371system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses 1372system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses 1373system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses 1374system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses 1375system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses 1376system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency 1377system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency 1378system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency 1379system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency 1380system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency 1381system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency 1382system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked 1383system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1384system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked 1385system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1386system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked 1387system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1388system.cpu1.icache.fast_writes 0 # number of fast writes performed 1389system.cpu1.icache.cache_copies 0 # number of cache copies performed 1390system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits 1391system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits 1392system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits 1393system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits 1394system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits 1395system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits 1396system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses 1397system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses 1398system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses 1399system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses 1400system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses 1401system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses 1402system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles 1403system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles 1404system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles 1405system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles 1406system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles 1407system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles 1408system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses 1409system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses 1410system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses 1411system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses 1412system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses 1413system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses 1414system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency 1415system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency 1416system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency 1417system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency 1418system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency 1419system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency 1420system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1421system.cpu1.dcache.replacements 61811 # number of replacements 1422system.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use 1423system.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. 1424system.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. 1425system.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. 1426system.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. 1427system.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor 1428system.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy 1429system.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy 1430system.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits 1431system.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits 1432system.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits 1433system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits 1434system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits 1435system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits 1436system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits 1437system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits 1438system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits 1439system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits 1440system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits 1441system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits 1442system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses 1443system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses 1444system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses 1445system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses 1446system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses 1447system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses 1448system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses 1449system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses 1450system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses 1451system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses 1452system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses 1453system.cpu1.dcache.overall_misses::total 266705 # number of overall misses 1454system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles 1455system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles 1456system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles 1457system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles 1458system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles 1459system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles 1460system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles 1461system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles 1462system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles 1463system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles 1464system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles 1465system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles 1466system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) 1467system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) 1468system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) 1469system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) 1470system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) 1471system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) 1472system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) 1473system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) 1474system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses 1475system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses 1476system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses 1477system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses 1478system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses 1479system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses 1480system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses 1481system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses 1482system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses 1483system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses 1484system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses 1485system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses 1486system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses 1487system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses 1488system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses 1489system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses 1490system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency 1491system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency 1492system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency 1493system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency 1494system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency 1495system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency 1496system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency 1497system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency 1498system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency 1499system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency 1500system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency 1501system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency 1502system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked 1503system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1504system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked 1505system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1506system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked 1507system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1508system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1509system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1510system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks 1511system.cpu1.dcache.writebacks::total 36517 # number of writebacks 1512system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits 1513system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits 1514system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits 1515system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits 1516system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits 1517system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits 1518system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits 1519system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits 1520system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits 1521system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits 1522system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses 1523system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses 1524system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses 1525system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses 1526system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses 1527system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses 1528system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses 1529system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses 1530system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses 1531system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses 1532system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses 1533system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses 1534system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles 1535system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles 1536system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles 1537system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles 1538system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles 1539system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles 1540system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles 1541system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles 1542system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles 1543system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles 1544system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles 1545system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles 1546system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles 1547system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles 1548system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles 1549system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles 1550system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles 1551system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles 1552system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses 1553system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses 1554system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses 1555system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses 1556system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses 1557system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses 1558system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses 1559system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses 1560system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses 1561system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses 1562system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses 1563system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses 1564system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency 1565system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency 1566system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency 1567system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency 1568system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency 1569system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency 1570system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency 1571system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency 1572system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency 1573system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency 1574system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency 1575system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency 1576system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1577system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1578system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1579system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1580system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1581system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1582system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1583system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1584system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 1585system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed 1586system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl 1587system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl 1588system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl 1589system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl 1590system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl 1591system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl 1592system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl 1593system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl 1594system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl 1595system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl 1596system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl 1597system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl 1598system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl 1599system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl 1600system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl 1601system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl 1602system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl 1603system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl 1604system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl 1605system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1606system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1607system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1608system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl 1609system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl 1610system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed 1611system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed 1612system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed 1613system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed 1614system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed 1615system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed 1616system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed 1617system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed 1618system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed 1619system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed 1620system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed 1621system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed 1622system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed 1623system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed 1624system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed 1625system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed 1626system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed 1627system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed 1628system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed 1629system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed 1630system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed 1631system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed 1632system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed 1633system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed 1634system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed 1635system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed 1636system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed 1637system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed 1638system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed 1639system.cpu0.kern.syscall::total 219 # number of syscalls executed 1640system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1641system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed 1642system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 1643system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 1644system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 1645system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed 1646system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed 1647system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed 1648system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed 1649system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed 1650system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed 1651system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed 1652system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed 1653system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed 1654system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed 1655system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed 1656system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed 1657system.cpu0.kern.callpal::total 184824 # number of callpals executed 1658system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches 1659system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches 1660system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1661system.cpu0.kern.mode_good::kernel 1250 1662system.cpu0.kern.mode_good::user 1251 1663system.cpu0.kern.mode_good::idle 0 1664system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches 1665system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1666system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 1667system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches 1668system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode 1669system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode 1670system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1671system.cpu0.kern.swap_context 3851 # number of times the context was actually changed 1672system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1673system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed 1674system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed 1675system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl 1676system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl 1677system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl 1678system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl 1679system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl 1680system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl 1681system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl 1682system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl 1683system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl 1684system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl 1685system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl 1686system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl 1687system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl 1688system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl 1689system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl 1690system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl 1691system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1692system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1693system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl 1694system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl 1695system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed 1696system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed 1697system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed 1698system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed 1699system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed 1700system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed 1701system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed 1702system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed 1703system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed 1704system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed 1705system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed 1706system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed 1707system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed 1708system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed 1709system.cpu1.kern.syscall::total 107 # number of syscalls executed 1710system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1711system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed 1712system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1713system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed 1714system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed 1715system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed 1716system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed 1717system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed 1718system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed 1719system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed 1720system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed 1721system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed 1722system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed 1723system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed 1724system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed 1725system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1726system.cpu1.kern.callpal::total 31584 # number of callpals executed 1727system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches 1728system.cpu1.kern.mode_switch::user 488 # number of protection mode switches 1729system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches 1730system.cpu1.kern.mode_good::kernel 514 1731system.cpu1.kern.mode_good::user 488 1732system.cpu1.kern.mode_good::idle 26 1733system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches 1734system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1735system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches 1736system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches 1737system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode 1738system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode 1739system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode 1740system.cpu1.kern.swap_context 386 # number of times the context was actually changed 1741 1742---------- End Simulation Statistics ---------- 1743