stats.txt revision 11754
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311754Sandreas.hansson@arm.comsim_seconds 1.909484 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 1909483951500 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 164890 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 164890 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 5556117262 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 341236 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 343.67 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 56668174 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 56668174 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory 2011680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory 2110576Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26307904 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory 2611754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7910400 # Number of bytes written to this memory 2811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory 2911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory 3011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory 3111680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory 3210576Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3311754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 411061 # Number of read requests responded to by this memory 3411754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory 3511754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 123600 # Number of write requests responded to by this memory 3611754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) 3711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) 3811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) 3911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) 4011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 4111754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) 4211754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) 4311754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) 4411754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) 4511754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) 4611754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) 4711754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) 4811754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) 4911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) 5011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) 5111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.readReqs 411061 # Number of read requests accepted 5511754Sandreas.hansson@arm.comsystem.physmem.writeReqs 123600 # Number of write requests accepted 5611754Sandreas.hansson@arm.comsystem.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue 5711754Sandreas.hansson@arm.comsystem.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue 5811754Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM 5911754Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue 6011754Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM 6111754Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side 6211754Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side 6311754Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue 6410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 26241 # Per bank write bursts 6711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25988 # Per bank write bursts 6811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25972 # Per bank write bursts 6911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25684 # Per bank write bursts 7011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25579 # Per bank write bursts 7111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 25567 # Per bank write bursts 7211754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 25634 # Per bank write bursts 7311754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25346 # Per bank write bursts 7411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 25590 # Per bank write bursts 7511754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25694 # Per bank write bursts 7611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25928 # Per bank write bursts 7711754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25514 # Per bank write bursts 7811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 26076 # Per bank write bursts 7911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25422 # Per bank write bursts 8011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25093 # Per bank write bursts 8111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25620 # Per bank write bursts 8211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 8582 # Per bank write bursts 8311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 8090 # Per bank write bursts 8411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7941 # Per bank write bursts 8511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7423 # Per bank write bursts 8611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7276 # Per bank write bursts 8711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 7412 # Per bank write bursts 8811754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 7548 # Per bank write bursts 8911754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 7160 # Per bank write bursts 9011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 7532 # Per bank write bursts 9111754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 7637 # Per bank write bursts 9211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7817 # Per bank write bursts 9311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 7733 # Per bank write bursts 9411754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 8265 # Per bank write bursts 9511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7849 # Per bank write bursts 9611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 7512 # Per bank write bursts 9711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7803 # Per bank write bursts 989978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911754Sandreas.hansson@arm.comsystem.physmem.numWrRetry 80 # Number of times write queue was full causing retry 10011754Sandreas.hansson@arm.comsystem.physmem.totGap 1909479571500 # Total gap between requests 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1069978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711754Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 411061 # Read request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1139978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411754Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 123600 # Write request sizes (log2) 11511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see 11611754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see 11711754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see 11811754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see 11911754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see 12011754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see 12111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see 12211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 13010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 13610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13710242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see 16311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see 16511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see 16611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see 16711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see 16811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see 16911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see 17011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see 17111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see 17211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see 17311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see 17411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see 17511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see 17611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see 17711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see 17811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see 17911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see 18011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see 18111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see 18211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see 18311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see 18411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see 18511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see 18611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see 18711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see 18811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see 18911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 19111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see 19211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see 19311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see 19411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see 19511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see 19611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see 19711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see 19811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see 19911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see 20011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see 20111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see 20211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see 20311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see 20411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see 20511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see 20611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see 20711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see 20811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see 20911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see 21011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see 21111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation 21211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation 21311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation 21411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation 21511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation 21611754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation 21711754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation 21811754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation 21911754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation 22011754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation 22111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation 22211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation 22311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation 22411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation 22511754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes 22611754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes 22711754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes 22811754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes 22910726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 23010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 23110352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 23211754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes 23311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads 23411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads 23511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads 23611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads 23711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads 23811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads 23911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads 24011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads 24111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads 24211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads 24311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads 24411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads 24511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads 24611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads 24711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads 24811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads 24911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads 25011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads 25111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads 25211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads 25311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads 25411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads 25511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads 25611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads 25711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads 25811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads 25911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads 26011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads 26111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads 26211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 26311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 26411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads 26511754Sandreas.hansson@arm.comsystem.physmem.totQLat 8180795500 # Total ticks spent queuing 26611754Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM 26711754Sandreas.hansson@arm.comsystem.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers 26811754Sandreas.hansson@arm.comsystem.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst 2699978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27011754Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst 27111754Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 27211754Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s 27311754Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 27411754Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s 2759978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27610892Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27710352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 27810892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 27911754Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing 28011754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 28111754Sandreas.hansson@arm.comsystem.physmem.readRowHits 370615 # Number of row buffer hits during reads 28211754Sandreas.hansson@arm.comsystem.physmem.writeRowHits 99546 # Number of row buffer hits during writes 28311680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads 28411754Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes 28511754Sandreas.hansson@arm.comsystem.physmem.avgGap 3571383.68 # Average gap between requests 28611680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined 28711754Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) 28811754Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) 28911754Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) 29011754Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) 29111754Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) 29211754Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) 29311754Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) 29411754Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) 29511754Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) 29611754Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) 29711754Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) 29811754Sandreas.hansson@arm.comsystem.physmem_0.averagePower 247.578716 # Core power per rank (mW) 29911754Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank 30011754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states 30111754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states 30211754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states 30311754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states 30411754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states 30511754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states 30611754Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) 30711754Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) 30811754Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) 30911754Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) 31011754Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) 31111754Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) 31211754Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) 31311754Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) 31411754Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) 31511754Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) 31611754Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) 31711754Sandreas.hansson@arm.comsystem.physmem_1.averagePower 247.436414 # Core power per rank (mW) 31811754Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank 31911754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states 32011754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states 32111754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states 32211754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states 32311754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states 32411754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states 32511754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 32611754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 32711754Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 16749334 # Number of BP lookups 32811754Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted 32911754Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect 33011754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups 33111754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits 3329481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33311754Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage 33411754Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. 33511754Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. 33611754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. 33711754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. 33811754Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. 33911754Sandreas.hansson@arm.comsystem.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. 34010576Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3418464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3428464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3438464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3448464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 34511754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9423503 # DTB read hits 34611754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 34044 # DTB read misses 34711754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 602 # DTB read access violations 34811754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 567323 # DTB read accesses 34911754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5707426 # DTB write hits 35011754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 8375 # DTB write misses 35111754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 432 # DTB write access violations 35211754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 185068 # DTB write accesses 35311754Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15130929 # DTB hits 35411754Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 42419 # DTB misses 35511754Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 1034 # DTB access violations 35611754Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 752391 # DTB accesses 35711754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 1309826 # ITB hits 35811754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 6979 # ITB misses 35911754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 608 # ITB acv 36011754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 1316805 # ITB accesses 3618464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3628464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3638464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3648464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3658464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3668464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3678464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3688464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3698464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3708464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3718464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3728464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 37311754Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 12955 # Number of power state transitions 37411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state 37511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state 37611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state 37711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 37811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state 37911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 38011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 38111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state 38211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states 38311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states 38411754Sandreas.hansson@arm.comsystem.cpu0.numCycles 119453997 # number of cpu cycles simulated 3858464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3868464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 38711754Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss 38811754Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed 38911754Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered 39011754Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken 39111754Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked 39211754Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing 39311680SCurtis.Dunham@arm.comsystem.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb 39411754Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39511754Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps 39611754Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions 39711754Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR 39811754Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched 39911754Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed 40011754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) 40111754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) 40211754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) 4038464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40411754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) 40511754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) 40611754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) 40711754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) 40811754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) 40911754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) 41011754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) 41111754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) 41211754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) 4138464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4148464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4158464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 41611754Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) 41711754Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle 41811754Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle 41911754Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle 42011754Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked 42111754Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running 42211754Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking 42311754Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing 42411754Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch 42511754Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction 42611754Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode 42711754Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode 42811754Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing 42911754Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle 43011754Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking 43111754Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst 43211754Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running 43311754Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking 43411754Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename 43511754Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full 43611754Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full 43711754Sandreas.hansson@arm.comsystem.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full 43811754Sandreas.hansson@arm.comsystem.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full 43911754Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed 44011754Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made 44111754Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups 44211754Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups 44311754Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed 44411754Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing 44511754Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed 44611754Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed 44711754Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer 44811754Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. 44911754Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. 45011754Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. 45111754Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. 45211754Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) 45311754Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ 45411754Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued 45511754Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued 45611754Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling 45711754Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph 45811754Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed 45911754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle 46011754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle 46111754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle 4628464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 46311754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle 46411754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle 46511754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle 46611754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle 46711754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle 46811754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle 46911754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle 47011754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle 47111754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle 4728464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4738464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4748464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 47511754Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle 4768464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47711754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available 47811754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available 47911754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available 48011754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available 48111754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available 48211754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available 48311754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available 48411754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available 48511754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available 48611754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available 48711754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available 48811754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available 48911754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available 49011754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available 49111754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available 49211754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available 49311754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available 49411754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available 49511754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available 49611754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available 49711754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available 49811754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available 49911754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available 50011754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available 50111754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available 50211754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available 50311754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available 50411754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available 50511754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available 50611754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available 50711754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available 50811754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available 50911754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available 51011754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available 51111754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available 5128464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5138464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 51411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued 51511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued 51611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued 51711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued 51811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued 51911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued 52011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued 52111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued 52211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued 52311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued 52411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued 52511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued 52611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued 52711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued 52811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued 52911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued 53011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued 53111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued 53211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued 53311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued 53411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued 53511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued 53611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued 53711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued 53811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued 53911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued 54011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued 54111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued 54211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued 54311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued 54411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued 54511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued 54611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued 54711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued 54811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued 54911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued 55011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued 5518464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 55211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued 55311754Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.440485 # Inst issue rate 55411754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested 55511754Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) 55611754Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads 55711754Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes 55811754Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses 55911754Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads 56011754Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes 56111754Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses 56211754Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses 56311754Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses 56411754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores 5658464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 56611754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed 56711754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed 56811754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations 56911754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed 5708464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5718464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 57211754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled 57311754Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked 5748464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 57511754Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing 57611754Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking 57711754Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking 57811754Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ 57911754Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch 58011754Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions 58111754Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions 58211754Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions 58311754Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall 58411754Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall 58511754Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations 58611754Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly 58711754Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly 58811754Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute 58911754Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions 59011754Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed 59111754Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute 5928464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 59311754Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3535809 # number of nop insts executed 59411754Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed 59511754Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 8258108 # Number of branches executed 59611754Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 5732729 # Number of stores executed 59711754Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.434781 # Inst execution rate 59811754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit 59911754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back 60011754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 26231692 # num instructions producing a value 60111754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value 60211754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle 60311754Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back 60411754Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit 60511754Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards 60611754Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted 60711754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle 60811754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle 60911754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle 6108241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 61111754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle 61211754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle 61311754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle 61411754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle 61511754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle 61611754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle 61711754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle 61811754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle 61911754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle 6208241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6218241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6228241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 62311754Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle 62411754Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 49593272 # Number of instructions committed 62511754Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed 6268241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 62711754Sandreas.hansson@arm.comsystem.cpu0.commit.refs 13266986 # Number of memory references committed 62811754Sandreas.hansson@arm.comsystem.cpu0.commit.loads 7864361 # Number of loads committed 62911754Sandreas.hansson@arm.comsystem.cpu0.commit.membars 192313 # Number of memory barriers committed 63011754Sandreas.hansson@arm.comsystem.cpu0.commit.branches 7507748 # Number of branches committed 63111754Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. 63211754Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. 63311754Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 632222 # Number of function calls committed. 63411754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction 63511754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction 63611754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction 63711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction 63811754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction 63911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction 64011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction 64111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction 64211687Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction 64311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction 64411687Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction 64511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction 64611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction 64711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction 64811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction 64911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction 65011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction 65111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction 65211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction 65311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction 65411680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction 65511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction 65611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction 65711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction 65811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction 65911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction 66011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction 66111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction 66211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction 66311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction 66411680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction 66511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction 66611754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction 66711754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction 66811754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction 66911754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction 67011754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction 67110220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 67211754Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction 67311754Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached 67411754Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 169631516 # The number of ROB reads 67511754Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 120597460 # The number of ROB writes 67611754Sandreas.hansson@arm.comsystem.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself 67711754Sandreas.hansson@arm.comsystem.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling 67811754Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 67911754Sandreas.hansson@arm.comsystem.cpu0.committedInsts 46709842 # Number of Instructions Simulated 68011754Sandreas.hansson@arm.comsystem.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated 68111754Sandreas.hansson@arm.comsystem.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction 68211754Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads 68311754Sandreas.hansson@arm.comsystem.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle 68411754Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads 68511754Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 67996788 # number of integer regfile reads 68611754Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 37259313 # number of integer regfile writes 68711754Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 121463 # number of floating regfile reads 68811754Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 130119 # number of floating regfile writes 68911754Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads 69011754Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 782234 # number of misc regfile writes 69111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 69211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1252644 # number of replacements 69311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use 69411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. 69511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. 69611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. 69711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. 69811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor 69911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy 70011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy 70111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 70211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 70311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 70411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id 70511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses 70611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses 70711754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 70811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits 70911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits 71011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits 71111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits 71211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits 71311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits 71411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits 71511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits 71611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits 71711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits 71811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits 71911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10297236 # number of overall hits 72011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses 72111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses 72211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses 72311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses 72411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses 72511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses 72611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses 72711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses 72811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses 72911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses 73011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses 73111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3235818 # number of overall misses 73211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles 73311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles 73411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles 73511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles 73611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles 73711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles 73811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles 73911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles 74011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles 74111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles 74211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles 74311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles 74411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) 74511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) 74611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) 74711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) 74811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) 74911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) 75011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) 75111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) 75211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses 75311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses 75411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses 75511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses 75611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses 75711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses 75811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses 75911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses 76011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses 76111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses 76211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses 76311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses 76411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses 76511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses 76611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses 76711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses 76811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency 76911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency 77011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency 77111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency 77211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency 77311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency 77411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency 77511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency 77611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency 77711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency 77811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency 77911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency 78011754Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked 78111754Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked 78211754Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked 78311754Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked 78411754Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked 78511754Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked 78611754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks 78711754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 737573 # number of writebacks 78811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits 78911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits 79011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits 79111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits 79211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits 79311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits 79411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits 79511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits 79611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits 79711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits 79811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses 79911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses 80011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses 80111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses 80211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses 80311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses 80411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses 80511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses 80611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses 80711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses 80811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses 80911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses 81011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 81111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable 81211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable 81311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable 81411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses 81511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses 81611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles 81711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles 81811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles 81911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles 82011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles 82111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles 82211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles 82311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles 82411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles 82511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles 82611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles 82711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles 82811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles 82911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles 83011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles 83111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles 83211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses 83311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses 83411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses 83511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses 83611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses 83711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses 83811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses 83911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses 84011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses 84111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses 84211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses 84311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses 84411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency 84511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency 84611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency 84711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency 84811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency 84911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency 85011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency 85111754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency 85211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency 85311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency 85411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency 85511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency 85611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency 85711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency 85811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency 85911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency 86011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 86111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 892272 # number of replacements 86211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use 86311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. 86411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. 86511754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. 86611754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. 86711754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor 86811754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy 86911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy 87011606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 87111680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id 87211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 87311606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 87411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses 87511754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses 87611754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 87711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits 87811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits 87911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits 88011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits 88111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits 88211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 7503325 # number of overall hits 88311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses 88411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses 88511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses 88611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses 88711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses 88811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 945376 # number of overall misses 88911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles 89011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles 89111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles 89211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles 89311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles 89411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles 89511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) 89611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) 89711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses 89811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses 89911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses 90011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses 90111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses 90211754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses 90311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses 90411754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses 90511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses 90611754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses 90711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency 90811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency 90911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency 91011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency 91111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency 91211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency 91311754Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked 91410576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91511754Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked 91610576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 91711754Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked 91810576Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91911754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 892272 # number of writebacks 92011754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 892272 # number of writebacks 92111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits 92211754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits 92311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits 92411754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits 92511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits 92611754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits 92711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses 92811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses 92911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses 93011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses 93111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses 93211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses 93311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles 93411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles 93511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles 93611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles 93711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles 93811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles 93911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses 94011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses 94111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses 94211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses 94311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses 94411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses 94511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency 94611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency 94711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency 94811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency 94911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency 95011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency 95111754Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 4441555 # Number of BP lookups 95211754Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted 95311754Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect 95411754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups 95511754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 883836 # Number of BTB hits 9569481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 95711754Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage 95811754Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. 95911754Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. 96011754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. 96111754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. 96211754Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. 96311754Sandreas.hansson@arm.comsystem.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. 9648464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 9658464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 9668464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 9678464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 96811754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2431988 # DTB read hits 96911754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 15687 # DTB read misses 97011754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 78 # DTB read access violations 97111754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 432427 # DTB read accesses 97211754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1439876 # DTB write hits 97311754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 3853 # DTB write misses 97411754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 69 # DTB write access violations 97511754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 163205 # DTB write accesses 97611754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 3871864 # DTB hits 97711754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 19540 # DTB misses 97811754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 147 # DTB access violations 97911754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 595632 # DTB accesses 98011754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 677957 # ITB hits 98111754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 3440 # ITB misses 98211754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 149 # ITB acv 98311754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 681397 # ITB accesses 9848464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 9858464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 9868464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 9878464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 9888464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 9898464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 9908464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 9918464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 9928464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 9938464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 9948464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 9958464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 99611754Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 5092 # Number of power state transitions 99711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state 99811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state 99911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state 100011754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state 100111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state 100211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state 100311754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state 100411754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states 100511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states 100611754Sandreas.hansson@arm.comsystem.cpu1.numCycles 17559475 # number of cpu cycles simulated 10078464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 10088464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 100911754Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss 101011754Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed 101111754Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered 101211754Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken 101311754Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked 101411754Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing 101511754Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 101611754Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps 101711754Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions 101811754Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR 101911754Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched 102011754Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed 102111754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) 102211754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) 102311754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) 10248464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 102511754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) 102611754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) 102711754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) 102811754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) 102911754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) 103011754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) 103111754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) 103211754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) 103311754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) 10348464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 10358464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 10368464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 103711754Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) 103811754Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle 103911754Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle 104011754Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle 104111754Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked 104211754Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running 104311754Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking 104411754Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing 104511754Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch 104611754Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction 104711754Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode 104811754Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode 104911754Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing 105011754Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle 105111754Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking 105211754Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst 105311754Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running 105411754Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking 105511754Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename 105611754Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full 105711754Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full 105811754Sandreas.hansson@arm.comsystem.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full 105911754Sandreas.hansson@arm.comsystem.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full 106011754Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed 106111754Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made 106211754Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups 106311754Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups 106411754Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed 106511754Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing 106611754Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed 106711754Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed 106811754Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer 106911754Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. 107011754Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. 107111754Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. 107211754Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. 107311754Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) 107411754Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ 107511754Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued 107611754Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued 107711754Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling 107811754Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph 107911754Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed 108011754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle 108111754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle 108211754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle 10838464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 108411754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle 108511754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle 108611754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle 108711754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle 108811754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle 108911754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle 109011754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle 109111754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle 109211754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle 10938464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 10948464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 10958464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 109611754Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle 10978464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 109811754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available 109911754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available 110011754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available 110111754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available 110211754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available 110311754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available 110411754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available 110511754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available 110611754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available 110711754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available 110811754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available 110911754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available 111011754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available 111111754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available 111211754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available 111311754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available 111411754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available 111511754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available 111611754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available 111711754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available 111811754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available 111911754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available 112011754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available 112111754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available 112211754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available 112311754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available 112411754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available 112511754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available 112611754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available 112711754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available 112811754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available 112911754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available 113011754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available 113111754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available 113211754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available 11338464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 11348464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 113511606Sandreas.sandberg@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued 113611754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued 113711754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued 113811754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 113911754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued 114011754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued 114111754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued 114211754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued 114311754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued 114411754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued 114511754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued 114611754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued 114711754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued 114811754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued 114911754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued 115011754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued 115111754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued 115211754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued 115311754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued 115411754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued 115511754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued 115611754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued 115711754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued 115811754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued 115911754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued 116011754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued 116111754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued 116211754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued 116311754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued 116411754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued 116511754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued 116611754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued 116711754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued 116811754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued 116911754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued 117011754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued 117111754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued 11728464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 117311754Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued 117411754Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.653242 # Inst issue rate 117511754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested 117611754Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) 117711754Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads 117811754Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes 117911754Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses 118011754Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads 118111754Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes 118211754Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses 118311754Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses 118411754Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses 118511754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores 11868464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 118711754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed 118811754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed 118911754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations 119011754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed 11918464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 11928464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 119311754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled 119411754Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked 11958464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 119611754Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing 119711754Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking 119811754Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking 119911754Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ 120011754Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch 120111754Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions 120211754Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions 120311754Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions 120411754Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall 120511754Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall 120611754Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations 120711754Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly 120811754Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly 120911754Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute 121011754Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions 121111754Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed 121211754Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute 12138464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 121411754Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 650640 # number of nop insts executed 121511754Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed 121611754Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 1689156 # Number of branches executed 121711754Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 1450305 # Number of stores executed 121811754Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.642403 # Inst execution rate 121911754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit 122011754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back 122111754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 5286560 # num instructions producing a value 122211754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value 122311754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle 122411754Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back 122511754Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit 122611754Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards 122711754Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted 122811754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle 122911754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle 123011754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle 12318464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 123211754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle 123311754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle 123411754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle 123511754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle 123611754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle 123711754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle 123811754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle 123911754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle 124011754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle 12418464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 12428464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 12438464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 124411754Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle 124511754Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 10444029 # Number of instructions committed 124611754Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed 12478464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 124811754Sandreas.hansson@arm.comsystem.cpu1.commit.refs 3355674 # Number of memory references committed 124911754Sandreas.hansson@arm.comsystem.cpu1.commit.loads 1990378 # Number of loads committed 125011754Sandreas.hansson@arm.comsystem.cpu1.commit.membars 48933 # Number of memory barriers committed 125111754Sandreas.hansson@arm.comsystem.cpu1.commit.branches 1499197 # Number of branches committed 125211754Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. 125311754Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. 125411754Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 163891 # Number of function calls committed. 125511754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction 125611754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction 125711754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction 125811754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction 125911754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction 126011754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction 126111754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction 126211754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction 126311754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction 126411754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction 126511754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction 126611754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction 126711754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction 126811754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction 126911754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction 127011754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction 127111754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction 127211754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction 127311754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction 127411754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction 127511754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction 127611754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction 127711754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction 127811754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction 127911754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction 128011754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction 128111754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction 128211754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction 128311754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction 128411754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction 128511754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction 128611754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction 128711754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction 128811754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction 128911754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction 129011754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction 129111754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction 129210220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 129311754Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction 129411754Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached 129511754Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 28763808 # The number of ROB reads 129611754Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 26546353 # The number of ROB writes 129711754Sandreas.hansson@arm.comsystem.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself 129811754Sandreas.hansson@arm.comsystem.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling 129911754Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 130011754Sandreas.hansson@arm.comsystem.cpu1.committedInsts 9958332 # Number of Instructions Simulated 130111754Sandreas.hansson@arm.comsystem.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated 130211754Sandreas.hansson@arm.comsystem.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction 130311754Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads 130411754Sandreas.hansson@arm.comsystem.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle 130511754Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads 130611754Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 14511646 # number of integer regfile reads 130711754Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 7905629 # number of integer regfile writes 130811754Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 58867 # number of floating regfile reads 130911754Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 57930 # number of floating regfile writes 131011754Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 573957 # number of misc regfile reads 131111754Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 245081 # number of misc regfile writes 131211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 131311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 131073 # number of replacements 131411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use 131511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. 131611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. 131711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. 131811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. 131911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor 132011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy 132111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy 132211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 132311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id 132411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 132511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 132611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 132711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses 132811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses 132911754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 133011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits 133111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits 133211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits 133311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits 133411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits 133511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits 133611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits 133711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits 133811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits 133911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits 134011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits 134111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 2974738 # number of overall hits 134211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses 134311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses 134411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses 134511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses 134611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses 134711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses 134811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses 134911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses 135011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses 135111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses 135211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses 135311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 533406 # number of overall misses 135411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles 135511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles 135611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles 135711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles 135811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles 135911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles 136011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles 136111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles 136211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles 136311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles 136411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles 136511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles 136611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) 136711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) 136811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) 136911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) 137011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) 137111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) 137211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) 137311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) 137411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses 137511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses 137611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses 137711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses 137811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses 137911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses 138011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses 138111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses 138211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses 138311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses 138411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses 138511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses 138611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses 138711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses 138811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses 138911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses 139011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency 139111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency 139211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency 139311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency 139411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency 139511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency 139611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency 139711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency 139811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency 139911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency 140011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency 140111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency 140211754Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked 140311754Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked 140411754Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked 140511754Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked 140611754Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked 140711754Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked 140811754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks 140911754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 84598 # number of writebacks 141011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits 141111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits 141211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits 141311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits 141411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits 141511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits 141611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits 141711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits 141811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits 141911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits 142011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses 142111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses 142211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses 142311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses 142411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses 142511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses 142611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses 142711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses 142811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses 142911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses 143011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses 143111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses 143211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 143311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable 143411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable 143511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable 143611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses 143711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses 143811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles 143911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles 144011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles 144111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles 144211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles 144311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles 144411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles 144511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles 144611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles 144711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles 144811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles 144911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles 145011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles 145111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles 145211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles 145311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles 145411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses 145511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses 145611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses 145711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses 145811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses 145911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses 146011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses 146111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses 146211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses 146311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses 146411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses 146511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses 146611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency 146711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency 146811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency 146911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency 147011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency 147111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency 147211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency 147311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency 147411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency 147511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency 147611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency 147711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency 147811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency 147911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency 148011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency 148111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency 148211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 148311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 256867 # number of replacements 148411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use 148511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. 148611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. 148711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. 148811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. 148911754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor 149011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy 149111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy 149211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 149311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 149411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 149511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id 149611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 149711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses 149811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses 149911754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 150011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits 150111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits 150211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits 150311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits 150411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits 150511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 1711658 # number of overall hits 150611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses 150711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses 150811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses 150911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses 151011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses 151111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 269479 # number of overall misses 151211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles 151311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles 151411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles 151511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles 151611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles 151711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles 151811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) 151911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) 152011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses 152111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses 152211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses 152311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses 152411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses 152511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses 152611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses 152711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses 152811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses 152911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses 153011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency 153111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency 153211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency 153311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency 153411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency 153511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency 153611754Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked 153710576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 153811754Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked 153910576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 154011754Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked 154110576Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 154211754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 256867 # number of writebacks 154311754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 256867 # number of writebacks 154411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits 154511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits 154611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits 154711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits 154811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits 154911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits 155011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses 155111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses 155211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses 155311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses 155411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses 155511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses 155611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles 155711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles 155811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles 155911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles 156011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles 156111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles 156211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses 156311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses 156411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses 156511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses 156611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses 156711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses 156811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency 156911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency 157011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency 157111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency 157211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency 157311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency 157410576Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 157510576Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 157610576Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 157710576Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 157810576Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 157910576Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 158010576Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 158110576Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 158210576Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 158310576Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 158410576Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 158510576Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 158611754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 158711606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 7374 # Transaction distribution 158811606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 7374 # Transaction distribution 158911754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 54619 # Transaction distribution 159011754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 54619 # Transaction distribution 159111754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) 159211606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 159310576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 159410576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 159510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 159610892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 159710576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 159811570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 159910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 160011754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) 160111606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 160211606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 160311754Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) 160411754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) 160511606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 160610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 160710576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 160810892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 160910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 161010576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 161111570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 161210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 161311754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) 161411606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 161511606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 161611754Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) 161711754Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) 161810576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 161911754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) 162010576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 162111502SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 162210576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 162311754Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) 162410576Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 162511754Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 162610576Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 162711754Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) 162810576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 162911754Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) 163010576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 163111754Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) 163210576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 163311754Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) 163410576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 163511754Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) 163610576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 163711754Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) 163810576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 163911606Sandreas.sandberg@arm.comsystem.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) 164010576Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 164111754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 164211606Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 164311754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use 164410576Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 164511606Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 164610576Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 164711754Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. 164811754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor 164911754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy 165011754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy 165110576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 165211606Sandreas.sandberg@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 165310576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 165411606Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 165511606Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 165611754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 165711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 165811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 165910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 166010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 166111606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 166211606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 166311606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 166411606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 41731 # number of overall misses 166511754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles 166611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles 166711754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles 166811754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles 166911754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles 167011754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles 167111754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles 167211754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles 167311606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 167411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 167510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 167610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 167711606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 167811606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 167911606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 168011606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 168110576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 168210576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 168310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 168410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 168510576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 168610576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 168710576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 168810576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 168911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency 169011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency 169111754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency 169211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency 169311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency 169411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency 169511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency 169611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency 169711754Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked 169810576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169911754Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 7 # number of cycles access was blocked 170010576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 170111754Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked 170210576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 170311103Snilay@cs.wisc.edusystem.iocache.writebacks::writebacks 41520 # number of writebacks 170411103Snilay@cs.wisc.edusystem.iocache.writebacks::total 41520 # number of writebacks 170511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 170611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 170710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 170810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 170911606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 171011606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 171111606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 171211606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 171311754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles 171411754Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles 171511754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles 171611754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles 171711754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles 171811754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles 171911754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles 172011754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles 172110576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 172210576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 172310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 172410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 172510576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 172610576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 172710576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 172810576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 172911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency 173011754Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency 173111754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency 173211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency 173311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency 173411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency 173511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency 173611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency 173711754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 173811754Sandreas.hansson@arm.comsystem.l2c.tags.replacements 345934 # number of replacements 173911754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use 174011754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. 174111754Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. 174211754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. 174311754Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. 174411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor 174511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor 174611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor 174711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor 174811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor 174911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy 175011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy 175111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy 175211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy 175311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy 175411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy 175511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 175611754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 175711754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id 175811754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id 175911754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id 176011754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id 176111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 176211754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 38356372 # Number of tag accesses 176311754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 38356372 # Number of data accesses 176411754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 176511754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits 176611754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits 176711754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits 176811754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits 176911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits 177011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits 177111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits 177211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits 177311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits 177411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits 177511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits 177611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits 177711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits 177811754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits 177911754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits 178011754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits 178111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits 178211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits 178311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits 178411754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits 178511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits 178611754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits 178711754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits 178811754Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2117738 # number of demand (read+write) hits 178911754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 879457 # number of overall hits 179011754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 867710 # number of overall hits 179111754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 255503 # number of overall hits 179211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 115068 # number of overall hits 179311754Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2117738 # number of overall hits 179411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses 179511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses 179611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses 179711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 179811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 179911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses 180011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses 180111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses 180211754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses 180311754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses 180411754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses 180511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses 180611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses 180711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses 180811754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses 180911754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses 181011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses 181111754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses 181211754Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 411506 # number of demand (read+write) misses 181311754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 13403 # number of overall misses 181411754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 382165 # number of overall misses 181511754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1908 # number of overall misses 181611754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 14030 # number of overall misses 181711754Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 411506 # number of overall misses 181811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles 181911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles 182011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles 182111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles 182211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles 182311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles 182411754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles 182511754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles 182611754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles 182711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles 182811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles 182911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles 183011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles 183111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles 183211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles 183311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles 183411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles 183511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles 183611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles 183711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles 183811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles 183911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles 184011754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) 184111754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) 184211754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) 184311754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) 184411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) 184511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) 184611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) 184711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) 184811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) 184911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) 185011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) 185111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) 185211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) 185311754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) 185411754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) 185511754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) 185611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) 185711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) 185811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) 185911754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses 186011754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses 186111754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses 186211754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses 186311754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses 186411754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses 186511754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses 186611754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses 186711754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses 186811754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses 186911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses 187011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses 187111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses 187211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses 187311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses 187411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses 187511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses 187611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses 187711754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses 187811754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses 187911754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses 188011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses 188111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses 188211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses 188311754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.015011 # 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number of SCUpgradeReq MSHR miss cycles 197111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles 197211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles 197311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles 197411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles 197511754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles 197611754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles 197711754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles 197811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles 197911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles 198011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles 198111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles 198211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles 198311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles 198411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles 198511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles 198611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles 198711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles 198811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles 198911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles 199011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles 199111754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles 199211754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles 199311754Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles 199411754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles 199511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles 199611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles 199710892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 199810892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 199911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses 200011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses 200111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses 200211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # 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mshr miss rate for ReadSharedReq accesses 201111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses 201211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses 201311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses 201411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses 201511754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses 201611754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses 201711754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses 201811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses 201911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses 202011754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses 202111754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses 202211754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses 202311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency 202411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency 202511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency 202611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency 202711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency 202811754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency 202911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency 203011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency 203111754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency 203211754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency 203311754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency 203411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency 203511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency 203611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency 203711754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency 203811754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency 203911754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency 204011754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency 204111754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency 204211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency 204311754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency 204411754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency 204511754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency 204611754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency 204711754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency 204811754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency 204911754Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency 205011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency 205111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency 205211754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency 205311754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. 205411754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. 205511754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 205611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 205711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 205811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 205911754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 206011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 7195 # Transaction distribution 206111754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 297263 # Transaction distribution 206211754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 13067 # Transaction distribution 206311754Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 13067 # Transaction distribution 206411754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 123600 # Transaction distribution 206511754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 263134 # Transaction distribution 206611754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 6631 # Transaction distribution 206711754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution 206811336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 206911754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 121851 # Transaction distribution 207011754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 121443 # Transaction distribution 207111754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution 207211754Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 45 # Transaction distribution 207310892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 207411754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 134 # Transaction distribution 207511754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) 207611754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) 207711754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) 207811754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) 207911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) 208011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) 208111754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) 208211754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) 208311754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) 208411754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) 208511103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 208611103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 208711754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) 208811754Sandreas.hansson@arm.comsystem.membus.snoops 12662 # Total snoops (count) 208911680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 28800 # Total snoop traffic (bytes) 209011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 485569 # Request fanout histogram 209111754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.001425 # Request fanout histogram 209211754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram 209310576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 209411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram 209511754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram 209610576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 209710576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 209811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 209910576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 210011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 485569 # Request fanout histogram 210111754Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) 210210576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 210311754Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) 210410576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 210511754Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) 210610576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 210711754Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) 210810726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 210911754Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) 211010576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 211111754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 211211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. 211311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. 211411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 211511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. 211611754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 211711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 211811754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 211911606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution 212011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution 212111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution 212211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution 212311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution 212411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution 212511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution 212611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution 212711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution 212811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution 212911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution 213011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution 213111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution 213211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution 213311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution 213411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution 213511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 213611754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) 213711754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) 213811754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) 213911754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) 214011754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) 214111754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) 214211754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) 214311754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) 214411754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) 214511754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) 214611754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 382331 # Total snoops (count) 214711754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) 214811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram 214911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram 215011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram 215110576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 215211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram 215311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram 215411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram 215511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram 215611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 215710576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 215811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 215911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 216011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram 216111754Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) 216210892Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 216311754Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) 216410576Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 216511754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) 216611103Snilay@cs.wisc.edusystem.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 216711754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) 216810726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 216911754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) 217010628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 217111754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) 217210576Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 217311754Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 217411754Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 217511754Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 217611754Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 217710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 217810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 217910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 218010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 218110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 218210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 218310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 218410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 218510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 218610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 218710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 218810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 218910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 219010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 219110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 219210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 219310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 219410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 219510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 219610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 219710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 219810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 219910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 220010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 220110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 220210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 220310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 220410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 220510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 220610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 220710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 220811754Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 220911754Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221011754Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221111754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221211754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221311754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221411754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221511754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221611754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221711754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221811754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 221911754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222011754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222111754Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222211754Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222311754Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222411754Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222511754Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222611754Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222711754Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222811754Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 222911754Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 223011754Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 22318464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 223211754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed 223311754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed 223411754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl 223511680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl 223611754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl 223711754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl 223811754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl 223911754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl 224011754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl 224111680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl 224211754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl 224311754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl 224411754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl 224511680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl 224611754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl 224711754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl 224811754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl 224911754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl 225011754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl 225111754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl 225211754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl 22538464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 22548464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 22558464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 225611754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl 225711754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl 22588464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 225911754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed 226011680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed 226111680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 226211680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 226311754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed 226411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed 226511754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed 226611754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed 226711754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed 226811680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed 226911680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed 227011754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed 227111680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed 227211754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed 227311680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed 227411606Sandreas.sandberg@arm.comsystem.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 227511754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 163481 # number of callpals executed 227611754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches 227711680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_switch::user 1070 # number of protection mode switches 22788464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 227911680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_good::kernel 1070 228011680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_good::user 1070 22818464SN/Asystem.cpu0.kern.mode_good::idle 0 228211754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches 22838464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 22848983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 228511754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches 228611754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode 228711754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode 22888464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 228911754Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3352 # number of times the context was actually changed 22908464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 229111754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed 229211754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed 229311754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl 229411754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl 229511754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl 229611754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl 229711754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl 229811754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl 229911754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl 230011754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl 230111754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl 230211754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl 230311754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl 230411754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl 230511754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl 230611754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl 230711754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl 230811754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl 23098464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 23108464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 231111754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl 231211754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl 23138464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 231411754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed 231511606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 231611606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 231711754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed 231811680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed 231911680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 232011754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed 232111754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed 232211754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed 232311754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed 232411754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed 232511680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed 232611754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed 232711680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed 232811606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed 23298464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 233011754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 54607 # number of callpals executed 233111754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches 233211754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 670 # number of protection mode switches 233311754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches 233411754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 890 233511754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 670 233611754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 220 233711754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches 23388464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 233911754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches 234011754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches 234111754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode 234211754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode 234311754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode 234411754Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 1231 # number of times the context was actually changed 23455703SN/A 23465703SN/A---------- End Simulation Statistics ---------- 2347