stats.txt revision 11754
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.909484 # Number of seconds simulated 4sim_ticks 1909483951500 # Number of ticks simulated 5final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 164890 # Simulator instruction rate (inst/s) 8host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5556117262 # Simulator tick rate (ticks/s) 10host_mem_usage 341236 # Number of bytes of host memory used 11host_seconds 343.67 # Real time elapsed on the host 12sim_insts 56668174 # Number of instructions simulated 13sim_ops 56668174 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 411061 # Number of read requests accepted 55system.physmem.writeReqs 123600 # Number of write requests accepted 56system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 26241 # Per bank write bursts 67system.physmem.perBankRdBursts::1 25988 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25972 # Per bank write bursts 69system.physmem.perBankRdBursts::3 25684 # Per bank write bursts 70system.physmem.perBankRdBursts::4 25579 # Per bank write bursts 71system.physmem.perBankRdBursts::5 25567 # Per bank write bursts 72system.physmem.perBankRdBursts::6 25634 # Per bank write bursts 73system.physmem.perBankRdBursts::7 25346 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25590 # Per bank write bursts 75system.physmem.perBankRdBursts::9 25694 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25928 # Per bank write bursts 77system.physmem.perBankRdBursts::11 25514 # Per bank write bursts 78system.physmem.perBankRdBursts::12 26076 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25422 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25093 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25620 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8582 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8090 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7941 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7423 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7276 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7412 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7548 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7160 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7532 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7637 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7817 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7733 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8265 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7849 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7512 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7803 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 80 # Number of times write queue was full causing retry 100system.physmem.totGap 1909479571500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 411061 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 123600 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads 265system.physmem.totQLat 8180795500 # Total ticks spent queuing 266system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.14 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 281system.physmem.readRowHits 370615 # Number of row buffer hits during reads 282system.physmem.writeRowHits 99546 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes 285system.physmem.avgGap 3571383.68 # Average gap between requests 286system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) 294system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) 295system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) 296system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) 297system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) 298system.physmem_0.averagePower 247.578716 # Core power per rank (mW) 299system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank 300system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states 301system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states 302system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states 303system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states 304system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states 305system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states 306system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) 313system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) 314system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) 315system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) 316system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) 317system.physmem_1.averagePower 247.436414 # Core power per rank (mW) 318system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank 319system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states 320system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states 321system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states 322system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states 323system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states 324system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states 325system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 326system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 327system.cpu0.branchPred.lookups 16749334 # Number of BP lookups 328system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted 329system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect 330system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups 331system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits 332system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 333system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage 334system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. 335system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. 336system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. 337system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. 338system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. 339system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. 340system.cpu_clk_domain.clock 500 # Clock period in ticks 341system.cpu0.dtb.fetch_hits 0 # ITB hits 342system.cpu0.dtb.fetch_misses 0 # ITB misses 343system.cpu0.dtb.fetch_acv 0 # ITB acv 344system.cpu0.dtb.fetch_accesses 0 # ITB accesses 345system.cpu0.dtb.read_hits 9423503 # DTB read hits 346system.cpu0.dtb.read_misses 34044 # DTB read misses 347system.cpu0.dtb.read_acv 602 # DTB read access violations 348system.cpu0.dtb.read_accesses 567323 # DTB read accesses 349system.cpu0.dtb.write_hits 5707426 # DTB write hits 350system.cpu0.dtb.write_misses 8375 # DTB write misses 351system.cpu0.dtb.write_acv 432 # DTB write access violations 352system.cpu0.dtb.write_accesses 185068 # DTB write accesses 353system.cpu0.dtb.data_hits 15130929 # DTB hits 354system.cpu0.dtb.data_misses 42419 # DTB misses 355system.cpu0.dtb.data_acv 1034 # DTB access violations 356system.cpu0.dtb.data_accesses 752391 # DTB accesses 357system.cpu0.itb.fetch_hits 1309826 # ITB hits 358system.cpu0.itb.fetch_misses 6979 # ITB misses 359system.cpu0.itb.fetch_acv 608 # ITB acv 360system.cpu0.itb.fetch_accesses 1316805 # ITB accesses 361system.cpu0.itb.read_hits 0 # DTB read hits 362system.cpu0.itb.read_misses 0 # DTB read misses 363system.cpu0.itb.read_acv 0 # DTB read access violations 364system.cpu0.itb.read_accesses 0 # DTB read accesses 365system.cpu0.itb.write_hits 0 # DTB write hits 366system.cpu0.itb.write_misses 0 # DTB write misses 367system.cpu0.itb.write_acv 0 # DTB write access violations 368system.cpu0.itb.write_accesses 0 # DTB write accesses 369system.cpu0.itb.data_hits 0 # DTB hits 370system.cpu0.itb.data_misses 0 # DTB misses 371system.cpu0.itb.data_acv 0 # DTB access violations 372system.cpu0.itb.data_accesses 0 # DTB accesses 373system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions 374system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state 375system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state 376system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state 377system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 378system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state 379system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 380system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 381system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state 382system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states 383system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states 384system.cpu0.numCycles 119453997 # number of cpu cycles simulated 385system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss 388system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed 389system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered 390system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken 391system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing 393system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb 394system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 395system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps 396system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions 397system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR 398system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched 399system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed 400system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) 401system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) 402system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) 403system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 404system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) 405system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) 406system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) 407system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) 408system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) 409system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) 410system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) 411system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) 412system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) 413system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 414system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 415system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 416system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) 417system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle 418system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle 419system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle 420system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked 421system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running 422system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking 423system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing 424system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch 425system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction 426system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode 427system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode 428system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing 429system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle 430system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking 431system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst 432system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running 433system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking 434system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename 435system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full 436system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full 437system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full 438system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full 439system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed 440system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made 441system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups 442system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups 443system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed 444system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing 445system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed 446system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed 447system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer 448system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. 449system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. 450system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. 451system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. 452system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) 453system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ 454system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued 455system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued 456system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling 457system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph 458system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed 459system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle 460system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle 461system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle 462system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 463system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle 464system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle 465system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle 466system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle 467system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle 468system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle 469system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle 470system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle 471system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle 472system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 473system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 474system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 475system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle 476system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 477system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available 478system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available 479system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available 480system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available 481system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available 482system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available 483system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available 484system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available 485system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available 486system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available 487system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available 488system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available 489system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available 490system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available 491system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available 492system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available 493system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available 494system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available 495system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available 496system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available 497system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available 498system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available 499system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available 500system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available 501system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available 502system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available 503system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available 504system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available 505system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available 506system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available 507system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available 508system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available 509system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available 510system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available 511system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available 512system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 513system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 514system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued 515system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued 516system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued 517system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued 518system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued 519system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued 520system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued 521system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued 522system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued 523system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued 524system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued 525system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued 526system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued 527system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued 528system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued 529system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued 530system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued 531system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued 532system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued 533system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued 534system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued 535system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued 536system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued 537system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued 538system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued 539system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued 540system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued 541system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued 542system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued 543system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued 544system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued 545system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued 546system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued 547system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued 548system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued 549system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued 550system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued 551system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 552system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued 553system.cpu0.iq.rate 0.440485 # Inst issue rate 554system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested 555system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) 556system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads 557system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes 558system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses 559system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads 560system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes 561system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses 562system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses 563system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses 564system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores 565system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 566system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed 567system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed 568system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations 569system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed 570system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 571system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 572system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled 573system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked 574system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 575system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing 576system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking 577system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking 578system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ 579system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch 580system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions 581system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions 582system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions 583system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall 584system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall 585system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations 586system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly 587system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly 588system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute 589system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions 590system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed 591system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute 592system.cpu0.iew.exec_swp 0 # number of swp insts executed 593system.cpu0.iew.exec_nop 3535809 # number of nop insts executed 594system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed 595system.cpu0.iew.exec_branches 8258108 # Number of branches executed 596system.cpu0.iew.exec_stores 5732729 # Number of stores executed 597system.cpu0.iew.exec_rate 0.434781 # Inst execution rate 598system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit 599system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back 600system.cpu0.iew.wb_producers 26231692 # num instructions producing a value 601system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value 602system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle 603system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back 604system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit 605system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards 606system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted 607system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle 608system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle 609system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle 610system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 611system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle 612system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle 613system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle 614system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle 615system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle 616system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle 617system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle 618system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle 619system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle 620system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 621system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 622system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 623system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle 624system.cpu0.commit.committedInsts 49593272 # Number of instructions committed 625system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed 626system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 627system.cpu0.commit.refs 13266986 # Number of memory references committed 628system.cpu0.commit.loads 7864361 # Number of loads committed 629system.cpu0.commit.membars 192313 # Number of memory barriers committed 630system.cpu0.commit.branches 7507748 # Number of branches committed 631system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. 632system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. 633system.cpu0.commit.function_calls 632222 # Number of function calls committed. 634system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction 635system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction 636system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction 637system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction 638system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction 639system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction 640system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction 641system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction 642system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction 643system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction 644system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction 645system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction 646system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction 647system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction 648system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction 649system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction 650system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction 651system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction 652system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction 653system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction 654system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction 655system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction 656system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction 657system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction 658system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction 659system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction 660system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction 661system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction 662system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction 663system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction 664system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction 665system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction 666system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction 667system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction 668system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction 669system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction 670system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction 671system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 672system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction 673system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached 674system.cpu0.rob.rob_reads 169631516 # The number of ROB reads 675system.cpu0.rob.rob_writes 120597460 # The number of ROB writes 676system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself 677system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling 678system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 679system.cpu0.committedInsts 46709842 # Number of Instructions Simulated 680system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated 681system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction 682system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads 683system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle 684system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads 685system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads 686system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes 687system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads 688system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes 689system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads 690system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes 691system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 692system.cpu0.dcache.tags.replacements 1252644 # number of replacements 693system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use 694system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. 695system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. 696system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. 697system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. 698system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor 699system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy 700system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy 701system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 702system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 703system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 704system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id 705system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses 706system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses 707system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 708system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits 709system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits 710system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits 711system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits 712system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits 713system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits 714system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits 715system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits 716system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits 717system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits 718system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits 719system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits 720system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses 721system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses 722system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses 723system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses 724system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses 725system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses 726system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses 727system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses 728system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses 729system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses 730system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses 731system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses 732system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles 733system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles 734system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles 735system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles 736system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles 737system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles 738system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles 739system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles 740system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles 741system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles 742system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles 743system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles 744system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) 745system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) 746system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) 747system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) 748system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) 749system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) 750system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) 751system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) 752system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses 753system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses 754system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses 755system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses 756system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses 757system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses 758system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses 759system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses 760system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses 761system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses 762system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses 763system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses 764system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses 765system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses 766system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses 767system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses 768system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency 769system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency 770system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency 771system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency 772system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency 773system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency 774system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency 775system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency 776system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency 777system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency 778system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency 779system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency 780system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked 781system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked 782system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked 783system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked 784system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked 785system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked 786system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks 787system.cpu0.dcache.writebacks::total 737573 # number of writebacks 788system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits 789system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits 790system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits 791system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits 792system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits 793system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits 794system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits 795system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits 796system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits 797system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits 798system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses 799system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses 800system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses 801system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses 802system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses 803system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses 804system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses 805system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses 806system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses 807system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses 808system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses 809system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses 810system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 811system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable 812system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable 813system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable 814system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses 815system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses 816system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles 817system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles 818system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles 819system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles 820system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles 821system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles 822system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles 823system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles 824system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles 825system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles 826system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles 827system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles 828system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles 830system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles 831system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles 832system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses 833system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses 834system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses 835system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses 836system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses 837system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses 838system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses 839system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses 840system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses 841system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses 842system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses 843system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses 844system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency 845system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency 846system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency 847system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency 848system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency 849system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency 850system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency 851system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency 852system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency 853system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency 854system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency 855system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency 856system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency 857system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency 858system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency 859system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency 860system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 861system.cpu0.icache.tags.replacements 892272 # number of replacements 862system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use 863system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. 864system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. 865system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. 866system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. 867system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor 868system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy 869system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy 870system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 871system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id 872system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 873system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 874system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses 875system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses 876system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 877system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits 878system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits 879system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits 880system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits 881system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits 882system.cpu0.icache.overall_hits::total 7503325 # number of overall hits 883system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses 884system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses 885system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses 886system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses 887system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses 888system.cpu0.icache.overall_misses::total 945376 # number of overall misses 889system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles 890system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles 891system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles 892system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles 893system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles 894system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles 895system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) 896system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) 897system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses 898system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses 899system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses 900system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses 901system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses 902system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses 903system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses 904system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses 905system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses 906system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses 907system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency 908system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency 909system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency 910system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency 911system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency 912system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency 913system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked 914system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 915system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked 916system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 917system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked 918system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 919system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks 920system.cpu0.icache.writebacks::total 892272 # number of writebacks 921system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits 922system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits 923system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits 924system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits 925system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits 926system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits 927system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses 928system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses 929system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses 930system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses 931system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses 932system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses 933system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles 934system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles 935system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles 936system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles 937system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles 938system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles 939system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses 940system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses 941system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses 942system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses 943system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses 944system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses 945system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency 946system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency 947system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency 948system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency 949system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency 950system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency 951system.cpu1.branchPred.lookups 4441555 # Number of BP lookups 952system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted 953system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect 954system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups 955system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits 956system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 957system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage 958system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. 959system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. 960system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. 961system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. 962system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. 963system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. 964system.cpu1.dtb.fetch_hits 0 # ITB hits 965system.cpu1.dtb.fetch_misses 0 # ITB misses 966system.cpu1.dtb.fetch_acv 0 # ITB acv 967system.cpu1.dtb.fetch_accesses 0 # ITB accesses 968system.cpu1.dtb.read_hits 2431988 # DTB read hits 969system.cpu1.dtb.read_misses 15687 # DTB read misses 970system.cpu1.dtb.read_acv 78 # DTB read access violations 971system.cpu1.dtb.read_accesses 432427 # DTB read accesses 972system.cpu1.dtb.write_hits 1439876 # DTB write hits 973system.cpu1.dtb.write_misses 3853 # DTB write misses 974system.cpu1.dtb.write_acv 69 # DTB write access violations 975system.cpu1.dtb.write_accesses 163205 # DTB write accesses 976system.cpu1.dtb.data_hits 3871864 # DTB hits 977system.cpu1.dtb.data_misses 19540 # DTB misses 978system.cpu1.dtb.data_acv 147 # DTB access violations 979system.cpu1.dtb.data_accesses 595632 # DTB accesses 980system.cpu1.itb.fetch_hits 677957 # ITB hits 981system.cpu1.itb.fetch_misses 3440 # ITB misses 982system.cpu1.itb.fetch_acv 149 # ITB acv 983system.cpu1.itb.fetch_accesses 681397 # ITB accesses 984system.cpu1.itb.read_hits 0 # DTB read hits 985system.cpu1.itb.read_misses 0 # DTB read misses 986system.cpu1.itb.read_acv 0 # DTB read access violations 987system.cpu1.itb.read_accesses 0 # DTB read accesses 988system.cpu1.itb.write_hits 0 # DTB write hits 989system.cpu1.itb.write_misses 0 # DTB write misses 990system.cpu1.itb.write_acv 0 # DTB write access violations 991system.cpu1.itb.write_accesses 0 # DTB write accesses 992system.cpu1.itb.data_hits 0 # DTB hits 993system.cpu1.itb.data_misses 0 # DTB misses 994system.cpu1.itb.data_acv 0 # DTB access violations 995system.cpu1.itb.data_accesses 0 # DTB accesses 996system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions 997system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state 998system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state 999system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state 1000system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state 1001system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state 1002system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state 1003system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state 1004system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states 1005system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states 1006system.cpu1.numCycles 17559475 # number of cpu cycles simulated 1007system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1008system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1009system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss 1010system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed 1011system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered 1012system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken 1013system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked 1014system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing 1015system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1016system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps 1017system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions 1018system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR 1019system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched 1020system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed 1021system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) 1022system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) 1023system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) 1024system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1025system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) 1026system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) 1027system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) 1028system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) 1029system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) 1030system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) 1031system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) 1032system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) 1033system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) 1034system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1035system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1036system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1037system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) 1038system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle 1039system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle 1040system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle 1041system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked 1042system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running 1043system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking 1044system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing 1045system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch 1046system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction 1047system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode 1048system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode 1049system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing 1050system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle 1051system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking 1052system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst 1053system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running 1054system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking 1055system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename 1056system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full 1057system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full 1058system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full 1059system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full 1060system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed 1061system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made 1062system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups 1063system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups 1064system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed 1065system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing 1066system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed 1067system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed 1068system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer 1069system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. 1070system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. 1071system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. 1072system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. 1073system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) 1074system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ 1075system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued 1076system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued 1077system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling 1078system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph 1079system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed 1080system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle 1081system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle 1082system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle 1083system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1084system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle 1085system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle 1086system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle 1087system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle 1088system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle 1089system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle 1090system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle 1091system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle 1092system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle 1093system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1094system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1095system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1096system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle 1097system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1098system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available 1099system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available 1100system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available 1101system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available 1102system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available 1103system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available 1104system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available 1105system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available 1106system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available 1107system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available 1108system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available 1109system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available 1110system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available 1111system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available 1112system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available 1113system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available 1114system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available 1115system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available 1116system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available 1117system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available 1118system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available 1119system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available 1120system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available 1121system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available 1122system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available 1123system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available 1124system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available 1125system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available 1126system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available 1127system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available 1128system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available 1129system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available 1130system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available 1131system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available 1132system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available 1133system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1134system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1135system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued 1136system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued 1137system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued 1138system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 1139system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued 1140system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued 1141system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued 1142system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued 1143system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued 1144system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued 1145system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued 1146system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued 1147system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued 1148system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued 1149system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued 1150system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued 1151system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued 1152system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued 1153system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued 1154system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued 1155system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued 1156system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued 1157system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued 1158system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued 1159system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued 1160system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued 1161system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued 1162system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued 1163system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued 1164system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued 1165system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued 1166system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued 1167system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued 1168system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued 1169system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued 1170system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued 1171system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued 1172system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1173system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued 1174system.cpu1.iq.rate 0.653242 # Inst issue rate 1175system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested 1176system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) 1177system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads 1178system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes 1179system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses 1180system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads 1181system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes 1182system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses 1183system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses 1184system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses 1185system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores 1186system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1187system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed 1188system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed 1189system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations 1190system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed 1191system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1192system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1193system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled 1194system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked 1195system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1196system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing 1197system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking 1198system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking 1199system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ 1200system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch 1201system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions 1202system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions 1203system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions 1204system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall 1205system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall 1206system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations 1207system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly 1208system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly 1209system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute 1210system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions 1211system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed 1212system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute 1213system.cpu1.iew.exec_swp 0 # number of swp insts executed 1214system.cpu1.iew.exec_nop 650640 # number of nop insts executed 1215system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed 1216system.cpu1.iew.exec_branches 1689156 # Number of branches executed 1217system.cpu1.iew.exec_stores 1450305 # Number of stores executed 1218system.cpu1.iew.exec_rate 0.642403 # Inst execution rate 1219system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit 1220system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back 1221system.cpu1.iew.wb_producers 5286560 # num instructions producing a value 1222system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value 1223system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle 1224system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back 1225system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit 1226system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards 1227system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted 1228system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle 1229system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle 1230system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle 1231system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1232system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle 1233system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle 1234system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle 1235system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle 1236system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle 1237system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle 1238system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle 1239system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle 1240system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle 1241system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1242system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1243system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1244system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle 1245system.cpu1.commit.committedInsts 10444029 # Number of instructions committed 1246system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed 1247system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1248system.cpu1.commit.refs 3355674 # Number of memory references committed 1249system.cpu1.commit.loads 1990378 # Number of loads committed 1250system.cpu1.commit.membars 48933 # Number of memory barriers committed 1251system.cpu1.commit.branches 1499197 # Number of branches committed 1252system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. 1253system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. 1254system.cpu1.commit.function_calls 163891 # Number of function calls committed. 1255system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction 1256system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction 1257system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction 1258system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction 1259system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction 1260system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction 1261system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction 1262system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction 1263system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction 1264system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction 1265system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction 1266system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction 1267system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction 1268system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction 1269system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction 1270system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction 1271system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction 1272system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction 1273system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction 1274system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction 1275system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction 1276system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction 1277system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction 1278system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction 1279system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction 1280system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction 1281system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction 1282system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction 1283system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction 1284system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction 1285system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction 1286system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction 1287system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction 1288system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction 1289system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction 1290system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction 1291system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction 1292system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1293system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction 1294system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached 1295system.cpu1.rob.rob_reads 28763808 # The number of ROB reads 1296system.cpu1.rob.rob_writes 26546353 # The number of ROB writes 1297system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself 1298system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling 1299system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1300system.cpu1.committedInsts 9958332 # Number of Instructions Simulated 1301system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated 1302system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction 1303system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads 1304system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle 1305system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads 1306system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads 1307system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes 1308system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads 1309system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes 1310system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads 1311system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes 1312system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1313system.cpu1.dcache.tags.replacements 131073 # number of replacements 1314system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use 1315system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. 1316system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. 1317system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. 1318system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. 1319system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor 1320system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy 1321system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy 1322system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1323system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id 1324system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 1325system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 1326system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1327system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses 1328system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses 1329system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1330system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits 1331system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits 1332system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits 1333system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits 1334system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits 1335system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits 1336system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits 1337system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits 1338system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits 1339system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits 1340system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits 1341system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits 1342system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses 1343system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses 1344system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses 1345system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses 1346system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses 1347system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses 1348system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses 1349system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses 1350system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses 1351system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses 1352system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses 1353system.cpu1.dcache.overall_misses::total 533406 # number of overall misses 1354system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles 1355system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles 1356system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles 1357system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles 1358system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles 1359system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles 1360system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles 1361system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles 1362system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles 1363system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles 1364system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles 1365system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles 1366system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) 1367system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) 1368system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) 1369system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) 1370system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) 1371system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) 1372system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) 1373system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) 1374system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses 1375system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses 1376system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses 1377system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses 1378system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses 1379system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses 1380system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses 1381system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses 1382system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses 1383system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses 1384system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses 1385system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses 1386system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses 1387system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses 1388system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses 1389system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses 1390system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency 1391system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency 1392system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency 1393system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency 1394system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency 1395system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency 1396system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency 1397system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency 1398system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency 1399system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency 1400system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency 1401system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency 1402system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked 1403system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked 1404system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked 1405system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked 1406system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked 1407system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked 1408system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks 1409system.cpu1.dcache.writebacks::total 84598 # number of writebacks 1410system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits 1411system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits 1412system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits 1413system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits 1414system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits 1415system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits 1416system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits 1417system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits 1418system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits 1419system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits 1420system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses 1421system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses 1422system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses 1423system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses 1424system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses 1425system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses 1426system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses 1427system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses 1428system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses 1429system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses 1430system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses 1431system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses 1432system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 1433system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable 1434system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable 1435system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable 1436system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses 1437system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses 1438system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles 1439system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles 1440system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles 1441system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles 1442system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles 1443system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles 1444system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles 1445system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles 1446system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles 1447system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles 1448system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles 1449system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles 1450system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles 1451system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles 1452system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles 1453system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles 1454system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses 1455system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses 1456system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses 1457system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses 1458system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses 1459system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses 1460system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses 1461system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses 1462system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses 1463system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses 1464system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses 1465system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses 1466system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency 1467system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency 1468system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency 1469system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency 1470system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency 1471system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency 1472system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency 1473system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency 1474system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency 1475system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency 1476system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency 1477system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency 1478system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency 1479system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency 1480system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency 1481system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency 1482system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1483system.cpu1.icache.tags.replacements 256867 # number of replacements 1484system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use 1485system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. 1486system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. 1487system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. 1488system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. 1489system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor 1490system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy 1491system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy 1492system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1493system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1494system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 1495system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id 1496system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1497system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses 1498system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses 1499system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1500system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits 1501system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits 1502system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits 1503system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits 1504system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits 1505system.cpu1.icache.overall_hits::total 1711658 # number of overall hits 1506system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses 1507system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses 1508system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses 1509system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses 1510system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses 1511system.cpu1.icache.overall_misses::total 269479 # number of overall misses 1512system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles 1513system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles 1514system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles 1515system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles 1516system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles 1517system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles 1518system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) 1519system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) 1520system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses 1521system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses 1522system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses 1523system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses 1524system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses 1525system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses 1526system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses 1527system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses 1528system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses 1529system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses 1530system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency 1531system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency 1532system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency 1533system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency 1534system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency 1535system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency 1536system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked 1537system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1538system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked 1539system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1540system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked 1541system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1542system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks 1543system.cpu1.icache.writebacks::total 256867 # number of writebacks 1544system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits 1545system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits 1546system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits 1547system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits 1548system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits 1549system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits 1550system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses 1551system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses 1552system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses 1553system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses 1554system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses 1555system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses 1556system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles 1557system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles 1558system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles 1559system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles 1560system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles 1561system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles 1562system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses 1563system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses 1564system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses 1565system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses 1566system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses 1567system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses 1568system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency 1569system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency 1570system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency 1571system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency 1572system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency 1573system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency 1574system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1575system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1576system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1577system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1578system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1579system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1580system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1581system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1582system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1583system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1584system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1585system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1586system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1587system.iobus.trans_dist::ReadReq 7374 # Transaction distribution 1588system.iobus.trans_dist::ReadResp 7374 # Transaction distribution 1589system.iobus.trans_dist::WriteReq 54619 # Transaction distribution 1590system.iobus.trans_dist::WriteResp 54619 # Transaction distribution 1591system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) 1592system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 1593system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1594system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1595system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1596system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1597system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1598system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1599system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1600system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) 1601system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 1602system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 1603system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) 1604system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) 1605system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 1606system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1607system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1608system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1609system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1610system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1611system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1612system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1613system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) 1614system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 1615system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 1616system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) 1617system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) 1618system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1619system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) 1620system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1621system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1622system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1623system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) 1624system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1625system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 1626system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1627system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) 1628system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1629system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) 1630system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1631system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) 1632system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1633system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) 1634system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1635system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) 1636system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1637system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) 1638system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1639system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) 1640system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1641system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1642system.iocache.tags.replacements 41699 # number of replacements 1643system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use 1644system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1645system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 1646system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1647system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. 1648system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor 1649system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy 1650system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy 1651system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1652system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1653system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1654system.iocache.tags.tag_accesses 375579 # Number of tag accesses 1655system.iocache.tags.data_accesses 375579 # Number of data accesses 1656system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1657system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 1658system.iocache.ReadReq_misses::total 179 # number of ReadReq misses 1659system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1660system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1661system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 1662system.iocache.demand_misses::total 41731 # number of demand (read+write) misses 1663system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 1664system.iocache.overall_misses::total 41731 # number of overall misses 1665system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles 1666system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles 1667system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles 1668system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles 1669system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles 1670system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles 1671system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles 1672system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles 1673system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 1674system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 1675system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1676system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1677system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 1678system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 1679system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 1680system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 1681system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1682system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1683system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1684system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1685system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1686system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1687system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1688system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1689system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency 1690system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency 1691system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency 1692system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency 1693system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency 1694system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency 1695system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency 1696system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency 1697system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked 1698system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1699system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked 1700system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1701system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked 1702system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1703system.iocache.writebacks::writebacks 41520 # number of writebacks 1704system.iocache.writebacks::total 41520 # number of writebacks 1705system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 1706system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 1707system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1708system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1709system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 1710system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 1711system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 1712system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 1713system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles 1714system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles 1715system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles 1716system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles 1717system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles 1718system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles 1719system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles 1720system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles 1721system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1722system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1723system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1724system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1725system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1726system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1727system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1728system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1729system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency 1730system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency 1731system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency 1732system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency 1733system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency 1734system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency 1735system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency 1736system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency 1737system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1738system.l2c.tags.replacements 345934 # number of replacements 1739system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use 1740system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. 1741system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. 1742system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. 1743system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. 1744system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor 1745system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor 1746system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor 1747system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor 1748system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor 1749system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy 1750system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy 1751system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy 1752system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy 1753system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy 1754system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy 1755system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 1756system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1757system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id 1758system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id 1759system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id 1760system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id 1761system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 1762system.l2c.tags.tag_accesses 38356372 # Number of tag accesses 1763system.l2c.tags.data_accesses 38356372 # Number of data accesses 1764system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 1765system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits 1766system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits 1767system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits 1768system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits 1769system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits 1770system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits 1771system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits 1772system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits 1773system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits 1774system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits 1775system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits 1776system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits 1777system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits 1778system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits 1779system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits 1780system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits 1781system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits 1782system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits 1783system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits 1784system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits 1785system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits 1786system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits 1787system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits 1788system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits 1789system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits 1790system.l2c.overall_hits::cpu0.data 867710 # number of overall hits 1791system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits 1792system.l2c.overall_hits::cpu1.data 115068 # number of overall hits 1793system.l2c.overall_hits::total 2117738 # number of overall hits 1794system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses 1795system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses 1796system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses 1797system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 1798system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 1799system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses 1800system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses 1801system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses 1802system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses 1803system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses 1804system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses 1805system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses 1806system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses 1807system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses 1808system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses 1809system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses 1810system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses 1811system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses 1812system.l2c.demand_misses::total 411506 # number of demand (read+write) misses 1813system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses 1814system.l2c.overall_misses::cpu0.data 382165 # number of overall misses 1815system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses 1816system.l2c.overall_misses::cpu1.data 14030 # number of overall misses 1817system.l2c.overall_misses::total 411506 # number of overall misses 1818system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles 1819system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles 1820system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles 1821system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles 1822system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles 1823system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles 1824system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles 1825system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles 1826system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles 1827system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles 1828system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles 1829system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles 1830system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles 1831system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles 1832system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles 1833system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles 1834system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles 1835system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles 1836system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles 1837system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles 1838system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles 1839system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles 1840system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) 1841system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) 1842system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) 1843system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) 1844system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) 1845system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) 1846system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) 1847system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) 1848system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) 1849system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) 1850system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) 1851system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) 1852system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) 1853system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) 1854system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) 1855system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) 1856system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) 1857system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) 1858system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) 1859system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses 1860system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses 1861system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses 1862system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses 1863system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses 1864system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses 1865system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses 1866system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses 1867system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses 1868system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses 1869system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses 1870system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses 1871system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses 1872system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses 1873system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses 1874system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses 1875system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses 1876system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses 1877system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses 1878system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses 1879system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses 1880system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses 1881system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses 1882system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses 1883system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses 1884system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses 1885system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses 1886system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses 1887system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses 1888system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses 1889system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses 1890system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses 1891system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses 1892system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses 1893system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency 1894system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency 1895system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency 1896system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency 1897system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency 1898system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency 1899system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency 1900system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency 1901system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency 1902system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency 1903system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency 1904system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency 1905system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency 1906system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency 1907system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency 1908system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency 1909system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency 1910system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency 1911system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency 1912system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency 1913system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency 1914system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency 1915system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1916system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1917system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1918system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1919system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1920system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1921system.l2c.writebacks::writebacks 82080 # number of writebacks 1922system.l2c.writebacks::total 82080 # number of writebacks 1923system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 1924system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits 1925system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 1926system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 1927system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 1928system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 1929system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 1930system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 1931system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 1932system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1933system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1934system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses 1935system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses 1936system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses 1937system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses 1938system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1939system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses 1940system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses 1941system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses 1942system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses 1943system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses 1944system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses 1945system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses 1946system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses 1947system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses 1948system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses 1949system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses 1950system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses 1951system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses 1952system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses 1953system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses 1954system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses 1955system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses 1956system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses 1957system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses 1958system.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 1959system.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 1960system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable 1961system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable 1962system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable 1963system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable 1964system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses 1965system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses 1966system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses 1967system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles 1968system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles 1969system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles 1970system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles 1971system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles 1972system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles 1973system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles 1974system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles 1975system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles 1976system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles 1977system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles 1978system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles 1979system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles 1980system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles 1981system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles 1982system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles 1983system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles 1984system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles 1985system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles 1986system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles 1987system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles 1988system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles 1989system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles 1990system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles 1991system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles 1992system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles 1993system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles 1994system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles 1995system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles 1996system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles 1997system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1998system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1999system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses 2000system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses 2001system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses 2002system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses 2003system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses 2004system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses 2005system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses 2006system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses 2007system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses 2008system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses 2009system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses 2010system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses 2011system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses 2012system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses 2013system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses 2014system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses 2015system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses 2016system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses 2017system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses 2018system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses 2019system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses 2020system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses 2021system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses 2022system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses 2023system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency 2024system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency 2025system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency 2026system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency 2027system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency 2028system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency 2029system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency 2030system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency 2031system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency 2032system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency 2033system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency 2034system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency 2035system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency 2036system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency 2037system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency 2038system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency 2039system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency 2040system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency 2041system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency 2042system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency 2043system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency 2044system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency 2045system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency 2046system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency 2047system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency 2048system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency 2049system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency 2050system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency 2051system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency 2052system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency 2053system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. 2054system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2055system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2056system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2057system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2058system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2059system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2060system.membus.trans_dist::ReadReq 7195 # Transaction distribution 2061system.membus.trans_dist::ReadResp 297263 # Transaction distribution 2062system.membus.trans_dist::WriteReq 13067 # Transaction distribution 2063system.membus.trans_dist::WriteResp 13067 # Transaction distribution 2064system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution 2065system.membus.trans_dist::CleanEvict 263134 # Transaction distribution 2066system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution 2067system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution 2068system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 2069system.membus.trans_dist::ReadExReq 121851 # Transaction distribution 2070system.membus.trans_dist::ReadExResp 121443 # Transaction distribution 2071system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution 2072system.membus.trans_dist::BadAddressError 45 # Transaction distribution 2073system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 2074system.membus.trans_dist::InvalidateResp 134 # Transaction distribution 2075system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) 2076system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) 2077system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) 2078system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) 2079system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) 2080system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) 2081system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) 2082system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) 2083system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) 2084system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) 2085system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 2086system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 2087system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) 2088system.membus.snoops 12662 # Total snoops (count) 2089system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) 2090system.membus.snoop_fanout::samples 485569 # Request fanout histogram 2091system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram 2092system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram 2093system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2094system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram 2095system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram 2096system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2097system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2098system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2099system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2100system.membus.snoop_fanout::total 485569 # Request fanout histogram 2101system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) 2102system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2103system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) 2104system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 2105system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) 2106system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2107system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) 2108system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 2109system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) 2110system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2111system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2112system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. 2113system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2114system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2115system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. 2116system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2117system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2118system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2119system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution 2120system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution 2121system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution 2122system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution 2123system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution 2124system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution 2125system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution 2126system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution 2127system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution 2128system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution 2129system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution 2130system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution 2131system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution 2132system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution 2133system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution 2134system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution 2135system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 2136system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) 2137system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) 2138system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) 2139system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) 2140system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) 2141system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) 2142system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) 2143system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) 2144system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) 2145system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) 2146system.toL2Bus.snoops 382331 # Total snoops (count) 2147system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) 2148system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram 2149system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram 2150system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram 2151system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2152system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram 2153system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram 2154system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram 2155system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram 2156system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2157system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2158system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2159system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2160system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram 2161system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) 2162system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 2163system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) 2164system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2165system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) 2166system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2167system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) 2168system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2169system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) 2170system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2171system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) 2172system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2173system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2174system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2175system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2176system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2177system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2178system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2179system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2180system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2181system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2182system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2183system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2184system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2185system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2186system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2187system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2188system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2189system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2190system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2191system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2192system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2193system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2194system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2195system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2196system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2197system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2198system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2199system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2200system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2201system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2202system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2203system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2204system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2205system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2206system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2207system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 2208system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2209system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2210system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2211system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2212system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2213system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2214system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2215system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2216system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2217system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2218system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2219system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2220system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2221system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2222system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2223system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2224system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2225system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2226system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2227system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2228system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2229system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2230system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states 2231system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2232system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed 2233system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed 2234system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl 2235system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl 2236system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl 2237system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl 2238system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl 2239system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl 2240system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl 2241system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl 2242system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl 2243system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl 2244system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl 2245system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl 2246system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl 2247system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl 2248system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl 2249system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl 2250system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl 2251system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl 2252system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl 2253system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2254system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2255system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2256system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl 2257system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl 2258system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2259system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed 2260system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed 2261system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 2262system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 2263system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed 2264system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed 2265system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed 2266system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed 2267system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed 2268system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed 2269system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed 2270system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed 2271system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed 2272system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed 2273system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed 2274system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 2275system.cpu0.kern.callpal::total 163481 # number of callpals executed 2276system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches 2277system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches 2278system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2279system.cpu0.kern.mode_good::kernel 1070 2280system.cpu0.kern.mode_good::user 1070 2281system.cpu0.kern.mode_good::idle 0 2282system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches 2283system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2284system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2285system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches 2286system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode 2287system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode 2288system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2289system.cpu0.kern.swap_context 3352 # number of times the context was actually changed 2290system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2291system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed 2292system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed 2293system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl 2294system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl 2295system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl 2296system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl 2297system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl 2298system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl 2299system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl 2300system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl 2301system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl 2302system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl 2303system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl 2304system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl 2305system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl 2306system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl 2307system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl 2308system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl 2309system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2310system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2311system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl 2312system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl 2313system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2314system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed 2315system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 2316system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 2317system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed 2318system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed 2319system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 2320system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed 2321system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed 2322system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed 2323system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed 2324system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed 2325system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed 2326system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed 2327system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed 2328system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed 2329system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2330system.cpu1.kern.callpal::total 54607 # number of callpals executed 2331system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches 2332system.cpu1.kern.mode_switch::user 670 # number of protection mode switches 2333system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches 2334system.cpu1.kern.mode_good::kernel 890 2335system.cpu1.kern.mode_good::user 670 2336system.cpu1.kern.mode_good::idle 220 2337system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches 2338system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2339system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches 2340system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches 2341system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode 2342system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode 2343system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode 2344system.cpu1.kern.swap_context 1231 # number of times the context was actually changed 2345 2346---------- End Simulation Statistics ---------- 2347