1# Copyright (c) 2013 ARM Limited
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3#
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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38#
39# Authors: Andreas Hansson
40
41from m5.objects import *
42from base_config import *
43
44root = BaseSESystemUniprocessor(mem_mode='timing',
45                                cpu_class=TimingSimpleCPU).create_root()
46