simple-timing-ruby.py revision 10524
12521SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 29814Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 58706Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 68706Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 78706Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 88706Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 98706Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 108706Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 118706Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 128706Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 138706Sandreas.hansson@arm.com# this software without specific prior written permission. 142521SN/A# 152521SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162521SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172521SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182521SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192521SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202521SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212521SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222521SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232521SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242521SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252521SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262521SN/A# 272521SN/A# Authors: Steve Reinhardt 282521SN/A 292521SN/Aimport m5 302521SN/Afrom m5.objects import * 312521SN/Afrom m5.defines import buildEnv 322521SN/Afrom m5.util import addToPath 332521SN/Aimport os, optparse, sys 342521SN/A 352521SN/A# Get paths we might need 362521SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 372521SN/Aconfig_root = os.path.dirname(config_path) 382521SN/AaddToPath(config_root+'/configs/common') 392665SN/AaddToPath(config_root+'/configs/ruby') 402665SN/AaddToPath(config_root+'/configs/topologies') 418706Sandreas.hansson@arm.com 422521SN/Aimport Ruby 432521SN/Aimport Options 442521SN/A 452982SN/Aparser = optparse.OptionParser() 462982SN/AOptions.addCommonOptions(parser) 472521SN/A 482521SN/A# Add the ruby specific and protocol specific options 4911793Sbrandon.potter@amd.comRuby.define_options(parser) 5011793Sbrandon.potter@amd.com 519850Sandreas.hansson@arm.com(options, args) = parser.parse_args() 522521SN/A 538706Sandreas.hansson@arm.com# 544070SN/A# Set the default cache size and associativity to be very small to encourage 559814Sandreas.hansson@arm.com# races between requests and writebacks. 568706Sandreas.hansson@arm.com# 578706Sandreas.hansson@arm.comoptions.l1d_size="256B" 588706Sandreas.hansson@arm.comoptions.l1i_size="256B" 598706Sandreas.hansson@arm.comoptions.l2_size="512B" 609814Sandreas.hansson@arm.comoptions.l3_size="1kB" 619814Sandreas.hansson@arm.comoptions.l1d_assoc=2 628706Sandreas.hansson@arm.comoptions.l1i_assoc=2 638706Sandreas.hansson@arm.comoptions.l2_assoc=2 648706Sandreas.hansson@arm.comoptions.l3_assoc=2 659814Sandreas.hansson@arm.com 669814Sandreas.hansson@arm.com# this is a uniprocessor only test 679814Sandreas.hansson@arm.comoptions.num_cpus = 1 688706Sandreas.hansson@arm.comcpu = TimingSimpleCPU(cpu_id=0) 698706Sandreas.hansson@arm.comsystem = System(cpu = cpu) 708706Sandreas.hansson@arm.com 718706Sandreas.hansson@arm.com# Dummy voltage domain for all our clock domains 728706Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 738706Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 742521SN/A voltage_domain = system.voltage_domain) 752521SN/A 768861Sandreas.hansson@arm.com# Create a seperate clock domain for components that should run at 772521SN/A# CPUs frequency 782521SN/Asystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 792521SN/A voltage_domain = system.voltage_domain) 808706Sandreas.hansson@arm.com 812521SN/Asystem.mem_ranges = AddrRange('256MB') 828706Sandreas.hansson@arm.comRuby.create_system(options, False, system) 838706Sandreas.hansson@arm.com 842521SN/A# Create a separate clock for Ruby 852521SN/Asystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 862521SN/A voltage_domain = system.voltage_domain) 8712532Sandreas.sandberg@arm.com 882521SN/Aassert(len(system.ruby._cpu_ports) == 1) 892521SN/A 902521SN/A# create the interrupt controller 912521SN/Acpu.createInterruptController() 922521SN/A 9310564Sandreas.hansson@arm.com# 942521SN/A# Tie the cpu cache ports to the ruby cpu ports and 952521SN/A# physmem, respectively 962521SN/A# 978706Sandreas.hansson@arm.comcpu.connectAllPorts(system.ruby._cpu_ports[0]) 982521SN/A 998706Sandreas.hansson@arm.com# ----------------------- 1008706Sandreas.hansson@arm.com# run simulation 1012521SN/A# ----------------------- 1022521SN/A 1032521SN/Aroot = Root(full_system = False, system = system) 10412532Sandreas.sandberg@arm.comroot.system.mem_mode = 'timing' 1052521SN/A 1062521SN/A# Not much point in this being higher than the L1 latency 1072521SN/Am5.ticks.setGlobalFrequency('1ns') 1082521SN/A