simple-timing-ruby.py revision 10524
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31from m5.defines import buildEnv 32from m5.util import addToPath 33import os, optparse, sys 34 35# Get paths we might need 36config_path = os.path.dirname(os.path.abspath(__file__)) 37config_root = os.path.dirname(config_path) 38addToPath(config_root+'/configs/common') 39addToPath(config_root+'/configs/ruby') 40addToPath(config_root+'/configs/topologies') 41 42import Ruby 43import Options 44 45parser = optparse.OptionParser() 46Options.addCommonOptions(parser) 47 48# Add the ruby specific and protocol specific options 49Ruby.define_options(parser) 50 51(options, args) = parser.parse_args() 52 53# 54# Set the default cache size and associativity to be very small to encourage 55# races between requests and writebacks. 56# 57options.l1d_size="256B" 58options.l1i_size="256B" 59options.l2_size="512B" 60options.l3_size="1kB" 61options.l1d_assoc=2 62options.l1i_assoc=2 63options.l2_assoc=2 64options.l3_assoc=2 65 66# this is a uniprocessor only test 67options.num_cpus = 1 68cpu = TimingSimpleCPU(cpu_id=0) 69system = System(cpu = cpu) 70 71# Dummy voltage domain for all our clock domains 72system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 73system.clk_domain = SrcClockDomain(clock = '1GHz', 74 voltage_domain = system.voltage_domain) 75 76# Create a seperate clock domain for components that should run at 77# CPUs frequency 78system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 79 voltage_domain = system.voltage_domain) 80 81system.mem_ranges = AddrRange('256MB') 82Ruby.create_system(options, False, system) 83 84# Create a separate clock for Ruby 85system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 86 voltage_domain = system.voltage_domain) 87 88assert(len(system.ruby._cpu_ports) == 1) 89 90# create the interrupt controller 91cpu.createInterruptController() 92 93# 94# Tie the cpu cache ports to the ruby cpu ports and 95# physmem, respectively 96# 97cpu.connectAllPorts(system.ruby._cpu_ports[0]) 98 99# ----------------------- 100# run simulation 101# ----------------------- 102 103root = Root(full_system = False, system = system) 104root.system.mem_mode = 'timing' 105 106# Not much point in this being higher than the L1 latency 107m5.ticks.setGlobalFrequency('1ns') 108