simple-timing-mp-ruby.py revision 13718
17322Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 27322Sgblack@eecs.umich.edu# All rights reserved. 37322Sgblack@eecs.umich.edu# 47322Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57322Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 67322Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 77322Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 87322Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 97322Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 107322Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 117322Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 127322Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 137322Sgblack@eecs.umich.edu# this software without specific prior written permission. 147322Sgblack@eecs.umich.edu# 157322Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167322Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177322Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187322Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197322Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207322Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217322Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227322Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237322Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247322Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257322Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267322Sgblack@eecs.umich.edu# 277322Sgblack@eecs.umich.edu# Authors: Ron Dreslinski 287322Sgblack@eecs.umich.edu 297322Sgblack@eecs.umich.eduimport m5 307322Sgblack@eecs.umich.edufrom m5.objects import * 317322Sgblack@eecs.umich.edufrom m5.defines import buildEnv 327322Sgblack@eecs.umich.edufrom m5.util import addToPath 337322Sgblack@eecs.umich.eduimport os, optparse, sys 347322Sgblack@eecs.umich.edu 357322Sgblack@eecs.umich.edum5.util.addToPath('../configs/') 367322Sgblack@eecs.umich.edu 377322Sgblack@eecs.umich.edufrom common import Options 387322Sgblack@eecs.umich.edufrom ruby import Ruby 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduparser = optparse.OptionParser() 417376Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 427376Sgblack@eecs.umich.edu 437376Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options 447376Sgblack@eecs.umich.eduRuby.define_options(parser) 457376Sgblack@eecs.umich.edu 467376Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 477376Sgblack@eecs.umich.edu 487376Sgblack@eecs.umich.edu# 497376Sgblack@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 507376Sgblack@eecs.umich.edu# races between requests and writebacks. 517376Sgblack@eecs.umich.edu# 527376Sgblack@eecs.umich.eduoptions.l1d_size="256B" 537376Sgblack@eecs.umich.eduoptions.l1i_size="256B" 547376Sgblack@eecs.umich.eduoptions.l2_size="512B" 557376Sgblack@eecs.umich.eduoptions.l3_size="1kB" 567376Sgblack@eecs.umich.eduoptions.l1d_assoc=2 577376Sgblack@eecs.umich.eduoptions.l1i_assoc=2 587376Sgblack@eecs.umich.eduoptions.l2_assoc=2 597376Sgblack@eecs.umich.eduoptions.l3_assoc=2 607376Sgblack@eecs.umich.edu 617376Sgblack@eecs.umich.edunb_cores = 4 627376Sgblack@eecs.umich.educpus = [ TimingSimpleCPU(cpu_id=i) for i in range(nb_cores) ] 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu# overwrite the num_cpus to equal nb_cores 657376Sgblack@eecs.umich.eduoptions.num_cpus = nb_cores 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edu# system simulated 687376Sgblack@eecs.umich.edusystem = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 697376Sgblack@eecs.umich.edu 707376Sgblack@eecs.umich.edu# Create a seperate clock domain for components that should run at 717376Sgblack@eecs.umich.edu# CPUs frequency 727376Sgblack@eecs.umich.edusystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 737376Sgblack@eecs.umich.edu 747376Sgblack@eecs.umich.eduRuby.create_system(options, False, system) 757376Sgblack@eecs.umich.edu 767376Sgblack@eecs.umich.edu# Create a separate clock domain for Ruby 777376Sgblack@eecs.umich.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.eduassert(options.num_cpus == len(system.ruby._cpu_ports)) 807376Sgblack@eecs.umich.edu 817376Sgblack@eecs.umich.edufor (i, cpu) in enumerate(system.cpu): 827376Sgblack@eecs.umich.edu # create the interrupt controller 837376Sgblack@eecs.umich.edu cpu.createInterruptController() 847376Sgblack@eecs.umich.edu 857376Sgblack@eecs.umich.edu # 867376Sgblack@eecs.umich.edu # Tie the cpu ports to the ruby cpu ports 877376Sgblack@eecs.umich.edu # 887376Sgblack@eecs.umich.edu cpu.connectAllPorts(system.ruby._cpu_ports[i]) 897376Sgblack@eecs.umich.edu 907376Sgblack@eecs.umich.edu# ----------------------- 917376Sgblack@eecs.umich.edu# run simulation 927376Sgblack@eecs.umich.edu# ----------------------- 937376Sgblack@eecs.umich.edu 947376Sgblack@eecs.umich.eduroot = Root( full_system=False, system = system ) 957376Sgblack@eecs.umich.eduroot.system.mem_mode = 'timing' 967376Sgblack@eecs.umich.edu