simple-timing-mp-ruby.py revision 13718
113170Sgiacomo.travaglini@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 213170Sgiacomo.travaglini@arm.com# All rights reserved. 313170Sgiacomo.travaglini@arm.com# 413170Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 513170Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 613170Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 713170Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 813170Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 913170Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 1013170Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 1113170Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 1213170Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 1313170Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 1413170Sgiacomo.travaglini@arm.com# 1513170Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1613170Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1713170Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1813170Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1913170Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2013170Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2113170Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2213170Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2313170Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2413170Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2513170Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2613170Sgiacomo.travaglini@arm.com# 2713170Sgiacomo.travaglini@arm.com# Authors: Ron Dreslinski 2813170Sgiacomo.travaglini@arm.com 2913170Sgiacomo.travaglini@arm.comimport m5 3013170Sgiacomo.travaglini@arm.comfrom m5.objects import * 3113170Sgiacomo.travaglini@arm.comfrom m5.defines import buildEnv 3213170Sgiacomo.travaglini@arm.comfrom m5.util import addToPath 3313170Sgiacomo.travaglini@arm.comimport os, optparse, sys 3413170Sgiacomo.travaglini@arm.com 3513170Sgiacomo.travaglini@arm.comm5.util.addToPath('../configs/') 3613170Sgiacomo.travaglini@arm.com 3713170Sgiacomo.travaglini@arm.comfrom common import Options 3813170Sgiacomo.travaglini@arm.comfrom ruby import Ruby 3913170Sgiacomo.travaglini@arm.com 4013170Sgiacomo.travaglini@arm.comparser = optparse.OptionParser() 4113170Sgiacomo.travaglini@arm.comOptions.addCommonOptions(parser) 4213170Sgiacomo.travaglini@arm.com 4313170Sgiacomo.travaglini@arm.com# Add the ruby specific and protocol specific options 4413170Sgiacomo.travaglini@arm.comRuby.define_options(parser) 4513170Sgiacomo.travaglini@arm.com 4613170Sgiacomo.travaglini@arm.com(options, args) = parser.parse_args() 4713170Sgiacomo.travaglini@arm.com 4813170Sgiacomo.travaglini@arm.com# 4913170Sgiacomo.travaglini@arm.com# Set the default cache size and associativity to be very small to encourage 5013170Sgiacomo.travaglini@arm.com# races between requests and writebacks. 5113170Sgiacomo.travaglini@arm.com# 5213170Sgiacomo.travaglini@arm.comoptions.l1d_size="256B" 5313170Sgiacomo.travaglini@arm.comoptions.l1i_size="256B" 5413170Sgiacomo.travaglini@arm.comoptions.l2_size="512B" 5513170Sgiacomo.travaglini@arm.comoptions.l3_size="1kB" 5613170Sgiacomo.travaglini@arm.comoptions.l1d_assoc=2 5713170Sgiacomo.travaglini@arm.comoptions.l1i_assoc=2 5813170Sgiacomo.travaglini@arm.comoptions.l2_assoc=2 5913170Sgiacomo.travaglini@arm.comoptions.l3_assoc=2 6013170Sgiacomo.travaglini@arm.com 6113170Sgiacomo.travaglini@arm.comnb_cores = 4 6213170Sgiacomo.travaglini@arm.comcpus = [ TimingSimpleCPU(cpu_id=i) for i in range(nb_cores) ] 6313170Sgiacomo.travaglini@arm.com 6413170Sgiacomo.travaglini@arm.com# overwrite the num_cpus to equal nb_cores 6513170Sgiacomo.travaglini@arm.comoptions.num_cpus = nb_cores 6613170Sgiacomo.travaglini@arm.com 6713170Sgiacomo.travaglini@arm.com# system simulated 6813170Sgiacomo.travaglini@arm.comsystem = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 6913170Sgiacomo.travaglini@arm.com 7013170Sgiacomo.travaglini@arm.com# Create a seperate clock domain for components that should run at 7113170Sgiacomo.travaglini@arm.com# CPUs frequency 7213170Sgiacomo.travaglini@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 7313170Sgiacomo.travaglini@arm.com 7413170Sgiacomo.travaglini@arm.comRuby.create_system(options, False, system) 7513170Sgiacomo.travaglini@arm.com 7613170Sgiacomo.travaglini@arm.com# Create a separate clock domain for Ruby 7713170Sgiacomo.travaglini@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 7813170Sgiacomo.travaglini@arm.com 7913170Sgiacomo.travaglini@arm.comassert(options.num_cpus == len(system.ruby._cpu_ports)) 8013170Sgiacomo.travaglini@arm.com 8113170Sgiacomo.travaglini@arm.comfor (i, cpu) in enumerate(system.cpu): 8213170Sgiacomo.travaglini@arm.com # create the interrupt controller 8313170Sgiacomo.travaglini@arm.com cpu.createInterruptController() 8413170Sgiacomo.travaglini@arm.com 8513170Sgiacomo.travaglini@arm.com # 8613170Sgiacomo.travaglini@arm.com # Tie the cpu ports to the ruby cpu ports 8713170Sgiacomo.travaglini@arm.com # 8813170Sgiacomo.travaglini@arm.com cpu.connectAllPorts(system.ruby._cpu_ports[i]) 8913170Sgiacomo.travaglini@arm.com 9013170Sgiacomo.travaglini@arm.com# ----------------------- 9113170Sgiacomo.travaglini@arm.com# run simulation 9213170Sgiacomo.travaglini@arm.com# ----------------------- 9313170Sgiacomo.travaglini@arm.com 9413170Sgiacomo.travaglini@arm.comroot = Root( full_system=False, system = system ) 9513170Sgiacomo.travaglini@arm.comroot.system.mem_mode = 'timing' 9613170Sgiacomo.travaglini@arm.com