pc-simple-timing-ruby.py revision 8968:6d11b01e2c53
114184Sgabeblack@google.com# Copyright (c) 2012 Mark D. Hill and David A. Wood 214184Sgabeblack@google.com# All rights reserved. 314184Sgabeblack@google.com# 414184Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 514184Sgabeblack@google.com# modification, are permitted provided that the following conditions are 614184Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 714184Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 814184Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 914184Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 1014184Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 1114184Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 1214184Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 1314184Sgabeblack@google.com# this software without specific prior written permission. 1414184Sgabeblack@google.com# 1514184Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1614184Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1714184Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1814184Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1914184Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2014184Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2114184Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2214184Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2314184Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2414184Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2514184Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2614184Sgabeblack@google.com# 2714184Sgabeblack@google.com# Authors: Nilay Vaish 2814184Sgabeblack@google.com 2914184Sgabeblack@google.comimport m5, os, optparse, sys 3014184Sgabeblack@google.comfrom m5.objects import * 3114184Sgabeblack@google.comm5.util.addToPath('../configs/common') 3214184Sgabeblack@google.comfrom Benchmarks import SysConfig 3314184Sgabeblack@google.comimport FSConfig 3414184Sgabeblack@google.com 3514184Sgabeblack@google.comm5.util.addToPath('../configs/ruby') 3614184Sgabeblack@google.comimport Ruby 3714184Sgabeblack@google.comimport Options 3814184Sgabeblack@google.com 3914184Sgabeblack@google.com# Add the ruby specific and protocol specific options 4014184Sgabeblack@google.comparser = optparse.OptionParser() 4114184Sgabeblack@google.comOptions.addCommonOptions(parser) 4214184Sgabeblack@google.comRuby.define_options(parser) 4314184Sgabeblack@google.com(options, args) = parser.parse_args() 4414184Sgabeblack@google.com 4514184Sgabeblack@google.com# Set the default cache size and associativity to be very small to encourage 4614184Sgabeblack@google.com# races between requests and writebacks. 4714184Sgabeblack@google.comoptions.l1d_size="32kB" 4814184Sgabeblack@google.comoptions.l1i_size="32kB" 4914184Sgabeblack@google.comoptions.l2_size="4MB" 5014184Sgabeblack@google.comoptions.l1d_assoc=2 5114184Sgabeblack@google.comoptions.l1i_assoc=2 52options.l2_assoc=2 53options.num_cpus = 2 54 55#the system 56mdesc = SysConfig(disk = 'linux-x86.img') 57system = FSConfig.makeLinuxX86System('timing', options.num_cpus, 58 mdesc=mdesc, Ruby=True) 59system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 60system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] 61Ruby.create_system(options, system, system.piobus, system._dma_ports) 62 63for (i, cpu) in enumerate(system.cpu): 64 # create the interrupt controller 65 cpu.createInterruptController() 66 # Tie the cpu ports to the correct ruby system ports 67 cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 68 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 69 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 70 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 71 cpu.interrupts.pio = system.piobus.master 72 cpu.interrupts.int_master = system.piobus.slave 73 cpu.interrupts.int_slave = system.piobus.master 74 cpu.clock = '2GHz' 75 76root = Root(full_system = True, system = system) 77m5.ticks.setGlobalFrequency('1THz') 78