pc-simple-timing-ruby.py revision 8968
1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nilay Vaish 28 29import m5, os, optparse, sys 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Benchmarks import SysConfig 33import FSConfig 34 35m5.util.addToPath('../configs/ruby') 36import Ruby 37import Options 38 39# Add the ruby specific and protocol specific options 40parser = optparse.OptionParser() 41Options.addCommonOptions(parser) 42Ruby.define_options(parser) 43(options, args) = parser.parse_args() 44 45# Set the default cache size and associativity to be very small to encourage 46# races between requests and writebacks. 47options.l1d_size="32kB" 48options.l1i_size="32kB" 49options.l2_size="4MB" 50options.l1d_assoc=2 51options.l1i_assoc=2 52options.l2_assoc=2 53options.num_cpus = 2 54 55#the system 56mdesc = SysConfig(disk = 'linux-x86.img') 57system = FSConfig.makeLinuxX86System('timing', options.num_cpus, 58 mdesc=mdesc, Ruby=True) 59system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 60system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] 61Ruby.create_system(options, system, system.piobus, system._dma_ports) 62 63for (i, cpu) in enumerate(system.cpu): 64 # create the interrupt controller 65 cpu.createInterruptController() 66 # Tie the cpu ports to the correct ruby system ports 67 cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 68 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 69 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 70 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 71 cpu.interrupts.pio = system.piobus.master 72 cpu.interrupts.int_master = system.piobus.slave 73 cpu.interrupts.int_slave = system.piobus.master 74 cpu.clock = '2GHz' 75 76root = Root(full_system = True, system = system) 77m5.ticks.setGlobalFrequency('1THz') 78