pc-simple-timing-ruby.py revision 10090:4eec7bdde5b0
111375Sandreas.hansson@arm.com# Copyright (c) 2012 Mark D. Hill and David A. Wood 211375Sandreas.hansson@arm.com# All rights reserved. 311375Sandreas.hansson@arm.com# 411375Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 511375Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 611375Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 711375Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 811375Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 911375Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 1011375Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 1111375Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 1211375Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 1311375Sandreas.hansson@arm.com# this software without specific prior written permission. 1411375Sandreas.hansson@arm.com# 1511375Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611375Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711375Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811375Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911375Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011375Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111375Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211375Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311375Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411375Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511375Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611375Sandreas.hansson@arm.com# 2711375Sandreas.hansson@arm.com# Authors: Nilay Vaish 2811375Sandreas.hansson@arm.com 2911375Sandreas.hansson@arm.comimport m5, os, optparse, sys 3011375Sandreas.hansson@arm.comfrom m5.objects import * 3111375Sandreas.hansson@arm.comm5.util.addToPath('../configs/common') 3211375Sandreas.hansson@arm.comfrom Benchmarks import SysConfig 3311375Sandreas.hansson@arm.comimport FSConfig 3411375Sandreas.hansson@arm.com 3511375Sandreas.hansson@arm.comm5.util.addToPath('../configs/ruby') 3611375Sandreas.hansson@arm.comm5.util.addToPath('../configs/topologies') 3711375Sandreas.hansson@arm.comimport Ruby 3811375Sandreas.hansson@arm.comimport Options 3911375Sandreas.hansson@arm.com 4011375Sandreas.hansson@arm.com# Add the ruby specific and protocol specific options 4111375Sandreas.hansson@arm.comparser = optparse.OptionParser() 4211375Sandreas.hansson@arm.comOptions.addCommonOptions(parser) 4311375Sandreas.hansson@arm.comRuby.define_options(parser) 4411375Sandreas.hansson@arm.com(options, args) = parser.parse_args() 4511375Sandreas.hansson@arm.com 4611375Sandreas.hansson@arm.com# Set the default cache size and associativity to be very small to encourage 4711375Sandreas.hansson@arm.com# races between requests and writebacks. 4811375Sandreas.hansson@arm.comoptions.l1d_size="32kB" 4911375Sandreas.hansson@arm.comoptions.l1i_size="32kB" 5011375Sandreas.hansson@arm.comoptions.l2_size="4MB" 5111375Sandreas.hansson@arm.comoptions.l1d_assoc=2 5212727Snikos.nikoleris@arm.comoptions.l1i_assoc=2 5311375Sandreas.hansson@arm.comoptions.l2_assoc=2 5411375Sandreas.hansson@arm.comoptions.num_cpus = 2 5512724Snikos.nikoleris@arm.com 5611375Sandreas.hansson@arm.com#the system 5711375Sandreas.hansson@arm.commdesc = SysConfig(disk = 'linux-x86.img') 5811375Sandreas.hansson@arm.comsystem = FSConfig.makeLinuxX86System('timing', options.num_cpus, 5911375Sandreas.hansson@arm.com mdesc=mdesc, Ruby=True) 6011375Sandreas.hansson@arm.com# Dummy voltage domain for all our clock domains 6111375Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 6211375Sandreas.hansson@arm.com 6311375Sandreas.hansson@arm.comsystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 6411375Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 6511375Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 6611375Sandreas.hansson@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 6711375Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 6811375Sandreas.hansson@arm.comsystem.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) 6911375Sandreas.hansson@arm.com for i in xrange(options.num_cpus)] 7011375Sandreas.hansson@arm.com 7111375Sandreas.hansson@arm.comRuby.create_system(options, system, system.piobus, system._dma_ports) 7211375Sandreas.hansson@arm.com 7311375Sandreas.hansson@arm.com# Create a seperate clock domain for Ruby 7411375Sandreas.hansson@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 7511375Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 7611375Sandreas.hansson@arm.com 7711375Sandreas.hansson@arm.comfor (i, cpu) in enumerate(system.cpu): 7811375Sandreas.hansson@arm.com # create the interrupt controller 7911375Sandreas.hansson@arm.com cpu.createInterruptController() 8011375Sandreas.hansson@arm.com # Tie the cpu ports to the correct ruby system ports 8111375Sandreas.hansson@arm.com cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 8211375Sandreas.hansson@arm.com cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 8311375Sandreas.hansson@arm.com cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 8411375Sandreas.hansson@arm.com cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 8511375Sandreas.hansson@arm.com cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master 8611375Sandreas.hansson@arm.com cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave 8711375Sandreas.hansson@arm.com cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master 8811375Sandreas.hansson@arm.com 8911375Sandreas.hansson@arm.com # Set access_phys_mem to True for ruby port 9011375Sandreas.hansson@arm.com system.ruby._cpu_ruby_ports[i].access_phys_mem = True 9111375Sandreas.hansson@arm.com 9211375Sandreas.hansson@arm.comsystem.physmem = [DDR3_1600_x64(range = r) 9311375Sandreas.hansson@arm.com for r in system.mem_ranges] 9411375Sandreas.hansson@arm.comfor i in xrange(len(system.physmem)): 9511375Sandreas.hansson@arm.com system.physmem[i].port = system.piobus.master 9611375Sandreas.hansson@arm.com 9711375Sandreas.hansson@arm.comroot = Root(full_system = True, system = system) 9811375Sandreas.hansson@arm.comm5.ticks.setGlobalFrequency('1THz') 9911375Sandreas.hansson@arm.com