pc-simple-timing-ruby.py revision 9577
18968Snilay@cs.wisc.edu# Copyright (c) 2012 Mark D. Hill and David A. Wood 28968Snilay@cs.wisc.edu# All rights reserved. 38968Snilay@cs.wisc.edu# 48968Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 58968Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 68968Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 78968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 88968Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 98968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 108968Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 118968Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 128968Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 138968Snilay@cs.wisc.edu# this software without specific prior written permission. 148968Snilay@cs.wisc.edu# 158968Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168968Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178968Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188968Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198968Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208968Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218968Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228968Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238968Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248968Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258968Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268968Snilay@cs.wisc.edu# 278968Snilay@cs.wisc.edu# Authors: Nilay Vaish 288968Snilay@cs.wisc.edu 298968Snilay@cs.wisc.eduimport m5, os, optparse, sys 308968Snilay@cs.wisc.edufrom m5.objects import * 318968Snilay@cs.wisc.edum5.util.addToPath('../configs/common') 328968Snilay@cs.wisc.edufrom Benchmarks import SysConfig 338968Snilay@cs.wisc.eduimport FSConfig 348968Snilay@cs.wisc.edu 358968Snilay@cs.wisc.edum5.util.addToPath('../configs/ruby') 369123Sandreas.hansson@arm.comm5.util.addToPath('../configs/topologies') 378968Snilay@cs.wisc.eduimport Ruby 388968Snilay@cs.wisc.eduimport Options 398968Snilay@cs.wisc.edu 408968Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 418968Snilay@cs.wisc.eduparser = optparse.OptionParser() 428968Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 438968Snilay@cs.wisc.eduRuby.define_options(parser) 448968Snilay@cs.wisc.edu(options, args) = parser.parse_args() 458968Snilay@cs.wisc.edu 468968Snilay@cs.wisc.edu# Set the default cache size and associativity to be very small to encourage 478968Snilay@cs.wisc.edu# races between requests and writebacks. 488968Snilay@cs.wisc.eduoptions.l1d_size="32kB" 498968Snilay@cs.wisc.eduoptions.l1i_size="32kB" 508968Snilay@cs.wisc.eduoptions.l2_size="4MB" 518968Snilay@cs.wisc.eduoptions.l1d_assoc=2 528968Snilay@cs.wisc.eduoptions.l1i_assoc=2 538968Snilay@cs.wisc.eduoptions.l2_assoc=2 548968Snilay@cs.wisc.eduoptions.num_cpus = 2 558968Snilay@cs.wisc.edu 568968Snilay@cs.wisc.edu#the system 578968Snilay@cs.wisc.edumdesc = SysConfig(disk = 'linux-x86.img') 588968Snilay@cs.wisc.edusystem = FSConfig.makeLinuxX86System('timing', options.num_cpus, 598968Snilay@cs.wisc.edu mdesc=mdesc, Ruby=True) 608968Snilay@cs.wisc.edusystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 618968Snilay@cs.wisc.edusystem.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] 628968Snilay@cs.wisc.eduRuby.create_system(options, system, system.piobus, system._dma_ports) 638968Snilay@cs.wisc.edu 648968Snilay@cs.wisc.edufor (i, cpu) in enumerate(system.cpu): 658968Snilay@cs.wisc.edu # create the interrupt controller 668968Snilay@cs.wisc.edu cpu.createInterruptController() 678968Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 688968Snilay@cs.wisc.edu cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 698968Snilay@cs.wisc.edu cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 708968Snilay@cs.wisc.edu cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 718968Snilay@cs.wisc.edu cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 728968Snilay@cs.wisc.edu cpu.interrupts.pio = system.piobus.master 738968Snilay@cs.wisc.edu cpu.interrupts.int_master = system.piobus.slave 748968Snilay@cs.wisc.edu cpu.interrupts.int_slave = system.piobus.master 758968Snilay@cs.wisc.edu cpu.clock = '2GHz' 768968Snilay@cs.wisc.edu 779577Snilay@cs.wisc.edu # Set access_phys_mem to True for ruby port 789577Snilay@cs.wisc.edu system.ruby._cpu_ruby_ports[i].access_phys_mem = True 799577Snilay@cs.wisc.edu 808968Snilay@cs.wisc.eduroot = Root(full_system = True, system = system) 818968Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('1THz') 82