vexpress_gem5_v1_base.dtsi revision 14114:ed18eaf9d344
1955SN/A/* 2955SN/A * Copyright (c) 2015-2017 ARM Limited 37816Ssteve.reinhardt@amd.com * All rights reserved 45871Snate@binkert.org * 51762SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 28955SN/A * Authors: Andreas Sandberg 29955SN/A */ 302665Ssaidi@eecs.umich.edu 312665Ssaidi@eecs.umich.edu/ { 325863Snate@binkert.org arm,hbi = <0x0>; 33955SN/A arm,vexpress,site = <0xf>; 34955SN/A interrupt-parent = <&gic>; 35955SN/A #address-cells = <2>; 36955SN/A #size-cells = <2>; 37955SN/A 388878Ssteve.reinhardt@amd.com gic: interrupt-controller@2c001000 { 392632Sstever@eecs.umich.edu compatible = "gem5,gic", "arm,gic-400"; 408878Ssteve.reinhardt@amd.com #interrupt-cells = <3>; 412632Sstever@eecs.umich.edu #address-cells = <0>; 42955SN/A interrupt-controller; 438878Ssteve.reinhardt@amd.com reg = <0 0x2c001000 0 0x1000>, 442632Sstever@eecs.umich.edu <0 0x2c002000 0 0x1000>, 452761Sstever@eecs.umich.edu <0 0x2c004000 0 0x2000>, 462632Sstever@eecs.umich.edu <0 0x2c006000 0 0x2000>; 472632Sstever@eecs.umich.edu interrupts = <1 9 0xf04>; 482632Sstever@eecs.umich.edu }; 492761Sstever@eecs.umich.edu 502761Sstever@eecs.umich.edu 512761Sstever@eecs.umich.edu timer { 528878Ssteve.reinhardt@amd.com compatible = "arm,cortex-a15-timer", 538878Ssteve.reinhardt@amd.com "arm,armv7-timer"; 542761Sstever@eecs.umich.edu interrupts = <1 13 0xf08>, 552761Sstever@eecs.umich.edu <1 14 0xf08>, 562761Sstever@eecs.umich.edu <1 11 0xf08>, 572761Sstever@eecs.umich.edu <1 10 0xf08>; 582761Sstever@eecs.umich.edu clocks = <&osc_sys>; 598878Ssteve.reinhardt@amd.com clock-names="apb_pclk"; 608878Ssteve.reinhardt@amd.com }; 612632Sstever@eecs.umich.edu 622632Sstever@eecs.umich.edu pci { 638878Ssteve.reinhardt@amd.com compatible = "pci-host-ecam-generic"; 648878Ssteve.reinhardt@amd.com device_type = "pci"; 652632Sstever@eecs.umich.edu #address-cells = <0x3>; 66955SN/A #size-cells = <0x2>; 67955SN/A #interrupt-cells = <0x1>; 68955SN/A 695863Snate@binkert.org reg = <0x0 0x30000000 0x0 0x10000000>; 705863Snate@binkert.org 715863Snate@binkert.org ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 725863Snate@binkert.org <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 735863Snate@binkert.org 745863Snate@binkert.org interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 755863Snate@binkert.org <0x000800 0x0 0x0 0 &gic 0 69 1>, 765863Snate@binkert.org <0x001000 0x0 0x0 0 &gic 0 70 1>, 775863Snate@binkert.org <0x001800 0x0 0x0 0 &gic 0 71 1>; 785863Snate@binkert.org 795863Snate@binkert.org interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 808878Ssteve.reinhardt@amd.com dma-coherent; 815863Snate@binkert.org }; 825863Snate@binkert.org 835863Snate@binkert.org kmi@1c060000 { 845863Snate@binkert.org compatible = "arm,pl050", "arm,primecell"; 855863Snate@binkert.org reg = <0x0 0x1c060000 0x0 0x1000>; 865863Snate@binkert.org interrupts = <0 12 4>; 875863Snate@binkert.org clocks = <&v2m_clk24mhz>, <&osc_smb>; 885863Snate@binkert.org clock-names = "KMIREFCLK", "apb_pclk"; 895863Snate@binkert.org }; 905863Snate@binkert.org 915863Snate@binkert.org kmi@1c070000 { 925863Snate@binkert.org compatible = "arm,pl050", "arm,primecell"; 935863Snate@binkert.org reg = <0x0 0x1c070000 0x0 0x1000>; 945863Snate@binkert.org interrupts = <0 13 4>; 955863Snate@binkert.org clocks = <&v2m_clk24mhz>, <&osc_smb>; 968878Ssteve.reinhardt@amd.com clock-names = "KMIREFCLK", "apb_pclk"; 975863Snate@binkert.org }; 985863Snate@binkert.org 995863Snate@binkert.org uart0: uart@1c090000 { 1006654Snate@binkert.org compatible = "arm,pl011", "arm,primecell"; 101955SN/A reg = <0x0 0x1c090000 0x0 0x1000>; 1025396Ssaidi@eecs.umich.edu interrupts = <0 5 4>; 1035863Snate@binkert.org clocks = <&osc_peripheral>, <&osc_smb>; 1045863Snate@binkert.org clock-names = "uartclk", "apb_pclk"; 1054202Sbinkertn@umich.edu }; 1065863Snate@binkert.org 1075863Snate@binkert.org rtc@1c170000 { 1085863Snate@binkert.org compatible = "arm,pl031", "arm,primecell"; 1095863Snate@binkert.org reg = <0x0 0x1c170000 0x0 0x1000>; 110955SN/A interrupts = <0 4 4>; 1116654Snate@binkert.org clocks = <&osc_smb>; 1125273Sstever@gmail.com clock-names = "apb_pclk"; 1135871Snate@binkert.org }; 1145273Sstever@gmail.com 1156655Snate@binkert.org v2m_clk24mhz: clk24mhz { 1168878Ssteve.reinhardt@amd.com compatible = "fixed-clock"; 1176655Snate@binkert.org #clock-cells = <0>; 1186655Snate@binkert.org clock-frequency = <24000000>; 1199219Spower.jg@gmail.com clock-output-names = "v2m:clk24mhz"; 1206655Snate@binkert.org }; 1215871Snate@binkert.org 1226654Snate@binkert.org 1238947Sandreas.hansson@arm.com v2m_sysreg: sysreg@1c010000 { 1245396Ssaidi@eecs.umich.edu compatible = "arm,vexpress-sysreg"; 1258120Sgblack@eecs.umich.edu reg = <0 0x1c010000 0x0 0x1000>; 1268120Sgblack@eecs.umich.edu gpio-controller; 1278120Sgblack@eecs.umich.edu #gpio-cells = <2>; 1288120Sgblack@eecs.umich.edu }; 1298120Sgblack@eecs.umich.edu 1308120Sgblack@eecs.umich.edu vio@1c130000 { 1318120Sgblack@eecs.umich.edu compatible = "virtio,mmio"; 1328120Sgblack@eecs.umich.edu reg = <0 0x1c130000 0x0 0x1000>; 1338879Ssteve.reinhardt@amd.com interrupts = <0 42 4>; 1348879Ssteve.reinhardt@amd.com }; 1358879Ssteve.reinhardt@amd.com 1368879Ssteve.reinhardt@amd.com vio@1c140000 { 1378879Ssteve.reinhardt@amd.com compatible = "virtio,mmio"; 1388879Ssteve.reinhardt@amd.com reg = <0 0x1c140000 0x0 0x1000>; 1398879Ssteve.reinhardt@amd.com interrupts = <0 43 4>; 1408879Ssteve.reinhardt@amd.com }; 1418879Ssteve.reinhardt@amd.com 1428879Ssteve.reinhardt@amd.com dcc { 1438879Ssteve.reinhardt@amd.com compatible = "arm,vexpress,config-bus"; 1448879Ssteve.reinhardt@amd.com arm,vexpress,config-bridge = <&v2m_sysreg>; 1458879Ssteve.reinhardt@amd.com 1468120Sgblack@eecs.umich.edu osc_pxl: osc@5 { 1478120Sgblack@eecs.umich.edu compatible = "arm,vexpress-osc"; 1488120Sgblack@eecs.umich.edu arm,vexpress-sysreg,func = <1 5>; 1498120Sgblack@eecs.umich.edu freq-range = <23750000 1000000000>; 1508120Sgblack@eecs.umich.edu #clock-cells = <0>; 1518120Sgblack@eecs.umich.edu clock-output-names = "oscclk5"; 1528120Sgblack@eecs.umich.edu }; 1538120Sgblack@eecs.umich.edu 1548120Sgblack@eecs.umich.edu osc_smb: osc@6 { 1558120Sgblack@eecs.umich.edu compatible = "arm,vexpress-osc"; 1568120Sgblack@eecs.umich.edu arm,vexpress-sysreg,func = <1 6>; 1578120Sgblack@eecs.umich.edu freq-range = <20000000 50000000>; 1588120Sgblack@eecs.umich.edu #clock-cells = <0>; 1598120Sgblack@eecs.umich.edu clock-output-names = "oscclk6"; 1608879Ssteve.reinhardt@amd.com }; 1618879Ssteve.reinhardt@amd.com 1628879Ssteve.reinhardt@amd.com osc_sys: osc@7 { 1638879Ssteve.reinhardt@amd.com compatible = "arm,vexpress-osc"; 1648879Ssteve.reinhardt@amd.com arm,vexpress-sysreg,func = <1 7>; 1658879Ssteve.reinhardt@amd.com freq-range = <20000000 60000000>; 1668879Ssteve.reinhardt@amd.com #clock-cells = <0>; 1678879Ssteve.reinhardt@amd.com clock-output-names = "oscclk7"; 1689227Sandreas.hansson@arm.com }; 1699227Sandreas.hansson@arm.com }; 1708879Ssteve.reinhardt@amd.com 1718879Ssteve.reinhardt@amd.com 1728879Ssteve.reinhardt@amd.com mcc { 1738879Ssteve.reinhardt@amd.com compatible = "arm,vexpress,config-bus"; 1748120Sgblack@eecs.umich.edu arm,vexpress,config-bridge = <&v2m_sysreg>; 1758947Sandreas.hansson@arm.com arm,vexpress,site = <0>; 1767816Ssteve.reinhardt@amd.com 1775871Snate@binkert.org osc_peripheral: osc@2 { 1785871Snate@binkert.org compatible = "arm,vexpress-osc"; 1796121Snate@binkert.org arm,vexpress-sysreg,func = <1 2>; 1805871Snate@binkert.org freq-range = <24000000 24000000>; 1815871Snate@binkert.org #clock-cells = <0>; 1829119Sandreas.hansson@arm.com clock-output-names = "v2m:oscclk2"; 1839396Sandreas.hansson@arm.com }; 1849396Sandreas.hansson@arm.com }; 185955SN/A}; 1869416SAndreas.Sandberg@ARM.com