1/* 2 * Copyright (c) 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 */ 30 31/ { 32 arm,hbi = <0x0>; 33 arm,vexpress,site = <0xf>; 34 interrupt-parent = <&gic>; 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 gic: interrupt-controller@2c001000 { 39 compatible = "gem5,gic", "arm,gic-400"; 40 #interrupt-cells = <3>; 41 #address-cells = <0>; 42 interrupt-controller; 43 reg = <0 0x2c001000 0 0x1000>, 44 <0 0x2c002000 0 0x1000>, 45 <0 0x2c004000 0 0x2000>, 46 <0 0x2c006000 0 0x2000>; 47 interrupts = <1 9 0xf04>; 48 }; 49 50 51 timer { 52 compatible = "arm,cortex-a15-timer", 53 "arm,armv7-timer"; 54 interrupts = <1 13 0xf08>, 55 <1 14 0xf08>, 56 <1 11 0xf08>, 57 <1 10 0xf08>; 58 clocks = <&osc_sys>; 59 clock-names="apb_pclk"; 60 }; 61 62 pci { 63 compatible = "pci-host-ecam-generic"; 64 device_type = "pci"; 65 #address-cells = <0x3>; 66 #size-cells = <0x2>; 67 #interrupt-cells = <0x1>; 68 69 reg = <0x0 0x30000000 0x0 0x10000000>; 70 71 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 72 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 73 74 interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 75 <0x000800 0x0 0x0 0 &gic 0 69 1>, 76 <0x001000 0x0 0x0 0 &gic 0 70 1>, 77 <0x001800 0x0 0x0 0 &gic 0 71 1>; 78 79 interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 80 dma-coherent; 81 }; 82 83 kmi@1c060000 { 84 compatible = "arm,pl050", "arm,primecell"; 85 reg = <0x0 0x1c060000 0x0 0x1000>; 86 interrupts = <0 12 4>; 87 clocks = <&v2m_clk24mhz>, <&osc_smb>; 88 clock-names = "KMIREFCLK", "apb_pclk"; 89 }; 90 91 kmi@1c070000 { 92 compatible = "arm,pl050", "arm,primecell"; 93 reg = <0x0 0x1c070000 0x0 0x1000>; 94 interrupts = <0 13 4>; 95 clocks = <&v2m_clk24mhz>, <&osc_smb>; 96 clock-names = "KMIREFCLK", "apb_pclk"; 97 }; 98 99 uart0: uart@1c090000 { 100 compatible = "arm,pl011", "arm,primecell"; 101 reg = <0x0 0x1c090000 0x0 0x1000>; 102 interrupts = <0 5 4>; 103 clocks = <&osc_peripheral>, <&osc_smb>; 104 clock-names = "uartclk", "apb_pclk"; 105 }; 106 107 rtc@1c170000 { 108 compatible = "arm,pl031", "arm,primecell"; 109 reg = <0x0 0x1c170000 0x0 0x1000>; 110 interrupts = <0 4 4>; 111 clocks = <&osc_smb>; 112 clock-names = "apb_pclk"; 113 }; 114 115 v2m_clk24mhz: clk24mhz { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <24000000>; 119 clock-output-names = "v2m:clk24mhz"; 120 }; 121 122 123 v2m_sysreg: sysreg@1c010000 { 124 compatible = "arm,vexpress-sysreg"; 125 reg = <0 0x1c010000 0x0 0x1000>; 126 gpio-controller; 127 #gpio-cells = <2>; 128 }; 129 130 vio@1c130000 { 131 compatible = "virtio,mmio"; 132 reg = <0 0x1c130000 0x0 0x1000>; 133 interrupts = <0 42 4>; 134 }; 135 136 vio@1c140000 { 137 compatible = "virtio,mmio"; 138 reg = <0 0x1c140000 0x0 0x1000>; 139 interrupts = <0 43 4>; 140 }; 141 142 dcc { 143 compatible = "arm,vexpress,config-bus"; 144 arm,vexpress,config-bridge = <&v2m_sysreg>; 145 146 osc_pxl: osc@5 { 147 compatible = "arm,vexpress-osc"; 148 arm,vexpress-sysreg,func = <1 5>; 149 freq-range = <23750000 1000000000>; 150 #clock-cells = <0>; 151 clock-output-names = "oscclk5"; 152 }; 153 154 osc_smb: osc@6 { 155 compatible = "arm,vexpress-osc"; 156 arm,vexpress-sysreg,func = <1 6>; 157 freq-range = <20000000 50000000>; 158 #clock-cells = <0>; 159 clock-output-names = "oscclk6"; 160 }; 161 162 osc_sys: osc@7 { 163 compatible = "arm,vexpress-osc"; 164 arm,vexpress-sysreg,func = <1 7>; 165 freq-range = <20000000 60000000>; 166 #clock-cells = <0>; 167 clock-output-names = "oscclk7"; 168 }; 169 }; 170 171 172 mcc { 173 compatible = "arm,vexpress,config-bus"; 174 arm,vexpress,config-bridge = <&v2m_sysreg>; 175 arm,vexpress,site = <0>; 176 177 osc_peripheral: osc@2 { 178 compatible = "arm,vexpress-osc"; 179 arm,vexpress-sysreg,func = <1 2>; 180 freq-range = <24000000 24000000>; 181 #clock-cells = <0>; 182 clock-output-names = "v2m:oscclk2"; 183 }; 184 }; 185}; 186