vexpress_gem5_v1_base.dtsi revision 12761
12SN/A/* 21762SN/A * Copyright (c) 2015-2017 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Andreas Sandberg 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A/ { 322SN/A arm,hbi = <0x0>; 3356SN/A arm,vexpress,site = <0xf>; 344167Sbinkertn@umich.edu interrupt-parent = <&gic>; 352SN/A #address-cells = <2>; 362107SN/A #size-cells = <2>; 372SN/A 382SN/A gic: interrupt-controller@2c001000 { 392107SN/A compatible = "gem5,gic", "arm,gic-400"; 404572Sacolyte@umich.edu #interrupt-cells = <3>; 414572Sacolyte@umich.edu #address-cells = <0>; 422SN/A interrupt-controller; 435870Snate@binkert.org reg = <0 0x2c001000 0 0x1000>, 445870Snate@binkert.org <0 0x2c002000 0 0x1000>, 455870Snate@binkert.org <0 0x2c004000 0 0x2000>, 465870Snate@binkert.org <0 0x2c006000 0 0x2000>; 475870Snate@binkert.org interrupts = <1 9 0xf04>; 485870Snate@binkert.org }; 495870Snate@binkert.org 505870Snate@binkert.org 512SN/A timer { 522107SN/A compatible = "arm,cortex-a15-timer", 532SN/A "arm,armv7-timer"; 547823Ssteve.reinhardt@amd.com interrupts = <1 13 0xf08>, 552SN/A <1 14 0xf08>, 562SN/A <1 11 0xf08>; 572SN/A clocks = <&osc_sys>; 582SN/A clock-names="apb_pclk"; 592SN/A }; 602SN/A 612SN/A pci { 622SN/A compatible = "pci-host-ecam-generic"; 632SN/A device_type = "pci"; 642SN/A #address-cells = <0x3>; 652SN/A #size-cells = <0x2>; 662SN/A #interrupt-cells = <0x1>; 672SN/A 682SN/A reg = <0x0 0x30000000 0x0 0x10000000>; 692SN/A 702SN/A ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 717720Sgblack@eecs.umich.edu <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 727720Sgblack@eecs.umich.edu 732SN/A interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 742SN/A <0x000800 0x0 0x0 0 &gic 0 69 1>, 752SN/A <0x001000 0x0 0x0 0 &gic 0 70 1>, 762SN/A <0x001800 0x0 0x0 0 &gic 0 71 1>; 772SN/A 782SN/A interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 792SN/A dma-coherent; 802680Sktlim@umich.edu }; 812SN/A 822SN/A kmi@1c060000 { 832SN/A compatible = "arm,pl050", "arm,primecell"; 842SN/A reg = <0x0 0x1c060000 0x0 0x1000>; 852SN/A interrupts = <0 12 4>; 862SN/A clocks = <&v2m_clk24mhz>, <&osc_smb>; 873271Sgblack@eecs.umich.edu clock-names = "KMIREFCLK", "apb_pclk"; 887720Sgblack@eecs.umich.edu }; 893271Sgblack@eecs.umich.edu 904539Sgblack@eecs.umich.edu kmi@1c070000 { 915870Snate@binkert.org compatible = "arm,pl050", "arm,primecell"; 923271Sgblack@eecs.umich.edu reg = <0x0 0x1c070000 0x0 0x1000>; 933271Sgblack@eecs.umich.edu interrupts = <0 13 4>; 947720Sgblack@eecs.umich.edu clocks = <&v2m_clk24mhz>, <&osc_smb>; 957720Sgblack@eecs.umich.edu clock-names = "KMIREFCLK", "apb_pclk"; 965870Snate@binkert.org }; 975870Snate@binkert.org 985870Snate@binkert.org uart0: uart@1c090000 { 995870Snate@binkert.org compatible = "arm,pl011", "arm,primecell"; 1005870Snate@binkert.org reg = <0x0 0x1c090000 0x0 0x1000>; 1015870Snate@binkert.org interrupts = <0 5 4>; 1027720Sgblack@eecs.umich.edu clocks = <&osc_peripheral>, <&osc_smb>; 1035870Snate@binkert.org clock-names = "uartclk", "apb_pclk"; 1045870Snate@binkert.org }; 1055870Snate@binkert.org 1065870Snate@binkert.org rtc@1c170000 { 1075870Snate@binkert.org compatible = "arm,pl031", "arm,primecell"; 1085870Snate@binkert.org reg = <0x0 0x1c170000 0x0 0x1000>; 1095870Snate@binkert.org interrupts = <0 4 4>; 1105870Snate@binkert.org clocks = <&osc_smb>; 1115870Snate@binkert.org clock-names = "apb_pclk"; 1125870Snate@binkert.org }; 1135870Snate@binkert.org 1145870Snate@binkert.org v2m_clk24mhz: clk24mhz { 1155870Snate@binkert.org compatible = "fixed-clock"; 1165870Snate@binkert.org #clock-cells = <0>; 1175870Snate@binkert.org clock-frequency = <24000000>; 118 clock-output-names = "v2m:clk24mhz"; 119 }; 120 121 122 v2m_sysreg: sysreg@1c010000 { 123 compatible = "arm,vexpress-sysreg"; 124 reg = <0 0x1c010000 0x0 0x1000>; 125 gpio-controller; 126 #gpio-cells = <2>; 127 }; 128 129 vio@1c130000 { 130 compatible = "virtio,mmio"; 131 reg = <0 0x1c130000 0x0 0x1000>; 132 interrupts = <0 42 4>; 133 }; 134 135 vio@1c140000 { 136 compatible = "virtio,mmio"; 137 reg = <0 0x1c140000 0x0 0x1000>; 138 interrupts = <0 43 4>; 139 }; 140 141 dcc { 142 compatible = "arm,vexpress,config-bus"; 143 arm,vexpress,config-bridge = <&v2m_sysreg>; 144 145 osc_pxl: osc@5 { 146 compatible = "arm,vexpress-osc"; 147 arm,vexpress-sysreg,func = <1 5>; 148 freq-range = <23750000 1000000000>; 149 #clock-cells = <0>; 150 clock-output-names = "oscclk5"; 151 }; 152 153 osc_smb: osc@6 { 154 compatible = "arm,vexpress-osc"; 155 arm,vexpress-sysreg,func = <1 6>; 156 freq-range = <20000000 50000000>; 157 #clock-cells = <0>; 158 clock-output-names = "oscclk6"; 159 }; 160 161 osc_sys: osc@7 { 162 compatible = "arm,vexpress-osc"; 163 arm,vexpress-sysreg,func = <1 7>; 164 freq-range = <20000000 60000000>; 165 #clock-cells = <0>; 166 clock-output-names = "oscclk7"; 167 }; 168 }; 169 170 171 mcc { 172 compatible = "arm,vexpress,config-bus"; 173 arm,vexpress,config-bridge = <&v2m_sysreg>; 174 arm,vexpress,site = <0>; 175 176 osc_peripheral: osc@2 { 177 compatible = "arm,vexpress-osc"; 178 arm,vexpress-sysreg,func = <1 2>; 179 freq-range = <24000000 24000000>; 180 #clock-cells = <0>; 181 clock-output-names = "v2m:oscclk2"; 182 }; 183 }; 184}; 185