rpb.h revision 8029
18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 1990 The Hewlett-Packard Development Company 38029Snate@binkert.org * All rights reserved. 48013Sbinkertn@umich.edu * 58029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 68029Snate@binkert.org * modification, are permitted provided that the following conditions are 78029Snate@binkert.org * met: redistributions of source code must retain the above copyright 88029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 98029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 108029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 118029Snate@binkert.org * documentation and/or other materials provided with the distribution; 128029Snate@binkert.org * neither the name of the copyright holders nor the names of its 138029Snate@binkert.org * contributors may be used to endorse or promote products derived from 148029Snate@binkert.org * this software without specific prior written permission. 158013Sbinkertn@umich.edu * 168029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278013Sbinkertn@umich.edu * 288013Sbinkertn@umich.edu */ 298012Ssaidi@eecs.umich.edu 308019Sbenash@umich.edu/* 318019Sbenash@umich.edu * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 328019Sbenash@umich.edu * All rights reserved. 338019Sbenash@umich.edu * 348019Sbenash@umich.edu * Author: Keith Bostic, Chris G. Demetriou 358019Sbenash@umich.edu * 368019Sbenash@umich.edu * Permission to use, copy, modify and distribute this software and 378019Sbenash@umich.edu * its documentation is hereby granted, provided that both the copyright 388019Sbenash@umich.edu * notice and this permission notice appear in all copies of the 398019Sbenash@umich.edu * software, derivative works or modified versions, and any portions 408019Sbenash@umich.edu * thereof, and that both notices appear in supporting documentation. 418019Sbenash@umich.edu * 428019Sbenash@umich.edu * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 438019Sbenash@umich.edu * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 448019Sbenash@umich.edu * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 458019Sbenash@umich.edu * 468019Sbenash@umich.edu * Carnegie Mellon requests users of this software to return to 478019Sbenash@umich.edu * 488019Sbenash@umich.edu * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 498019Sbenash@umich.edu * School of Computer Science 508019Sbenash@umich.edu * Carnegie Mellon University 518019Sbenash@umich.edu * Pittsburgh PA 15213-3890 528019Sbenash@umich.edu * 538019Sbenash@umich.edu * any improvements or extensions that they make and grant Carnegie the 548019Sbenash@umich.edu * rights to redistribute these changes. 558019Sbenash@umich.edu */ 568019Sbenash@umich.edu 577977Shsul@eecs.umich.edu/* 587977Shsul@eecs.umich.edu * Defines for the architected startup addresses. 597977Shsul@eecs.umich.edu */ 607977Shsul@eecs.umich.edu#define HWRPB_ADDR 0x10000000 /* 256 MB */ 617977Shsul@eecs.umich.edu#define BOOT_ADDR 0x20000000 /* 512 MB */ 627977Shsul@eecs.umich.edu#define PGTBL_ADDR 0x40000000 /* 1 GB */ 637977Shsul@eecs.umich.edu 647977Shsul@eecs.umich.edu/* 657977Shsul@eecs.umich.edu * Values for the "haltcode" field in the per-cpu portion of the HWRPB 667977Shsul@eecs.umich.edu * 677977Shsul@eecs.umich.edu * Bit defines for the "sysvar" field in the HWRPB. 687977Shsul@eecs.umich.edu * Each platform has different values for SYSBOARD and IOBOARD bits. 697977Shsul@eecs.umich.edu */ 707977Shsul@eecs.umich.edu#define HALT_PWRUP 0 /* power up */ 717977Shsul@eecs.umich.edu#define HALT_OPR 1 /* operator issued halt cmd */ 727977Shsul@eecs.umich.edu#define HALT_KSTK 2 /* kernel stack not valid */ 737977Shsul@eecs.umich.edu#define HALT_SCBB 3 /* invalid SCBB */ 747977Shsul@eecs.umich.edu#define HALT_PTBR 4 /* invalid PTBR */ 757977Shsul@eecs.umich.edu#define HALT_EXE 5 /* kernel executed halt instruction */ 767977Shsul@eecs.umich.edu#define HALT_DBLE 6 /* double error abort */ 777977Shsul@eecs.umich.edu 787977Shsul@eecs.umich.edu/* 797977Shsul@eecs.umich.edu * Bit defines for the "state" field in the per-cpu portion of the HWRPB 807977Shsul@eecs.umich.edu */ 817977Shsul@eecs.umich.edu#define STATE_BIP 0x00000001 /* bootstrap in progress */ 827977Shsul@eecs.umich.edu#define STATE_RC 0x00000002 /* restart capable */ 837977Shsul@eecs.umich.edu#define STATE_PA 0x00000004 /* processor available to OS */ 847977Shsul@eecs.umich.edu#define STATE_PP 0x00000008 /* processor present */ 857977Shsul@eecs.umich.edu#define STATE_OH 0x00000010 /* operator halted */ 867977Shsul@eecs.umich.edu#define STATE_CV 0x00000020 /* context valid */ 877977Shsul@eecs.umich.edu#define STATE_PV 0x00000040 /* PALcode valid */ 887977Shsul@eecs.umich.edu#define STATE_PMV 0x00000080 /* PALcode memory valid */ 897977Shsul@eecs.umich.edu#define STATE_PL 0x00000100 /* PALcode loaded */ 907977Shsul@eecs.umich.edu#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */ 917977Shsul@eecs.umich.edu#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */ 927977Shsul@eecs.umich.edu#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */ 937977Shsul@eecs.umich.edu#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */ 947977Shsul@eecs.umich.edu#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */ 957977Shsul@eecs.umich.edu#define STATE_HALT 0x00040000 /* Remain halted (no restart) */ 967977Shsul@eecs.umich.edu 977977Shsul@eecs.umich.edu 987977Shsul@eecs.umich.edu#define SV_PF_RSVD 0x00000000 /* RESERVED */ 998013Sbinkertn@umich.edu#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */ 1007977Shsul@eecs.umich.edu#define SV_MPCAP 0x00000001 /* MP capable */ 1017977Shsul@eecs.umich.edu#define SV_PF_UNITED 0x00000020 /* United */ 1027977Shsul@eecs.umich.edu#define SV_PF_SEPARATE 0x00000040 /* Separate */ 1037977Shsul@eecs.umich.edu#define SV_PF_FULLBB 0x00000060 /* Full battery backup */ 1047977Shsul@eecs.umich.edu#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */ 1057977Shsul@eecs.umich.edu#define SV_PF_RESTART 0x00000100 /* Powerfail restart */ 1067977Shsul@eecs.umich.edu 1077977Shsul@eecs.umich.edu#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */ 1087977Shsul@eecs.umich.edu 1098013Sbinkertn@umich.edu#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */ 1108013Sbinkertn@umich.edu#define SV_SANDPIPER 0x00000400 /* others define system platforms */ 1117977Shsul@eecs.umich.edu#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */ 1127977Shsul@eecs.umich.edu#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */ 1137977Shsul@eecs.umich.edu#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */ 1147977Shsul@eecs.umich.edu#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */ 1157977Shsul@eecs.umich.edu#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */ 1167977Shsul@eecs.umich.edu#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */ 1177977Shsul@eecs.umich.edu#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */ 1187977Shsul@eecs.umich.edu 1197977Shsul@eecs.umich.edu#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */ 1207977Shsul@eecs.umich.edu 1217977Shsul@eecs.umich.edu#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */ 1227977Shsul@eecs.umich.edu 1237977Shsul@eecs.umich.edu/* 1247977Shsul@eecs.umich.edu * Values for the "console type" field in the CTB portion of the HWRPB 1257977Shsul@eecs.umich.edu */ 1267977Shsul@eecs.umich.edu#define CONS_NONE 0 /* no console present */ 1277977Shsul@eecs.umich.edu#define CONS_SRVC 1 /* console is service processor */ 1287977Shsul@eecs.umich.edu#define CONS_DZ 2 /* console is dz/dl VT device */ 1298013Sbinkertn@umich.edu#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/ 1307977Shsul@eecs.umich.edu#define CONS_REM 4 /* cons is remote, protocal enet/MOP */ 1317977Shsul@eecs.umich.edu 1327977Shsul@eecs.umich.edu/* 1337977Shsul@eecs.umich.edu * PALcode variants that we're interested in. 1347977Shsul@eecs.umich.edu * Used as indices into the "palrev_avail" array in the per-cpu portion 1357977Shsul@eecs.umich.edu * of the HWRPB. 1367977Shsul@eecs.umich.edu */ 1377977Shsul@eecs.umich.edu#define PALvar_reserved 0 1387977Shsul@eecs.umich.edu#define PALvar_OpenVMS 1 1397977Shsul@eecs.umich.edu#define PALvar_OSF1 2 1407977Shsul@eecs.umich.edu 1417977Shsul@eecs.umich.edu/* 1427977Shsul@eecs.umich.edu * The Alpha restart parameter block, which is a page or 2 in low memory 1437977Shsul@eecs.umich.edu */ 1447977Shsul@eecs.umich.edustruct rpb { 1457977Shsul@eecs.umich.edu struct rpb *rpb_selfref; /* 000: physical self-reference */ 1468013Sbinkertn@umich.edu long rpb_string; /* 008: contains string "HWRPB" */ 1478013Sbinkertn@umich.edu long rpb_vers; /* 010: HWRPB version number */ 1488013Sbinkertn@umich.edu ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */ 1498013Sbinkertn@umich.edu ulong rpb_cpuid; /* 020: primary cpu id */ 1508013Sbinkertn@umich.edu ulong rpb_pagesize; /* 028: page size in bytes */ 1518013Sbinkertn@umich.edu ulong rpb_addrbits; /* 030: number of phys addr bits */ 1528013Sbinkertn@umich.edu ulong rpb_maxasn; /* 038: max valid ASN */ 1538013Sbinkertn@umich.edu char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */ 1548013Sbinkertn@umich.edu ulong grpb_systype; /* 050: system type */ 1558013Sbinkertn@umich.edu long rpb_sysvar; /* 058: system variation */ 1568013Sbinkertn@umich.edu long rpb_sysrev; /* 060: system revision */ 1578013Sbinkertn@umich.edu ulong rpb_clock; /* 068: scaled interval clock intr freq */ 1588013Sbinkertn@umich.edu ulong rpb_counter; /* 070: cycle counter frequency */ 1598013Sbinkertn@umich.edu ulong rpb_vptb; /* 078: virtual page table base */ 1608013Sbinkertn@umich.edu long rpb_res1; /* 080: reserved */ 1618013Sbinkertn@umich.edu ulong rpb_trans_off; /* 088: offset to translation buffer hint */ 1628013Sbinkertn@umich.edu ulong rpb_numprocs; /* 090: number of processor slots */ 1638013Sbinkertn@umich.edu ulong rpb_slotsize; /* 098: per-cpu slot size */ 1648013Sbinkertn@umich.edu ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */ 1658013Sbinkertn@umich.edu ulong rpb_num_ctb; /* 0A8: number of CTBs */ 1668013Sbinkertn@umich.edu ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */ 1678013Sbinkertn@umich.edu ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */ 1688013Sbinkertn@umich.edu ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */ 1698013Sbinkertn@umich.edu ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */ 1708013Sbinkertn@umich.edu ulong rpb_config_off; /* 0D0: offset to config data block */ 1718013Sbinkertn@umich.edu ulong rpb_fru_off; /* 0D8: offset to FRU table */ 1728013Sbinkertn@umich.edu void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */ 1738013Sbinkertn@umich.edu long rpb_saveterm_pv; /* 0E8: proc value for save term routine */ 1748013Sbinkertn@umich.edu void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */ 1758013Sbinkertn@umich.edu long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */ 1768013Sbinkertn@umich.edu void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */ 1778013Sbinkertn@umich.edu long rpb_restart_pv; /* 108: proc value for CPU restart routine */ 1788013Sbinkertn@umich.edu long rpb_software; /* 110: used to determine presence of kdebug */ 1798013Sbinkertn@umich.edu long rpb_hardware; /* 118: reserved for hardware */ 1808013Sbinkertn@umich.edu long rpb_checksum; /* 120: checksum of prior entries in rpb */ 1818013Sbinkertn@umich.edu long rpb_rxrdy; /* 128: receive ready bitmask */ 1828013Sbinkertn@umich.edu long rpb_txrdy; /* 130: transmit ready bitmask */ 1838013Sbinkertn@umich.edu ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */ 1847977Shsul@eecs.umich.edu}; 1857977Shsul@eecs.umich.edu 1867977Shsul@eecs.umich.edu#define rpb_kdebug rpb_software 1877977Shsul@eecs.umich.edu 1887977Shsul@eecs.umich.edu#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23)) 1897977Shsul@eecs.umich.edu 1907977Shsul@eecs.umich.edu/* 1917977Shsul@eecs.umich.edu * This is the format for the boot/restart HWPCB. It must match the 1927977Shsul@eecs.umich.edu * initial fields of the pcb structure as defined in pcb.h, but must 1937977Shsul@eecs.umich.edu * additionally contain the appropriate amount of padding to line up 1947977Shsul@eecs.umich.edu * with formats used by other palcode types. 1957977Shsul@eecs.umich.edu */ 1967977Shsul@eecs.umich.edustruct bootpcb { 1978013Sbinkertn@umich.edu long rpb_ksp; /* 000: kernel stack pointer */ 1988013Sbinkertn@umich.edu long rpb_usp; /* 008: user stack pointer */ 1998013Sbinkertn@umich.edu long rpb_ptbr; /* 010: page table base register */ 2008013Sbinkertn@umich.edu int rpb_cc; /* 018: cycle counter */ 2018013Sbinkertn@umich.edu int rpb_asn; /* 01C: address space number */ 2028013Sbinkertn@umich.edu long rpb_proc_uniq; /* 020: proc/thread unique value */ 2038013Sbinkertn@umich.edu long rpb_fen; /* 028: floating point enable */ 2048013Sbinkertn@umich.edu long rpb_palscr[2]; /* 030: pal scratch area */ 2058013Sbinkertn@umich.edu long rpb_pcbpad[8]; /* 040: padding for fixed size */ 2067977Shsul@eecs.umich.edu}; 2077977Shsul@eecs.umich.edu 2087977Shsul@eecs.umich.edu/* 2097977Shsul@eecs.umich.edu * Inter-Console Communications Buffer 2107977Shsul@eecs.umich.edu * Used for the primary processor to communcate with the console 2117977Shsul@eecs.umich.edu * of secondary processors. 2127977Shsul@eecs.umich.edu */ 2137977Shsul@eecs.umich.edustruct iccb { 2148013Sbinkertn@umich.edu uint iccb_rxlen; /* receive length in bytes */ 2158013Sbinkertn@umich.edu uint iccb_txlen; /* transmit length in bytes */ 2168013Sbinkertn@umich.edu char iccb_rxbuf[80]; /* receive buffer */ 2178013Sbinkertn@umich.edu char iccb_txbuf[80]; /* transmit buffer */ 2187977Shsul@eecs.umich.edu}; 2197977Shsul@eecs.umich.edu 2207977Shsul@eecs.umich.edu/* 2217977Shsul@eecs.umich.edu * The per-cpu portion of the Alpha HWRPB. 2227977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size, 2237977Shsul@eecs.umich.edu * hence this must be a separate structure. 2247977Shsul@eecs.umich.edu * 2257977Shsul@eecs.umich.edu */ 2267977Shsul@eecs.umich.edustruct rpb_percpu { 2277977Shsul@eecs.umich.edu struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */ 2288013Sbinkertn@umich.edu long rpb_state; /* 080: per-cpu state bits */ 2298013Sbinkertn@umich.edu long rpb_palmem; /* 088: palcode memory length */ 2308013Sbinkertn@umich.edu long rpb_palscratch; /* 090: palcode scratch length */ 2318013Sbinkertn@umich.edu long rpb_palmem_addr; /* 098: phys addr of palcode mem space */ 2328013Sbinkertn@umich.edu long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */ 2338013Sbinkertn@umich.edu long rpb_palrev; /* 0A8: PALcode rev required */ 2348013Sbinkertn@umich.edu long rpb_proctype; /* 0B0: processor type */ 2358013Sbinkertn@umich.edu long rpb_procvar; /* 0B8: processor variation */ 2368013Sbinkertn@umich.edu long rpb_procrev; /* 0C0: processor revision */ 2378013Sbinkertn@umich.edu char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */ 2388013Sbinkertn@umich.edu long rpb_logout; /* 0D8: phys addr of logout area */ 2398013Sbinkertn@umich.edu long rpb_logout_len; /* 0E0: length in bytes of logout area */ 2408013Sbinkertn@umich.edu long rpb_haltpb; /* 0E8: halt pcb base */ 2418013Sbinkertn@umich.edu long rpb_haltpc; /* 0F0: halt pc */ 2428013Sbinkertn@umich.edu long rpb_haltps; /* 0F8: halt ps */ 2438013Sbinkertn@umich.edu long rpb_haltal; /* 100: halt arg list (R25) */ 2448013Sbinkertn@umich.edu long rpb_haltra; /* 108: halt return address (R26) */ 2458013Sbinkertn@umich.edu long rpb_haltpv; /* 110: halt procedure value (R27) */ 2468013Sbinkertn@umich.edu long rpb_haltcode; /* 118: reason for halt */ 2478013Sbinkertn@umich.edu long rpb_software; /* 120: for software */ 2488013Sbinkertn@umich.edu struct iccb rpb_iccb; /* 128: inter-console communications buffer */ 2498013Sbinkertn@umich.edu long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */ 2508013Sbinkertn@umich.edu long rpb_pcrsvd[6]; /* 250: reserved for arch use */ 2517977Shsul@eecs.umich.edu/* the dump stack grows from the end of the rpb page not to reach here */ 2527977Shsul@eecs.umich.edu}; 2537977Shsul@eecs.umich.edu 2547977Shsul@eecs.umich.edu/* The firmware revision is in the (unused) first entry of palrevs available */ 2557977Shsul@eecs.umich.edu#define rpb_firmrev rpb_palrev_avail[0] 2567977Shsul@eecs.umich.edu 2577977Shsul@eecs.umich.edu/* 2587977Shsul@eecs.umich.edu * The memory cluster descriptor. 2597977Shsul@eecs.umich.edu */ 2607977Shsul@eecs.umich.edustruct rpb_cluster { 2618013Sbinkertn@umich.edu long rpb_pfn; /* 000: starting PFN of this cluster */ 2628013Sbinkertn@umich.edu long rpb_pfncount; /* 008: count of PFNs in this cluster */ 2638013Sbinkertn@umich.edu long rpb_pfntested; /* 010: count of tested PFNs in cluster */ 2648013Sbinkertn@umich.edu long rpb_va; /* 018: va of bitmap */ 2658013Sbinkertn@umich.edu long rpb_pa; /* 020: pa of bitmap */ 2668013Sbinkertn@umich.edu long rpb_checksum; /* 028: checksum of bitmap */ 2678013Sbinkertn@umich.edu long rpb_usage; /* 030: usage of cluster */ 2687977Shsul@eecs.umich.edu}; 2697977Shsul@eecs.umich.edu#define CLUSTER_USAGE_OS ((long)0) 2707977Shsul@eecs.umich.edu#define CLUSTER_USAGE_PAL ((long)1) 2717977Shsul@eecs.umich.edu#define CLUSTER_USAGE_NVRAM ((long)2) 2727977Shsul@eecs.umich.edu 2737977Shsul@eecs.umich.edu/* 2747977Shsul@eecs.umich.edu * The "memory descriptor table" portion of the HWRPB. 2757977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size and there is a 2767977Shsul@eecs.umich.edu * variable number of per-cpu slots, hence this must be a separate structure. 2777977Shsul@eecs.umich.edu * Also note that the memory descriptor table contains a fixed portion plus 2787977Shsul@eecs.umich.edu * a variable number of "memory cluster descriptors" (one for each "cluster" 2797977Shsul@eecs.umich.edu * of memory). 2807977Shsul@eecs.umich.edu */ 2817977Shsul@eecs.umich.edustruct rpb_mdt { 2828013Sbinkertn@umich.edu long rpb_checksum; /* 000: checksum of entire mem desc table */ 2838013Sbinkertn@umich.edu long rpb_impaddr; /* 008: PA of implementation dep info */ 2848013Sbinkertn@umich.edu long rpb_numcl; /* 010: number of clusters */ 2857977Shsul@eecs.umich.edu struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */ 2867977Shsul@eecs.umich.edu}; 2877977Shsul@eecs.umich.edu 2887977Shsul@eecs.umich.edu/* 2897977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB, for serial line 2907977Shsul@eecs.umich.edu * UART console device. 2917977Shsul@eecs.umich.edu */ 2927977Shsul@eecs.umich.edustruct ctb_tt { 2938019Sbenash@umich.edu 2948019Sbenash@umich.edu long ctb_type; /* 0: always 4 */ 2958019Sbenash@umich.edu long ctb_unit; /* 8: */ 2968019Sbenash@umich.edu long ctb_reserved; /* 16: */ 2978019Sbenash@umich.edu long ctb_len; /* 24: bytes of info */ 2988019Sbenash@umich.edu long ctb_ipl; /* 32: console ipl level */ 2998019Sbenash@umich.edu long ctb_tintr_vec; /* 40: transmit vec (0x800) */ 3008019Sbenash@umich.edu long ctb_rintr_vec; /* 48: receive vec (0x800) */ 3018019Sbenash@umich.edu#define CTB_GRAPHICS 3 /* graphics device */ 3028019Sbenash@umich.edu#define CTB_NETWORK 0xC0 /* network device */ 3038019Sbenash@umich.edu#define CTB_PRINTERPORT 2 /* printer port on the SCC */ 3048019Sbenash@umich.edu long ctb_term_type; /* 56: terminal type */ 3058019Sbenash@umich.edu long ctb_keybd_type; /* 64: keyboard nationality */ 3068019Sbenash@umich.edu long ctb_keybd_trans; /* 72: trans. table addr */ 3078019Sbenash@umich.edu long ctb_keybd_map; /* 80: map table addr */ 3088019Sbenash@umich.edu long ctb_keybd_state; /* 88: keyboard flags */ 3098019Sbenash@umich.edu long ctb_keybd_last; /* 96: last key entered */ 3108019Sbenash@umich.edu long ctb_font_us; /* 104: US font table addr */ 3118019Sbenash@umich.edu long ctb_font_mcs; /* 112: MCS font table addr */ 3128019Sbenash@umich.edu long ctb_font_width; /* 120: font width, height */ 3138019Sbenash@umich.edu long ctb_font_height; /* 128: in pixels */ 3148019Sbenash@umich.edu long ctb_mon_width; /* 136: monitor width, height */ 3158019Sbenash@umich.edu long ctb_mon_height; /* 144: in pixels */ 3168019Sbenash@umich.edu long ctb_dpi; /* 152: monitor dots per inch */ 3178019Sbenash@umich.edu long ctb_planes; /* 160: # of planes */ 3188019Sbenash@umich.edu long ctb_cur_width; /* 168: cursor width, height */ 3198019Sbenash@umich.edu long ctb_cur_height; /* 176: in pixels */ 3208019Sbenash@umich.edu long ctb_head_cnt; /* 184: # of heads */ 3218019Sbenash@umich.edu long ctb_opwindow; /* 192: opwindow on screen */ 3228019Sbenash@umich.edu long ctb_head_offset; /* 200: offset to head info */ 3238019Sbenash@umich.edu long ctb_putchar; /* 208: output char to TURBO */ 3248019Sbenash@umich.edu long ctb_io_state; /* 216: I/O flags */ 3258019Sbenash@umich.edu long ctb_listen_state; /* 224: listener flags */ 3268019Sbenash@umich.edu long ctb_xaddr; /* 232: extended info addr */ 3278019Sbenash@umich.edu long ctb_turboslot; /* 248: TURBOchannel slot # */ 3288019Sbenash@umich.edu long ctb_server_off; /* 256: offset to server info */ 3298019Sbenash@umich.edu long ctb_line_off; /* 264: line parameter offset */ 3308019Sbenash@umich.edu char ctb_csd; /* 272: console specific data */ 3317977Shsul@eecs.umich.edu}; 3327977Shsul@eecs.umich.edu 3337977Shsul@eecs.umich.edu/* 3347977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB. 3357977Shsul@eecs.umich.edu */ 3367977Shsul@eecs.umich.edustruct rpb_ctb { 3378013Sbinkertn@umich.edu long rpb_type; /* 000: console type */ 3388013Sbinkertn@umich.edu long rpb_unit; /* 008: console unit */ 3398013Sbinkertn@umich.edu long rpb_resv; /* 010: reserved */ 3408013Sbinkertn@umich.edu long rpb_length; /* 018: byte length of device dep portion */ 3418013Sbinkertn@umich.edu long rpb_first; /* 000: first field of device dep portion */ 3427977Shsul@eecs.umich.edu}; 3437977Shsul@eecs.umich.edu 3447977Shsul@eecs.umich.edu/* 3457977Shsul@eecs.umich.edu * The physical/virtual map for the console routine block. 3467977Shsul@eecs.umich.edu */ 3477977Shsul@eecs.umich.edustruct rpb_map { 3488013Sbinkertn@umich.edu long rpb_virt; /* virtual address for map entry */ 3498013Sbinkertn@umich.edu long rpb_phys; /* phys address for map entry */ 3508013Sbinkertn@umich.edu long rpb_pgcount; /* page count for map entry */ 3517977Shsul@eecs.umich.edu}; 3527977Shsul@eecs.umich.edu 3537977Shsul@eecs.umich.edu/* 3547977Shsul@eecs.umich.edu * The "Console Routine Block" portion of the HWRPB. 3557977Shsul@eecs.umich.edu * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR). 3567977Shsul@eecs.umich.edu */ 3577977Shsul@eecs.umich.edustruct rpb_crb { 3588013Sbinkertn@umich.edu long rpb_va_disp; /* va of call-back dispatch rtn */ 3598013Sbinkertn@umich.edu long rpb_pa_disp; /* pa of call-back dispatch rtn */ 3608013Sbinkertn@umich.edu long rpb_va_fixup; /* va of call-back fixup rtn */ 3618013Sbinkertn@umich.edu long rpb_pa_fixup; /* pa of call-back fixup rtn */ 3628013Sbinkertn@umich.edu long rpb_num; /* number of entries in phys/virt map */ 3638013Sbinkertn@umich.edu long rpb_mapped_pages; /* Number of pages to be mapped */ 3648013Sbinkertn@umich.edu struct rpb_map rpb_map[1]; /* first instance of a map entry */ 3657977Shsul@eecs.umich.edu}; 3667977Shsul@eecs.umich.edu 3677977Shsul@eecs.umich.edu/* 3687977Shsul@eecs.umich.edu * These macros define where within the HWRPB the CTB and CRB are located. 3697977Shsul@eecs.umich.edu */ 3708013Sbinkertn@umich.edu#define CTB_SETUP \ 3718013Sbinkertn@umich.edu ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off))) 3728013Sbinkertn@umich.edu 3738013Sbinkertn@umich.edu#define CRB_SETUP \ 3748013Sbinkertn@umich.edu ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off))) 3757977Shsul@eecs.umich.edu 3767977Shsul@eecs.umich.edu/* 3777977Shsul@eecs.umich.edu * The "Dynamic System Recognition" portion of the HWRPB. 3787977Shsul@eecs.umich.edu * It is used to obtain the platform specific data need to allow 3797977Shsul@eecs.umich.edu * the platform define the platform name, the platform SMM and LURT 3807977Shsul@eecs.umich.edu * data for software licensing 3817977Shsul@eecs.umich.edu */ 3827977Shsul@eecs.umich.edustruct rpb_dsr { 3838013Sbinkertn@umich.edu long rpb_smm; /* SMM nubber used by LMF */ 3848013Sbinkertn@umich.edu ulong rpb_lurt_off; /* offset to LURT table */ 3858013Sbinkertn@umich.edu ulong rpb_sysname_off; /* offset to sysname char count */ 3868013Sbinkertn@umich.edu int lurt[10]; /* XXM has one LURT entry */ 3877977Shsul@eecs.umich.edu}; 388