1/* 2 * Copyright (c) 1990 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30/* 31 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 32 * All rights reserved. 33 * 34 * Author: Keith Bostic, Chris G. Demetriou 35 * 36 * Permission to use, copy, modify and distribute this software and 37 * its documentation is hereby granted, provided that both the copyright 38 * notice and this permission notice appear in all copies of the 39 * software, derivative works or modified versions, and any portions 40 * thereof, and that both notices appear in supporting documentation. 41 * 42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 44 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 45 * 46 * Carnegie Mellon requests users of this software to return to 47 * 48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 49 * School of Computer Science 50 * Carnegie Mellon University 51 * Pittsburgh PA 15213-3890 52 * 53 * any improvements or extensions that they make and grant Carnegie the 54 * rights to redistribute these changes. 55 */ 56 57/* 58 * Defines for the architected startup addresses. 59 */ 60#define HWRPB_ADDR 0x10000000 /* 256 MB */ 61#define BOOT_ADDR 0x20000000 /* 512 MB */ 62#define PGTBL_ADDR 0x40000000 /* 1 GB */ 63 64/* 65 * Values for the "haltcode" field in the per-cpu portion of the HWRPB 66 * 67 * Bit defines for the "sysvar" field in the HWRPB. 68 * Each platform has different values for SYSBOARD and IOBOARD bits. 69 */ 70#define HALT_PWRUP 0 /* power up */ 71#define HALT_OPR 1 /* operator issued halt cmd */ 72#define HALT_KSTK 2 /* kernel stack not valid */ 73#define HALT_SCBB 3 /* invalid SCBB */ 74#define HALT_PTBR 4 /* invalid PTBR */ 75#define HALT_EXE 5 /* kernel executed halt instruction */ 76#define HALT_DBLE 6 /* double error abort */ 77 78/* 79 * Bit defines for the "state" field in the per-cpu portion of the HWRPB 80 */ 81#define STATE_BIP 0x00000001 /* bootstrap in progress */ 82#define STATE_RC 0x00000002 /* restart capable */ 83#define STATE_PA 0x00000004 /* processor available to OS */ 84#define STATE_PP 0x00000008 /* processor present */ 85#define STATE_OH 0x00000010 /* operator halted */ 86#define STATE_CV 0x00000020 /* context valid */ 87#define STATE_PV 0x00000040 /* PALcode valid */ 88#define STATE_PMV 0x00000080 /* PALcode memory valid */ 89#define STATE_PL 0x00000100 /* PALcode loaded */ 90#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */ 91#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */ 92#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */ 93#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */ 94#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */ 95#define STATE_HALT 0x00040000 /* Remain halted (no restart) */ 96 97 98#define SV_PF_RSVD 0x00000000 /* RESERVED */ 99#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */ 100#define SV_MPCAP 0x00000001 /* MP capable */ 101#define SV_PF_UNITED 0x00000020 /* United */ 102#define SV_PF_SEPARATE 0x00000040 /* Separate */ 103#define SV_PF_FULLBB 0x00000060 /* Full battery backup */ 104#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */ 105#define SV_PF_RESTART 0x00000100 /* Powerfail restart */ 106 107#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */ 108 109#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */ 110#define SV_SANDPIPER 0x00000400 /* others define system platforms */ 111#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */ 112#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */ 113#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */ 114#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */ 115#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */ 116#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */ 117#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */ 118 119#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */ 120 121#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */ 122 123/* 124 * Values for the "console type" field in the CTB portion of the HWRPB 125 */ 126#define CONS_NONE 0 /* no console present */ 127#define CONS_SRVC 1 /* console is service processor */ 128#define CONS_DZ 2 /* console is dz/dl VT device */ 129#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/ 130#define CONS_REM 4 /* cons is remote, protocal enet/MOP */ 131 132/* 133 * PALcode variants that we're interested in. 134 * Used as indices into the "palrev_avail" array in the per-cpu portion 135 * of the HWRPB. 136 */ 137#define PALvar_reserved 0 138#define PALvar_OpenVMS 1 139#define PALvar_OSF1 2 140 141/* 142 * The Alpha restart parameter block, which is a page or 2 in low memory 143 */ 144struct rpb { 145 struct rpb *rpb_selfref; /* 000: physical self-reference */ 146 long rpb_string; /* 008: contains string "HWRPB" */ 147 long rpb_vers; /* 010: HWRPB version number */ 148 ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */ 149 ulong rpb_cpuid; /* 020: primary cpu id */ 150 ulong rpb_pagesize; /* 028: page size in bytes */ 151 ulong rpb_addrbits; /* 030: number of phys addr bits */ 152 ulong rpb_maxasn; /* 038: max valid ASN */ 153 char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */ 154 ulong grpb_systype; /* 050: system type */ 155 long rpb_sysvar; /* 058: system variation */ 156 long rpb_sysrev; /* 060: system revision */ 157 ulong rpb_clock; /* 068: scaled interval clock intr freq */ 158 ulong rpb_counter; /* 070: cycle counter frequency */ 159 ulong rpb_vptb; /* 078: virtual page table base */ 160 long rpb_res1; /* 080: reserved */ 161 ulong rpb_trans_off; /* 088: offset to translation buffer hint */ 162 ulong rpb_numprocs; /* 090: number of processor slots */ 163 ulong rpb_slotsize; /* 098: per-cpu slot size */ 164 ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */ 165 ulong rpb_num_ctb; /* 0A8: number of CTBs */ 166 ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */ 167 ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */ 168 ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */ 169 ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */ 170 ulong rpb_config_off; /* 0D0: offset to config data block */ 171 ulong rpb_fru_off; /* 0D8: offset to FRU table */ 172 void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */ 173 long rpb_saveterm_pv; /* 0E8: proc value for save term routine */ 174 void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */ 175 long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */ 176 void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */ 177 long rpb_restart_pv; /* 108: proc value for CPU restart routine */ 178 long rpb_software; /* 110: used to determine presence of kdebug */ 179 long rpb_hardware; /* 118: reserved for hardware */ 180 long rpb_checksum; /* 120: checksum of prior entries in rpb */ 181 long rpb_rxrdy; /* 128: receive ready bitmask */ 182 long rpb_txrdy; /* 130: transmit ready bitmask */ 183 ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */ 184}; 185 186#define rpb_kdebug rpb_software 187 188#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23)) 189 190/* 191 * This is the format for the boot/restart HWPCB. It must match the 192 * initial fields of the pcb structure as defined in pcb.h, but must 193 * additionally contain the appropriate amount of padding to line up 194 * with formats used by other palcode types. 195 */ 196struct bootpcb { 197 long rpb_ksp; /* 000: kernel stack pointer */ 198 long rpb_usp; /* 008: user stack pointer */ 199 long rpb_ptbr; /* 010: page table base register */ 200 int rpb_cc; /* 018: cycle counter */ 201 int rpb_asn; /* 01C: address space number */ 202 long rpb_proc_uniq; /* 020: proc/thread unique value */ 203 long rpb_fen; /* 028: floating point enable */ 204 long rpb_palscr[2]; /* 030: pal scratch area */ 205 long rpb_pcbpad[8]; /* 040: padding for fixed size */ 206}; 207 208/* 209 * Inter-Console Communications Buffer 210 * Used for the primary processor to communcate with the console 211 * of secondary processors. 212 */ 213struct iccb { 214 uint iccb_rxlen; /* receive length in bytes */ 215 uint iccb_txlen; /* transmit length in bytes */ 216 char iccb_rxbuf[80]; /* receive buffer */ 217 char iccb_txbuf[80]; /* transmit buffer */ 218}; 219 220/* 221 * The per-cpu portion of the Alpha HWRPB. 222 * Note that the main portion of the HWRPB is of variable size, 223 * hence this must be a separate structure. 224 * 225 */ 226struct rpb_percpu { 227 struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */ 228 long rpb_state; /* 080: per-cpu state bits */ 229 long rpb_palmem; /* 088: palcode memory length */ 230 long rpb_palscratch; /* 090: palcode scratch length */ 231 long rpb_palmem_addr; /* 098: phys addr of palcode mem space */ 232 long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */ 233 long rpb_palrev; /* 0A8: PALcode rev required */ 234 long rpb_proctype; /* 0B0: processor type */ 235 long rpb_procvar; /* 0B8: processor variation */ 236 long rpb_procrev; /* 0C0: processor revision */ 237 char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */ 238 long rpb_logout; /* 0D8: phys addr of logout area */ 239 long rpb_logout_len; /* 0E0: length in bytes of logout area */ 240 long rpb_haltpb; /* 0E8: halt pcb base */ 241 long rpb_haltpc; /* 0F0: halt pc */ 242 long rpb_haltps; /* 0F8: halt ps */ 243 long rpb_haltal; /* 100: halt arg list (R25) */ 244 long rpb_haltra; /* 108: halt return address (R26) */ 245 long rpb_haltpv; /* 110: halt procedure value (R27) */ 246 long rpb_haltcode; /* 118: reason for halt */ 247 long rpb_software; /* 120: for software */ 248 struct iccb rpb_iccb; /* 128: inter-console communications buffer */ 249 long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */ 250 long rpb_pcrsvd[6]; /* 250: reserved for arch use */ 251/* the dump stack grows from the end of the rpb page not to reach here */ 252}; 253 254/* The firmware revision is in the (unused) first entry of palrevs available */ 255#define rpb_firmrev rpb_palrev_avail[0] 256 257/* 258 * The memory cluster descriptor. 259 */ 260struct rpb_cluster { 261 long rpb_pfn; /* 000: starting PFN of this cluster */ 262 long rpb_pfncount; /* 008: count of PFNs in this cluster */ 263 long rpb_pfntested; /* 010: count of tested PFNs in cluster */ 264 long rpb_va; /* 018: va of bitmap */ 265 long rpb_pa; /* 020: pa of bitmap */ 266 long rpb_checksum; /* 028: checksum of bitmap */ 267 long rpb_usage; /* 030: usage of cluster */ 268}; 269#define CLUSTER_USAGE_OS ((long)0) 270#define CLUSTER_USAGE_PAL ((long)1) 271#define CLUSTER_USAGE_NVRAM ((long)2) 272 273/* 274 * The "memory descriptor table" portion of the HWRPB. 275 * Note that the main portion of the HWRPB is of variable size and there is a 276 * variable number of per-cpu slots, hence this must be a separate structure. 277 * Also note that the memory descriptor table contains a fixed portion plus 278 * a variable number of "memory cluster descriptors" (one for each "cluster" 279 * of memory). 280 */ 281struct rpb_mdt { 282 long rpb_checksum; /* 000: checksum of entire mem desc table */ 283 long rpb_impaddr; /* 008: PA of implementation dep info */ 284 long rpb_numcl; /* 010: number of clusters */ 285 struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */ 286}; 287 288/* 289 * The "Console Terminal Block" portion of the HWRPB, for serial line 290 * UART console device. 291 */ 292struct ctb_tt { 293 294 long ctb_type; /* 0: always 4 */ 295 long ctb_unit; /* 8: */ 296 long ctb_reserved; /* 16: */ 297 long ctb_len; /* 24: bytes of info */ 298 long ctb_ipl; /* 32: console ipl level */ 299 long ctb_tintr_vec; /* 40: transmit vec (0x800) */ 300 long ctb_rintr_vec; /* 48: receive vec (0x800) */ 301#define CTB_GRAPHICS 3 /* graphics device */ 302#define CTB_NETWORK 0xC0 /* network device */ 303#define CTB_PRINTERPORT 2 /* printer port on the SCC */ 304 long ctb_term_type; /* 56: terminal type */ 305 long ctb_keybd_type; /* 64: keyboard nationality */ 306 long ctb_keybd_trans; /* 72: trans. table addr */ 307 long ctb_keybd_map; /* 80: map table addr */ 308 long ctb_keybd_state; /* 88: keyboard flags */ 309 long ctb_keybd_last; /* 96: last key entered */ 310 long ctb_font_us; /* 104: US font table addr */ 311 long ctb_font_mcs; /* 112: MCS font table addr */ 312 long ctb_font_width; /* 120: font width, height */ 313 long ctb_font_height; /* 128: in pixels */ 314 long ctb_mon_width; /* 136: monitor width, height */ 315 long ctb_mon_height; /* 144: in pixels */ 316 long ctb_dpi; /* 152: monitor dots per inch */ 317 long ctb_planes; /* 160: # of planes */ 318 long ctb_cur_width; /* 168: cursor width, height */ 319 long ctb_cur_height; /* 176: in pixels */ 320 long ctb_head_cnt; /* 184: # of heads */ 321 long ctb_opwindow; /* 192: opwindow on screen */ 322 long ctb_head_offset; /* 200: offset to head info */ 323 long ctb_putchar; /* 208: output char to TURBO */ 324 long ctb_io_state; /* 216: I/O flags */ 325 long ctb_listen_state; /* 224: listener flags */ 326 long ctb_xaddr; /* 232: extended info addr */ 327 long ctb_turboslot; /* 248: TURBOchannel slot # */ 328 long ctb_server_off; /* 256: offset to server info */ 329 long ctb_line_off; /* 264: line parameter offset */ 330 char ctb_csd; /* 272: console specific data */ 331}; 332 333/* 334 * The "Console Terminal Block" portion of the HWRPB. 335 */ 336struct rpb_ctb { 337 long rpb_type; /* 000: console type */ 338 long rpb_unit; /* 008: console unit */ 339 long rpb_resv; /* 010: reserved */ 340 long rpb_length; /* 018: byte length of device dep portion */ 341 long rpb_first; /* 000: first field of device dep portion */ 342}; 343 344/* 345 * The physical/virtual map for the console routine block. 346 */ 347struct rpb_map { 348 long rpb_virt; /* virtual address for map entry */ 349 long rpb_phys; /* phys address for map entry */ 350 long rpb_pgcount; /* page count for map entry */ 351}; 352 353/* 354 * The "Console Routine Block" portion of the HWRPB. 355 * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR). 356 */ 357struct rpb_crb { 358 long rpb_va_disp; /* va of call-back dispatch rtn */ 359 long rpb_pa_disp; /* pa of call-back dispatch rtn */ 360 long rpb_va_fixup; /* va of call-back fixup rtn */ 361 long rpb_pa_fixup; /* pa of call-back fixup rtn */ 362 long rpb_num; /* number of entries in phys/virt map */ 363 long rpb_mapped_pages; /* Number of pages to be mapped */ 364 struct rpb_map rpb_map[1]; /* first instance of a map entry */ 365}; 366 367/* 368 * These macros define where within the HWRPB the CTB and CRB are located. 369 */ 370#define CTB_SETUP \ 371 ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off))) 372 373#define CRB_SETUP \ 374 ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off))) 375 376/* 377 * The "Dynamic System Recognition" portion of the HWRPB. 378 * It is used to obtain the platform specific data need to allow 379 * the platform define the platform name, the platform SMM and LURT 380 * data for software licensing 381 */ 382struct rpb_dsr { 383 long rpb_smm; /* SMM nubber used by LMF */ 384 ulong rpb_lurt_off; /* offset to LURT table */ 385 ulong rpb_sysname_off; /* offset to sysname char count */ 386 int lurt[10]; /* XXM has one LURT entry */ 387}; 388