rpb.h revision 8013
18012Ssaidi@eecs.umich.edu/* 28013Sbinkertn@umich.edu * Copyright 1990 Hewlett-Packard Development Company, L.P. 38013Sbinkertn@umich.edu * 48013Sbinkertn@umich.edu * Permission is hereby granted, free of charge, to any person 58013Sbinkertn@umich.edu * obtaining a copy of this software and associated documentation 68013Sbinkertn@umich.edu * files (the "Software"), to deal in the Software without 78013Sbinkertn@umich.edu * restriction, including without limitation the rights to use, copy, 88013Sbinkertn@umich.edu * modify, merge, publish, distribute, sublicense, and/or sell copies 98013Sbinkertn@umich.edu * of the Software, and to permit persons to whom the Software is 108013Sbinkertn@umich.edu * furnished to do so, subject to the following conditions: 118013Sbinkertn@umich.edu * 128013Sbinkertn@umich.edu * The above copyright notice and this permission notice shall be 138013Sbinkertn@umich.edu * included in all copies or substantial portions of the Software. 148013Sbinkertn@umich.edu * 158013Sbinkertn@umich.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 168013Sbinkertn@umich.edu * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 178013Sbinkertn@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 188013Sbinkertn@umich.edu * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 198013Sbinkertn@umich.edu * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 208013Sbinkertn@umich.edu * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 218013Sbinkertn@umich.edu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 228013Sbinkertn@umich.edu * SOFTWARE. 238013Sbinkertn@umich.edu */ 248012Ssaidi@eecs.umich.edu 257977Shsul@eecs.umich.edu/* 267977Shsul@eecs.umich.edu * Defines for the architected startup addresses. 277977Shsul@eecs.umich.edu */ 287977Shsul@eecs.umich.edu#define HWRPB_ADDR 0x10000000 /* 256 MB */ 297977Shsul@eecs.umich.edu#define BOOT_ADDR 0x20000000 /* 512 MB */ 307977Shsul@eecs.umich.edu#define PGTBL_ADDR 0x40000000 /* 1 GB */ 317977Shsul@eecs.umich.edu 327977Shsul@eecs.umich.edu/* 337977Shsul@eecs.umich.edu * Values for the "haltcode" field in the per-cpu portion of the HWRPB 347977Shsul@eecs.umich.edu * 357977Shsul@eecs.umich.edu * Bit defines for the "sysvar" field in the HWRPB. 367977Shsul@eecs.umich.edu * Each platform has different values for SYSBOARD and IOBOARD bits. 377977Shsul@eecs.umich.edu */ 387977Shsul@eecs.umich.edu#define HALT_PWRUP 0 /* power up */ 397977Shsul@eecs.umich.edu#define HALT_OPR 1 /* operator issued halt cmd */ 407977Shsul@eecs.umich.edu#define HALT_KSTK 2 /* kernel stack not valid */ 417977Shsul@eecs.umich.edu#define HALT_SCBB 3 /* invalid SCBB */ 427977Shsul@eecs.umich.edu#define HALT_PTBR 4 /* invalid PTBR */ 437977Shsul@eecs.umich.edu#define HALT_EXE 5 /* kernel executed halt instruction */ 447977Shsul@eecs.umich.edu#define HALT_DBLE 6 /* double error abort */ 457977Shsul@eecs.umich.edu 467977Shsul@eecs.umich.edu/* 477977Shsul@eecs.umich.edu * Bit defines for the "state" field in the per-cpu portion of the HWRPB 487977Shsul@eecs.umich.edu */ 497977Shsul@eecs.umich.edu#define STATE_BIP 0x00000001 /* bootstrap in progress */ 507977Shsul@eecs.umich.edu#define STATE_RC 0x00000002 /* restart capable */ 517977Shsul@eecs.umich.edu#define STATE_PA 0x00000004 /* processor available to OS */ 527977Shsul@eecs.umich.edu#define STATE_PP 0x00000008 /* processor present */ 537977Shsul@eecs.umich.edu#define STATE_OH 0x00000010 /* operator halted */ 547977Shsul@eecs.umich.edu#define STATE_CV 0x00000020 /* context valid */ 557977Shsul@eecs.umich.edu#define STATE_PV 0x00000040 /* PALcode valid */ 567977Shsul@eecs.umich.edu#define STATE_PMV 0x00000080 /* PALcode memory valid */ 577977Shsul@eecs.umich.edu#define STATE_PL 0x00000100 /* PALcode loaded */ 587977Shsul@eecs.umich.edu#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */ 597977Shsul@eecs.umich.edu#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */ 607977Shsul@eecs.umich.edu#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */ 617977Shsul@eecs.umich.edu#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */ 627977Shsul@eecs.umich.edu#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */ 637977Shsul@eecs.umich.edu#define STATE_HALT 0x00040000 /* Remain halted (no restart) */ 647977Shsul@eecs.umich.edu 657977Shsul@eecs.umich.edu 667977Shsul@eecs.umich.edu#define SV_PF_RSVD 0x00000000 /* RESERVED */ 678013Sbinkertn@umich.edu#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */ 687977Shsul@eecs.umich.edu#define SV_MPCAP 0x00000001 /* MP capable */ 697977Shsul@eecs.umich.edu#define SV_PF_UNITED 0x00000020 /* United */ 707977Shsul@eecs.umich.edu#define SV_PF_SEPARATE 0x00000040 /* Separate */ 717977Shsul@eecs.umich.edu#define SV_PF_FULLBB 0x00000060 /* Full battery backup */ 727977Shsul@eecs.umich.edu#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */ 737977Shsul@eecs.umich.edu#define SV_PF_RESTART 0x00000100 /* Powerfail restart */ 747977Shsul@eecs.umich.edu 757977Shsul@eecs.umich.edu#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */ 767977Shsul@eecs.umich.edu 778013Sbinkertn@umich.edu#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */ 788013Sbinkertn@umich.edu#define SV_SANDPIPER 0x00000400 /* others define system platforms */ 797977Shsul@eecs.umich.edu#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */ 807977Shsul@eecs.umich.edu#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */ 817977Shsul@eecs.umich.edu#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */ 827977Shsul@eecs.umich.edu#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */ 837977Shsul@eecs.umich.edu#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */ 847977Shsul@eecs.umich.edu#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */ 857977Shsul@eecs.umich.edu#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */ 867977Shsul@eecs.umich.edu 877977Shsul@eecs.umich.edu#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */ 887977Shsul@eecs.umich.edu 897977Shsul@eecs.umich.edu#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */ 907977Shsul@eecs.umich.edu 917977Shsul@eecs.umich.edu/* 927977Shsul@eecs.umich.edu * Values for the "console type" field in the CTB portion of the HWRPB 937977Shsul@eecs.umich.edu */ 947977Shsul@eecs.umich.edu#define CONS_NONE 0 /* no console present */ 957977Shsul@eecs.umich.edu#define CONS_SRVC 1 /* console is service processor */ 967977Shsul@eecs.umich.edu#define CONS_DZ 2 /* console is dz/dl VT device */ 978013Sbinkertn@umich.edu#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/ 987977Shsul@eecs.umich.edu#define CONS_REM 4 /* cons is remote, protocal enet/MOP */ 997977Shsul@eecs.umich.edu 1007977Shsul@eecs.umich.edu/* 1017977Shsul@eecs.umich.edu * PALcode variants that we're interested in. 1027977Shsul@eecs.umich.edu * Used as indices into the "palrev_avail" array in the per-cpu portion 1037977Shsul@eecs.umich.edu * of the HWRPB. 1047977Shsul@eecs.umich.edu */ 1057977Shsul@eecs.umich.edu#define PALvar_reserved 0 1067977Shsul@eecs.umich.edu#define PALvar_OpenVMS 1 1077977Shsul@eecs.umich.edu#define PALvar_OSF1 2 1087977Shsul@eecs.umich.edu 1097977Shsul@eecs.umich.edu/* 1107977Shsul@eecs.umich.edu * The Alpha restart parameter block, which is a page or 2 in low memory 1117977Shsul@eecs.umich.edu */ 1127977Shsul@eecs.umich.edustruct rpb { 1137977Shsul@eecs.umich.edu struct rpb *rpb_selfref; /* 000: physical self-reference */ 1148013Sbinkertn@umich.edu long rpb_string; /* 008: contains string "HWRPB" */ 1158013Sbinkertn@umich.edu long rpb_vers; /* 010: HWRPB version number */ 1168013Sbinkertn@umich.edu ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */ 1178013Sbinkertn@umich.edu ulong rpb_cpuid; /* 020: primary cpu id */ 1188013Sbinkertn@umich.edu ulong rpb_pagesize; /* 028: page size in bytes */ 1198013Sbinkertn@umich.edu ulong rpb_addrbits; /* 030: number of phys addr bits */ 1208013Sbinkertn@umich.edu ulong rpb_maxasn; /* 038: max valid ASN */ 1218013Sbinkertn@umich.edu char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */ 1228013Sbinkertn@umich.edu ulong grpb_systype; /* 050: system type */ 1238013Sbinkertn@umich.edu long rpb_sysvar; /* 058: system variation */ 1248013Sbinkertn@umich.edu long rpb_sysrev; /* 060: system revision */ 1258013Sbinkertn@umich.edu ulong rpb_clock; /* 068: scaled interval clock intr freq */ 1268013Sbinkertn@umich.edu ulong rpb_counter; /* 070: cycle counter frequency */ 1278013Sbinkertn@umich.edu ulong rpb_vptb; /* 078: virtual page table base */ 1288013Sbinkertn@umich.edu long rpb_res1; /* 080: reserved */ 1298013Sbinkertn@umich.edu ulong rpb_trans_off; /* 088: offset to translation buffer hint */ 1308013Sbinkertn@umich.edu ulong rpb_numprocs; /* 090: number of processor slots */ 1318013Sbinkertn@umich.edu ulong rpb_slotsize; /* 098: per-cpu slot size */ 1328013Sbinkertn@umich.edu ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */ 1338013Sbinkertn@umich.edu ulong rpb_num_ctb; /* 0A8: number of CTBs */ 1348013Sbinkertn@umich.edu ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */ 1358013Sbinkertn@umich.edu ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */ 1368013Sbinkertn@umich.edu ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */ 1378013Sbinkertn@umich.edu ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */ 1388013Sbinkertn@umich.edu ulong rpb_config_off; /* 0D0: offset to config data block */ 1398013Sbinkertn@umich.edu ulong rpb_fru_off; /* 0D8: offset to FRU table */ 1408013Sbinkertn@umich.edu void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */ 1418013Sbinkertn@umich.edu long rpb_saveterm_pv; /* 0E8: proc value for save term routine */ 1428013Sbinkertn@umich.edu void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */ 1438013Sbinkertn@umich.edu long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */ 1448013Sbinkertn@umich.edu void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */ 1458013Sbinkertn@umich.edu long rpb_restart_pv; /* 108: proc value for CPU restart routine */ 1468013Sbinkertn@umich.edu long rpb_software; /* 110: used to determine presence of kdebug */ 1478013Sbinkertn@umich.edu long rpb_hardware; /* 118: reserved for hardware */ 1488013Sbinkertn@umich.edu long rpb_checksum; /* 120: checksum of prior entries in rpb */ 1498013Sbinkertn@umich.edu long rpb_rxrdy; /* 128: receive ready bitmask */ 1508013Sbinkertn@umich.edu long rpb_txrdy; /* 130: transmit ready bitmask */ 1518013Sbinkertn@umich.edu ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */ 1527977Shsul@eecs.umich.edu}; 1537977Shsul@eecs.umich.edu 1547977Shsul@eecs.umich.edu#define rpb_kdebug rpb_software 1557977Shsul@eecs.umich.edu 1567977Shsul@eecs.umich.edu#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23)) 1577977Shsul@eecs.umich.edu 1587977Shsul@eecs.umich.edu/* 1597977Shsul@eecs.umich.edu * This is the format for the boot/restart HWPCB. It must match the 1607977Shsul@eecs.umich.edu * initial fields of the pcb structure as defined in pcb.h, but must 1617977Shsul@eecs.umich.edu * additionally contain the appropriate amount of padding to line up 1627977Shsul@eecs.umich.edu * with formats used by other palcode types. 1637977Shsul@eecs.umich.edu */ 1647977Shsul@eecs.umich.edustruct bootpcb { 1658013Sbinkertn@umich.edu long rpb_ksp; /* 000: kernel stack pointer */ 1668013Sbinkertn@umich.edu long rpb_usp; /* 008: user stack pointer */ 1678013Sbinkertn@umich.edu long rpb_ptbr; /* 010: page table base register */ 1688013Sbinkertn@umich.edu int rpb_cc; /* 018: cycle counter */ 1698013Sbinkertn@umich.edu int rpb_asn; /* 01C: address space number */ 1708013Sbinkertn@umich.edu long rpb_proc_uniq; /* 020: proc/thread unique value */ 1718013Sbinkertn@umich.edu long rpb_fen; /* 028: floating point enable */ 1728013Sbinkertn@umich.edu long rpb_palscr[2]; /* 030: pal scratch area */ 1738013Sbinkertn@umich.edu long rpb_pcbpad[8]; /* 040: padding for fixed size */ 1747977Shsul@eecs.umich.edu}; 1757977Shsul@eecs.umich.edu 1767977Shsul@eecs.umich.edu/* 1777977Shsul@eecs.umich.edu * Inter-Console Communications Buffer 1787977Shsul@eecs.umich.edu * Used for the primary processor to communcate with the console 1797977Shsul@eecs.umich.edu * of secondary processors. 1807977Shsul@eecs.umich.edu */ 1817977Shsul@eecs.umich.edustruct iccb { 1828013Sbinkertn@umich.edu uint iccb_rxlen; /* receive length in bytes */ 1838013Sbinkertn@umich.edu uint iccb_txlen; /* transmit length in bytes */ 1848013Sbinkertn@umich.edu char iccb_rxbuf[80]; /* receive buffer */ 1858013Sbinkertn@umich.edu char iccb_txbuf[80]; /* transmit buffer */ 1867977Shsul@eecs.umich.edu}; 1877977Shsul@eecs.umich.edu 1887977Shsul@eecs.umich.edu/* 1897977Shsul@eecs.umich.edu * The per-cpu portion of the Alpha HWRPB. 1907977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size, 1917977Shsul@eecs.umich.edu * hence this must be a separate structure. 1927977Shsul@eecs.umich.edu * 1937977Shsul@eecs.umich.edu */ 1947977Shsul@eecs.umich.edustruct rpb_percpu { 1957977Shsul@eecs.umich.edu struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */ 1968013Sbinkertn@umich.edu long rpb_state; /* 080: per-cpu state bits */ 1978013Sbinkertn@umich.edu long rpb_palmem; /* 088: palcode memory length */ 1988013Sbinkertn@umich.edu long rpb_palscratch; /* 090: palcode scratch length */ 1998013Sbinkertn@umich.edu long rpb_palmem_addr; /* 098: phys addr of palcode mem space */ 2008013Sbinkertn@umich.edu long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */ 2018013Sbinkertn@umich.edu long rpb_palrev; /* 0A8: PALcode rev required */ 2028013Sbinkertn@umich.edu long rpb_proctype; /* 0B0: processor type */ 2038013Sbinkertn@umich.edu long rpb_procvar; /* 0B8: processor variation */ 2048013Sbinkertn@umich.edu long rpb_procrev; /* 0C0: processor revision */ 2058013Sbinkertn@umich.edu char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */ 2068013Sbinkertn@umich.edu long rpb_logout; /* 0D8: phys addr of logout area */ 2078013Sbinkertn@umich.edu long rpb_logout_len; /* 0E0: length in bytes of logout area */ 2088013Sbinkertn@umich.edu long rpb_haltpb; /* 0E8: halt pcb base */ 2098013Sbinkertn@umich.edu long rpb_haltpc; /* 0F0: halt pc */ 2108013Sbinkertn@umich.edu long rpb_haltps; /* 0F8: halt ps */ 2118013Sbinkertn@umich.edu long rpb_haltal; /* 100: halt arg list (R25) */ 2128013Sbinkertn@umich.edu long rpb_haltra; /* 108: halt return address (R26) */ 2138013Sbinkertn@umich.edu long rpb_haltpv; /* 110: halt procedure value (R27) */ 2148013Sbinkertn@umich.edu long rpb_haltcode; /* 118: reason for halt */ 2158013Sbinkertn@umich.edu long rpb_software; /* 120: for software */ 2168013Sbinkertn@umich.edu struct iccb rpb_iccb; /* 128: inter-console communications buffer */ 2178013Sbinkertn@umich.edu long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */ 2188013Sbinkertn@umich.edu long rpb_pcrsvd[6]; /* 250: reserved for arch use */ 2197977Shsul@eecs.umich.edu/* the dump stack grows from the end of the rpb page not to reach here */ 2207977Shsul@eecs.umich.edu}; 2217977Shsul@eecs.umich.edu 2227977Shsul@eecs.umich.edu/* The firmware revision is in the (unused) first entry of palrevs available */ 2237977Shsul@eecs.umich.edu#define rpb_firmrev rpb_palrev_avail[0] 2247977Shsul@eecs.umich.edu 2257977Shsul@eecs.umich.edu/* 2267977Shsul@eecs.umich.edu * The memory cluster descriptor. 2277977Shsul@eecs.umich.edu */ 2287977Shsul@eecs.umich.edustruct rpb_cluster { 2298013Sbinkertn@umich.edu long rpb_pfn; /* 000: starting PFN of this cluster */ 2308013Sbinkertn@umich.edu long rpb_pfncount; /* 008: count of PFNs in this cluster */ 2318013Sbinkertn@umich.edu long rpb_pfntested; /* 010: count of tested PFNs in cluster */ 2328013Sbinkertn@umich.edu long rpb_va; /* 018: va of bitmap */ 2338013Sbinkertn@umich.edu long rpb_pa; /* 020: pa of bitmap */ 2348013Sbinkertn@umich.edu long rpb_checksum; /* 028: checksum of bitmap */ 2358013Sbinkertn@umich.edu long rpb_usage; /* 030: usage of cluster */ 2367977Shsul@eecs.umich.edu}; 2377977Shsul@eecs.umich.edu#define CLUSTER_USAGE_OS ((long)0) 2387977Shsul@eecs.umich.edu#define CLUSTER_USAGE_PAL ((long)1) 2397977Shsul@eecs.umich.edu#define CLUSTER_USAGE_NVRAM ((long)2) 2407977Shsul@eecs.umich.edu 2417977Shsul@eecs.umich.edu/* 2427977Shsul@eecs.umich.edu * The "memory descriptor table" portion of the HWRPB. 2437977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size and there is a 2447977Shsul@eecs.umich.edu * variable number of per-cpu slots, hence this must be a separate structure. 2457977Shsul@eecs.umich.edu * Also note that the memory descriptor table contains a fixed portion plus 2467977Shsul@eecs.umich.edu * a variable number of "memory cluster descriptors" (one for each "cluster" 2477977Shsul@eecs.umich.edu * of memory). 2487977Shsul@eecs.umich.edu */ 2497977Shsul@eecs.umich.edustruct rpb_mdt { 2508013Sbinkertn@umich.edu long rpb_checksum; /* 000: checksum of entire mem desc table */ 2518013Sbinkertn@umich.edu long rpb_impaddr; /* 008: PA of implementation dep info */ 2528013Sbinkertn@umich.edu long rpb_numcl; /* 010: number of clusters */ 2537977Shsul@eecs.umich.edu struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */ 2547977Shsul@eecs.umich.edu}; 2557977Shsul@eecs.umich.edu 2567977Shsul@eecs.umich.edu/* 2577977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB, for serial line 2587977Shsul@eecs.umich.edu * UART console device. 2597977Shsul@eecs.umich.edu */ 2607977Shsul@eecs.umich.edustruct ctb_tt { 2618013Sbinkertn@umich.edu long ctb_type; /* 000: console type */ 2628013Sbinkertn@umich.edu long ctb_unit; /* 008: console unit */ 2638013Sbinkertn@umich.edu long ctb_resv; /* 010: reserved */ 2648013Sbinkertn@umich.edu long ctb_length; /* 018: byte length of device dep portion */ 2658013Sbinkertn@umich.edu long ctb_csr; /* 020: CSR Address */ 2668013Sbinkertn@umich.edu long ctb_tivec; /* 028: <63>=tie; interrupt vector */ 2678013Sbinkertn@umich.edu long ctb_rivec; /* 030: <63>=rie; interrupt vector */ 2688013Sbinkertn@umich.edu long ctb_baud; /* 038: baud rate */ 2698013Sbinkertn@umich.edu long ctb_put_sts; /* 040: PUTS callback extended status */ 2708013Sbinkertn@umich.edu long ctb_get_sts; /* 048: GETS callback extended status */ 2718013Sbinkertn@umich.edu long ctb_rsvd[1]; /* 050: reserved for console use */ 2727977Shsul@eecs.umich.edu}; 2737977Shsul@eecs.umich.edu 2747977Shsul@eecs.umich.edu/* 2757977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB. 2767977Shsul@eecs.umich.edu */ 2777977Shsul@eecs.umich.edustruct rpb_ctb { 2788013Sbinkertn@umich.edu long rpb_type; /* 000: console type */ 2798013Sbinkertn@umich.edu long rpb_unit; /* 008: console unit */ 2808013Sbinkertn@umich.edu long rpb_resv; /* 010: reserved */ 2818013Sbinkertn@umich.edu long rpb_length; /* 018: byte length of device dep portion */ 2828013Sbinkertn@umich.edu long rpb_first; /* 000: first field of device dep portion */ 2837977Shsul@eecs.umich.edu}; 2847977Shsul@eecs.umich.edu 2857977Shsul@eecs.umich.edu/* 2867977Shsul@eecs.umich.edu * The physical/virtual map for the console routine block. 2877977Shsul@eecs.umich.edu */ 2887977Shsul@eecs.umich.edustruct rpb_map { 2898013Sbinkertn@umich.edu long rpb_virt; /* virtual address for map entry */ 2908013Sbinkertn@umich.edu long rpb_phys; /* phys address for map entry */ 2918013Sbinkertn@umich.edu long rpb_pgcount; /* page count for map entry */ 2927977Shsul@eecs.umich.edu}; 2937977Shsul@eecs.umich.edu 2947977Shsul@eecs.umich.edu/* 2957977Shsul@eecs.umich.edu * The "Console Routine Block" portion of the HWRPB. 2967977Shsul@eecs.umich.edu * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR). 2977977Shsul@eecs.umich.edu */ 2987977Shsul@eecs.umich.edustruct rpb_crb { 2998013Sbinkertn@umich.edu long rpb_va_disp; /* va of call-back dispatch rtn */ 3008013Sbinkertn@umich.edu long rpb_pa_disp; /* pa of call-back dispatch rtn */ 3018013Sbinkertn@umich.edu long rpb_va_fixup; /* va of call-back fixup rtn */ 3028013Sbinkertn@umich.edu long rpb_pa_fixup; /* pa of call-back fixup rtn */ 3038013Sbinkertn@umich.edu long rpb_num; /* number of entries in phys/virt map */ 3048013Sbinkertn@umich.edu long rpb_mapped_pages; /* Number of pages to be mapped */ 3058013Sbinkertn@umich.edu struct rpb_map rpb_map[1]; /* first instance of a map entry */ 3067977Shsul@eecs.umich.edu}; 3077977Shsul@eecs.umich.edu 3087977Shsul@eecs.umich.edu/* 3097977Shsul@eecs.umich.edu * These macros define where within the HWRPB the CTB and CRB are located. 3107977Shsul@eecs.umich.edu */ 3118013Sbinkertn@umich.edu#define CTB_SETUP \ 3128013Sbinkertn@umich.edu ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off))) 3138013Sbinkertn@umich.edu 3148013Sbinkertn@umich.edu#define CRB_SETUP \ 3158013Sbinkertn@umich.edu ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off))) 3167977Shsul@eecs.umich.edu 3177977Shsul@eecs.umich.edu/* 3187977Shsul@eecs.umich.edu * The "Dynamic System Recognition" portion of the HWRPB. 3197977Shsul@eecs.umich.edu * It is used to obtain the platform specific data need to allow 3207977Shsul@eecs.umich.edu * the platform define the platform name, the platform SMM and LURT 3217977Shsul@eecs.umich.edu * data for software licensing 3227977Shsul@eecs.umich.edu */ 3237977Shsul@eecs.umich.edustruct rpb_dsr { 3248013Sbinkertn@umich.edu long rpb_smm; /* SMM nubber used by LMF */ 3258013Sbinkertn@umich.edu ulong rpb_lurt_off; /* offset to LURT table */ 3268013Sbinkertn@umich.edu ulong rpb_sysname_off; /* offset to sysname char count */ 3278013Sbinkertn@umich.edu int lurt[10]; /* XXM has one LURT entry */ 3287977Shsul@eecs.umich.edu}; 329