ev5_impure.h revision 7997
17997Ssaidi@eecs.umich.edu#ifndef EV5_IMPURE_INCLUDED 27997Ssaidi@eecs.umich.edu#define EV5_IMPURE_INCLUDED 37997Ssaidi@eecs.umich.edu 47997Ssaidi@eecs.umich.edu/* 57997Ssaidi@eecs.umich.edu// This uses the Hudson file format from "impure.h" but with the fields from 67997Ssaidi@eecs.umich.edu// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 77997Ssaidi@eecs.umich.edu 87997Ssaidi@eecs.umich.edu//orig file: impure.sdl 97997Ssaidi@eecs.umich.edu//orig 107997Ssaidi@eecs.umich.edu//orig Abstract: PAL impure scratch area and logout area data structure definitions for 117997Ssaidi@eecs.umich.edu//orig Alpha firmware. 127997Ssaidi@eecs.umich.edu//orig 137997Ssaidi@eecs.umich.edu//orig 147997Ssaidi@eecs.umich.edu//orig module $pal_impure; 157997Ssaidi@eecs.umich.edu//orig 167997Ssaidi@eecs.umich.edu//orig Edit Date Who Description 177997Ssaidi@eecs.umich.edu//orig ---- --------- --- --------------------- 187997Ssaidi@eecs.umich.edu//orig 1 7-Jul-93 JEM Initial Entry 197997Ssaidi@eecs.umich.edu//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 207997Ssaidi@eecs.umich.edu//orig Delete mvptbr 217997Ssaidi@eecs.umich.edu//orig Calculate pal$logout from end of impure area 227997Ssaidi@eecs.umich.edu//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 237997Ssaidi@eecs.umich.edu//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl; 247997Ssaidi@eecs.umich.edu//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl, 257997Ssaidi@eecs.umich.edu//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock 267997Ssaidi@eecs.umich.edu//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4 277997Ssaidi@eecs.umich.edu//orig add cns$ipr_offset 287997Ssaidi@eecs.umich.edu//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 297997Ssaidi@eecs.umich.edu//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame 307997Ssaidi@eecs.umich.edu//orig 317997Ssaidi@eecs.umich.edu//orig 327997Ssaidi@eecs.umich.edu//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file 337997Ssaidi@eecs.umich.edu//orig 347997Ssaidi@eecs.umich.edu 357997Ssaidi@eecs.umich.edu** Macros for saving/restoring data to/from the PAL impure scratch 367997Ssaidi@eecs.umich.edu** area. 377997Ssaidi@eecs.umich.edu** 387997Ssaidi@eecs.umich.edu** The console save state area is larger than the addressibility 397997Ssaidi@eecs.umich.edu** of the HW_LD/ST instructions (10-bit signed byte displacement), 407997Ssaidi@eecs.umich.edu** so some adjustments to the base offsets, as well as the offsets 417997Ssaidi@eecs.umich.edu** within each base region, are necessary. 427997Ssaidi@eecs.umich.edu** 437997Ssaidi@eecs.umich.edu** The console save state area is divided into two segments; the 447997Ssaidi@eecs.umich.edu** CPU-specific segment and the platform-specific segment. The 457997Ssaidi@eecs.umich.edu** state that is saved in the CPU-specific segment includes GPRs, 467997Ssaidi@eecs.umich.edu** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 477997Ssaidi@eecs.umich.edu** in the platform-specific segment. 487997Ssaidi@eecs.umich.edu** 497997Ssaidi@eecs.umich.edu** The impure pointer will need to be adjusted by a different offset 507997Ssaidi@eecs.umich.edu** value for each region within a given segment. The SAVE and RESTORE 517997Ssaidi@eecs.umich.edu** macros will auto-magically adjust the offsets accordingly. 527997Ssaidi@eecs.umich.edu** 537997Ssaidi@eecs.umich.edu*/ 547997Ssaidi@eecs.umich.edu#if 0 557997Ssaidi@eecs.umich.edu#define SAVE_GPR(reg,offset,base) \ 567997Ssaidi@eecs.umich.edu stq_p reg, ((offset-0x200)&0x3FF)(base) 577997Ssaidi@eecs.umich.edu 587997Ssaidi@eecs.umich.edu#define RESTORE_GPR(reg,offset,base) \ 597997Ssaidi@eecs.umich.edu ldq_p reg, ((offset-0x200)&0x3FF)(base) 607997Ssaidi@eecs.umich.edu 617997Ssaidi@eecs.umich.edu 627997Ssaidi@eecs.umich.edu#define SAVE_FPR(reg,offset,base) \ 637997Ssaidi@eecs.umich.edu stt reg, ((offset-0x200)&0x3FF)(base) 647997Ssaidi@eecs.umich.edu 657997Ssaidi@eecs.umich.edu#define RESTORE_FPR(reg,offset,base) \ 667997Ssaidi@eecs.umich.edu ldt reg, ((offset-0x200)&0x3FF)(base) 677997Ssaidi@eecs.umich.edu 687997Ssaidi@eecs.umich.edu#define SAVE_IPR(reg,offset,base) \ 697997Ssaidi@eecs.umich.edu mfpr v0, reg; \ 707997Ssaidi@eecs.umich.edu stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base) 717997Ssaidi@eecs.umich.edu 727997Ssaidi@eecs.umich.edu#define RESTORE_IPR(reg,offset,base) \ 737997Ssaidi@eecs.umich.edu ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \ 747997Ssaidi@eecs.umich.edu mtpr v0, reg 757997Ssaidi@eecs.umich.edu 767997Ssaidi@eecs.umich.edu#define SAVE_SHADOW(reg,offset,base) \ 777997Ssaidi@eecs.umich.edu stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) 787997Ssaidi@eecs.umich.edu 797997Ssaidi@eecs.umich.edu#define RESTORE_SHADOW(reg,offset,base)\ 807997Ssaidi@eecs.umich.edu ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) 817997Ssaidi@eecs.umich.edu#else 827997Ssaidi@eecs.umich.edu//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 837997Ssaidi@eecs.umich.edu#define SEXT10(X) ((X) & 0x3ff) 847997Ssaidi@eecs.umich.edu//#define SEXT10(X) (((X) << 55) >> 55) 857997Ssaidi@eecs.umich.edu 867997Ssaidi@eecs.umich.edu#define SAVE_GPR(reg,offset,base) \ 877997Ssaidi@eecs.umich.edu stq_p reg, (SEXT10(offset-0x200))(base) 887997Ssaidi@eecs.umich.edu 897997Ssaidi@eecs.umich.edu#define RESTORE_GPR(reg,offset,base) \ 907997Ssaidi@eecs.umich.edu ldq_p reg, (SEXT10(offset-0x200))(base) 917997Ssaidi@eecs.umich.edu 927997Ssaidi@eecs.umich.edu 937997Ssaidi@eecs.umich.edu#define SAVE_FPR(reg,offset,base) \ 947997Ssaidi@eecs.umich.edu stt reg, (SEXT10(offset-0x200))(base) 957997Ssaidi@eecs.umich.edu 967997Ssaidi@eecs.umich.edu#define RESTORE_FPR(reg,offset,base) \ 977997Ssaidi@eecs.umich.edu ldt reg, (SEXT10(offset-0x200))(base) 987997Ssaidi@eecs.umich.edu 997997Ssaidi@eecs.umich.edu#define SAVE_IPR(reg,offset,base) \ 1007997Ssaidi@eecs.umich.edu mfpr v0, reg; \ 1017997Ssaidi@eecs.umich.edu stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) 1027997Ssaidi@eecs.umich.edu 1037997Ssaidi@eecs.umich.edu#define RESTORE_IPR(reg,offset,base) \ 1047997Ssaidi@eecs.umich.edu ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 1057997Ssaidi@eecs.umich.edu mtpr v0, reg 1067997Ssaidi@eecs.umich.edu 1077997Ssaidi@eecs.umich.edu#define SAVE_SHADOW(reg,offset,base) \ 1087997Ssaidi@eecs.umich.edu stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 1097997Ssaidi@eecs.umich.edu 1107997Ssaidi@eecs.umich.edu#define RESTORE_SHADOW(reg,offset,base)\ 1117997Ssaidi@eecs.umich.edu ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 1127997Ssaidi@eecs.umich.edu#endif 1137997Ssaidi@eecs.umich.edu/* orig Structure of the processor-specific impure area */ 1147997Ssaidi@eecs.umich.edu 1157997Ssaidi@eecs.umich.edu/* orig aggregate impure struct prefix "" tag ""; 1167997Ssaidi@eecs.umich.edu * orig cns$flag quadword; 1177997Ssaidi@eecs.umich.edu * orig cns$hlt quadword; 1187997Ssaidi@eecs.umich.edu*/ 1197997Ssaidi@eecs.umich.edu 1207997Ssaidi@eecs.umich.edu/* Define base for debug monitor compatibility */ 1217997Ssaidi@eecs.umich.edu#define CNS_Q_BASE 0x000 1227997Ssaidi@eecs.umich.edu#define CNS_Q_FLAG 0x100 1237997Ssaidi@eecs.umich.edu#define CNS_Q_HALT 0x108 1247997Ssaidi@eecs.umich.edu 1257997Ssaidi@eecs.umich.edu 1267997Ssaidi@eecs.umich.edu/* orig constant ( 1277997Ssaidi@eecs.umich.edu * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 1287997Ssaidi@eecs.umich.edu * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 1297997Ssaidi@eecs.umich.edu * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 1307997Ssaidi@eecs.umich.edu * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 1317997Ssaidi@eecs.umich.edu * orig ) equals . increment 8 prefix "" tag ""; 1327997Ssaidi@eecs.umich.edu * orig cns$gpr quadword dimension 32; 1337997Ssaidi@eecs.umich.edu*/ 1347997Ssaidi@eecs.umich.edu/* Offset to base of saved GPR area - 32 quadword */ 1357997Ssaidi@eecs.umich.edu#define CNS_Q_GPR 0x110 1367997Ssaidi@eecs.umich.edu#define cns_gpr CNS_Q_GPR 1377997Ssaidi@eecs.umich.edu 1387997Ssaidi@eecs.umich.edu/* orig constant ( 1397997Ssaidi@eecs.umich.edu * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 1407997Ssaidi@eecs.umich.edu * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 1417997Ssaidi@eecs.umich.edu * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 1427997Ssaidi@eecs.umich.edu * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 1437997Ssaidi@eecs.umich.edu * orig ) equals . increment 8 prefix "" tag ""; 1447997Ssaidi@eecs.umich.edu * orig cns$fpr quadword dimension 32; 1457997Ssaidi@eecs.umich.edu*/ 1467997Ssaidi@eecs.umich.edu/* Offset to base of saved FPR area - 32 quadwords */ 1477997Ssaidi@eecs.umich.edu#define CNS_Q_FPR 0x210 1487997Ssaidi@eecs.umich.edu 1497997Ssaidi@eecs.umich.edu/* orig #t=.; 1507997Ssaidi@eecs.umich.edu * orig cns$mchkflag quadword; 1517997Ssaidi@eecs.umich.edu*/ 1527997Ssaidi@eecs.umich.edu#define CNS_Q_MCHK 0x310 1537997Ssaidi@eecs.umich.edu 1547997Ssaidi@eecs.umich.edu/* orig constant cns$pt_offset equals .; 1557997Ssaidi@eecs.umich.edu * orig constant ( 1567997Ssaidi@eecs.umich.edu * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 1577997Ssaidi@eecs.umich.edu * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 1587997Ssaidi@eecs.umich.edu * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 1597997Ssaidi@eecs.umich.edu * orig cns$pt21,cns$pt22,cns$pt23 1607997Ssaidi@eecs.umich.edu * orig ) equals . increment 8 prefix "" tag ""; 1617997Ssaidi@eecs.umich.edu * orig cns$pt quadword dimension 24; 1627997Ssaidi@eecs.umich.edu*/ 1637997Ssaidi@eecs.umich.edu/* Offset to base of saved PALtemp area - 25 quadwords */ 1647997Ssaidi@eecs.umich.edu#define CNS_Q_PT 0x318 1657997Ssaidi@eecs.umich.edu 1667997Ssaidi@eecs.umich.edu/* orig cns$shadow8 quadword; 1677997Ssaidi@eecs.umich.edu * orig cns$shadow9 quadword; 1687997Ssaidi@eecs.umich.edu * orig cns$shadow10 quadword; 1697997Ssaidi@eecs.umich.edu * orig cns$shadow11 quadword; 1707997Ssaidi@eecs.umich.edu * orig cns$shadow12 quadword; 1717997Ssaidi@eecs.umich.edu * orig cns$shadow13 quadword; 1727997Ssaidi@eecs.umich.edu * orig cns$shadow14 quadword; 1737997Ssaidi@eecs.umich.edu * orig cns$shadow25 quadword; 1747997Ssaidi@eecs.umich.edu*/ 1757997Ssaidi@eecs.umich.edu/* Offset to base of saved PALshadow area - 8 quadwords */ 1767997Ssaidi@eecs.umich.edu#define CNS_Q_SHADOW 0x3D8 1777997Ssaidi@eecs.umich.edu 1787997Ssaidi@eecs.umich.edu/* Offset to base of saved IPR area */ 1797997Ssaidi@eecs.umich.edu#define CNS_Q_IPR 0x418 1807997Ssaidi@eecs.umich.edu 1817997Ssaidi@eecs.umich.edu/* orig constant cns$ipr_offset equals .; */ 1827997Ssaidi@eecs.umich.edu/* orig cns$exc_addr quadword; */ 1837997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_ADDR 0x418 1847997Ssaidi@eecs.umich.edu/* orig cns$pal_base quadword; */ 1857997Ssaidi@eecs.umich.edu#define CNS_Q_PAL_BASE 0x420 1867997Ssaidi@eecs.umich.edu/* orig cns$mm_stat quadword; */ 1877997Ssaidi@eecs.umich.edu#define CNS_Q_MM_STAT 0x428 1887997Ssaidi@eecs.umich.edu/* orig cns$va quadword; */ 1897997Ssaidi@eecs.umich.edu#define CNS_Q_VA 0x430 1907997Ssaidi@eecs.umich.edu/* orig cns$icsr quadword; */ 1917997Ssaidi@eecs.umich.edu#define CNS_Q_ICSR 0x438 1927997Ssaidi@eecs.umich.edu/* orig cns$ipl quadword; */ 1937997Ssaidi@eecs.umich.edu#define CNS_Q_IPL 0x440 1947997Ssaidi@eecs.umich.edu/* orig cns$ps quadword; // Ibox current mode */ 1957997Ssaidi@eecs.umich.edu#define CNS_Q_IPS 0x448 1967997Ssaidi@eecs.umich.edu/* orig cns$itb_asn quadword; */ 1977997Ssaidi@eecs.umich.edu#define CNS_Q_ITB_ASN 0x450 1987997Ssaidi@eecs.umich.edu/* orig cns$aster quadword; */ 1997997Ssaidi@eecs.umich.edu#define CNS_Q_ASTER 0x458 2007997Ssaidi@eecs.umich.edu/* orig cns$astrr quadword; */ 2017997Ssaidi@eecs.umich.edu#define CNS_Q_ASTRR 0x460 2027997Ssaidi@eecs.umich.edu/* orig cns$isr quadword; */ 2037997Ssaidi@eecs.umich.edu#define CNS_Q_ISR 0x468 2047997Ssaidi@eecs.umich.edu/* orig cns$ivptbr quadword; */ 2057997Ssaidi@eecs.umich.edu#define CNS_Q_IVPTBR 0x470 2067997Ssaidi@eecs.umich.edu/* orig cns$mcsr quadword; */ 2077997Ssaidi@eecs.umich.edu#define CNS_Q_MCSR 0x478 2087997Ssaidi@eecs.umich.edu/* orig cns$dc_mode quadword; */ 2097997Ssaidi@eecs.umich.edu#define CNS_Q_DC_MODE 0x480 2107997Ssaidi@eecs.umich.edu/* orig cns$maf_mode quadword; */ 2117997Ssaidi@eecs.umich.edu#define CNS_Q_MAF_MODE 0x488 2127997Ssaidi@eecs.umich.edu/* orig cns$sirr quadword; */ 2137997Ssaidi@eecs.umich.edu#define CNS_Q_SIRR 0x490 2147997Ssaidi@eecs.umich.edu/* orig cns$fpcsr quadword; */ 2157997Ssaidi@eecs.umich.edu#define CNS_Q_FPCSR 0x498 2167997Ssaidi@eecs.umich.edu/* orig cns$icperr_stat quadword; */ 2177997Ssaidi@eecs.umich.edu#define CNS_Q_ICPERR_STAT 0x4A0 2187997Ssaidi@eecs.umich.edu/* orig cns$pmctr quadword; */ 2197997Ssaidi@eecs.umich.edu#define CNS_Q_PM_CTR 0x4A8 2207997Ssaidi@eecs.umich.edu/* orig cns$exc_sum quadword; */ 2217997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_SUM 0x4B0 2227997Ssaidi@eecs.umich.edu/* orig cns$exc_mask quadword; */ 2237997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_MASK 0x4B8 2247997Ssaidi@eecs.umich.edu/* orig cns$intid quadword; */ 2257997Ssaidi@eecs.umich.edu#define CNS_Q_INT_ID 0x4C0 2267997Ssaidi@eecs.umich.edu/* orig cns$dcperr_stat quadword; */ 2277997Ssaidi@eecs.umich.edu#define CNS_Q_DCPERR_STAT 0x4C8 2287997Ssaidi@eecs.umich.edu/* orig cns$sc_stat quadword; */ 2297997Ssaidi@eecs.umich.edu#define CNS_Q_SC_STAT 0x4D0 2307997Ssaidi@eecs.umich.edu/* orig cns$sc_addr quadword; */ 2317997Ssaidi@eecs.umich.edu#define CNS_Q_SC_ADDR 0x4D8 2327997Ssaidi@eecs.umich.edu/* orig cns$sc_ctl quadword; */ 2337997Ssaidi@eecs.umich.edu#define CNS_Q_SC_CTL 0x4E0 2347997Ssaidi@eecs.umich.edu/* orig cns$bc_tag_addr quadword; */ 2357997Ssaidi@eecs.umich.edu#define CNS_Q_BC_TAG_ADDR 0x4E8 2367997Ssaidi@eecs.umich.edu/* orig cns$ei_stat quadword; */ 2377997Ssaidi@eecs.umich.edu#define CNS_Q_EI_STAT 0x4F0 2387997Ssaidi@eecs.umich.edu/* orig cns$ei_addr quadword; */ 2397997Ssaidi@eecs.umich.edu#define CNS_Q_EI_ADDR 0x4F8 2407997Ssaidi@eecs.umich.edu/* orig cns$fill_syn quadword; */ 2417997Ssaidi@eecs.umich.edu#define CNS_Q_FILL_SYN 0x500 2427997Ssaidi@eecs.umich.edu/* orig cns$ld_lock quadword; */ 2437997Ssaidi@eecs.umich.edu#define CNS_Q_LD_LOCK 0x508 2447997Ssaidi@eecs.umich.edu/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */ 2457997Ssaidi@eecs.umich.edu#define CNS_Q_BC_CTL 0x510 2467997Ssaidi@eecs.umich.edu/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ 2477997Ssaidi@eecs.umich.edu#define CNS_Q_PM_CTL 0x518 2487997Ssaidi@eecs.umich.edu/* orig cns$bc_config quadword; // shadow of on chip bc_config */ 2497997Ssaidi@eecs.umich.edu#define CNS_Q_BC_CFG 0x520 2507997Ssaidi@eecs.umich.edu 2517997Ssaidi@eecs.umich.edu/* orig constant cns$size equals .; 2527997Ssaidi@eecs.umich.edu * orig 2537997Ssaidi@eecs.umich.edu * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 2547997Ssaidi@eecs.umich.edu * orig constant pal$impure_specific_size equals (.+7) & %xfff8; 2557997Ssaidi@eecs.umich.edu * orig constant cns$mchksize equals (.+7-#t) & %xfff8; 2567997Ssaidi@eecs.umich.edu * orig constant pal$logout_area equals pal$impure_specific_size ; 2577997Ssaidi@eecs.umich.edu * orig end impure; 2587997Ssaidi@eecs.umich.edu*/ 2597997Ssaidi@eecs.umich.edu 2607997Ssaidi@eecs.umich.edu/* This next set of stuff came from the old code ..pb */ 2617997Ssaidi@eecs.umich.edu#define CNS_Q_SROM_REV 0x528 2627997Ssaidi@eecs.umich.edu#define CNS_Q_PROC_ID 0x530 2637997Ssaidi@eecs.umich.edu#define CNS_Q_MEM_SIZE 0x538 2647997Ssaidi@eecs.umich.edu#define CNS_Q_CYCLE_CNT 0x540 2657997Ssaidi@eecs.umich.edu#define CNS_Q_SIGNATURE 0x548 2667997Ssaidi@eecs.umich.edu#define CNS_Q_PROC_MASK 0x550 2677997Ssaidi@eecs.umich.edu#define CNS_Q_SYSCTX 0x558 2687997Ssaidi@eecs.umich.edu 2697997Ssaidi@eecs.umich.edu 2707997Ssaidi@eecs.umich.edu 2717997Ssaidi@eecs.umich.edu#define MACHINE_CHECK_CRD_BASE 0 2727997Ssaidi@eecs.umich.edu#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 2737997Ssaidi@eecs.umich.edu 2747997Ssaidi@eecs.umich.edu 2757997Ssaidi@eecs.umich.edu 2767997Ssaidi@eecs.umich.edu/* orig 2777997Ssaidi@eecs.umich.edu * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 2787997Ssaidi@eecs.umich.edu * orig SPROCESS bitfield length 1 ; 2797997Ssaidi@eecs.umich.edu * orig FILL_0 bitfield length 3 fill tag $$; 2807997Ssaidi@eecs.umich.edu * orig FRQ2 bitfield length 2 ; 2817997Ssaidi@eecs.umich.edu * orig FRQ1 bitfield length 2 ; 2827997Ssaidi@eecs.umich.edu * orig FRQ0 bitfield length 2 ; 2837997Ssaidi@eecs.umich.edu * orig CTL2 bitfield length 2 ; 2847997Ssaidi@eecs.umich.edu * orig CTL1 bitfield length 2 ; 2857997Ssaidi@eecs.umich.edu * orig CTL0 bitfield length 2 ; 2867997Ssaidi@eecs.umich.edu * orig FILL_1 bitfield length 16 fill tag $$; 2877997Ssaidi@eecs.umich.edu * orig FILL_2 bitfield length 32 fill tag $$; 2887997Ssaidi@eecs.umich.edu * orig end EV5PMCTRCTL_BITS; 2897997Ssaidi@eecs.umich.edu * orig 2907997Ssaidi@eecs.umich.edu * orig end_module $pal_impure; 2917997Ssaidi@eecs.umich.edu * orig 2927997Ssaidi@eecs.umich.edu * orig module $pal_logout; 2937997Ssaidi@eecs.umich.edu * orig 2947997Ssaidi@eecs.umich.edu * orig // 2957997Ssaidi@eecs.umich.edu * orig // Start definition of Corrected Error Frame 2967997Ssaidi@eecs.umich.edu * orig // 2977997Ssaidi@eecs.umich.edu */ 2987997Ssaidi@eecs.umich.edu 2997997Ssaidi@eecs.umich.edu/* 3007997Ssaidi@eecs.umich.edu * orig aggregate crd_logout struct prefix "" tag ""; 3017997Ssaidi@eecs.umich.edu */ 3027997Ssaidi@eecs.umich.edu 3037997Ssaidi@eecs.umich.edu#ifdef SIMOS 3047997Ssaidi@eecs.umich.edu#define pal_logout_area 0x600 3057997Ssaidi@eecs.umich.edu#define mchk_crd_base 0 3067997Ssaidi@eecs.umich.edu#endif 3077997Ssaidi@eecs.umich.edu 3087997Ssaidi@eecs.umich.edu/* orig mchk$crd_flag quadword; */ 3097997Ssaidi@eecs.umich.edu#define mchk_crd_flag 0 3107997Ssaidi@eecs.umich.edu/* orig mchk$crd_offsets quadword; */ 3117997Ssaidi@eecs.umich.edu#define mchk_crd_offsets 8 3127997Ssaidi@eecs.umich.edu/* orig 3137997Ssaidi@eecs.umich.edu * orig // Pal-specific information */ 3147997Ssaidi@eecs.umich.edu#define mchk_crd_mchk_code 0x10 3157997Ssaidi@eecs.umich.edu/* orig mchk$crd_mchk_code quadword; 3167997Ssaidi@eecs.umich.edu * orig 3177997Ssaidi@eecs.umich.edu * orig // CPU-specific information 3187997Ssaidi@eecs.umich.edu * orig constant mchk$crd_cpu_base equals . ; 3197997Ssaidi@eecs.umich.edu * orig mchk$crd_ei_addr quadword; */ 3207997Ssaidi@eecs.umich.edu#define mchk_crd_ei_addr 0x18 3217997Ssaidi@eecs.umich.edu/* orig mchk$crd_fill_syn quadword; */ 3227997Ssaidi@eecs.umich.edu#define mchk_crd_fill_syn 0x20 3237997Ssaidi@eecs.umich.edu/* orig mchk$crd_ei_stat quadword; */ 3247997Ssaidi@eecs.umich.edu#define mchk_crd_ei_stat 0x28 3257997Ssaidi@eecs.umich.edu/* orig mchk$crd_isr quadword; */ 3267997Ssaidi@eecs.umich.edu#define mchk_crd_isr 0x30 3277997Ssaidi@eecs.umich.edu 3287997Ssaidi@eecs.umich.edu/* 3297997Ssaidi@eecs.umich.edu * Hacked up constants for the turbolaser build. Hope 3307997Ssaidi@eecs.umich.edu * this is moreless correct 3317997Ssaidi@eecs.umich.edu */ 3327997Ssaidi@eecs.umich.edu 3337997Ssaidi@eecs.umich.edu#define mchk_crd_whami 0x38 3347997Ssaidi@eecs.umich.edu#define mchk_crd_tldev 0x40 3357997Ssaidi@eecs.umich.edu#define mchk_crd_tlber 0x48 3367997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr0 0x50 3377997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr1 0x58 3387997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr2 0x60 3397997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr3 0x68 3407997Ssaidi@eecs.umich.edu#define mchk_crd_rsvd 0x70 3417997Ssaidi@eecs.umich.edu 3427997Ssaidi@eecs.umich.edu 3437997Ssaidi@eecs.umich.edu#ifdef SIMOS 3447997Ssaidi@eecs.umich.edu/* 3457997Ssaidi@eecs.umich.edu * mchk area seems different for tlaser 3467997Ssaidi@eecs.umich.edu */ 3477997Ssaidi@eecs.umich.edu 3487997Ssaidi@eecs.umich.edu#define mchk_crd_size 0x80 3497997Ssaidi@eecs.umich.edu#define mchk_mchk_base (mchk_crd_size) 3507997Ssaidi@eecs.umich.edu 3517997Ssaidi@eecs.umich.edu#define mchk_tlber 0x0 3527997Ssaidi@eecs.umich.edu#define mchk_tlepaerr 0x8 3537997Ssaidi@eecs.umich.edu#define mchk_tlepderr 0x10 3547997Ssaidi@eecs.umich.edu#define mchk_tlepmerr 0x18 3557997Ssaidi@eecs.umich.edu 3567997Ssaidi@eecs.umich.edu 3577997Ssaidi@eecs.umich.edu#endif 3587997Ssaidi@eecs.umich.edu 3597997Ssaidi@eecs.umich.edu 3607997Ssaidi@eecs.umich.edu/* orig 3617997Ssaidi@eecs.umich.edu * orig // System-specific information 3627997Ssaidi@eecs.umich.edu * orig constant mchk$crd_sys_base equals . ; 3637997Ssaidi@eecs.umich.edu * orig constant mchk$crd_size equals (.+7) & %xfff8; 3647997Ssaidi@eecs.umich.edu * orig 3657997Ssaidi@eecs.umich.edu * orig end crd_logout; 3667997Ssaidi@eecs.umich.edu * orig // 3677997Ssaidi@eecs.umich.edu * orig // Start definition of Machine check logout Frame 3687997Ssaidi@eecs.umich.edu * orig // 3697997Ssaidi@eecs.umich.edu * orig aggregate logout struct prefix "" tag ""; 3707997Ssaidi@eecs.umich.edu * orig mchk$flag quadword; */ 3717997Ssaidi@eecs.umich.edu/* orig mchk$offsets quadword; */ 3727997Ssaidi@eecs.umich.edu/* orig 3737997Ssaidi@eecs.umich.edu * orig // Pal-specific information 3747997Ssaidi@eecs.umich.edu * orig mchk$mchk_code quadword; */ 3757997Ssaidi@eecs.umich.edu/* 3767997Ssaidi@eecs.umich.edu 3777997Ssaidi@eecs.umich.edu * orig mchk$pt quadword dimension 24; 3787997Ssaidi@eecs.umich.edu * orig 3797997Ssaidi@eecs.umich.edu * orig // CPU-specific information 3807997Ssaidi@eecs.umich.edu * orig constant mchk$cpu_base equals . ; 3817997Ssaidi@eecs.umich.edu * orig mchk$exc_addr quadword; 3827997Ssaidi@eecs.umich.edu * orig mchk$exc_sum quadword; 3837997Ssaidi@eecs.umich.edu * orig mchk$exc_mask quadword; 3847997Ssaidi@eecs.umich.edu * orig mchk$pal_base quadword; 3857997Ssaidi@eecs.umich.edu * orig mchk$isr quadword; 3867997Ssaidi@eecs.umich.edu * orig mchk$icsr quadword; 3877997Ssaidi@eecs.umich.edu * orig mchk$ic_perr_stat quadword; 3887997Ssaidi@eecs.umich.edu * orig mchk$dc_perr_stat quadword; 3897997Ssaidi@eecs.umich.edu * orig mchk$va quadword; 3907997Ssaidi@eecs.umich.edu * orig mchk$mm_stat quadword; 3917997Ssaidi@eecs.umich.edu * orig mchk$sc_addr quadword; 3927997Ssaidi@eecs.umich.edu * orig mchk$sc_stat quadword; 3937997Ssaidi@eecs.umich.edu * orig mchk$bc_tag_addr quadword; 3947997Ssaidi@eecs.umich.edu * orig mchk$ei_addr quadword; 3957997Ssaidi@eecs.umich.edu * orig mchk$fill_syn quadword; 3967997Ssaidi@eecs.umich.edu * orig mchk$ei_stat quadword; 3977997Ssaidi@eecs.umich.edu * orig mchk$ld_lock quadword; 3987997Ssaidi@eecs.umich.edu * orig 3997997Ssaidi@eecs.umich.edu * orig // System-specific information 4007997Ssaidi@eecs.umich.edu * orig 4017997Ssaidi@eecs.umich.edu * orig constant mchk$sys_base equals . ; 4027997Ssaidi@eecs.umich.edu * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 4037997Ssaidi@eecs.umich.edu * orig 4047997Ssaidi@eecs.umich.edu * orig constant mchk$size equals (.+7) & %xfff8; 4057997Ssaidi@eecs.umich.edu * orig 4067997Ssaidi@eecs.umich.edu * orig 4077997Ssaidi@eecs.umich.edu * orig constant mchk$crd_base equals 0 ; 4087997Ssaidi@eecs.umich.edu * orig constant mchk$mchk_base equals mchk$crd_size ; 4097997Ssaidi@eecs.umich.edu * orig 4107997Ssaidi@eecs.umich.edu * orig 4117997Ssaidi@eecs.umich.edu * orig end logout; 4127997Ssaidi@eecs.umich.edu * orig 4137997Ssaidi@eecs.umich.edu * orig end_module $pal_logout; 4147997Ssaidi@eecs.umich.edu*/ 4157997Ssaidi@eecs.umich.edu 4167997Ssaidi@eecs.umich.edu 4177997Ssaidi@eecs.umich.edu 4187997Ssaidi@eecs.umich.edu 4197997Ssaidi@eecs.umich.edu/* this is lingering in the old ladbx code but looks like it was from ev4 days. 4207997Ssaidi@eecs.umich.edu * This was 0x160 in the old days..pb 4217997Ssaidi@eecs.umich.edu*/ 4227997Ssaidi@eecs.umich.edu#define LAF_K_SIZE MACHINE_CHECK_SIZE 4237997Ssaidi@eecs.umich.edu#endif 424