1/* 2 * Copyright (c) 1993 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef EV5_IMPURE_INCLUDED 30#define EV5_IMPURE_INCLUDED 31 32// This uses the Hudson file format from "impure.h" but with the fields from 33// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 34 35// file: impure.sdl 36// 37// PAL impure scratch area and logout area data structure definitions for 38// Alpha firmware. 39// 40// 41// module $pal_impure; 42// 43// Edit Date Who Description 44// ---- --------- --- --------------------- 45// 1 7-Jul-93 JEM Initial Entry 46// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 47// Delete mvptbr 48// Calculate pal$logout from end of impure area 49// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 50// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, 51// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, 52// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, 53// ei_addr, fill_syn, ld_lock 54// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be 55// consistent with ev4 56// add cns$ipr_offset 57// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 58// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant 59// to mchk logout frame 60// 61// 62// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file 63//orig 64 65/* 66** Macros for saving/restoring data to/from the PAL impure scratch 67** area. 68** 69** The console save state area is larger than the addressibility 70** of the HW_LD/ST instructions (10-bit signed byte displacement), 71** so some adjustments to the base offsets, as well as the offsets 72** within each base region, are necessary. 73** 74** The console save state area is divided into two segments; the 75** CPU-specific segment and the platform-specific segment. The 76** state that is saved in the CPU-specific segment includes GPRs, 77** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 78** in the platform-specific segment. 79** 80** The impure pointer will need to be adjusted by a different offset 81** value for each region within a given segment. The SAVE and RESTORE 82** macros will auto-magically adjust the offsets accordingly. 83** 84*/ 85//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 86#define SEXT10(X) ((X) & 0x3ff) 87//#define SEXT10(X) (((X) << 55) >> 55) 88 89#define SAVE_GPR(reg,offset,base) \ 90 stq_p reg, (SEXT10(offset-0x200))(base) 91 92#define RESTORE_GPR(reg,offset,base) \ 93 ldq_p reg, (SEXT10(offset-0x200))(base) 94 95 96#define SAVE_FPR(reg,offset,base) \ 97 stt reg, (SEXT10(offset-0x200))(base) 98 99#define RESTORE_FPR(reg,offset,base) \ 100 ldt reg, (SEXT10(offset-0x200))(base) 101 102#define SAVE_IPR(reg,offset,base) \ 103 mfpr v0, reg; \ 104 stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) 105 106#define RESTORE_IPR(reg,offset,base) \ 107 ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 108 mtpr v0, reg 109 110#define SAVE_SHADOW(reg,offset,base) \ 111 stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 112 113#define RESTORE_SHADOW(reg,offset,base)\ 114 ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 115 116/* Structure of the processor-specific impure area */ 117 118/* aggregate impure struct prefix "" tag ""; 119 * cns$flag quadword; 120 * cns$hlt quadword; 121 */ 122 123/* Define base for debug monitor compatibility */ 124#define CNS_Q_BASE 0x000 125#define CNS_Q_FLAG 0x100 126#define CNS_Q_HALT 0x108 127 128 129/* constant ( 130 * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 131 * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 132 * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 133 * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 134 * ) equals . increment 8 prefix "" tag ""; 135 * cns$gpr quadword dimension 32; 136 */ 137 138/* Offset to base of saved GPR area - 32 quadword */ 139#define CNS_Q_GPR 0x110 140#define cns_gpr CNS_Q_GPR 141 142/* constant ( 143 * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 144 * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 145 * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 146 * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 147 * ) equals . increment 8 prefix "" tag ""; 148 * cns$fpr quadword dimension 32; 149 */ 150 151/* Offset to base of saved FPR area - 32 quadwords */ 152#define CNS_Q_FPR 0x210 153 154/* #t=.; 155 * cns$mchkflag quadword; 156 */ 157#define CNS_Q_MCHK 0x310 158 159/* constant cns$pt_offset equals .; 160 * constant ( 161 * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 162 * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 163 * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 164 * cns$pt21,cns$pt22,cns$pt23 165 * ) equals . increment 8 prefix "" tag ""; 166 * cns$pt quadword dimension 24; 167 */ 168/* Offset to base of saved PALtemp area - 25 quadwords */ 169#define CNS_Q_PT 0x318 170 171/* cns$shadow8 quadword; 172 * cns$shadow9 quadword; 173 * cns$shadow10 quadword; 174 * cns$shadow11 quadword; 175 * cns$shadow12 quadword; 176 * cns$shadow13 quadword; 177 * cns$shadow14 quadword; 178 * cns$shadow25 quadword; 179 */ 180/* Offset to base of saved PALshadow area - 8 quadwords */ 181#define CNS_Q_SHADOW 0x3D8 182 183/* Offset to base of saved IPR area */ 184#define CNS_Q_IPR 0x418 185 186/* constant cns$ipr_offset equals .; */ 187/* cns$exc_addr quadword; */ 188#define CNS_Q_EXC_ADDR 0x418 189/* cns$pal_base quadword; */ 190#define CNS_Q_PAL_BASE 0x420 191/* cns$mm_stat quadword; */ 192#define CNS_Q_MM_STAT 0x428 193/* cns$va quadword; */ 194#define CNS_Q_VA 0x430 195/* cns$icsr quadword; */ 196#define CNS_Q_ICSR 0x438 197/* cns$ipl quadword; */ 198#define CNS_Q_IPL 0x440 199/* cns$ps quadword; // Ibox current mode */ 200#define CNS_Q_IPS 0x448 201/* cns$itb_asn quadword; */ 202#define CNS_Q_ITB_ASN 0x450 203/* cns$aster quadword; */ 204#define CNS_Q_ASTER 0x458 205/* cns$astrr quadword; */ 206#define CNS_Q_ASTRR 0x460 207/* cns$isr quadword; */ 208#define CNS_Q_ISR 0x468 209/* cns$ivptbr quadword; */ 210#define CNS_Q_IVPTBR 0x470 211/* cns$mcsr quadword; */ 212#define CNS_Q_MCSR 0x478 213/* cns$dc_mode quadword; */ 214#define CNS_Q_DC_MODE 0x480 215/* cns$maf_mode quadword; */ 216#define CNS_Q_MAF_MODE 0x488 217/* cns$sirr quadword; */ 218#define CNS_Q_SIRR 0x490 219/* cns$fpcsr quadword; */ 220#define CNS_Q_FPCSR 0x498 221/* cns$icperr_stat quadword; */ 222#define CNS_Q_ICPERR_STAT 0x4A0 223/* cns$pmctr quadword; */ 224#define CNS_Q_PM_CTR 0x4A8 225/* cns$exc_sum quadword; */ 226#define CNS_Q_EXC_SUM 0x4B0 227/* cns$exc_mask quadword; */ 228#define CNS_Q_EXC_MASK 0x4B8 229/* cns$intid quadword; */ 230#define CNS_Q_INT_ID 0x4C0 231/* cns$dcperr_stat quadword; */ 232#define CNS_Q_DCPERR_STAT 0x4C8 233/* cns$sc_stat quadword; */ 234#define CNS_Q_SC_STAT 0x4D0 235/* cns$sc_addr quadword; */ 236#define CNS_Q_SC_ADDR 0x4D8 237/* cns$sc_ctl quadword; */ 238#define CNS_Q_SC_CTL 0x4E0 239/* cns$bc_tag_addr quadword; */ 240#define CNS_Q_BC_TAG_ADDR 0x4E8 241/* cns$ei_stat quadword; */ 242#define CNS_Q_EI_STAT 0x4F0 243/* cns$ei_addr quadword; */ 244#define CNS_Q_EI_ADDR 0x4F8 245/* cns$fill_syn quadword; */ 246#define CNS_Q_FILL_SYN 0x500 247/* cns$ld_lock quadword; */ 248#define CNS_Q_LD_LOCK 0x508 249/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ 250#define CNS_Q_BC_CTL 0x510 251/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ 252#define CNS_Q_PM_CTL 0x518 253/* cns$bc_config quadword; // shadow of on chip bc_config */ 254#define CNS_Q_BC_CFG 0x520 255 256/* constant cns$size equals .; 257 * 258 * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 259 * constant pal$impure_specific_size equals (.+7) & %xfff8; 260 * constant cns$mchksize equals (.+7-#t) & %xfff8; 261 * constant pal$logout_area equals pal$impure_specific_size ; 262 * end impure; 263*/ 264 265/* This next set of stuff came from the old code ..pb */ 266#define CNS_Q_SROM_REV 0x528 267#define CNS_Q_PROC_ID 0x530 268#define CNS_Q_MEM_SIZE 0x538 269#define CNS_Q_CYCLE_CNT 0x540 270#define CNS_Q_SIGNATURE 0x548 271#define CNS_Q_PROC_MASK 0x550 272#define CNS_Q_SYSCTX 0x558 273 274 275 276#define MACHINE_CHECK_CRD_BASE 0 277#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 278 279 280 281/* 282 * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 283 * SPROCESS bitfield length 1 ; 284 * FILL_0 bitfield length 3 fill tag $$; 285 * FRQ2 bitfield length 2 ; 286 * FRQ1 bitfield length 2 ; 287 * FRQ0 bitfield length 2 ; 288 * CTL2 bitfield length 2 ; 289 * CTL1 bitfield length 2 ; 290 * CTL0 bitfield length 2 ; 291 * FILL_1 bitfield length 16 fill tag $$; 292 * FILL_2 bitfield length 32 fill tag $$; 293 * end EV5PMCTRCTL_BITS; 294 * 295 * end_module $pal_impure; 296 * 297 * module $pal_logout; 298 * 299 * // 300 * // Start definition of Corrected Error Frame 301 * // 302 */ 303 304/* 305 * aggregate crd_logout struct prefix "" tag ""; 306 */ 307 308#define pal_logout_area 0x600 309#define mchk_crd_base 0 310 311/* mchk$crd_flag quadword; */ 312#define mchk_crd_flag 0 313/* mchk$crd_offsets quadword; */ 314#define mchk_crd_offsets 8 315/* 316 * // Pal-specific information */ 317#define mchk_crd_mchk_code 0x10 318/* mchk$crd_mchk_code quadword; 319 * 320 * // CPU-specific information 321 * constant mchk$crd_cpu_base equals . ; 322 * mchk$crd_ei_addr quadword; */ 323#define mchk_crd_ei_addr 0x18 324/* mchk$crd_fill_syn quadword; */ 325#define mchk_crd_fill_syn 0x20 326/* mchk$crd_ei_stat quadword; */ 327#define mchk_crd_ei_stat 0x28 328/* mchk$crd_isr quadword; */ 329#define mchk_crd_isr 0x30 330 331/* 332 * Hacked up constants for the turbolaser build. Hope 333 * this is moreless correct 334 */ 335 336#define mchk_crd_whami 0x38 337#define mchk_crd_tldev 0x40 338#define mchk_crd_tlber 0x48 339#define mchk_crd_tlesr0 0x50 340#define mchk_crd_tlesr1 0x58 341#define mchk_crd_tlesr2 0x60 342#define mchk_crd_tlesr3 0x68 343#define mchk_crd_rsvd 0x70 344 345 346/* 347 * mchk area seems different for tlaser 348 */ 349 350#define mchk_crd_size 0x80 351#define mchk_mchk_base (mchk_crd_size) 352 353#define mchk_tlber 0x0 354#define mchk_tlepaerr 0x8 355#define mchk_tlepderr 0x10 356#define mchk_tlepmerr 0x18 357 358 359/* 360 * // System-specific information 361 * constant mchk$crd_sys_base equals . ; 362 * constant mchk$crd_size equals (.+7) & %xfff8; 363 * 364 * end crd_logout; 365 * // 366 * // Start definition of Machine check logout Frame 367 * // 368 * aggregate logout struct prefix "" tag ""; 369 * mchk$flag quadword; */ 370/* mchk$offsets quadword; */ 371/* 372 * // Pal-specific information 373 * mchk$mchk_code quadword; */ 374/* 375 376 * mchk$pt quadword dimension 24; 377 * 378 * // CPU-specific information 379 * constant mchk$cpu_base equals . ; 380 * mchk$exc_addr quadword; 381 * mchk$exc_sum quadword; 382 * mchk$exc_mask quadword; 383 * mchk$pal_base quadword; 384 * mchk$isr quadword; 385 * mchk$icsr quadword; 386 * mchk$ic_perr_stat quadword; 387 * mchk$dc_perr_stat quadword; 388 * mchk$va quadword; 389 * mchk$mm_stat quadword; 390 * mchk$sc_addr quadword; 391 * mchk$sc_stat quadword; 392 * mchk$bc_tag_addr quadword; 393 * mchk$ei_addr quadword; 394 * mchk$fill_syn quadword; 395 * mchk$ei_stat quadword; 396 * mchk$ld_lock quadword; 397 * 398 * // System-specific information 399 * 400 * constant mchk$sys_base equals . ; 401 * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 402 * 403 * constant mchk$size equals (.+7) & %xfff8; 404 * 405 * 406 * constant mchk$crd_base equals 0 ; 407 * constant mchk$mchk_base equals mchk$crd_size ; 408 * 409 * 410 * end logout; 411 * 412 * end_module $pal_logout; 413*/ 414 415/* 416 * this is lingering in the old ladbx code but looks like it was from 417 * ev4 days. This was 0x160 in the old days..pb 418 */ 419#define LAF_K_SIZE MACHINE_CHECK_SIZE 420#endif 421