ev5_alpha_defs.h revision 7997
17997Ssaidi@eecs.umich.edu#ifndef EV5_ALPHA_DEFS_INCLUDED 27997Ssaidi@eecs.umich.edu#define EV5_ALPHA_DEFS_INCLUDED 1 37997Ssaidi@eecs.umich.edu 47997Ssaidi@eecs.umich.edu// from ev5_alpha_defs.mar from Lance's fetch directory 57997Ssaidi@eecs.umich.edu// Lower-caseified and $ signs removed ... pb Nov/95 67997Ssaidi@eecs.umich.edu 77997Ssaidi@eecs.umich.edu// .MACRO _ALPHADEFS 87997Ssaidi@eecs.umich.edu// ALPHADEF_VER == 6 ; Flag the version number of this file. 97997Ssaidi@eecs.umich.edu// .ENDM 107997Ssaidi@eecs.umich.edu// .MACRO _PSDEF,_GBL 117997Ssaidi@eecs.umich.edu// _DEFINI PS,_GBL 127997Ssaidi@eecs.umich.edu//;+ 137997Ssaidi@eecs.umich.edu//; PS Layout - PS 147997Ssaidi@eecs.umich.edu//; Loc Size name function 157997Ssaidi@eecs.umich.edu//; ------ ------ ______ ----------------------------------- 167997Ssaidi@eecs.umich.edu//; <31:29> 3 SA stack alignment 177997Ssaidi@eecs.umich.edu//; <31:13> 24 RES Reserved MBZ 187997Ssaidi@eecs.umich.edu//; <12:8> 5 IPL Priority level 197997Ssaidi@eecs.umich.edu//; <7> 1 VMM Virtual Mach Monitor 207997Ssaidi@eecs.umich.edu//; <6:5> 2 RES Reserved MBZ 217997Ssaidi@eecs.umich.edu//; <4:3> 2 CM Current Mode 227997Ssaidi@eecs.umich.edu//; <2> 1 IP Interrupt Pending 237997Ssaidi@eecs.umich.edu//; <1:0> 2 SW Software bits 247997Ssaidi@eecs.umich.edu//;- 257997Ssaidi@eecs.umich.edu 267997Ssaidi@eecs.umich.edu#define ps_v_sw 0 277997Ssaidi@eecs.umich.edu#define ps_m_sw (3<<ps_v_sw) 287997Ssaidi@eecs.umich.edu 297997Ssaidi@eecs.umich.edu#define ps_v_ip 2 307997Ssaidi@eecs.umich.edu#define ps_m_ip (1<<ps_v_ip) 317997Ssaidi@eecs.umich.edu 327997Ssaidi@eecs.umich.edu#define ps_v_cm 3 337997Ssaidi@eecs.umich.edu#define ps_m_cm (3<<ps_v_cm) 347997Ssaidi@eecs.umich.edu 357997Ssaidi@eecs.umich.edu#define ps_v_vmm 7 367997Ssaidi@eecs.umich.edu#define ps_m_vmm (1<<ps_v_vmm) 377997Ssaidi@eecs.umich.edu 387997Ssaidi@eecs.umich.edu#define ps_v_ipl 8 397997Ssaidi@eecs.umich.edu#define ps_m_ipl (0x1f<<ps_v_ipl) 407997Ssaidi@eecs.umich.edu 417997Ssaidi@eecs.umich.edu#define ps_v_sp (0x38) 427997Ssaidi@eecs.umich.edu#define ps_m_sp (0x3f<<ps_v_sp) 437997Ssaidi@eecs.umich.edu 447997Ssaidi@eecs.umich.edu 457997Ssaidi@eecs.umich.edu#define ps_c_kern (0x00) 467997Ssaidi@eecs.umich.edu#define ps_c_exec (0x08) 477997Ssaidi@eecs.umich.edu#define ps_c_supr (0x10) 487997Ssaidi@eecs.umich.edu#define ps_c_user (0x18) 497997Ssaidi@eecs.umich.edu#define ps_c_ipl0 (0x0000) 507997Ssaidi@eecs.umich.edu#define ps_c_ipl1 (0x0100) 517997Ssaidi@eecs.umich.edu#define ps_c_ipl2 (0x0200) 527997Ssaidi@eecs.umich.edu#define ps_c_ipl3 (0x0300) 537997Ssaidi@eecs.umich.edu#define ps_c_ipl4 (0x0400) 547997Ssaidi@eecs.umich.edu#define ps_c_ipl5 (0x0500) 557997Ssaidi@eecs.umich.edu#define ps_c_ipl6 (0x0600) 567997Ssaidi@eecs.umich.edu#define ps_c_ipl7 (0x0700) 577997Ssaidi@eecs.umich.edu#define ps_c_ipl8 (0x0800) 587997Ssaidi@eecs.umich.edu#define ps_c_ipl9 (0x0900) 597997Ssaidi@eecs.umich.edu#define ps_c_ipl10 (0x0A00) 607997Ssaidi@eecs.umich.edu#define ps_c_ipl11 (0x0B00) 617997Ssaidi@eecs.umich.edu#define ps_c_ipl12 (0x0C00) 627997Ssaidi@eecs.umich.edu#define ps_c_ipl13 (0x0D00) 637997Ssaidi@eecs.umich.edu#define ps_c_ipl14 (0x0E00) 647997Ssaidi@eecs.umich.edu#define ps_c_ipl15 (0x0F00) 657997Ssaidi@eecs.umich.edu#define ps_c_ipl16 (0x1000) 667997Ssaidi@eecs.umich.edu#define ps_c_ipl17 (0x1100) 677997Ssaidi@eecs.umich.edu#define ps_c_ipl18 (0x1200) 687997Ssaidi@eecs.umich.edu#define ps_c_ipl19 (0x1300) 697997Ssaidi@eecs.umich.edu#define ps_c_ipl20 (0x1400) 707997Ssaidi@eecs.umich.edu#define ps_c_ipl21 (0x1500) 717997Ssaidi@eecs.umich.edu#define ps_c_ipl22 (0x1600) 727997Ssaidi@eecs.umich.edu#define ps_c_ipl23 (0x1700) 737997Ssaidi@eecs.umich.edu#define ps_c_ipl24 (0x1800) 747997Ssaidi@eecs.umich.edu#define ps_c_ipl25 (0x1900) 757997Ssaidi@eecs.umich.edu#define ps_c_ipl26 (0x1A00) 767997Ssaidi@eecs.umich.edu#define ps_c_ipl27 (0x1B00) 777997Ssaidi@eecs.umich.edu#define ps_c_ipl28 (0x1C00) 787997Ssaidi@eecs.umich.edu#define ps_c_ipl29 (0x1D00) 797997Ssaidi@eecs.umich.edu#define ps_c_ipl30 (0x1E00) 807997Ssaidi@eecs.umich.edu#define ps_c_ipl31 (0x1F00) 817997Ssaidi@eecs.umich.edu 827997Ssaidi@eecs.umich.edu// _DEFEND PS,_GBL,DEF 837997Ssaidi@eecs.umich.edu// .ENDM 847997Ssaidi@eecs.umich.edu//;+ 857997Ssaidi@eecs.umich.edu//; PTE layout - symbol prefix PTE_ 867997Ssaidi@eecs.umich.edu//; 877997Ssaidi@eecs.umich.edu//; Loc Size name function 887997Ssaidi@eecs.umich.edu//; ------ ------ ------ ----------------------------------- 897997Ssaidi@eecs.umich.edu//; <63:32> 32 PFN Page Frame Number 907997Ssaidi@eecs.umich.edu//; <31:16> 16 SOFT Bits reserved for software use 917997Ssaidi@eecs.umich.edu//; <15> 1 UWE User write enable 927997Ssaidi@eecs.umich.edu//; <14> 1 SWE Super write enable 937997Ssaidi@eecs.umich.edu//; <13> 1 EWE Exec write enable 947997Ssaidi@eecs.umich.edu//; <12> 1 KWE Kernel write enable 957997Ssaidi@eecs.umich.edu//; <11> 1 URE User read enable 967997Ssaidi@eecs.umich.edu//; <10> 1 SRE Super read enable 977997Ssaidi@eecs.umich.edu//; <9> 1 ERE Exec read enable 987997Ssaidi@eecs.umich.edu//; <8> 1 KRE Kernel read enable 997997Ssaidi@eecs.umich.edu//; <7:6> 2 RES Reserved SBZ 1007997Ssaidi@eecs.umich.edu//; <5> 1 HPF Huge Page Flag 1017997Ssaidi@eecs.umich.edu//; <4> 1 ASM Wild card address space number match 1027997Ssaidi@eecs.umich.edu//; <3> 1 FOE Fault On execute 1037997Ssaidi@eecs.umich.edu//; <2> 1 FOW Fault On Write 1047997Ssaidi@eecs.umich.edu//; <1> 1 FOR Fault On Read 1057997Ssaidi@eecs.umich.edu//; <0> 1 V valid bit 1067997Ssaidi@eecs.umich.edu//;- 1077997Ssaidi@eecs.umich.edu// .MACRO _PTEDEF,_GBL 1087997Ssaidi@eecs.umich.edu// _DEFINI PTE,_GBL 1097997Ssaidi@eecs.umich.edu 1107997Ssaidi@eecs.umich.edu#define pte_v_pfn 32 1117997Ssaidi@eecs.umich.edu#define pte_m_soft (0xFFFF0000) 1127997Ssaidi@eecs.umich.edu#define pte_v_soft 16 1137997Ssaidi@eecs.umich.edu#define pte_m_uwe (0x8000) 1147997Ssaidi@eecs.umich.edu#define pte_v_uwe 15 1157997Ssaidi@eecs.umich.edu#define pte_m_swe (0x4000) 1167997Ssaidi@eecs.umich.edu#define pte_v_swe 14 1177997Ssaidi@eecs.umich.edu#define pte_m_ewe (0x2000) 1187997Ssaidi@eecs.umich.edu#define pte_v_ewe 13 1197997Ssaidi@eecs.umich.edu#define pte_m_kwe (0x1000) 1207997Ssaidi@eecs.umich.edu#define pte_v_kwe 12 1217997Ssaidi@eecs.umich.edu#define pte_m_ure (0x0800) 1227997Ssaidi@eecs.umich.edu#define pte_v_ure 11 1237997Ssaidi@eecs.umich.edu#define pte_m_sre (0x0400) 1247997Ssaidi@eecs.umich.edu#define pte_v_sre 10 1257997Ssaidi@eecs.umich.edu#define pte_m_ere (0x0200) 1267997Ssaidi@eecs.umich.edu#define pte_v_ere 9 1277997Ssaidi@eecs.umich.edu#define pte_m_kre (0x0100) 1287997Ssaidi@eecs.umich.edu#define pte_v_kre 8 1297997Ssaidi@eecs.umich.edu#define pte_m_hpf (0x0020) 1307997Ssaidi@eecs.umich.edu#define pte_v_hpf 5 1317997Ssaidi@eecs.umich.edu#define pte_m_asm (0x0010) 1327997Ssaidi@eecs.umich.edu#define pte_v_asm 4 1337997Ssaidi@eecs.umich.edu#define pte_m_foe (0x0008) 1347997Ssaidi@eecs.umich.edu#define pte_v_foe 3 1357997Ssaidi@eecs.umich.edu#define pte_m_fow (0x0004) 1367997Ssaidi@eecs.umich.edu#define pte_v_fow 2 1377997Ssaidi@eecs.umich.edu#define pte_m_for (0x0002) 1387997Ssaidi@eecs.umich.edu#define pte_v_for 1 1397997Ssaidi@eecs.umich.edu#define pte_m_v (0x0001) 1407997Ssaidi@eecs.umich.edu#define pte_v_v 0 1417997Ssaidi@eecs.umich.edu 1427997Ssaidi@eecs.umich.edu// _DEFEND PTE,_GBL,DEF 1437997Ssaidi@eecs.umich.edu// .ENDM 1447997Ssaidi@eecs.umich.edu//;+ 1457997Ssaidi@eecs.umich.edu//; VA layout - symbol prefix VA_ 1467997Ssaidi@eecs.umich.edu//; 1477997Ssaidi@eecs.umich.edu//; Loc Size name function 1487997Ssaidi@eecs.umich.edu//; ------ ------ ------- ----------------------------------- 1497997Ssaidi@eecs.umich.edu//; <42:33> 10 SEG1 First seg table offset for mapping 1507997Ssaidi@eecs.umich.edu//; <32:23> 10 SEG2 Second seg table offset for mapping 1517997Ssaidi@eecs.umich.edu//; <22:13> 10 SEG3 Third seg table offset for mapping 1527997Ssaidi@eecs.umich.edu//; <12:0> 13 OFFSET Byte within page 1537997Ssaidi@eecs.umich.edu//;- 1547997Ssaidi@eecs.umich.edu// .MACRO _VADEF,_GBL 1557997Ssaidi@eecs.umich.edu// _DEFINI VA,_GBL 1567997Ssaidi@eecs.umich.edu 1577997Ssaidi@eecs.umich.edu#define va_m_offset (0x000000001FFF) 1587997Ssaidi@eecs.umich.edu#define va_v_offset 0 1597997Ssaidi@eecs.umich.edu#define va_m_seg3 (0x0000007FE000) 1607997Ssaidi@eecs.umich.edu#define va_v_seg3 13 1617997Ssaidi@eecs.umich.edu#define va_m_seg2 (0x0001FF800000) 1627997Ssaidi@eecs.umich.edu#define va_v_seg2 23 1637997Ssaidi@eecs.umich.edu#define va_m_seg1 (0x7FE00000000) 1647997Ssaidi@eecs.umich.edu#define va_v_seg1 33 1657997Ssaidi@eecs.umich.edu 1667997Ssaidi@eecs.umich.edu// _DEFEND VA,_GBL,DEF 1677997Ssaidi@eecs.umich.edu// .ENDM 1687997Ssaidi@eecs.umich.edu//;+ 1697997Ssaidi@eecs.umich.edu//; PRIVILEGED CONTEXT BLOCK (PCB) 1707997Ssaidi@eecs.umich.edu//;- 1717997Ssaidi@eecs.umich.edu// .MACRO _PCBDEF,_GBL 1727997Ssaidi@eecs.umich.edu// _DEFINI PCB,_GBL 1737997Ssaidi@eecs.umich.edu#define pcb_q_ksp 0 1747997Ssaidi@eecs.umich.edu#define pcb_q_esp 8 1757997Ssaidi@eecs.umich.edu#define pcb_q_ssp 16 1767997Ssaidi@eecs.umich.edu#define pcb_q_usp 24 1777997Ssaidi@eecs.umich.edu#define pcb_q_ptbr 32 1787997Ssaidi@eecs.umich.edu#define pcb_q_asn 40 1797997Ssaidi@eecs.umich.edu#define pcb_q_ast 48 1807997Ssaidi@eecs.umich.edu#define pcb_q_fen 56 1817997Ssaidi@eecs.umich.edu#define pcb_q_cc 64 1827997Ssaidi@eecs.umich.edu#define pcb_q_unq 72 1837997Ssaidi@eecs.umich.edu#define pcb_q_sct 80 1847997Ssaidi@eecs.umich.edu 1857997Ssaidi@eecs.umich.edu#define pcb_v_asten 0 1867997Ssaidi@eecs.umich.edu#define pcb_m_asten (0x0f<<pcb_v_asten) 1877997Ssaidi@eecs.umich.edu#define pcb_v_astsr 4 1887997Ssaidi@eecs.umich.edu#define pcb_m_astsr (0x0f<<pcb_v_astsr) 1897997Ssaidi@eecs.umich.edu#define pcb_v_dat 63 1907997Ssaidi@eecs.umich.edu#define pcb_v_pme 62 1917997Ssaidi@eecs.umich.edu 1927997Ssaidi@eecs.umich.edu// _DEFEND PCB,_GBL,DEF 1937997Ssaidi@eecs.umich.edu// .ENDM 1947997Ssaidi@eecs.umich.edu//;+ 1957997Ssaidi@eecs.umich.edu//; SYSTEM CONTROL BLOCK (SCB) 1967997Ssaidi@eecs.umich.edu//;- 1977997Ssaidi@eecs.umich.edu// .MACRO _SCBDEF,_GBL 1987997Ssaidi@eecs.umich.edu// _DEFINI SCB,_GBL 1997997Ssaidi@eecs.umich.edu 2007997Ssaidi@eecs.umich.edu#define scb_v_fen (0x0010) 2017997Ssaidi@eecs.umich.edu#define scb_v_acv (0x0080) 2027997Ssaidi@eecs.umich.edu#define scb_v_tnv (0x0090) 2037997Ssaidi@eecs.umich.edu#define scb_v_for (0x00A0) 2047997Ssaidi@eecs.umich.edu#define scb_v_fow (0x00B0) 2057997Ssaidi@eecs.umich.edu#define scb_v_foe (0x00C0) 2067997Ssaidi@eecs.umich.edu#define scb_v_arith (0x0200) 2077997Ssaidi@eecs.umich.edu#define scb_v_kast (0x0240) 2087997Ssaidi@eecs.umich.edu#define scb_v_east (0x0250) 2097997Ssaidi@eecs.umich.edu#define scb_v_sast (0x0260) 2107997Ssaidi@eecs.umich.edu#define scb_v_uast (0x0270) 2117997Ssaidi@eecs.umich.edu#define scb_v_unalign (0x0280) 2127997Ssaidi@eecs.umich.edu#define scb_v_bpt (0x0400) 2137997Ssaidi@eecs.umich.edu#define scb_v_bugchk (0x0410) 2147997Ssaidi@eecs.umich.edu#define scb_v_opcdec (0x0420) 2157997Ssaidi@eecs.umich.edu#define scb_v_illpal (0x0430) 2167997Ssaidi@eecs.umich.edu#define scb_v_trap (0x0440) 2177997Ssaidi@eecs.umich.edu#define scb_v_chmk (0x0480) 2187997Ssaidi@eecs.umich.edu#define scb_v_chme (0x0490) 2197997Ssaidi@eecs.umich.edu#define scb_v_chms (0x04A0) 2207997Ssaidi@eecs.umich.edu#define scb_v_chmu (0x04B0) 2217997Ssaidi@eecs.umich.edu#define scb_v_sw0 (0x0500) 2227997Ssaidi@eecs.umich.edu#define scb_v_sw1 (0x0510) 2237997Ssaidi@eecs.umich.edu#define scb_v_sw2 (0x0520) 2247997Ssaidi@eecs.umich.edu#define scb_v_sw3 (0x0530) 2257997Ssaidi@eecs.umich.edu#define scb_v_sw4 (0x0540) 2267997Ssaidi@eecs.umich.edu#define scb_v_sw5 (0x0550) 2277997Ssaidi@eecs.umich.edu#define scb_v_sw6 (0x0560) 2287997Ssaidi@eecs.umich.edu#define scb_v_sw7 (0x0570) 2297997Ssaidi@eecs.umich.edu#define scb_v_sw8 (0x0580) 2307997Ssaidi@eecs.umich.edu#define scb_v_sw9 (0x0590) 2317997Ssaidi@eecs.umich.edu#define scb_v_sw10 (0x05A0) 2327997Ssaidi@eecs.umich.edu#define scb_v_sw11 (0x05B0) 2337997Ssaidi@eecs.umich.edu#define scb_v_sw12 (0x05C0) 2347997Ssaidi@eecs.umich.edu#define scb_v_sw13 (0x05D0) 2357997Ssaidi@eecs.umich.edu#define scb_v_sw14 (0x05E0) 2367997Ssaidi@eecs.umich.edu#define scb_v_sw15 (0x05F0) 2377997Ssaidi@eecs.umich.edu#define scb_v_clock (0x0600) 2387997Ssaidi@eecs.umich.edu#define scb_v_inter (0x0610) 2397997Ssaidi@eecs.umich.edu#define scb_v_sys_corr_err (0x0620) 2407997Ssaidi@eecs.umich.edu#define scb_v_proc_corr_err (0x0630) 2417997Ssaidi@eecs.umich.edu#define scb_v_pwrfail (0x0640) 2427997Ssaidi@eecs.umich.edu#define scb_v_perfmon (0x0650) 2437997Ssaidi@eecs.umich.edu#define scb_v_sysmchk (0x0660) 2447997Ssaidi@eecs.umich.edu#define scb_v_procmchk (0x0670) 2457997Ssaidi@eecs.umich.edu#define scb_v_passive_rel (0x06F0) 2467997Ssaidi@eecs.umich.edu 2477997Ssaidi@eecs.umich.edu// _DEFEND SCB,_GBL,DEF 2487997Ssaidi@eecs.umich.edu// .ENDM 2497997Ssaidi@eecs.umich.edu//;+ 2507997Ssaidi@eecs.umich.edu//; Stack frame (FRM) 2517997Ssaidi@eecs.umich.edu//;- 2527997Ssaidi@eecs.umich.edu// .MACRO _FRMDEF,_GBL 2537997Ssaidi@eecs.umich.edu// _DEFINI FRM,_GBL 2547997Ssaidi@eecs.umich.edu 2557997Ssaidi@eecs.umich.edu#define frm_v_r2 (0x0000) 2567997Ssaidi@eecs.umich.edu#define frm_v_r3 (0x0008) 2577997Ssaidi@eecs.umich.edu#define frm_v_r4 (0x0010) 2587997Ssaidi@eecs.umich.edu#define frm_v_r5 (0x0018) 2597997Ssaidi@eecs.umich.edu#define frm_v_r6 (0x0020) 2607997Ssaidi@eecs.umich.edu#define frm_v_r7 (0x0028) 2617997Ssaidi@eecs.umich.edu#define frm_v_pc (0x0030) 2627997Ssaidi@eecs.umich.edu#define frm_v_ps (0x0038) 2637997Ssaidi@eecs.umich.edu 2647997Ssaidi@eecs.umich.edu// _DEFEND FRM,_GBL,DEF 2657997Ssaidi@eecs.umich.edu// .ENDM 2667997Ssaidi@eecs.umich.edu//;+ 2677997Ssaidi@eecs.umich.edu//; Exeception summary register (EXS) 2687997Ssaidi@eecs.umich.edu//;- 2697997Ssaidi@eecs.umich.edu// .MACRO _EXSDEF,_GBL 2707997Ssaidi@eecs.umich.edu// _DEFINI EXS,_GBL 2717997Ssaidi@eecs.umich.edu// exs_v_swc <0> ; Software completion 2727997Ssaidi@eecs.umich.edu// exs_v_inv <1> ; Ivalid operation 2737997Ssaidi@eecs.umich.edu// exs_v_dze <2> ; Div by zero 2747997Ssaidi@eecs.umich.edu// exs_v_fov <3> ; Floating point overflow 2757997Ssaidi@eecs.umich.edu// exs_v_unf <4> ; Floating point underflow 2767997Ssaidi@eecs.umich.edu// exs_v_ine <5> ; Floating point inexact 2777997Ssaidi@eecs.umich.edu// exs_v_iov <6> ; Floating convert to integer overflow 2787997Ssaidi@eecs.umich.edu#define exs_v_swc 0 2797997Ssaidi@eecs.umich.edu#define exs_v_inv 1 2807997Ssaidi@eecs.umich.edu#define exs_v_dze 2 2817997Ssaidi@eecs.umich.edu#define exs_v_fov 3 2827997Ssaidi@eecs.umich.edu#define exs_v_unf 4 2837997Ssaidi@eecs.umich.edu#define exs_v_ine 5 2847997Ssaidi@eecs.umich.edu#define exs_v_iov 6 2857997Ssaidi@eecs.umich.edu 2867997Ssaidi@eecs.umich.edu#define exs_m_swc (1<<exs_v_swc) 2877997Ssaidi@eecs.umich.edu#define exs_m_inv (1<<exs_v_inv) 2887997Ssaidi@eecs.umich.edu#define exs_m_dze (1<<exs_v_dze) 2897997Ssaidi@eecs.umich.edu#define exs_m_fov (1<<exs_v_fov) 2907997Ssaidi@eecs.umich.edu#define exs_m_unf (1<<exs_v_unf) 2917997Ssaidi@eecs.umich.edu#define exs_m_ine (1<<exs_v_ine) 2927997Ssaidi@eecs.umich.edu#define exs_m_iov (1<<exs_v_iov) 2937997Ssaidi@eecs.umich.edu 2947997Ssaidi@eecs.umich.edu// _defend exs,_gbl,def 2957997Ssaidi@eecs.umich.edu// .endm 2967997Ssaidi@eecs.umich.edu//;+ 2977997Ssaidi@eecs.umich.edu//; machine check error summary register (mces) 2987997Ssaidi@eecs.umich.edu//;- 2997997Ssaidi@eecs.umich.edu// .macro _mcesdef,_gbl 3007997Ssaidi@eecs.umich.edu// _defini mces,_gbl 3017997Ssaidi@eecs.umich.edu// mces_v_mchk <0> ; machine check in progress 3027997Ssaidi@eecs.umich.edu// mces_v_sce <1> ; system correctable error 3037997Ssaidi@eecs.umich.edu// mces_v_pce <2> ; processor correctable error 3047997Ssaidi@eecs.umich.edu// mces_v_dpc <3> ; disable reporting of processor correctable errors 3057997Ssaidi@eecs.umich.edu// mces_v_dsc <4> ; disable reporting of system correctable errors 3067997Ssaidi@eecs.umich.edu#define mces_v_mchk 0 3077997Ssaidi@eecs.umich.edu#define mces_v_sce 1 3087997Ssaidi@eecs.umich.edu#define mces_v_pce 2 3097997Ssaidi@eecs.umich.edu#define mces_v_dpc 3 3107997Ssaidi@eecs.umich.edu#define mces_v_dsc 4 3117997Ssaidi@eecs.umich.edu 3127997Ssaidi@eecs.umich.edu#define mces_m_mchk (1<<mces_v_mchk) 3137997Ssaidi@eecs.umich.edu#define mces_m_sce (1<<mces_v_sce) 3147997Ssaidi@eecs.umich.edu#define mces_m_pce (1<<mces_v_pce) 3157997Ssaidi@eecs.umich.edu#define mces_m_dpc (1<<mces_v_dpc) 3167997Ssaidi@eecs.umich.edu#define mces_m_dsc (1<<mces_v_dsc) 3177997Ssaidi@eecs.umich.edu#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc)) 3187997Ssaidi@eecs.umich.edu// _defend mces,_gbl,def 3197997Ssaidi@eecs.umich.edu// .endm 3207997Ssaidi@eecs.umich.edu 3217997Ssaidi@eecs.umich.edu 3227997Ssaidi@eecs.umich.edu 3237997Ssaidi@eecs.umich.edu#endif 324