1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 main.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 /****************************************/ 39 /* Main Filename: main.cc */ 40 /****************************************/ 41 /* */ 42 /* 9-bit bool = 6-bit bool + 6-bit bool */ 43 /* */ 44 /* Max addition is 63 + 63 */ 45 /* */ 46 /****************************************/ 47 48#include "datawidth.h" 49#include "stimgen.h" 50 51int sc_main(int ac, char *av[]) 52{ 53 54// Parameter Settings 55 int result_size = 9; 56 int in1_size = 6; 57 int in2_size = 6; 58 59// Signal Instantiation 60 signal_bool_vector6 in1 ("in1"); 61 signal_bool_vector6 in2 ("in2"); 62 signal_bool_vector9 result ("result"); 63 sc_signal<bool> ready ("ready"); 64 65// Clock Instantiation 66 sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS); 67 68// Process Instantiation 69 datawidth D1 ("D1", clk, in1, in2, ready, result, 70 in1_size, in2_size, result_size); 71 72 stimgen T1 ("T1", clk, result, in1, in2, ready); 73 74// Simulation Run Control 75 sc_start(); 76 return 0; 77} 78