1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test06.cpp -- test multiple interfaces 23 24 Original Author: Andy Goodrich, Forte Design Systems, 03 April 2007 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38// test of multiple interfaces for an sc_fifo 39 40#include "systemc.h" 41 42#define W_INFO(msg,iface) \ 43 cout << sc_time_stamp() << "," << sc_delta_count() \ 44 << ": writer" << iface << ": " << msg << endl; 45 46#define R_INFO(msg,iface) \ 47 cout << sc_time_stamp() << "," << sc_delta_count() \ 48 << ": reader" << iface << ": " << msg << endl; 49 50SC_MODULE( writer ) 51{ 52 // port(s) 53 sc_fifo_out<int> out; 54 55 // process(es) 56 void main_action() 57 { 58 int val = 0; 59 while( true ) { 60 wait( 10, SC_NS ); // wait for 10 ns 61 for ( int iface=0; iface < 3; iface++ ) 62 { 63 W_INFO( "blocking write", iface ); 64 for( int i = 0; i < 20; i ++ ) { 65 out[iface]->write( val ++ ); // blocking write 66 } 67 } 68 } 69 } 70 71 SC_CTOR( writer ) 72 { 73 SC_THREAD( main_action ); 74 sensitive << out.data_read(); 75 } 76}; 77 78SC_MODULE( reader ) 79{ 80 // port(s) 81 sc_fifo_in<int> in; 82 83 // process(es) 84 void main_action() 85 { 86 int iface; 87 int val; 88 while( true ) { 89 wait( 10, SC_NS ); // wait for 10 ns 90 for ( iface=0; iface < 3; iface++ ) 91 { 92 R_INFO( "blocking read 1", iface ); 93 for( int i = 0; i < 15; i ++ ) { 94 in[iface]->read( val ); // blocking read 95 R_INFO( val, iface ); 96 } 97 } 98 wait( 10, SC_NS ); 99 R_INFO( in.num_available() << " available samples", iface ); 100 R_INFO( "blocking read 2", iface ); 101 for ( iface=0; iface < 3; iface++ ) 102 { 103 for( int i = 0; i < 15; i ++ ) { 104 val = in[iface]->read(); // blocking read 105 R_INFO( val, iface ); 106 } 107 } 108 } 109 } 110 111 SC_CTOR( reader ) 112 { 113 SC_THREAD( main_action ); 114 sensitive << in.data_written(); 115 } 116}; 117 118int sc_main( int, char*[] ) 119{ 120 // sc_clock c; 121 122 // declare channel(s) 123 sc_fifo<int> fifo( 10 ); 124 sc_fifo<int> fifo1( 10 ); 125 sc_fifo<int> fifo2( 10 ); 126 127 // instantiate block(s) and connect to channel(s) 128 writer w( "writer" ); 129 reader r( "reader" ); 130 131 w.out( fifo ); 132 w.out( fifo1 ); 133 w.out( fifo2 ); 134 r.in( fifo ); 135 r.in( fifo1 ); 136 r.in( fifo2 ); 137 138 // run the simulation 139 sc_start( 100, SC_NS ); 140 141 return 0; 142} 143