1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20//==================================================================== 21// Nov 06, 2008 22// 23// Updated by: 24// Xiaopeng Qiu, JEDA Technologies, Inc 25// Email: qiuxp@jedatechnologies.net 26// 27// To fix violations of TLM2.0 rules, which are detected by JEDA 28// TLM2.0 checker. 29// 30//==================================================================== 31 32#ifndef __SIMPLE_LT_INITIATOR1_H__ 33#define __SIMPLE_LT_INITIATOR1_H__ 34 35#include "tlm.h" /// TLM definitions 36#include <cassert> /// STD assert () 37 38class SimpleLTInitiator1 : 39 public sc_core::sc_module, 40 public virtual tlm::tlm_bw_transport_if<> 41{ 42public: 43 typedef tlm::tlm_generic_payload transaction_type; 44 typedef tlm::tlm_phase phase_type; 45 typedef tlm::tlm_sync_enum sync_enum_type; 46 typedef tlm::tlm_fw_transport_if<> fw_interface_type; 47 typedef tlm::tlm_bw_transport_if<> bw_interface_type; 48 typedef tlm::tlm_initiator_socket<32> initiator_socket_type; 49 50public: 51 initiator_socket_type socket; 52 53public: 54 SC_HAS_PROCESS(SimpleLTInitiator1); 55 SimpleLTInitiator1(sc_core::sc_module_name name, 56 unsigned int nrOfTransactions = 0x5, 57 unsigned int baseAddress = 0x0) : 58 sc_core::sc_module(name), 59 socket("socket"), 60 mNrOfTransactions(nrOfTransactions), 61 mBaseAddress(baseAddress), 62 mTransactionCount(0) 63 { 64 // Bind this initiator's interface to the initiator socket 65 socket(*this); 66 67 // Initiator thread 68 SC_THREAD(run); 69 } 70 71 bool initTransaction(transaction_type& trans) 72 { 73 if (mTransactionCount < mNrOfTransactions) { 74 trans.set_address(mBaseAddress + 4*mTransactionCount); 75 mData = mTransactionCount; 76 trans.set_command(tlm::TLM_WRITE_COMMAND); 77 78 } else if (mTransactionCount < 2 * mNrOfTransactions) { 79 trans.set_address(mBaseAddress + 4*(mTransactionCount - mNrOfTransactions)); 80 mData = 0; 81 trans.set_command(tlm::TLM_READ_COMMAND); 82 83 } else { 84 return false; 85 } 86 87 trans.set_data_ptr(reinterpret_cast<unsigned char*>(&mData)); 88 trans.set_data_length(4); 89 trans.set_streaming_width(4); 90 trans.set_dmi_allowed(false); 91 trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); 92 93 ++mTransactionCount; 94 return true; 95 } 96 97 void logStartTransation(transaction_type& trans) 98 { 99 if (trans.get_command() == tlm::TLM_WRITE_COMMAND) { 100 std::cout << name() << ": Send write request: A = 0x" 101 << std::hex << (unsigned int)trans.get_address() 102 << ", D = 0x" << mData << std::dec 103 << " @ " << sc_core::sc_time_stamp() << std::endl; 104 105 } else { 106 std::cout << name() << ": Send read request: A = 0x" 107 << std::hex << (unsigned int)trans.get_address() << std::dec 108 << " @ " << sc_core::sc_time_stamp() << std::endl; 109 } 110 } 111 112 void logEndTransaction(transaction_type& trans) 113 { 114 if (trans.get_response_status() != tlm::TLM_OK_RESPONSE) { 115 std::cout << name() << ": Received error response @ " 116 << sc_core::sc_time_stamp() << std::endl; 117 118 } else { 119 std::cout << name() << ": Received ok response"; 120 if (trans.get_command() == tlm::TLM_READ_COMMAND) { 121 std::cout << ": D = 0x" << std::hex << mData << std::dec; 122 } 123 std::cout << " @ " << sc_core::sc_time_stamp() << std::endl; 124 } 125 } 126 127 void run() 128 { 129 transaction_type trans; 130 sc_core::sc_time t(sc_core::SC_ZERO_TIME); 131 while (initTransaction(trans)) { 132 logStartTransation(trans); 133 socket->b_transport(trans, t); 134 wait(t); 135 logEndTransaction(trans); 136 t = sc_core::SC_ZERO_TIME; 137 } 138 wait(); 139 140 } 141 142 tlm::tlm_sync_enum nb_transport_bw(transaction_type &,phase_type &,sc_core::sc_time & ) 143 { 144 assert(0); // should never happen 145 return tlm::TLM_COMPLETED; 146 } 147 148 void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, 149 sc_dt::uint64 end_range) 150 { 151 // No DMI support: ignore 152 } 153 154private: 155 sc_core::sc_event mEndEvent; 156 unsigned int mNrOfTransactions; 157 unsigned int mBaseAddress; 158 unsigned int mTransactionCount; 159 unsigned int mData; 160}; 161 162#endif 163