README.txt revision 12922:a4f51f3405ac
111424Sdavid.guillen@arm.comSimpleLTInitiator1/SimpleLTTarget1 211424Sdavid.guillen@arm.com---------------------------------- 311424Sdavid.guillen@arm.com 411424Sdavid.guillen@arm.com- LT Initiator/Target model using the base (standard) tlm socket 511424Sdavid.guillen@arm.com- Added support for DMI in SimpleLTTarget1 611424Sdavid.guillen@arm.com 711424Sdavid.guillen@arm.comSimpleLTInitiator1_DMI 811424Sdavid.guillen@arm.com---------------------- 911424Sdavid.guillen@arm.com 1011424Sdavid.guillen@arm.com- uses DMI transactions, the DMI structure is using the DMI-hint 1111424Sdavid.guillen@arm.com to check if a DMI request would make sense. 1211424Sdavid.guillen@arm.com- uses a single transport_dbg transaction at end_of_simulation() 1311424Sdavid.guillen@arm.com 1411424Sdavid.guillen@arm.comSimpleLTInitiator2/SimpleLTTarget2 1511424Sdavid.guillen@arm.com---------------------------------- 1611424Sdavid.guillen@arm.com 1711424Sdavid.guillen@arm.com- LT Initiator/Target model using the convenience tlm socket 1811424Sdavid.guillen@arm.com- Target and Initiator model use the REGISTER_DEBUGTRANSPORT macro to register 1911424Sdavid.guillen@arm.com a transport callback to the socket 2011424Sdavid.guillen@arm.com- Added support for DMI handling, callback registration with 2111424Sdavid.guillen@arm.com REGISTER_DMI 2211424Sdavid.guillen@arm.com- SimpleLTTarget2 does not register the transport_dbg callback, so that 2311424Sdavid.guillen@arm.com we are able to test this case in bus_dmi. 2411424Sdavid.guillen@arm.com 2511424Sdavid.guillen@arm.comSimpleLTInitiator2_DMI 2611424Sdavid.guillen@arm.com---------------------- 2711424Sdavid.guillen@arm.com 2811424Sdavid.guillen@arm.com- uses DMI transactions, but ignoring the DMI hint 2911424Sdavid.guillen@arm.com- uses a single transport_dbg transaction at end_of_simulation() 3011424Sdavid.guillen@arm.com 3111424Sdavid.guillen@arm.comSimpleLTInitiator3 3211424Sdavid.guillen@arm.com------------------ 3311424Sdavid.guillen@arm.com 3411424Sdavid.guillen@arm.com- LT Initiator model using the convenience tlm socket 3511424Sdavid.guillen@arm.com- Initiator model uses the endEvent of the socket to wait until the 3611424Sdavid.guillen@arm.com transaction is finished 3711424Sdavid.guillen@arm.com 3811424Sdavid.guillen@arm.comSimpleLTInitiator3_DMI 3911424Sdavid.guillen@arm.com---------------------- 4011424Sdavid.guillen@arm.com 4111424Sdavid.guillen@arm.com- based on SimpleInitiator3, uses DMI (without DMI hint) 4211424Sdavid.guillen@arm.com 4311424Sdavid.guillen@arm.comSimpleATInitiator1/SimpleATTarget1 4411424Sdavid.guillen@arm.com---------------------------------- 4511424Sdavid.guillen@arm.com 4611424Sdavid.guillen@arm.com- AT Initiator/Target model implementing the AT protocol 4711424Sdavid.guillen@arm.com- one call of nb_transport for each timing point in the protocol (BEGIN_REQ, 4811424Sdavid.guillen@arm.com END_REQ, BEGIN_RESP and END_RESP) 4911424Sdavid.guillen@arm.com 5011424Sdavid.guillen@arm.comSimpleATInitiator2/SimpleATTarget2 5111424Sdavid.guillen@arm.com---------------------------------- 5211424Sdavid.guillen@arm.com 5311424Sdavid.guillen@arm.com- AT Initiator/Target model implementing the AT protocol with timing annotation 5411424Sdavid.guillen@arm.com- only a call of nb_transport for the start of a phase (BEGIN_REQ and 5511424Sdavid.guillen@arm.com BEGIN_RESP) 5611424Sdavid.guillen@arm.com- end of a phase is notified via timing annotation (t argument) 5711424Sdavid.guillen@arm.com 5811424Sdavid.guillen@arm.comCoreDecouplingLTInitiator 5911424Sdavid.guillen@arm.com------------------------- 6011424Sdavid.guillen@arm.com 6111424Sdavid.guillen@arm.com- LT Initiator using 'Core Decoupling' 6211424Sdavid.guillen@arm.com 6311424Sdavid.guillen@arm.comExplicitLTTarget 6411424Sdavid.guillen@arm.com---------------- 6511424Sdavid.guillen@arm.com 6611424Sdavid.guillen@arm.com- LT Target that uses explicit timing (calls wait) 6711424Sdavid.guillen@arm.com- added support for debug transactions 6811424Sdavid.guillen@arm.com 6911424Sdavid.guillen@arm.comExplicitLTTarget 7011424Sdavid.guillen@arm.com---------------- 7111424Sdavid.guillen@arm.com 7211424Sdavid.guillen@arm.com- AT Target, only registers nb_transport 7311424Sdavid.guillen@arm.com 7411424Sdavid.guillen@arm.comSimpleBus 7511424Sdavid.guillen@arm.com--------- 7611424Sdavid.guillen@arm.com 7711424Sdavid.guillen@arm.com- Simple bus model 7811424Sdavid.guillen@arm.com- Runtime switcheable between LT and AT (can only switch if no transactions 7911424Sdavid.guillen@arm.com are pending) 8011424Sdavid.guillen@arm.com- No limitation on number of pending transactions (all targets that can return 8111424Sdavid.guillen@arm.com false must support multiple transactions) 8211424Sdavid.guillen@arm.com- added support for DMI and debug transactions 8311424Sdavid.guillen@arm.com- LT mode: 8411424Sdavid.guillen@arm.com-- Forward nb_transport calls to initiator/targets 8511424Sdavid.guillen@arm.com-- Only one active request/response phase 8611424Sdavid.guillen@arm.com- AT mode: 8711424Sdavid.guillen@arm.com-- Incoming transactions are queued 8811424Sdavid.guillen@arm.com-- AT protocol is executed from a different SC_THREAD 8911424Sdavid.guillen@arm.com-- A target is notified immediately of the end of a transaction (using timing 9011424Sdavid.guillen@arm.com annotation). This is needed because the initiator can re-use the 9111424Sdavid.guillen@arm.com transaction (and the target may use the transaction pointer to identify the 9211424Sdavid.guillen@arm.com transaction) 9311424Sdavid.guillen@arm.com